2 * Atmel SDMMC controller driver.
4 * Copyright (C) 2015 Atmel,
5 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com>
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/err.h>
21 #include <linux/kernel.h>
22 #include <linux/mmc/host.h>
23 #include <linux/mmc/slot-gpio.h>
24 #include <linux/module.h>
26 #include <linux/of_device.h>
28 #include <linux/pm_runtime.h>
30 #include "sdhci-pltfm.h"
32 #define SDMMC_MC1R 0x204
33 #define SDMMC_MC1R_DDR BIT(3)
34 #define SDMMC_MC1R_FCD BIT(7)
35 #define SDMMC_CACR 0x230
36 #define SDMMC_CACR_CAPWREN BIT(0)
37 #define SDMMC_CACR_KEY (0x46 << 8)
39 #define SDHCI_AT91_PRESET_COMMON_CONF 0x400 /* drv type B, programmable clock mode */
41 struct sdhci_at91_priv {
48 static void sdhci_at91_set_force_card_detect(struct sdhci_host *host)
52 mc1r = readb(host->ioaddr + SDMMC_MC1R);
53 mc1r |= SDMMC_MC1R_FCD;
54 writeb(mc1r, host->ioaddr + SDMMC_MC1R);
57 static void sdhci_at91_set_clock(struct sdhci_host *host, unsigned int clock)
60 unsigned long timeout;
62 host->mmc->actual_clock = 0;
65 * There is no requirement to disable the internal clock before
66 * changing the SD clock configuration. Moreover, disabling the
67 * internal clock, changing the configuration and re-enabling the
68 * internal clock causes some bugs. It can prevent to get the internal
69 * clock stable flag ready and an unexpected switch to the base clock
72 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
73 clk &= SDHCI_CLOCK_INT_EN;
74 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
79 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
81 clk |= SDHCI_CLOCK_INT_EN;
82 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
86 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
87 & SDHCI_CLOCK_INT_STABLE)) {
89 pr_err("%s: Internal clock never stabilised.\n",
90 mmc_hostname(host->mmc));
97 clk |= SDHCI_CLOCK_CARD_EN;
98 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
102 * In this specific implementation of the SDHCI controller, the power register
103 * needs to have a valid voltage set even when the power supply is managed by
104 * an external regulator.
106 static void sdhci_at91_set_power(struct sdhci_host *host, unsigned char mode,
109 if (!IS_ERR(host->mmc->supply.vmmc)) {
110 struct mmc_host *mmc = host->mmc;
112 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
114 sdhci_set_power_noreg(host, mode, vdd);
117 void sdhci_at91_set_uhs_signaling(struct sdhci_host *host, unsigned int timing)
119 if (timing == MMC_TIMING_MMC_DDR52)
120 sdhci_writeb(host, SDMMC_MC1R_DDR, SDMMC_MC1R);
121 sdhci_set_uhs_signaling(host, timing);
124 static void sdhci_at91_reset(struct sdhci_host *host, u8 mask)
126 sdhci_reset(host, mask);
128 if ((host->mmc->caps & MMC_CAP_NONREMOVABLE)
129 || mmc_gpio_get_cd(host->mmc) >= 0)
130 sdhci_at91_set_force_card_detect(host);
133 static const struct sdhci_ops sdhci_at91_sama5d2_ops = {
134 .set_clock = sdhci_at91_set_clock,
135 .set_bus_width = sdhci_set_bus_width,
136 .reset = sdhci_at91_reset,
137 .set_uhs_signaling = sdhci_at91_set_uhs_signaling,
138 .set_power = sdhci_at91_set_power,
141 static const struct sdhci_pltfm_data soc_data_sama5d2 = {
142 .ops = &sdhci_at91_sama5d2_ops,
145 static const struct of_device_id sdhci_at91_dt_match[] = {
146 { .compatible = "atmel,sama5d2-sdhci", .data = &soc_data_sama5d2 },
149 MODULE_DEVICE_TABLE(of, sdhci_at91_dt_match);
151 static int sdhci_at91_set_clks_presets(struct device *dev)
153 struct sdhci_host *host = dev_get_drvdata(dev);
154 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
155 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
157 unsigned int caps0, caps1;
158 unsigned int clk_base, clk_mul;
159 unsigned int gck_rate, real_gck_rate;
160 unsigned int preset_div;
163 * The mult clock is provided by as a generated clock by the PMC
164 * controller. In order to set the rate of gck, we have to get the
165 * base clock rate and the clock mult from capabilities.
167 clk_prepare_enable(priv->hclock);
168 caps0 = readl(host->ioaddr + SDHCI_CAPABILITIES);
169 caps1 = readl(host->ioaddr + SDHCI_CAPABILITIES_1);
170 clk_base = (caps0 & SDHCI_CLOCK_V3_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
171 clk_mul = (caps1 & SDHCI_CLOCK_MUL_MASK) >> SDHCI_CLOCK_MUL_SHIFT;
172 gck_rate = clk_base * 1000000 * (clk_mul + 1);
173 ret = clk_set_rate(priv->gck, gck_rate);
175 dev_err(dev, "failed to set gck");
176 clk_disable_unprepare(priv->hclock);
180 * We need to check if we have the requested rate for gck because in
181 * some cases this rate could be not supported. If it happens, the rate
182 * is the closest one gck can provide. We have to update the value
185 real_gck_rate = clk_get_rate(priv->gck);
186 if (real_gck_rate != gck_rate) {
187 clk_mul = real_gck_rate / (clk_base * 1000000) - 1;
188 caps1 &= (~SDHCI_CLOCK_MUL_MASK);
189 caps1 |= ((clk_mul << SDHCI_CLOCK_MUL_SHIFT) &
190 SDHCI_CLOCK_MUL_MASK);
191 /* Set capabilities in r/w mode. */
192 writel(SDMMC_CACR_KEY | SDMMC_CACR_CAPWREN,
193 host->ioaddr + SDMMC_CACR);
194 writel(caps1, host->ioaddr + SDHCI_CAPABILITIES_1);
195 /* Set capabilities in ro mode. */
196 writel(0, host->ioaddr + SDMMC_CACR);
197 dev_info(dev, "update clk mul to %u as gck rate is %u Hz\n",
198 clk_mul, real_gck_rate);
202 * We have to set preset values because it depends on the clk_mul
203 * value. Moreover, SDR104 is supported in a degraded mode since the
204 * maximum sd clock value is 120 MHz instead of 208 MHz. For that
205 * reason, we need to use presets to support SDR104.
207 preset_div = DIV_ROUND_UP(real_gck_rate, 24000000) - 1;
208 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
209 host->ioaddr + SDHCI_PRESET_FOR_SDR12);
210 preset_div = DIV_ROUND_UP(real_gck_rate, 50000000) - 1;
211 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
212 host->ioaddr + SDHCI_PRESET_FOR_SDR25);
213 preset_div = DIV_ROUND_UP(real_gck_rate, 100000000) - 1;
214 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
215 host->ioaddr + SDHCI_PRESET_FOR_SDR50);
216 preset_div = DIV_ROUND_UP(real_gck_rate, 120000000) - 1;
217 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
218 host->ioaddr + SDHCI_PRESET_FOR_SDR104);
219 preset_div = DIV_ROUND_UP(real_gck_rate, 50000000) - 1;
220 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
221 host->ioaddr + SDHCI_PRESET_FOR_DDR50);
223 clk_prepare_enable(priv->mainck);
224 clk_prepare_enable(priv->gck);
229 #ifdef CONFIG_PM_SLEEP
230 static int sdhci_at91_suspend(struct device *dev)
232 struct sdhci_host *host = dev_get_drvdata(dev);
233 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
234 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
237 ret = pm_runtime_force_suspend(dev);
239 priv->restore_needed = true;
243 #endif /* CONFIG_PM_SLEEP */
246 static int sdhci_at91_runtime_suspend(struct device *dev)
248 struct sdhci_host *host = dev_get_drvdata(dev);
249 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
250 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
253 ret = sdhci_runtime_suspend_host(host);
255 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
256 mmc_retune_needed(host->mmc);
258 clk_disable_unprepare(priv->gck);
259 clk_disable_unprepare(priv->hclock);
260 clk_disable_unprepare(priv->mainck);
265 static int sdhci_at91_runtime_resume(struct device *dev)
267 struct sdhci_host *host = dev_get_drvdata(dev);
268 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
269 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
272 if (priv->restore_needed) {
273 ret = sdhci_at91_set_clks_presets(dev);
277 priv->restore_needed = false;
281 ret = clk_prepare_enable(priv->mainck);
283 dev_err(dev, "can't enable mainck\n");
287 ret = clk_prepare_enable(priv->hclock);
289 dev_err(dev, "can't enable hclock\n");
293 ret = clk_prepare_enable(priv->gck);
295 dev_err(dev, "can't enable gck\n");
300 return sdhci_runtime_resume_host(host);
302 #endif /* CONFIG_PM */
304 static const struct dev_pm_ops sdhci_at91_dev_pm_ops = {
305 SET_SYSTEM_SLEEP_PM_OPS(sdhci_at91_suspend, pm_runtime_force_resume)
306 SET_RUNTIME_PM_OPS(sdhci_at91_runtime_suspend,
307 sdhci_at91_runtime_resume,
311 static int sdhci_at91_probe(struct platform_device *pdev)
313 const struct of_device_id *match;
314 const struct sdhci_pltfm_data *soc_data;
315 struct sdhci_host *host;
316 struct sdhci_pltfm_host *pltfm_host;
317 struct sdhci_at91_priv *priv;
320 match = of_match_device(sdhci_at91_dt_match, &pdev->dev);
323 soc_data = match->data;
325 host = sdhci_pltfm_init(pdev, soc_data, sizeof(*priv));
327 return PTR_ERR(host);
329 pltfm_host = sdhci_priv(host);
330 priv = sdhci_pltfm_priv(pltfm_host);
332 priv->mainck = devm_clk_get(&pdev->dev, "baseclk");
333 if (IS_ERR(priv->mainck)) {
334 dev_err(&pdev->dev, "failed to get baseclk\n");
335 ret = PTR_ERR(priv->mainck);
336 goto sdhci_pltfm_free;
339 priv->hclock = devm_clk_get(&pdev->dev, "hclock");
340 if (IS_ERR(priv->hclock)) {
341 dev_err(&pdev->dev, "failed to get hclock\n");
342 ret = PTR_ERR(priv->hclock);
343 goto sdhci_pltfm_free;
346 priv->gck = devm_clk_get(&pdev->dev, "multclk");
347 if (IS_ERR(priv->gck)) {
348 dev_err(&pdev->dev, "failed to get multclk\n");
349 ret = PTR_ERR(priv->gck);
350 goto sdhci_pltfm_free;
353 ret = sdhci_at91_set_clks_presets(&pdev->dev);
355 goto sdhci_pltfm_free;
357 priv->restore_needed = false;
359 ret = mmc_of_parse(host->mmc);
361 goto clocks_disable_unprepare;
363 sdhci_get_of_property(pdev);
365 pm_runtime_get_noresume(&pdev->dev);
366 pm_runtime_set_active(&pdev->dev);
367 pm_runtime_enable(&pdev->dev);
368 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
369 pm_runtime_use_autosuspend(&pdev->dev);
371 /* HS200 is broken at this moment */
372 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
374 ret = sdhci_add_host(host);
376 goto pm_runtime_disable;
379 * When calling sdhci_runtime_suspend_host(), the sdhci layer makes
380 * the assumption that all the clocks of the controller are disabled.
381 * It means we can't get irq from it when it is runtime suspended.
382 * For that reason, it is not planned to wake-up on a card detect irq
383 * from the controller.
384 * If we want to use runtime PM and to be able to wake-up on card
385 * insertion, we have to use a GPIO for the card detection or we can
386 * use polling. Be aware that using polling will resume/suspend the
387 * controller between each attempt.
388 * Disable SDHCI_QUIRK_BROKEN_CARD_DETECTION to be sure nobody tries
389 * to enable polling via device tree with broken-cd property.
391 if (mmc_card_is_removable(host->mmc) &&
392 mmc_gpio_get_cd(host->mmc) < 0) {
393 host->mmc->caps |= MMC_CAP_NEEDS_POLL;
394 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
398 * If the device attached to the MMC bus is not removable, it is safer
399 * to set the Force Card Detect bit. People often don't connect the
400 * card detect signal and use this pin for another purpose. If the card
401 * detect pin is not muxed to SDHCI controller, a default value is
402 * used. This value can be different from a SoC revision to another
403 * one. Problems come when this default value is not card present. To
404 * avoid this case, if the device is non removable then the card
405 * detection procedure using the SDMCC_CD signal is bypassed.
406 * This bit is reset when a software reset for all command is performed
407 * so we need to implement our own reset function to set back this bit.
409 * WA: SAMA5D2 doesn't drive CMD if using CD GPIO line.
411 if ((host->mmc->caps & MMC_CAP_NONREMOVABLE)
412 || mmc_gpio_get_cd(host->mmc) >= 0)
413 sdhci_at91_set_force_card_detect(host);
415 pm_runtime_put_autosuspend(&pdev->dev);
420 pm_runtime_disable(&pdev->dev);
421 pm_runtime_set_suspended(&pdev->dev);
422 pm_runtime_put_noidle(&pdev->dev);
423 clocks_disable_unprepare:
424 clk_disable_unprepare(priv->gck);
425 clk_disable_unprepare(priv->mainck);
426 clk_disable_unprepare(priv->hclock);
428 sdhci_pltfm_free(pdev);
432 static int sdhci_at91_remove(struct platform_device *pdev)
434 struct sdhci_host *host = platform_get_drvdata(pdev);
435 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
436 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
437 struct clk *gck = priv->gck;
438 struct clk *hclock = priv->hclock;
439 struct clk *mainck = priv->mainck;
441 pm_runtime_get_sync(&pdev->dev);
442 pm_runtime_disable(&pdev->dev);
443 pm_runtime_put_noidle(&pdev->dev);
445 sdhci_pltfm_unregister(pdev);
447 clk_disable_unprepare(gck);
448 clk_disable_unprepare(hclock);
449 clk_disable_unprepare(mainck);
454 static struct platform_driver sdhci_at91_driver = {
456 .name = "sdhci-at91",
457 .of_match_table = sdhci_at91_dt_match,
458 .pm = &sdhci_at91_dev_pm_ops,
460 .probe = sdhci_at91_probe,
461 .remove = sdhci_at91_remove,
464 module_platform_driver(sdhci_at91_driver);
466 MODULE_DESCRIPTION("SDHCI driver for at91");
467 MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>");
468 MODULE_LICENSE("GPL v2");