1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Arasan Secure Digital Host Controller Interface.
4 * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>
5 * Copyright (c) 2012 Wind River Systems, Inc.
6 * Copyright (C) 2013 Pengutronix e.K.
7 * Copyright (C) 2013 Xilinx Inc.
9 * Based on sdhci-of-esdhc.c
11 * Copyright (c) 2007 Freescale Semiconductor, Inc.
12 * Copyright (c) 2009 MontaVista Software, Inc.
14 * Authors: Xiaobo Xie <X.Xie@freescale.com>
15 * Anton Vorontsov <avorontsov@ru.mvista.com>
18 #include <linux/clk-provider.h>
19 #include <linux/mfd/syscon.h>
20 #include <linux/module.h>
21 #include <linux/of_device.h>
22 #include <linux/phy/phy.h>
23 #include <linux/regmap.h>
25 #include <linux/firmware/xlnx-zynqmp.h>
28 #include "sdhci-cqhci.h"
29 #include "sdhci-pltfm.h"
31 #define SDHCI_ARASAN_VENDOR_REGISTER 0x78
33 #define SDHCI_ARASAN_ITAPDLY_REGISTER 0xF0F8
34 #define SDHCI_ARASAN_ITAPDLY_SEL_MASK 0xFF
36 #define SDHCI_ARASAN_OTAPDLY_REGISTER 0xF0FC
37 #define SDHCI_ARASAN_OTAPDLY_SEL_MASK 0x3F
39 #define SDHCI_ARASAN_CQE_BASE_ADDR 0x200
40 #define VENDOR_ENHANCED_STROBE BIT(0)
42 #define PHY_CLK_TOO_SLOW_HZ 400000
44 #define SDHCI_ITAPDLY_CHGWIN 0x200
45 #define SDHCI_ITAPDLY_ENABLE 0x100
46 #define SDHCI_OTAPDLY_ENABLE 0x40
48 /* Default settings for ZynqMP Clock Phases */
49 #define ZYNQMP_ICLK_PHASE {0, 63, 63, 0, 63, 0, 0, 183, 54, 0, 0}
50 #define ZYNQMP_OCLK_PHASE {0, 72, 60, 0, 60, 72, 135, 48, 72, 135, 0}
52 #define VERSAL_ICLK_PHASE {0, 132, 132, 0, 132, 0, 0, 162, 90, 0, 0}
53 #define VERSAL_OCLK_PHASE {0, 60, 48, 0, 48, 72, 90, 36, 60, 90, 0}
56 * On some SoCs the syscon area has a feature where the upper 16-bits of
57 * each 32-bit register act as a write mask for the lower 16-bits. This allows
58 * atomic updates of the register without locking. This macro is used on SoCs
59 * that have that feature.
61 #define HIWORD_UPDATE(val, mask, shift) \
62 ((val) << (shift) | (mask) << ((shift) + 16))
65 * struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map
67 * @reg: Offset within the syscon of the register containing this field
68 * @width: Number of bits for this field
69 * @shift: Bit offset within @reg of this field (or -1 if not avail)
71 struct sdhci_arasan_soc_ctl_field {
78 * struct sdhci_arasan_soc_ctl_map - Map in syscon to corecfg registers
80 * @baseclkfreq: Where to find corecfg_baseclkfreq
81 * @clockmultiplier: Where to find corecfg_clockmultiplier
82 * @support64b: Where to find SUPPORT64B bit
83 * @hiword_update: If true, use HIWORD_UPDATE to access the syscon
85 * It's up to the licensee of the Arsan IP block to make these available
86 * somewhere if needed. Presumably these will be scattered somewhere that's
87 * accessible via the syscon API.
89 struct sdhci_arasan_soc_ctl_map {
90 struct sdhci_arasan_soc_ctl_field baseclkfreq;
91 struct sdhci_arasan_soc_ctl_field clockmultiplier;
92 struct sdhci_arasan_soc_ctl_field support64b;
97 * struct sdhci_arasan_clk_ops - Clock Operations for Arasan SD controller
99 * @sdcardclk_ops: The output clock related operations
100 * @sampleclk_ops: The sample clock related operations
102 struct sdhci_arasan_clk_ops {
103 const struct clk_ops *sdcardclk_ops;
104 const struct clk_ops *sampleclk_ops;
108 * struct sdhci_arasan_clk_data - Arasan Controller Clock Data.
110 * @sdcardclk_hw: Struct for the clock we might provide to a PHY.
111 * @sdcardclk: Pointer to normal 'struct clock' for sdcardclk_hw.
112 * @sampleclk_hw: Struct for the clock we might provide to a PHY.
113 * @sampleclk: Pointer to normal 'struct clock' for sampleclk_hw.
114 * @clk_phase_in: Array of Input Clock Phase Delays for all speed modes
115 * @clk_phase_out: Array of Output Clock Phase Delays for all speed modes
116 * @set_clk_delays: Function pointer for setting Clock Delays
117 * @clk_of_data: Platform specific runtime clock data storage pointer
119 struct sdhci_arasan_clk_data {
120 struct clk_hw sdcardclk_hw;
121 struct clk *sdcardclk;
122 struct clk_hw sampleclk_hw;
123 struct clk *sampleclk;
124 int clk_phase_in[MMC_TIMING_MMC_HS400 + 1];
125 int clk_phase_out[MMC_TIMING_MMC_HS400 + 1];
126 void (*set_clk_delays)(struct sdhci_host *host);
131 * struct sdhci_arasan_data - Arasan Controller Data
133 * @host: Pointer to the main SDHCI host structure.
134 * @clk_ahb: Pointer to the AHB clock
135 * @phy: Pointer to the generic phy
136 * @is_phy_on: True if the PHY is on; false if not.
137 * @has_cqe: True if controller has command queuing engine.
138 * @clk_data: Struct for the Arasan Controller Clock Data.
139 * @clk_ops: Struct for the Arasan Controller Clock Operations.
140 * @soc_ctl_base: Pointer to regmap for syscon for soc_ctl registers.
141 * @soc_ctl_map: Map to get offsets into soc_ctl registers.
142 * @quirks: Arasan deviations from spec.
144 struct sdhci_arasan_data {
145 struct sdhci_host *host;
151 struct sdhci_arasan_clk_data clk_data;
152 const struct sdhci_arasan_clk_ops *clk_ops;
154 struct regmap *soc_ctl_base;
155 const struct sdhci_arasan_soc_ctl_map *soc_ctl_map;
158 /* Controller does not have CD wired and will not function normally without */
159 #define SDHCI_ARASAN_QUIRK_FORCE_CDTEST BIT(0)
160 /* Controller immediately reports SDHCI_CLOCK_INT_STABLE after enabling the
161 * internal clock even when the clock isn't stable */
162 #define SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE BIT(1)
164 * Some of the Arasan variations might not have timing requirements
165 * met at 25MHz for Default Speed mode, those controllers work at
168 #define SDHCI_ARASAN_QUIRK_CLOCK_25_BROKEN BIT(2)
171 struct sdhci_arasan_of_data {
172 const struct sdhci_arasan_soc_ctl_map *soc_ctl_map;
173 const struct sdhci_pltfm_data *pdata;
174 const struct sdhci_arasan_clk_ops *clk_ops;
177 static const struct sdhci_arasan_soc_ctl_map rk3399_soc_ctl_map = {
178 .baseclkfreq = { .reg = 0xf000, .width = 8, .shift = 8 },
179 .clockmultiplier = { .reg = 0xf02c, .width = 8, .shift = 0},
180 .hiword_update = true,
183 static const struct sdhci_arasan_soc_ctl_map intel_lgm_emmc_soc_ctl_map = {
184 .baseclkfreq = { .reg = 0xa0, .width = 8, .shift = 2 },
185 .clockmultiplier = { .reg = 0, .width = -1, .shift = -1 },
186 .hiword_update = false,
189 static const struct sdhci_arasan_soc_ctl_map intel_lgm_sdxc_soc_ctl_map = {
190 .baseclkfreq = { .reg = 0x80, .width = 8, .shift = 2 },
191 .clockmultiplier = { .reg = 0, .width = -1, .shift = -1 },
192 .hiword_update = false,
195 static const struct sdhci_arasan_soc_ctl_map intel_keembay_soc_ctl_map = {
196 .baseclkfreq = { .reg = 0x0, .width = 8, .shift = 14 },
197 .clockmultiplier = { .reg = 0x4, .width = 8, .shift = 14 },
198 .support64b = { .reg = 0x4, .width = 1, .shift = 24 },
199 .hiword_update = false,
203 * sdhci_arasan_syscon_write - Write to a field in soc_ctl registers
205 * @host: The sdhci_host
206 * @fld: The field to write to
207 * @val: The value to write
209 * This function allows writing to fields in sdhci_arasan_soc_ctl_map.
210 * Note that if a field is specified as not available (shift < 0) then
211 * this function will silently return an error code. It will be noisy
212 * and print errors for any other (unexpected) errors.
214 * Return: 0 on success and error value on error
216 static int sdhci_arasan_syscon_write(struct sdhci_host *host,
217 const struct sdhci_arasan_soc_ctl_field *fld,
220 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
221 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
222 struct regmap *soc_ctl_base = sdhci_arasan->soc_ctl_base;
224 u16 width = fld->width;
225 s16 shift = fld->shift;
229 * Silently return errors for shift < 0 so caller doesn't have
230 * to check for fields which are optional. For fields that
231 * are required then caller needs to do something special
237 if (sdhci_arasan->soc_ctl_map->hiword_update)
238 ret = regmap_write(soc_ctl_base, reg,
239 HIWORD_UPDATE(val, GENMASK(width, 0),
242 ret = regmap_update_bits(soc_ctl_base, reg,
243 GENMASK(shift + width, shift),
246 /* Yell about (unexpected) regmap errors */
248 pr_warn("%s: Regmap write fail: %d\n",
249 mmc_hostname(host->mmc), ret);
254 static void sdhci_arasan_set_clock(struct sdhci_host *host, unsigned int clock)
256 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
257 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
258 struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data;
259 bool ctrl_phy = false;
261 if (!IS_ERR(sdhci_arasan->phy)) {
262 if (!sdhci_arasan->is_phy_on && clock <= PHY_CLK_TOO_SLOW_HZ) {
264 * If PHY off, set clock to max speed and power PHY on.
266 * Although PHY docs apparently suggest power cycling
267 * when changing the clock the PHY doesn't like to be
268 * powered on while at low speeds like those used in ID
269 * mode. Even worse is powering the PHY on while the
272 * To workaround the PHY limitations, the best we can
273 * do is to power it on at a faster speed and then slam
274 * through low speeds without power cycling.
276 sdhci_set_clock(host, host->max_clk);
277 if (phy_power_on(sdhci_arasan->phy)) {
278 pr_err("%s: Cannot power on phy.\n",
279 mmc_hostname(host->mmc));
283 sdhci_arasan->is_phy_on = true;
286 * We'll now fall through to the below case with
287 * ctrl_phy = false (so we won't turn off/on). The
288 * sdhci_set_clock() will set the real clock.
290 } else if (clock > PHY_CLK_TOO_SLOW_HZ) {
292 * At higher clock speeds the PHY is fine being power
293 * cycled and docs say you _should_ power cycle when
294 * changing clock speeds.
300 if (ctrl_phy && sdhci_arasan->is_phy_on) {
301 phy_power_off(sdhci_arasan->phy);
302 sdhci_arasan->is_phy_on = false;
305 if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_CLOCK_25_BROKEN) {
307 * Some of the Arasan variations might not have timing
308 * requirements met at 25MHz for Default Speed mode,
309 * those controllers work at 19MHz instead.
311 if (clock == DEFAULT_SPEED_MAX_DTR)
312 clock = (DEFAULT_SPEED_MAX_DTR * 19) / 25;
315 /* Set the Input and Output Clock Phase Delays */
316 if (clk_data->set_clk_delays)
317 clk_data->set_clk_delays(host);
319 sdhci_set_clock(host, clock);
321 if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE)
323 * Some controllers immediately report SDHCI_CLOCK_INT_STABLE
324 * after enabling the clock even though the clock is not
325 * stable. Trying to use a clock without waiting here results
326 * in EILSEQ while detecting some older/slower cards. The
327 * chosen delay is the maximum delay from sdhci_set_clock.
332 if (phy_power_on(sdhci_arasan->phy)) {
333 pr_err("%s: Cannot power on phy.\n",
334 mmc_hostname(host->mmc));
338 sdhci_arasan->is_phy_on = true;
342 static void sdhci_arasan_hs400_enhanced_strobe(struct mmc_host *mmc,
346 struct sdhci_host *host = mmc_priv(mmc);
348 vendor = sdhci_readl(host, SDHCI_ARASAN_VENDOR_REGISTER);
349 if (ios->enhanced_strobe)
350 vendor |= VENDOR_ENHANCED_STROBE;
352 vendor &= ~VENDOR_ENHANCED_STROBE;
354 sdhci_writel(host, vendor, SDHCI_ARASAN_VENDOR_REGISTER);
357 static void sdhci_arasan_reset(struct sdhci_host *host, u8 mask)
360 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
361 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
363 sdhci_and_cqhci_reset(host, mask);
365 if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_FORCE_CDTEST) {
366 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
367 ctrl |= SDHCI_CTRL_CDTEST_INS | SDHCI_CTRL_CDTEST_EN;
368 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
372 static int sdhci_arasan_voltage_switch(struct mmc_host *mmc,
375 switch (ios->signal_voltage) {
376 case MMC_SIGNAL_VOLTAGE_180:
378 * Plese don't switch to 1V8 as arasan,5.1 doesn't
379 * actually refer to this setting to indicate the
380 * signal voltage and the state machine will be broken
381 * actually if we force to enable 1V8. That's something
382 * like broken quirk but we could work around here.
385 case MMC_SIGNAL_VOLTAGE_330:
386 case MMC_SIGNAL_VOLTAGE_120:
387 /* We don't support 3V3 and 1V2 */
394 static const struct sdhci_ops sdhci_arasan_ops = {
395 .set_clock = sdhci_arasan_set_clock,
396 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
397 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
398 .set_bus_width = sdhci_set_bus_width,
399 .reset = sdhci_arasan_reset,
400 .set_uhs_signaling = sdhci_set_uhs_signaling,
401 .set_power = sdhci_set_power_and_bus_voltage,
404 static u32 sdhci_arasan_cqhci_irq(struct sdhci_host *host, u32 intmask)
409 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
412 cqhci_irq(host->mmc, intmask, cmd_error, data_error);
417 static void sdhci_arasan_dumpregs(struct mmc_host *mmc)
419 sdhci_dumpregs(mmc_priv(mmc));
422 static void sdhci_arasan_cqe_enable(struct mmc_host *mmc)
424 struct sdhci_host *host = mmc_priv(mmc);
427 reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
428 while (reg & SDHCI_DATA_AVAILABLE) {
429 sdhci_readl(host, SDHCI_BUFFER);
430 reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
433 sdhci_cqe_enable(mmc);
436 static const struct cqhci_host_ops sdhci_arasan_cqhci_ops = {
437 .enable = sdhci_arasan_cqe_enable,
438 .disable = sdhci_cqe_disable,
439 .dumpregs = sdhci_arasan_dumpregs,
442 static const struct sdhci_ops sdhci_arasan_cqe_ops = {
443 .set_clock = sdhci_arasan_set_clock,
444 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
445 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
446 .set_bus_width = sdhci_set_bus_width,
447 .reset = sdhci_arasan_reset,
448 .set_uhs_signaling = sdhci_set_uhs_signaling,
449 .set_power = sdhci_set_power_and_bus_voltage,
450 .irq = sdhci_arasan_cqhci_irq,
453 static const struct sdhci_pltfm_data sdhci_arasan_cqe_pdata = {
454 .ops = &sdhci_arasan_cqe_ops,
455 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
456 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
457 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN,
460 #ifdef CONFIG_PM_SLEEP
462 * sdhci_arasan_suspend - Suspend method for the driver
463 * @dev: Address of the device structure
465 * Put the device in a low power state.
467 * Return: 0 on success and error value on error
469 static int sdhci_arasan_suspend(struct device *dev)
471 struct sdhci_host *host = dev_get_drvdata(dev);
472 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
473 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
476 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
477 mmc_retune_needed(host->mmc);
479 if (sdhci_arasan->has_cqe) {
480 ret = cqhci_suspend(host->mmc);
485 ret = sdhci_suspend_host(host);
489 if (!IS_ERR(sdhci_arasan->phy) && sdhci_arasan->is_phy_on) {
490 ret = phy_power_off(sdhci_arasan->phy);
492 dev_err(dev, "Cannot power off phy.\n");
493 if (sdhci_resume_host(host))
494 dev_err(dev, "Cannot resume host.\n");
498 sdhci_arasan->is_phy_on = false;
501 clk_disable(pltfm_host->clk);
502 clk_disable(sdhci_arasan->clk_ahb);
508 * sdhci_arasan_resume - Resume method for the driver
509 * @dev: Address of the device structure
511 * Resume operation after suspend
513 * Return: 0 on success and error value on error
515 static int sdhci_arasan_resume(struct device *dev)
517 struct sdhci_host *host = dev_get_drvdata(dev);
518 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
519 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
522 ret = clk_enable(sdhci_arasan->clk_ahb);
524 dev_err(dev, "Cannot enable AHB clock.\n");
528 ret = clk_enable(pltfm_host->clk);
530 dev_err(dev, "Cannot enable SD clock.\n");
534 if (!IS_ERR(sdhci_arasan->phy) && host->mmc->actual_clock) {
535 ret = phy_power_on(sdhci_arasan->phy);
537 dev_err(dev, "Cannot power on phy.\n");
540 sdhci_arasan->is_phy_on = true;
543 ret = sdhci_resume_host(host);
545 dev_err(dev, "Cannot resume host.\n");
549 if (sdhci_arasan->has_cqe)
550 return cqhci_resume(host->mmc);
554 #endif /* ! CONFIG_PM_SLEEP */
556 static SIMPLE_DEV_PM_OPS(sdhci_arasan_dev_pm_ops, sdhci_arasan_suspend,
557 sdhci_arasan_resume);
560 * sdhci_arasan_sdcardclk_recalc_rate - Return the card clock rate
562 * @hw: Pointer to the hardware clock structure.
563 * @parent_rate: The parent rate (should be rate of clk_xin).
565 * Return the current actual rate of the SD card clock. This can be used
566 * to communicate with out PHY.
568 * Return: The card clock rate.
570 static unsigned long sdhci_arasan_sdcardclk_recalc_rate(struct clk_hw *hw,
571 unsigned long parent_rate)
573 struct sdhci_arasan_clk_data *clk_data =
574 container_of(hw, struct sdhci_arasan_clk_data, sdcardclk_hw);
575 struct sdhci_arasan_data *sdhci_arasan =
576 container_of(clk_data, struct sdhci_arasan_data, clk_data);
577 struct sdhci_host *host = sdhci_arasan->host;
579 return host->mmc->actual_clock;
582 static const struct clk_ops arasan_sdcardclk_ops = {
583 .recalc_rate = sdhci_arasan_sdcardclk_recalc_rate,
587 * sdhci_arasan_sampleclk_recalc_rate - Return the sampling clock rate
589 * @hw: Pointer to the hardware clock structure.
590 * @parent_rate: The parent rate (should be rate of clk_xin).
592 * Return the current actual rate of the sampling clock. This can be used
593 * to communicate with out PHY.
595 * Return: The sample clock rate.
597 static unsigned long sdhci_arasan_sampleclk_recalc_rate(struct clk_hw *hw,
598 unsigned long parent_rate)
600 struct sdhci_arasan_clk_data *clk_data =
601 container_of(hw, struct sdhci_arasan_clk_data, sampleclk_hw);
602 struct sdhci_arasan_data *sdhci_arasan =
603 container_of(clk_data, struct sdhci_arasan_data, clk_data);
604 struct sdhci_host *host = sdhci_arasan->host;
606 return host->mmc->actual_clock;
609 static const struct clk_ops arasan_sampleclk_ops = {
610 .recalc_rate = sdhci_arasan_sampleclk_recalc_rate,
614 * sdhci_zynqmp_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
616 * @hw: Pointer to the hardware clock structure.
617 * @degrees: The clock phase shift between 0 - 359.
619 * Set the SD Output Clock Tap Delays for Output path
621 * Return: 0 on success and error value on error
623 static int sdhci_zynqmp_sdcardclk_set_phase(struct clk_hw *hw, int degrees)
625 struct sdhci_arasan_clk_data *clk_data =
626 container_of(hw, struct sdhci_arasan_clk_data, sdcardclk_hw);
627 struct sdhci_arasan_data *sdhci_arasan =
628 container_of(clk_data, struct sdhci_arasan_data, clk_data);
629 struct sdhci_host *host = sdhci_arasan->host;
630 const char *clk_name = clk_hw_get_name(hw);
631 u32 node_id = !strcmp(clk_name, "clk_out_sd0") ? NODE_SD_0 : NODE_SD_1;
632 u8 tap_delay, tap_max = 0;
635 /* This is applicable for SDHCI_SPEC_300 and above */
636 if (host->version < SDHCI_SPEC_300)
639 switch (host->timing) {
640 case MMC_TIMING_MMC_HS:
641 case MMC_TIMING_SD_HS:
642 case MMC_TIMING_UHS_SDR25:
643 case MMC_TIMING_UHS_DDR50:
644 case MMC_TIMING_MMC_DDR52:
645 /* For 50MHz clock, 30 Taps are available */
648 case MMC_TIMING_UHS_SDR50:
649 /* For 100MHz clock, 15 Taps are available */
652 case MMC_TIMING_UHS_SDR104:
653 case MMC_TIMING_MMC_HS200:
654 /* For 200MHz clock, 8 Taps are available */
660 tap_delay = (degrees * tap_max) / 360;
662 /* Set the Clock Phase */
663 ret = zynqmp_pm_set_sd_tapdelay(node_id, PM_TAPDELAY_OUTPUT, tap_delay);
665 pr_err("Error setting Output Tap Delay\n");
667 /* Release DLL Reset */
668 zynqmp_pm_sd_dll_reset(node_id, PM_DLL_RESET_RELEASE);
673 static const struct clk_ops zynqmp_sdcardclk_ops = {
674 .recalc_rate = sdhci_arasan_sdcardclk_recalc_rate,
675 .set_phase = sdhci_zynqmp_sdcardclk_set_phase,
679 * sdhci_zynqmp_sampleclk_set_phase - Set the SD Input Clock Tap Delays
681 * @hw: Pointer to the hardware clock structure.
682 * @degrees: The clock phase shift between 0 - 359.
684 * Set the SD Input Clock Tap Delays for Input path
686 * Return: 0 on success and error value on error
688 static int sdhci_zynqmp_sampleclk_set_phase(struct clk_hw *hw, int degrees)
690 struct sdhci_arasan_clk_data *clk_data =
691 container_of(hw, struct sdhci_arasan_clk_data, sampleclk_hw);
692 struct sdhci_arasan_data *sdhci_arasan =
693 container_of(clk_data, struct sdhci_arasan_data, clk_data);
694 struct sdhci_host *host = sdhci_arasan->host;
695 const char *clk_name = clk_hw_get_name(hw);
696 u32 node_id = !strcmp(clk_name, "clk_in_sd0") ? NODE_SD_0 : NODE_SD_1;
697 u8 tap_delay, tap_max = 0;
700 /* This is applicable for SDHCI_SPEC_300 and above */
701 if (host->version < SDHCI_SPEC_300)
704 /* Assert DLL Reset */
705 zynqmp_pm_sd_dll_reset(node_id, PM_DLL_RESET_ASSERT);
707 switch (host->timing) {
708 case MMC_TIMING_MMC_HS:
709 case MMC_TIMING_SD_HS:
710 case MMC_TIMING_UHS_SDR25:
711 case MMC_TIMING_UHS_DDR50:
712 case MMC_TIMING_MMC_DDR52:
713 /* For 50MHz clock, 120 Taps are available */
716 case MMC_TIMING_UHS_SDR50:
717 /* For 100MHz clock, 60 Taps are available */
720 case MMC_TIMING_UHS_SDR104:
721 case MMC_TIMING_MMC_HS200:
722 /* For 200MHz clock, 30 Taps are available */
728 tap_delay = (degrees * tap_max) / 360;
730 /* Set the Clock Phase */
731 ret = zynqmp_pm_set_sd_tapdelay(node_id, PM_TAPDELAY_INPUT, tap_delay);
733 pr_err("Error setting Input Tap Delay\n");
738 static const struct clk_ops zynqmp_sampleclk_ops = {
739 .recalc_rate = sdhci_arasan_sampleclk_recalc_rate,
740 .set_phase = sdhci_zynqmp_sampleclk_set_phase,
744 * sdhci_versal_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
746 * @hw: Pointer to the hardware clock structure.
747 * @degrees: The clock phase shift between 0 - 359.
749 * Set the SD Output Clock Tap Delays for Output path
751 * Return: 0 on success and error value on error
753 static int sdhci_versal_sdcardclk_set_phase(struct clk_hw *hw, int degrees)
755 struct sdhci_arasan_clk_data *clk_data =
756 container_of(hw, struct sdhci_arasan_clk_data, sdcardclk_hw);
757 struct sdhci_arasan_data *sdhci_arasan =
758 container_of(clk_data, struct sdhci_arasan_data, clk_data);
759 struct sdhci_host *host = sdhci_arasan->host;
760 u8 tap_delay, tap_max = 0;
762 /* This is applicable for SDHCI_SPEC_300 and above */
763 if (host->version < SDHCI_SPEC_300)
766 switch (host->timing) {
767 case MMC_TIMING_MMC_HS:
768 case MMC_TIMING_SD_HS:
769 case MMC_TIMING_UHS_SDR25:
770 case MMC_TIMING_UHS_DDR50:
771 case MMC_TIMING_MMC_DDR52:
772 /* For 50MHz clock, 30 Taps are available */
775 case MMC_TIMING_UHS_SDR50:
776 /* For 100MHz clock, 15 Taps are available */
779 case MMC_TIMING_UHS_SDR104:
780 case MMC_TIMING_MMC_HS200:
781 /* For 200MHz clock, 8 Taps are available */
787 tap_delay = (degrees * tap_max) / 360;
789 /* Set the Clock Phase */
793 regval = sdhci_readl(host, SDHCI_ARASAN_OTAPDLY_REGISTER);
794 regval |= SDHCI_OTAPDLY_ENABLE;
795 sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
796 regval &= ~SDHCI_ARASAN_OTAPDLY_SEL_MASK;
798 sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
804 static const struct clk_ops versal_sdcardclk_ops = {
805 .recalc_rate = sdhci_arasan_sdcardclk_recalc_rate,
806 .set_phase = sdhci_versal_sdcardclk_set_phase,
810 * sdhci_versal_sampleclk_set_phase - Set the SD Input Clock Tap Delays
812 * @hw: Pointer to the hardware clock structure.
813 * @degrees: The clock phase shift between 0 - 359.
815 * Set the SD Input Clock Tap Delays for Input path
817 * Return: 0 on success and error value on error
819 static int sdhci_versal_sampleclk_set_phase(struct clk_hw *hw, int degrees)
821 struct sdhci_arasan_clk_data *clk_data =
822 container_of(hw, struct sdhci_arasan_clk_data, sampleclk_hw);
823 struct sdhci_arasan_data *sdhci_arasan =
824 container_of(clk_data, struct sdhci_arasan_data, clk_data);
825 struct sdhci_host *host = sdhci_arasan->host;
826 u8 tap_delay, tap_max = 0;
828 /* This is applicable for SDHCI_SPEC_300 and above */
829 if (host->version < SDHCI_SPEC_300)
832 switch (host->timing) {
833 case MMC_TIMING_MMC_HS:
834 case MMC_TIMING_SD_HS:
835 case MMC_TIMING_UHS_SDR25:
836 case MMC_TIMING_UHS_DDR50:
837 case MMC_TIMING_MMC_DDR52:
838 /* For 50MHz clock, 120 Taps are available */
841 case MMC_TIMING_UHS_SDR50:
842 /* For 100MHz clock, 60 Taps are available */
845 case MMC_TIMING_UHS_SDR104:
846 case MMC_TIMING_MMC_HS200:
847 /* For 200MHz clock, 30 Taps are available */
853 tap_delay = (degrees * tap_max) / 360;
855 /* Set the Clock Phase */
859 regval = sdhci_readl(host, SDHCI_ARASAN_ITAPDLY_REGISTER);
860 regval |= SDHCI_ITAPDLY_CHGWIN;
861 sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
862 regval |= SDHCI_ITAPDLY_ENABLE;
863 sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
864 regval &= ~SDHCI_ARASAN_ITAPDLY_SEL_MASK;
866 sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
867 regval &= ~SDHCI_ITAPDLY_CHGWIN;
868 sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
874 static const struct clk_ops versal_sampleclk_ops = {
875 .recalc_rate = sdhci_arasan_sampleclk_recalc_rate,
876 .set_phase = sdhci_versal_sampleclk_set_phase,
879 static void arasan_zynqmp_dll_reset(struct sdhci_host *host, u32 deviceid)
883 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
884 clk &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_INT_EN);
885 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
887 /* Issue DLL Reset */
888 zynqmp_pm_sd_dll_reset(deviceid, PM_DLL_RESET_PULSE);
890 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
892 sdhci_enable_clk(host, clk);
895 static int arasan_zynqmp_execute_tuning(struct mmc_host *mmc, u32 opcode)
897 struct sdhci_host *host = mmc_priv(mmc);
898 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
899 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
900 struct clk_hw *hw = &sdhci_arasan->clk_data.sdcardclk_hw;
901 const char *clk_name = clk_hw_get_name(hw);
902 u32 device_id = !strcmp(clk_name, "clk_out_sd0") ? NODE_SD_0 :
906 arasan_zynqmp_dll_reset(host, device_id);
908 err = sdhci_execute_tuning(mmc, opcode);
912 arasan_zynqmp_dll_reset(host, device_id);
918 * sdhci_arasan_update_clockmultiplier - Set corecfg_clockmultiplier
920 * @host: The sdhci_host
921 * @value: The value to write
923 * The corecfg_clockmultiplier is supposed to contain clock multiplier
924 * value of programmable clock generator.
927 * - Many existing devices don't seem to do this and work fine. To keep
928 * compatibility for old hardware where the device tree doesn't provide a
929 * register map, this function is a noop if a soc_ctl_map hasn't been provided
931 * - The value of corecfg_clockmultiplier should sync with that of corresponding
932 * value reading from sdhci_capability_register. So this function is called
933 * once at probe time and never called again.
935 static void sdhci_arasan_update_clockmultiplier(struct sdhci_host *host,
938 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
939 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
940 const struct sdhci_arasan_soc_ctl_map *soc_ctl_map =
941 sdhci_arasan->soc_ctl_map;
943 /* Having a map is optional */
947 /* If we have a map, we expect to have a syscon */
948 if (!sdhci_arasan->soc_ctl_base) {
949 pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",
950 mmc_hostname(host->mmc));
954 sdhci_arasan_syscon_write(host, &soc_ctl_map->clockmultiplier, value);
958 * sdhci_arasan_update_baseclkfreq - Set corecfg_baseclkfreq
960 * @host: The sdhci_host
962 * The corecfg_baseclkfreq is supposed to contain the MHz of clk_xin. This
963 * function can be used to make that happen.
966 * - Many existing devices don't seem to do this and work fine. To keep
967 * compatibility for old hardware where the device tree doesn't provide a
968 * register map, this function is a noop if a soc_ctl_map hasn't been provided
970 * - It's assumed that clk_xin is not dynamic and that we use the SDHCI divider
971 * to achieve lower clock rates. That means that this function is called once
972 * at probe time and never called again.
974 static void sdhci_arasan_update_baseclkfreq(struct sdhci_host *host)
976 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
977 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
978 const struct sdhci_arasan_soc_ctl_map *soc_ctl_map =
979 sdhci_arasan->soc_ctl_map;
980 u32 mhz = DIV_ROUND_CLOSEST(clk_get_rate(pltfm_host->clk), 1000000);
982 /* Having a map is optional */
986 /* If we have a map, we expect to have a syscon */
987 if (!sdhci_arasan->soc_ctl_base) {
988 pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",
989 mmc_hostname(host->mmc));
993 sdhci_arasan_syscon_write(host, &soc_ctl_map->baseclkfreq, mhz);
996 static void sdhci_arasan_set_clk_delays(struct sdhci_host *host)
998 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
999 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
1000 struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data;
1002 clk_set_phase(clk_data->sampleclk,
1003 clk_data->clk_phase_in[host->timing]);
1004 clk_set_phase(clk_data->sdcardclk,
1005 clk_data->clk_phase_out[host->timing]);
1008 static void arasan_dt_read_clk_phase(struct device *dev,
1009 struct sdhci_arasan_clk_data *clk_data,
1010 unsigned int timing, const char *prop)
1012 struct device_node *np = dev->of_node;
1014 int clk_phase[2] = {0};
1017 * Read Tap Delay values from DT, if the DT does not contain the
1018 * Tap Values then use the pre-defined values.
1020 if (of_property_read_variable_u32_array(np, prop, &clk_phase[0],
1022 dev_dbg(dev, "Using predefined clock phase for %s = %d %d\n",
1023 prop, clk_data->clk_phase_in[timing],
1024 clk_data->clk_phase_out[timing]);
1028 /* The values read are Input and Output Clock Delays in order */
1029 clk_data->clk_phase_in[timing] = clk_phase[0];
1030 clk_data->clk_phase_out[timing] = clk_phase[1];
1034 * arasan_dt_parse_clk_phases - Read Clock Delay values from DT
1036 * @dev: Pointer to our struct device.
1037 * @clk_data: Pointer to the Clock Data structure
1039 * Called at initialization to parse the values of Clock Delays.
1041 static void arasan_dt_parse_clk_phases(struct device *dev,
1042 struct sdhci_arasan_clk_data *clk_data)
1048 * This has been kept as a pointer and is assigned a function here.
1049 * So that different controller variants can assign their own handling
1052 clk_data->set_clk_delays = sdhci_arasan_set_clk_delays;
1054 if (of_device_is_compatible(dev->of_node, "xlnx,zynqmp-8.9a")) {
1055 u32 zynqmp_iclk_phase[MMC_TIMING_MMC_HS400 + 1] =
1057 u32 zynqmp_oclk_phase[MMC_TIMING_MMC_HS400 + 1] =
1060 of_property_read_u32(dev->of_node, "xlnx,mio-bank", &mio_bank);
1061 if (mio_bank == 2) {
1062 zynqmp_oclk_phase[MMC_TIMING_UHS_SDR104] = 90;
1063 zynqmp_oclk_phase[MMC_TIMING_MMC_HS200] = 90;
1066 for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
1067 clk_data->clk_phase_in[i] = zynqmp_iclk_phase[i];
1068 clk_data->clk_phase_out[i] = zynqmp_oclk_phase[i];
1072 if (of_device_is_compatible(dev->of_node, "xlnx,versal-8.9a")) {
1073 u32 versal_iclk_phase[MMC_TIMING_MMC_HS400 + 1] =
1075 u32 versal_oclk_phase[MMC_TIMING_MMC_HS400 + 1] =
1078 for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
1079 clk_data->clk_phase_in[i] = versal_iclk_phase[i];
1080 clk_data->clk_phase_out[i] = versal_oclk_phase[i];
1084 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_LEGACY,
1085 "clk-phase-legacy");
1086 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_HS,
1087 "clk-phase-mmc-hs");
1088 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_SD_HS,
1090 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR12,
1091 "clk-phase-uhs-sdr12");
1092 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR25,
1093 "clk-phase-uhs-sdr25");
1094 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR50,
1095 "clk-phase-uhs-sdr50");
1096 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR104,
1097 "clk-phase-uhs-sdr104");
1098 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_DDR50,
1099 "clk-phase-uhs-ddr50");
1100 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_DDR52,
1101 "clk-phase-mmc-ddr52");
1102 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_HS200,
1103 "clk-phase-mmc-hs200");
1104 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_HS400,
1105 "clk-phase-mmc-hs400");
1108 static const struct sdhci_pltfm_data sdhci_arasan_pdata = {
1109 .ops = &sdhci_arasan_ops,
1110 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
1111 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1112 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
1113 SDHCI_QUIRK2_STOP_WITH_TC,
1116 static const struct sdhci_arasan_clk_ops arasan_clk_ops = {
1117 .sdcardclk_ops = &arasan_sdcardclk_ops,
1118 .sampleclk_ops = &arasan_sampleclk_ops,
1121 static struct sdhci_arasan_of_data sdhci_arasan_generic_data = {
1122 .pdata = &sdhci_arasan_pdata,
1123 .clk_ops = &arasan_clk_ops,
1126 static const struct sdhci_pltfm_data sdhci_keembay_emmc_pdata = {
1127 .ops = &sdhci_arasan_cqe_ops,
1128 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
1129 SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
1130 SDHCI_QUIRK_NO_LED |
1131 SDHCI_QUIRK_32BIT_DMA_ADDR |
1132 SDHCI_QUIRK_32BIT_DMA_SIZE |
1133 SDHCI_QUIRK_32BIT_ADMA_SIZE,
1134 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1135 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
1136 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
1137 SDHCI_QUIRK2_STOP_WITH_TC |
1138 SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
1141 static const struct sdhci_pltfm_data sdhci_keembay_sd_pdata = {
1142 .ops = &sdhci_arasan_ops,
1143 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
1144 SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
1145 SDHCI_QUIRK_NO_LED |
1146 SDHCI_QUIRK_32BIT_DMA_ADDR |
1147 SDHCI_QUIRK_32BIT_DMA_SIZE |
1148 SDHCI_QUIRK_32BIT_ADMA_SIZE,
1149 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1150 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
1151 SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
1152 SDHCI_QUIRK2_STOP_WITH_TC |
1153 SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
1156 static const struct sdhci_pltfm_data sdhci_keembay_sdio_pdata = {
1157 .ops = &sdhci_arasan_ops,
1158 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
1159 SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
1160 SDHCI_QUIRK_NO_LED |
1161 SDHCI_QUIRK_32BIT_DMA_ADDR |
1162 SDHCI_QUIRK_32BIT_DMA_SIZE |
1163 SDHCI_QUIRK_32BIT_ADMA_SIZE,
1164 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1165 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
1166 SDHCI_QUIRK2_HOST_OFF_CARD_ON |
1167 SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
1170 static struct sdhci_arasan_of_data sdhci_arasan_rk3399_data = {
1171 .soc_ctl_map = &rk3399_soc_ctl_map,
1172 .pdata = &sdhci_arasan_cqe_pdata,
1173 .clk_ops = &arasan_clk_ops,
1176 static struct sdhci_arasan_of_data intel_lgm_emmc_data = {
1177 .soc_ctl_map = &intel_lgm_emmc_soc_ctl_map,
1178 .pdata = &sdhci_arasan_cqe_pdata,
1179 .clk_ops = &arasan_clk_ops,
1182 static struct sdhci_arasan_of_data intel_lgm_sdxc_data = {
1183 .soc_ctl_map = &intel_lgm_sdxc_soc_ctl_map,
1184 .pdata = &sdhci_arasan_cqe_pdata,
1185 .clk_ops = &arasan_clk_ops,
1188 static const struct sdhci_pltfm_data sdhci_arasan_zynqmp_pdata = {
1189 .ops = &sdhci_arasan_ops,
1190 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1191 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
1192 SDHCI_QUIRK2_STOP_WITH_TC,
1195 static const struct sdhci_arasan_clk_ops zynqmp_clk_ops = {
1196 .sdcardclk_ops = &zynqmp_sdcardclk_ops,
1197 .sampleclk_ops = &zynqmp_sampleclk_ops,
1200 static struct sdhci_arasan_of_data sdhci_arasan_zynqmp_data = {
1201 .pdata = &sdhci_arasan_zynqmp_pdata,
1202 .clk_ops = &zynqmp_clk_ops,
1205 static const struct sdhci_arasan_clk_ops versal_clk_ops = {
1206 .sdcardclk_ops = &versal_sdcardclk_ops,
1207 .sampleclk_ops = &versal_sampleclk_ops,
1210 static struct sdhci_arasan_of_data sdhci_arasan_versal_data = {
1211 .pdata = &sdhci_arasan_zynqmp_pdata,
1212 .clk_ops = &versal_clk_ops,
1215 static struct sdhci_arasan_of_data intel_keembay_emmc_data = {
1216 .soc_ctl_map = &intel_keembay_soc_ctl_map,
1217 .pdata = &sdhci_keembay_emmc_pdata,
1218 .clk_ops = &arasan_clk_ops,
1221 static struct sdhci_arasan_of_data intel_keembay_sd_data = {
1222 .soc_ctl_map = &intel_keembay_soc_ctl_map,
1223 .pdata = &sdhci_keembay_sd_pdata,
1224 .clk_ops = &arasan_clk_ops,
1227 static struct sdhci_arasan_of_data intel_keembay_sdio_data = {
1228 .soc_ctl_map = &intel_keembay_soc_ctl_map,
1229 .pdata = &sdhci_keembay_sdio_pdata,
1230 .clk_ops = &arasan_clk_ops,
1233 static const struct of_device_id sdhci_arasan_of_match[] = {
1234 /* SoC-specific compatible strings w/ soc_ctl_map */
1236 .compatible = "rockchip,rk3399-sdhci-5.1",
1237 .data = &sdhci_arasan_rk3399_data,
1240 .compatible = "intel,lgm-sdhci-5.1-emmc",
1241 .data = &intel_lgm_emmc_data,
1244 .compatible = "intel,lgm-sdhci-5.1-sdxc",
1245 .data = &intel_lgm_sdxc_data,
1248 .compatible = "intel,keembay-sdhci-5.1-emmc",
1249 .data = &intel_keembay_emmc_data,
1252 .compatible = "intel,keembay-sdhci-5.1-sd",
1253 .data = &intel_keembay_sd_data,
1256 .compatible = "intel,keembay-sdhci-5.1-sdio",
1257 .data = &intel_keembay_sdio_data,
1259 /* Generic compatible below here */
1261 .compatible = "arasan,sdhci-8.9a",
1262 .data = &sdhci_arasan_generic_data,
1265 .compatible = "arasan,sdhci-5.1",
1266 .data = &sdhci_arasan_generic_data,
1269 .compatible = "arasan,sdhci-4.9a",
1270 .data = &sdhci_arasan_generic_data,
1273 .compatible = "xlnx,zynqmp-8.9a",
1274 .data = &sdhci_arasan_zynqmp_data,
1277 .compatible = "xlnx,versal-8.9a",
1278 .data = &sdhci_arasan_versal_data,
1282 MODULE_DEVICE_TABLE(of, sdhci_arasan_of_match);
1285 * sdhci_arasan_register_sdcardclk - Register the sdcardclk for a PHY to use
1287 * @sdhci_arasan: Our private data structure.
1288 * @clk_xin: Pointer to the functional clock
1289 * @dev: Pointer to our struct device.
1291 * Some PHY devices need to know what the actual card clock is. In order for
1292 * them to find out, we'll provide a clock through the common clock framework
1293 * for them to query.
1295 * Return: 0 on success and error value on error
1298 sdhci_arasan_register_sdcardclk(struct sdhci_arasan_data *sdhci_arasan,
1299 struct clk *clk_xin,
1302 struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data;
1303 struct device_node *np = dev->of_node;
1304 struct clk_init_data sdcardclk_init;
1305 const char *parent_clk_name;
1308 ret = of_property_read_string_index(np, "clock-output-names", 0,
1309 &sdcardclk_init.name);
1311 dev_err(dev, "DT has #clock-cells but no clock-output-names\n");
1315 parent_clk_name = __clk_get_name(clk_xin);
1316 sdcardclk_init.parent_names = &parent_clk_name;
1317 sdcardclk_init.num_parents = 1;
1318 sdcardclk_init.flags = CLK_GET_RATE_NOCACHE;
1319 sdcardclk_init.ops = sdhci_arasan->clk_ops->sdcardclk_ops;
1321 clk_data->sdcardclk_hw.init = &sdcardclk_init;
1322 clk_data->sdcardclk =
1323 devm_clk_register(dev, &clk_data->sdcardclk_hw);
1324 if (IS_ERR(clk_data->sdcardclk))
1325 return PTR_ERR(clk_data->sdcardclk);
1326 clk_data->sdcardclk_hw.init = NULL;
1328 ret = of_clk_add_provider(np, of_clk_src_simple_get,
1329 clk_data->sdcardclk);
1331 dev_err(dev, "Failed to add sdcard clock provider\n");
1337 * sdhci_arasan_register_sampleclk - Register the sampleclk for a PHY to use
1339 * @sdhci_arasan: Our private data structure.
1340 * @clk_xin: Pointer to the functional clock
1341 * @dev: Pointer to our struct device.
1343 * Some PHY devices need to know what the actual card clock is. In order for
1344 * them to find out, we'll provide a clock through the common clock framework
1345 * for them to query.
1347 * Return: 0 on success and error value on error
1350 sdhci_arasan_register_sampleclk(struct sdhci_arasan_data *sdhci_arasan,
1351 struct clk *clk_xin,
1354 struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data;
1355 struct device_node *np = dev->of_node;
1356 struct clk_init_data sampleclk_init;
1357 const char *parent_clk_name;
1360 ret = of_property_read_string_index(np, "clock-output-names", 1,
1361 &sampleclk_init.name);
1363 dev_err(dev, "DT has #clock-cells but no clock-output-names\n");
1367 parent_clk_name = __clk_get_name(clk_xin);
1368 sampleclk_init.parent_names = &parent_clk_name;
1369 sampleclk_init.num_parents = 1;
1370 sampleclk_init.flags = CLK_GET_RATE_NOCACHE;
1371 sampleclk_init.ops = sdhci_arasan->clk_ops->sampleclk_ops;
1373 clk_data->sampleclk_hw.init = &sampleclk_init;
1374 clk_data->sampleclk =
1375 devm_clk_register(dev, &clk_data->sampleclk_hw);
1376 if (IS_ERR(clk_data->sampleclk))
1377 return PTR_ERR(clk_data->sampleclk);
1378 clk_data->sampleclk_hw.init = NULL;
1380 ret = of_clk_add_provider(np, of_clk_src_simple_get,
1381 clk_data->sampleclk);
1383 dev_err(dev, "Failed to add sample clock provider\n");
1389 * sdhci_arasan_unregister_sdclk - Undoes sdhci_arasan_register_sdclk()
1391 * @dev: Pointer to our struct device.
1393 * Should be called any time we're exiting and sdhci_arasan_register_sdclk()
1396 static void sdhci_arasan_unregister_sdclk(struct device *dev)
1398 struct device_node *np = dev->of_node;
1400 if (!of_find_property(np, "#clock-cells", NULL))
1403 of_clk_del_provider(dev->of_node);
1407 * sdhci_arasan_update_support64b - Set SUPPORT_64B (64-bit System Bus Support)
1409 * This should be set based on the System Address Bus.
1410 * 0: the Core supports only 32-bit System Address Bus.
1411 * 1: the Core supports 64-bit System Address Bus.
1414 * - For Keem Bay, it is required to clear this bit. Its default value is 1'b1.
1415 * Keem Bay does not support 64-bit access.
1417 * @host: The sdhci_host
1418 * @value: The value to write
1420 static void sdhci_arasan_update_support64b(struct sdhci_host *host, u32 value)
1422 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1423 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
1424 const struct sdhci_arasan_soc_ctl_map *soc_ctl_map =
1425 sdhci_arasan->soc_ctl_map;
1427 /* Having a map is optional */
1431 /* If we have a map, we expect to have a syscon */
1432 if (!sdhci_arasan->soc_ctl_base) {
1433 pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",
1434 mmc_hostname(host->mmc));
1438 sdhci_arasan_syscon_write(host, &soc_ctl_map->support64b, value);
1442 * sdhci_arasan_register_sdclk - Register the sdcardclk for a PHY to use
1444 * @sdhci_arasan: Our private data structure.
1445 * @clk_xin: Pointer to the functional clock
1446 * @dev: Pointer to our struct device.
1448 * Some PHY devices need to know what the actual card clock is. In order for
1449 * them to find out, we'll provide a clock through the common clock framework
1450 * for them to query.
1452 * Note: without seriously re-architecting SDHCI's clock code and testing on
1453 * all platforms, there's no way to create a totally beautiful clock here
1454 * with all clock ops implemented. Instead, we'll just create a clock that can
1455 * be queried and set the CLK_GET_RATE_NOCACHE attribute to tell common clock
1456 * framework that we're doing things behind its back. This should be sufficient
1457 * to create nice clean device tree bindings and later (if needed) we can try
1458 * re-architecting SDHCI if we see some benefit to it.
1460 * Return: 0 on success and error value on error
1462 static int sdhci_arasan_register_sdclk(struct sdhci_arasan_data *sdhci_arasan,
1463 struct clk *clk_xin,
1466 struct device_node *np = dev->of_node;
1470 /* Providing a clock to the PHY is optional; no error if missing */
1471 if (of_property_read_u32(np, "#clock-cells", &num_clks) < 0)
1474 ret = sdhci_arasan_register_sdcardclk(sdhci_arasan, clk_xin, dev);
1479 ret = sdhci_arasan_register_sampleclk(sdhci_arasan, clk_xin,
1482 sdhci_arasan_unregister_sdclk(dev);
1490 static int sdhci_arasan_add_host(struct sdhci_arasan_data *sdhci_arasan)
1492 struct sdhci_host *host = sdhci_arasan->host;
1493 struct cqhci_host *cq_host;
1497 if (!sdhci_arasan->has_cqe)
1498 return sdhci_add_host(host);
1500 ret = sdhci_setup_host(host);
1504 cq_host = devm_kzalloc(host->mmc->parent,
1505 sizeof(*cq_host), GFP_KERNEL);
1511 cq_host->mmio = host->ioaddr + SDHCI_ARASAN_CQE_BASE_ADDR;
1512 cq_host->ops = &sdhci_arasan_cqhci_ops;
1514 dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
1516 cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
1518 ret = cqhci_init(cq_host, host->mmc, dma64);
1522 ret = __sdhci_add_host(host);
1529 sdhci_cleanup_host(host);
1533 static int sdhci_arasan_probe(struct platform_device *pdev)
1536 const struct of_device_id *match;
1537 struct device_node *node;
1538 struct clk *clk_xin;
1539 struct sdhci_host *host;
1540 struct sdhci_pltfm_host *pltfm_host;
1541 struct sdhci_arasan_data *sdhci_arasan;
1542 struct device_node *np = pdev->dev.of_node;
1543 const struct sdhci_arasan_of_data *data;
1545 match = of_match_node(sdhci_arasan_of_match, pdev->dev.of_node);
1547 host = sdhci_pltfm_init(pdev, data->pdata, sizeof(*sdhci_arasan));
1550 return PTR_ERR(host);
1552 pltfm_host = sdhci_priv(host);
1553 sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
1554 sdhci_arasan->host = host;
1556 sdhci_arasan->soc_ctl_map = data->soc_ctl_map;
1557 sdhci_arasan->clk_ops = data->clk_ops;
1559 node = of_parse_phandle(pdev->dev.of_node, "arasan,soc-ctl-syscon", 0);
1561 sdhci_arasan->soc_ctl_base = syscon_node_to_regmap(node);
1564 if (IS_ERR(sdhci_arasan->soc_ctl_base)) {
1565 ret = dev_err_probe(&pdev->dev,
1566 PTR_ERR(sdhci_arasan->soc_ctl_base),
1567 "Can't get syscon\n");
1568 goto err_pltfm_free;
1572 sdhci_arasan->clk_ahb = devm_clk_get(&pdev->dev, "clk_ahb");
1573 if (IS_ERR(sdhci_arasan->clk_ahb)) {
1574 dev_err(&pdev->dev, "clk_ahb clock not found.\n");
1575 ret = PTR_ERR(sdhci_arasan->clk_ahb);
1576 goto err_pltfm_free;
1579 clk_xin = devm_clk_get(&pdev->dev, "clk_xin");
1580 if (IS_ERR(clk_xin)) {
1581 dev_err(&pdev->dev, "clk_xin clock not found.\n");
1582 ret = PTR_ERR(clk_xin);
1583 goto err_pltfm_free;
1586 ret = clk_prepare_enable(sdhci_arasan->clk_ahb);
1588 dev_err(&pdev->dev, "Unable to enable AHB clock.\n");
1589 goto err_pltfm_free;
1592 ret = clk_prepare_enable(clk_xin);
1594 dev_err(&pdev->dev, "Unable to enable SD clock.\n");
1598 sdhci_get_of_property(pdev);
1600 if (of_property_read_bool(np, "xlnx,fails-without-test-cd"))
1601 sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_FORCE_CDTEST;
1603 if (of_property_read_bool(np, "xlnx,int-clock-stable-broken"))
1604 sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE;
1606 pltfm_host->clk = clk_xin;
1608 if (of_device_is_compatible(pdev->dev.of_node,
1609 "rockchip,rk3399-sdhci-5.1"))
1610 sdhci_arasan_update_clockmultiplier(host, 0x0);
1612 if (of_device_is_compatible(np, "intel,keembay-sdhci-5.1-emmc") ||
1613 of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sd") ||
1614 of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sdio")) {
1615 sdhci_arasan_update_clockmultiplier(host, 0x0);
1616 sdhci_arasan_update_support64b(host, 0x0);
1618 host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
1621 sdhci_arasan_update_baseclkfreq(host);
1623 ret = sdhci_arasan_register_sdclk(sdhci_arasan, clk_xin, &pdev->dev);
1625 goto clk_disable_all;
1627 if (of_device_is_compatible(np, "xlnx,zynqmp-8.9a")) {
1628 host->mmc_host_ops.execute_tuning =
1629 arasan_zynqmp_execute_tuning;
1631 sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_CLOCK_25_BROKEN;
1634 arasan_dt_parse_clk_phases(&pdev->dev, &sdhci_arasan->clk_data);
1636 ret = mmc_of_parse(host->mmc);
1638 if (ret != -EPROBE_DEFER)
1639 dev_err(&pdev->dev, "parsing dt failed (%d)\n", ret);
1643 sdhci_arasan->phy = ERR_PTR(-ENODEV);
1644 if (of_device_is_compatible(pdev->dev.of_node,
1645 "arasan,sdhci-5.1")) {
1646 sdhci_arasan->phy = devm_phy_get(&pdev->dev,
1648 if (IS_ERR(sdhci_arasan->phy)) {
1649 ret = PTR_ERR(sdhci_arasan->phy);
1650 dev_err(&pdev->dev, "No phy for arasan,sdhci-5.1.\n");
1654 ret = phy_init(sdhci_arasan->phy);
1656 dev_err(&pdev->dev, "phy_init err.\n");
1660 host->mmc_host_ops.hs400_enhanced_strobe =
1661 sdhci_arasan_hs400_enhanced_strobe;
1662 host->mmc_host_ops.start_signal_voltage_switch =
1663 sdhci_arasan_voltage_switch;
1664 sdhci_arasan->has_cqe = true;
1665 host->mmc->caps2 |= MMC_CAP2_CQE;
1667 if (!of_property_read_bool(np, "disable-cqe-dcmd"))
1668 host->mmc->caps2 |= MMC_CAP2_CQE_DCMD;
1671 ret = sdhci_arasan_add_host(sdhci_arasan);
1678 if (!IS_ERR(sdhci_arasan->phy))
1679 phy_exit(sdhci_arasan->phy);
1681 sdhci_arasan_unregister_sdclk(&pdev->dev);
1683 clk_disable_unprepare(clk_xin);
1685 clk_disable_unprepare(sdhci_arasan->clk_ahb);
1687 sdhci_pltfm_free(pdev);
1691 static int sdhci_arasan_remove(struct platform_device *pdev)
1694 struct sdhci_host *host = platform_get_drvdata(pdev);
1695 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1696 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
1697 struct clk *clk_ahb = sdhci_arasan->clk_ahb;
1699 if (!IS_ERR(sdhci_arasan->phy)) {
1700 if (sdhci_arasan->is_phy_on)
1701 phy_power_off(sdhci_arasan->phy);
1702 phy_exit(sdhci_arasan->phy);
1705 sdhci_arasan_unregister_sdclk(&pdev->dev);
1707 ret = sdhci_pltfm_unregister(pdev);
1709 clk_disable_unprepare(clk_ahb);
1714 static struct platform_driver sdhci_arasan_driver = {
1716 .name = "sdhci-arasan",
1717 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1718 .of_match_table = sdhci_arasan_of_match,
1719 .pm = &sdhci_arasan_dev_pm_ops,
1721 .probe = sdhci_arasan_probe,
1722 .remove = sdhci_arasan_remove,
1725 module_platform_driver(sdhci_arasan_driver);
1727 MODULE_DESCRIPTION("Driver for the Arasan SDHCI Controller");
1728 MODULE_AUTHOR("Soeren Brinkmann <soren.brinkmann@xilinx.com>");
1729 MODULE_LICENSE("GPL");