GNU Linux-libre 4.14.259-gnu1
[releases.git] / drivers / mmc / host / sdhci-msm.c
1 /*
2  * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver
3  *
4  * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 and
8  * only version 2 as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  */
16
17 #include <linux/module.h>
18 #include <linux/of_device.h>
19 #include <linux/delay.h>
20 #include <linux/mmc/mmc.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/slab.h>
23 #include <linux/iopoll.h>
24
25 #include "sdhci-pltfm.h"
26
27 #define CORE_MCI_VERSION                0x50
28 #define CORE_VERSION_MAJOR_SHIFT        28
29 #define CORE_VERSION_MAJOR_MASK         (0xf << CORE_VERSION_MAJOR_SHIFT)
30 #define CORE_VERSION_MINOR_MASK         0xff
31
32 #define CORE_HC_MODE            0x78
33 #define HC_MODE_EN              0x1
34 #define CORE_POWER              0x0
35 #define CORE_SW_RST             BIT(7)
36 #define FF_CLK_SW_RST_DIS       BIT(13)
37
38 #define CORE_PWRCTL_STATUS      0xdc
39 #define CORE_PWRCTL_MASK        0xe0
40 #define CORE_PWRCTL_CLEAR       0xe4
41 #define CORE_PWRCTL_CTL         0xe8
42 #define CORE_PWRCTL_BUS_OFF     BIT(0)
43 #define CORE_PWRCTL_BUS_ON      BIT(1)
44 #define CORE_PWRCTL_IO_LOW      BIT(2)
45 #define CORE_PWRCTL_IO_HIGH     BIT(3)
46 #define CORE_PWRCTL_BUS_SUCCESS BIT(0)
47 #define CORE_PWRCTL_IO_SUCCESS  BIT(2)
48 #define REQ_BUS_OFF             BIT(0)
49 #define REQ_BUS_ON              BIT(1)
50 #define REQ_IO_LOW              BIT(2)
51 #define REQ_IO_HIGH             BIT(3)
52 #define INT_MASK                0xf
53 #define MAX_PHASES              16
54 #define CORE_DLL_LOCK           BIT(7)
55 #define CORE_DDR_DLL_LOCK       BIT(11)
56 #define CORE_DLL_EN             BIT(16)
57 #define CORE_CDR_EN             BIT(17)
58 #define CORE_CK_OUT_EN          BIT(18)
59 #define CORE_CDR_EXT_EN         BIT(19)
60 #define CORE_DLL_PDN            BIT(29)
61 #define CORE_DLL_RST            BIT(30)
62 #define CORE_DLL_CONFIG         0x100
63 #define CORE_CMD_DAT_TRACK_SEL  BIT(0)
64 #define CORE_DLL_STATUS         0x108
65
66 #define CORE_DLL_CONFIG_2       0x1b4
67 #define CORE_DDR_CAL_EN         BIT(0)
68 #define CORE_FLL_CYCLE_CNT      BIT(18)
69 #define CORE_DLL_CLOCK_DISABLE  BIT(21)
70
71 #define CORE_VENDOR_SPEC        0x10c
72 #define CORE_VENDOR_SPEC_POR_VAL        0xa1c
73 #define CORE_CLK_PWRSAVE        BIT(1)
74 #define CORE_HC_MCLK_SEL_DFLT   (2 << 8)
75 #define CORE_HC_MCLK_SEL_HS400  (3 << 8)
76 #define CORE_HC_MCLK_SEL_MASK   (3 << 8)
77 #define CORE_HC_SELECT_IN_EN    BIT(18)
78 #define CORE_HC_SELECT_IN_HS400 (6 << 19)
79 #define CORE_HC_SELECT_IN_MASK  (7 << 19)
80
81 #define CORE_CSR_CDC_CTLR_CFG0          0x130
82 #define CORE_SW_TRIG_FULL_CALIB         BIT(16)
83 #define CORE_HW_AUTOCAL_ENA             BIT(17)
84
85 #define CORE_CSR_CDC_CTLR_CFG1          0x134
86 #define CORE_CSR_CDC_CAL_TIMER_CFG0     0x138
87 #define CORE_TIMER_ENA                  BIT(16)
88
89 #define CORE_CSR_CDC_CAL_TIMER_CFG1     0x13C
90 #define CORE_CSR_CDC_REFCOUNT_CFG       0x140
91 #define CORE_CSR_CDC_COARSE_CAL_CFG     0x144
92 #define CORE_CDC_OFFSET_CFG             0x14C
93 #define CORE_CSR_CDC_DELAY_CFG          0x150
94 #define CORE_CDC_SLAVE_DDA_CFG          0x160
95 #define CORE_CSR_CDC_STATUS0            0x164
96 #define CORE_CALIBRATION_DONE           BIT(0)
97
98 #define CORE_CDC_ERROR_CODE_MASK        0x7000000
99
100 #define CORE_CSR_CDC_GEN_CFG            0x178
101 #define CORE_CDC_SWITCH_BYPASS_OFF      BIT(0)
102 #define CORE_CDC_SWITCH_RC_EN           BIT(1)
103
104 #define CORE_DDR_200_CFG                0x184
105 #define CORE_CDC_T4_DLY_SEL             BIT(0)
106 #define CORE_CMDIN_RCLK_EN              BIT(1)
107 #define CORE_START_CDC_TRAFFIC          BIT(6)
108 #define CORE_VENDOR_SPEC3       0x1b0
109 #define CORE_PWRSAVE_DLL        BIT(3)
110
111 #define CORE_DDR_CONFIG         0x1b8
112 #define DDR_CONFIG_POR_VAL      0x80040853
113
114 #define CORE_VENDOR_SPEC_CAPABILITIES0  0x11c
115
116 #define INVALID_TUNING_PHASE    -1
117 #define SDHCI_MSM_MIN_CLOCK     400000
118 #define CORE_FREQ_100MHZ        (100 * 1000 * 1000)
119
120 #define CDR_SELEXT_SHIFT        20
121 #define CDR_SELEXT_MASK         (0xf << CDR_SELEXT_SHIFT)
122 #define CMUX_SHIFT_PHASE_SHIFT  24
123 #define CMUX_SHIFT_PHASE_MASK   (7 << CMUX_SHIFT_PHASE_SHIFT)
124
125 #define MSM_MMC_AUTOSUSPEND_DELAY_MS    50
126 struct sdhci_msm_host {
127         struct platform_device *pdev;
128         void __iomem *core_mem; /* MSM SDCC mapped address */
129         int pwr_irq;            /* power irq */
130         struct clk *clk;        /* main SD/MMC bus clock */
131         struct clk *pclk;       /* SDHC peripheral bus clock */
132         struct clk *bus_clk;    /* SDHC bus voter clock */
133         struct clk *xo_clk;     /* TCXO clk needed for FLL feature of cm_dll*/
134         unsigned long clk_rate;
135         struct mmc_host *mmc;
136         bool use_14lpp_dll_reset;
137         bool tuning_done;
138         bool calibration_done;
139         u8 saved_tuning_phase;
140         bool use_cdclp533;
141         bool use_cdr;
142         u32 transfer_mode;
143 };
144
145 static unsigned int msm_get_clock_rate_for_bus_mode(struct sdhci_host *host,
146                                                     unsigned int clock)
147 {
148         struct mmc_ios ios = host->mmc->ios;
149         /*
150          * The SDHC requires internal clock frequency to be double the
151          * actual clock that will be set for DDR mode. The controller
152          * uses the faster clock(100/400MHz) for some of its parts and
153          * send the actual required clock (50/200MHz) to the card.
154          */
155         if (ios.timing == MMC_TIMING_UHS_DDR50 ||
156             ios.timing == MMC_TIMING_MMC_DDR52 ||
157             ios.timing == MMC_TIMING_MMC_HS400 ||
158             host->flags & SDHCI_HS400_TUNING)
159                 clock *= 2;
160         return clock;
161 }
162
163 static void msm_set_clock_rate_for_bus_mode(struct sdhci_host *host,
164                                             unsigned int clock)
165 {
166         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
167         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
168         struct mmc_ios curr_ios = host->mmc->ios;
169         int rc;
170
171         clock = msm_get_clock_rate_for_bus_mode(host, clock);
172         rc = clk_set_rate(msm_host->clk, clock);
173         if (rc) {
174                 pr_err("%s: Failed to set clock at rate %u at timing %d\n",
175                        mmc_hostname(host->mmc), clock,
176                        curr_ios.timing);
177                 return;
178         }
179         msm_host->clk_rate = clock;
180         pr_debug("%s: Setting clock at rate %lu at timing %d\n",
181                  mmc_hostname(host->mmc), clk_get_rate(msm_host->clk),
182                  curr_ios.timing);
183 }
184
185 /* Platform specific tuning */
186 static inline int msm_dll_poll_ck_out_en(struct sdhci_host *host, u8 poll)
187 {
188         u32 wait_cnt = 50;
189         u8 ck_out_en;
190         struct mmc_host *mmc = host->mmc;
191
192         /* Poll for CK_OUT_EN bit.  max. poll time = 50us */
193         ck_out_en = !!(readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) &
194                         CORE_CK_OUT_EN);
195
196         while (ck_out_en != poll) {
197                 if (--wait_cnt == 0) {
198                         dev_err(mmc_dev(mmc), "%s: CK_OUT_EN bit is not %d\n",
199                                mmc_hostname(mmc), poll);
200                         return -ETIMEDOUT;
201                 }
202                 udelay(1);
203
204                 ck_out_en = !!(readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) &
205                                 CORE_CK_OUT_EN);
206         }
207
208         return 0;
209 }
210
211 static int msm_config_cm_dll_phase(struct sdhci_host *host, u8 phase)
212 {
213         int rc;
214         static const u8 grey_coded_phase_table[] = {
215                 0x0, 0x1, 0x3, 0x2, 0x6, 0x7, 0x5, 0x4,
216                 0xc, 0xd, 0xf, 0xe, 0xa, 0xb, 0x9, 0x8
217         };
218         unsigned long flags;
219         u32 config;
220         struct mmc_host *mmc = host->mmc;
221
222         if (phase > 0xf)
223                 return -EINVAL;
224
225         spin_lock_irqsave(&host->lock, flags);
226
227         config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
228         config &= ~(CORE_CDR_EN | CORE_CK_OUT_EN);
229         config |= (CORE_CDR_EXT_EN | CORE_DLL_EN);
230         writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
231
232         /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '0' */
233         rc = msm_dll_poll_ck_out_en(host, 0);
234         if (rc)
235                 goto err_out;
236
237         /*
238          * Write the selected DLL clock output phase (0 ... 15)
239          * to CDR_SELEXT bit field of DLL_CONFIG register.
240          */
241         config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
242         config &= ~CDR_SELEXT_MASK;
243         config |= grey_coded_phase_table[phase] << CDR_SELEXT_SHIFT;
244         writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
245
246         config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
247         config |= CORE_CK_OUT_EN;
248         writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
249
250         /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '1' */
251         rc = msm_dll_poll_ck_out_en(host, 1);
252         if (rc)
253                 goto err_out;
254
255         config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
256         config |= CORE_CDR_EN;
257         config &= ~CORE_CDR_EXT_EN;
258         writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
259         goto out;
260
261 err_out:
262         dev_err(mmc_dev(mmc), "%s: Failed to set DLL phase: %d\n",
263                mmc_hostname(mmc), phase);
264 out:
265         spin_unlock_irqrestore(&host->lock, flags);
266         return rc;
267 }
268
269 /*
270  * Find out the greatest range of consecuitive selected
271  * DLL clock output phases that can be used as sampling
272  * setting for SD3.0 UHS-I card read operation (in SDR104
273  * timing mode) or for eMMC4.5 card read operation (in
274  * HS400/HS200 timing mode).
275  * Select the 3/4 of the range and configure the DLL with the
276  * selected DLL clock output phase.
277  */
278
279 static int msm_find_most_appropriate_phase(struct sdhci_host *host,
280                                            u8 *phase_table, u8 total_phases)
281 {
282         int ret;
283         u8 ranges[MAX_PHASES][MAX_PHASES] = { {0}, {0} };
284         u8 phases_per_row[MAX_PHASES] = { 0 };
285         int row_index = 0, col_index = 0, selected_row_index = 0, curr_max = 0;
286         int i, cnt, phase_0_raw_index = 0, phase_15_raw_index = 0;
287         bool phase_0_found = false, phase_15_found = false;
288         struct mmc_host *mmc = host->mmc;
289
290         if (!total_phases || (total_phases > MAX_PHASES)) {
291                 dev_err(mmc_dev(mmc), "%s: Invalid argument: total_phases=%d\n",
292                        mmc_hostname(mmc), total_phases);
293                 return -EINVAL;
294         }
295
296         for (cnt = 0; cnt < total_phases; cnt++) {
297                 ranges[row_index][col_index] = phase_table[cnt];
298                 phases_per_row[row_index] += 1;
299                 col_index++;
300
301                 if ((cnt + 1) == total_phases) {
302                         continue;
303                 /* check if next phase in phase_table is consecutive or not */
304                 } else if ((phase_table[cnt] + 1) != phase_table[cnt + 1]) {
305                         row_index++;
306                         col_index = 0;
307                 }
308         }
309
310         if (row_index >= MAX_PHASES)
311                 return -EINVAL;
312
313         /* Check if phase-0 is present in first valid window? */
314         if (!ranges[0][0]) {
315                 phase_0_found = true;
316                 phase_0_raw_index = 0;
317                 /* Check if cycle exist between 2 valid windows */
318                 for (cnt = 1; cnt <= row_index; cnt++) {
319                         if (phases_per_row[cnt]) {
320                                 for (i = 0; i < phases_per_row[cnt]; i++) {
321                                         if (ranges[cnt][i] == 15) {
322                                                 phase_15_found = true;
323                                                 phase_15_raw_index = cnt;
324                                                 break;
325                                         }
326                                 }
327                         }
328                 }
329         }
330
331         /* If 2 valid windows form cycle then merge them as single window */
332         if (phase_0_found && phase_15_found) {
333                 /* number of phases in raw where phase 0 is present */
334                 u8 phases_0 = phases_per_row[phase_0_raw_index];
335                 /* number of phases in raw where phase 15 is present */
336                 u8 phases_15 = phases_per_row[phase_15_raw_index];
337
338                 if (phases_0 + phases_15 >= MAX_PHASES)
339                         /*
340                          * If there are more than 1 phase windows then total
341                          * number of phases in both the windows should not be
342                          * more than or equal to MAX_PHASES.
343                          */
344                         return -EINVAL;
345
346                 /* Merge 2 cyclic windows */
347                 i = phases_15;
348                 for (cnt = 0; cnt < phases_0; cnt++) {
349                         ranges[phase_15_raw_index][i] =
350                             ranges[phase_0_raw_index][cnt];
351                         if (++i >= MAX_PHASES)
352                                 break;
353                 }
354
355                 phases_per_row[phase_0_raw_index] = 0;
356                 phases_per_row[phase_15_raw_index] = phases_15 + phases_0;
357         }
358
359         for (cnt = 0; cnt <= row_index; cnt++) {
360                 if (phases_per_row[cnt] > curr_max) {
361                         curr_max = phases_per_row[cnt];
362                         selected_row_index = cnt;
363                 }
364         }
365
366         i = (curr_max * 3) / 4;
367         if (i)
368                 i--;
369
370         ret = ranges[selected_row_index][i];
371
372         if (ret >= MAX_PHASES) {
373                 ret = -EINVAL;
374                 dev_err(mmc_dev(mmc), "%s: Invalid phase selected=%d\n",
375                        mmc_hostname(mmc), ret);
376         }
377
378         return ret;
379 }
380
381 static inline void msm_cm_dll_set_freq(struct sdhci_host *host)
382 {
383         u32 mclk_freq = 0, config;
384
385         /* Program the MCLK value to MCLK_FREQ bit field */
386         if (host->clock <= 112000000)
387                 mclk_freq = 0;
388         else if (host->clock <= 125000000)
389                 mclk_freq = 1;
390         else if (host->clock <= 137000000)
391                 mclk_freq = 2;
392         else if (host->clock <= 150000000)
393                 mclk_freq = 3;
394         else if (host->clock <= 162000000)
395                 mclk_freq = 4;
396         else if (host->clock <= 175000000)
397                 mclk_freq = 5;
398         else if (host->clock <= 187000000)
399                 mclk_freq = 6;
400         else if (host->clock <= 200000000)
401                 mclk_freq = 7;
402
403         config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
404         config &= ~CMUX_SHIFT_PHASE_MASK;
405         config |= mclk_freq << CMUX_SHIFT_PHASE_SHIFT;
406         writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
407 }
408
409 /* Initialize the DLL (Programmable Delay Line) */
410 static int msm_init_cm_dll(struct sdhci_host *host)
411 {
412         struct mmc_host *mmc = host->mmc;
413         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
414         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
415         int wait_cnt = 50;
416         unsigned long flags;
417         u32 config;
418
419         spin_lock_irqsave(&host->lock, flags);
420
421         /*
422          * Make sure that clock is always enabled when DLL
423          * tuning is in progress. Keeping PWRSAVE ON may
424          * turn off the clock.
425          */
426         config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
427         config &= ~CORE_CLK_PWRSAVE;
428         writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
429
430         if (msm_host->use_14lpp_dll_reset) {
431                 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
432                 config &= ~CORE_CK_OUT_EN;
433                 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
434
435                 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2);
436                 config |= CORE_DLL_CLOCK_DISABLE;
437                 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG_2);
438         }
439
440         config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
441         config |= CORE_DLL_RST;
442         writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
443
444         config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
445         config |= CORE_DLL_PDN;
446         writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
447         msm_cm_dll_set_freq(host);
448
449         if (msm_host->use_14lpp_dll_reset &&
450             !IS_ERR_OR_NULL(msm_host->xo_clk)) {
451                 u32 mclk_freq = 0;
452
453                 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2);
454                 config &= CORE_FLL_CYCLE_CNT;
455                 if (config)
456                         mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 8),
457                                         clk_get_rate(msm_host->xo_clk));
458                 else
459                         mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 4),
460                                         clk_get_rate(msm_host->xo_clk));
461
462                 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2);
463                 config &= ~(0xFF << 10);
464                 config |= mclk_freq << 10;
465
466                 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG_2);
467                 /* wait for 5us before enabling DLL clock */
468                 udelay(5);
469         }
470
471         config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
472         config &= ~CORE_DLL_RST;
473         writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
474
475         config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
476         config &= ~CORE_DLL_PDN;
477         writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
478
479         if (msm_host->use_14lpp_dll_reset) {
480                 msm_cm_dll_set_freq(host);
481                 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2);
482                 config &= ~CORE_DLL_CLOCK_DISABLE;
483                 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG_2);
484         }
485
486         config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
487         config |= CORE_DLL_EN;
488         writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
489
490         config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
491         config |= CORE_CK_OUT_EN;
492         writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
493
494         /* Wait until DLL_LOCK bit of DLL_STATUS register becomes '1' */
495         while (!(readl_relaxed(host->ioaddr + CORE_DLL_STATUS) &
496                  CORE_DLL_LOCK)) {
497                 /* max. wait for 50us sec for LOCK bit to be set */
498                 if (--wait_cnt == 0) {
499                         dev_err(mmc_dev(mmc), "%s: DLL failed to LOCK\n",
500                                mmc_hostname(mmc));
501                         spin_unlock_irqrestore(&host->lock, flags);
502                         return -ETIMEDOUT;
503                 }
504                 udelay(1);
505         }
506
507         spin_unlock_irqrestore(&host->lock, flags);
508         return 0;
509 }
510
511 static void msm_hc_select_default(struct sdhci_host *host)
512 {
513         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
514         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
515         u32 config;
516
517         if (!msm_host->use_cdclp533) {
518                 config = readl_relaxed(host->ioaddr +
519                                 CORE_VENDOR_SPEC3);
520                 config &= ~CORE_PWRSAVE_DLL;
521                 writel_relaxed(config, host->ioaddr +
522                                 CORE_VENDOR_SPEC3);
523         }
524
525         config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
526         config &= ~CORE_HC_MCLK_SEL_MASK;
527         config |= CORE_HC_MCLK_SEL_DFLT;
528         writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
529
530         /*
531          * Disable HC_SELECT_IN to be able to use the UHS mode select
532          * configuration from Host Control2 register for all other
533          * modes.
534          * Write 0 to HC_SELECT_IN and HC_SELECT_IN_EN field
535          * in VENDOR_SPEC_FUNC
536          */
537         config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
538         config &= ~CORE_HC_SELECT_IN_EN;
539         config &= ~CORE_HC_SELECT_IN_MASK;
540         writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
541
542         /*
543          * Make sure above writes impacting free running MCLK are completed
544          * before changing the clk_rate at GCC.
545          */
546         wmb();
547 }
548
549 static void msm_hc_select_hs400(struct sdhci_host *host)
550 {
551         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
552         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
553         struct mmc_ios ios = host->mmc->ios;
554         u32 config, dll_lock;
555         int rc;
556
557         /* Select the divided clock (free running MCLK/2) */
558         config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
559         config &= ~CORE_HC_MCLK_SEL_MASK;
560         config |= CORE_HC_MCLK_SEL_HS400;
561
562         writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
563         /*
564          * Select HS400 mode using the HC_SELECT_IN from VENDOR SPEC
565          * register
566          */
567         if ((msm_host->tuning_done || ios.enhanced_strobe) &&
568             !msm_host->calibration_done) {
569                 config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
570                 config |= CORE_HC_SELECT_IN_HS400;
571                 config |= CORE_HC_SELECT_IN_EN;
572                 writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
573         }
574         if (!msm_host->clk_rate && !msm_host->use_cdclp533) {
575                 /*
576                  * Poll on DLL_LOCK or DDR_DLL_LOCK bits in
577                  * CORE_DLL_STATUS to be set.  This should get set
578                  * within 15 us at 200 MHz.
579                  */
580                 rc = readl_relaxed_poll_timeout(host->ioaddr +
581                                                 CORE_DLL_STATUS,
582                                                 dll_lock,
583                                                 (dll_lock &
584                                                 (CORE_DLL_LOCK |
585                                                 CORE_DDR_DLL_LOCK)), 10,
586                                                 1000);
587                 if (rc == -ETIMEDOUT)
588                         pr_err("%s: Unable to get DLL_LOCK/DDR_DLL_LOCK, dll_status: 0x%08x\n",
589                                mmc_hostname(host->mmc), dll_lock);
590         }
591         /*
592          * Make sure above writes impacting free running MCLK are completed
593          * before changing the clk_rate at GCC.
594          */
595         wmb();
596 }
597
598 /*
599  * sdhci_msm_hc_select_mode :- In general all timing modes are
600  * controlled via UHS mode select in Host Control2 register.
601  * eMMC specific HS200/HS400 doesn't have their respective modes
602  * defined here, hence we use these values.
603  *
604  * HS200 - SDR104 (Since they both are equivalent in functionality)
605  * HS400 - This involves multiple configurations
606  *              Initially SDR104 - when tuning is required as HS200
607  *              Then when switching to DDR @ 400MHz (HS400) we use
608  *              the vendor specific HC_SELECT_IN to control the mode.
609  *
610  * In addition to controlling the modes we also need to select the
611  * correct input clock for DLL depending on the mode.
612  *
613  * HS400 - divided clock (free running MCLK/2)
614  * All other modes - default (free running MCLK)
615  */
616 static void sdhci_msm_hc_select_mode(struct sdhci_host *host)
617 {
618         struct mmc_ios ios = host->mmc->ios;
619
620         if (ios.timing == MMC_TIMING_MMC_HS400 ||
621             host->flags & SDHCI_HS400_TUNING)
622                 msm_hc_select_hs400(host);
623         else
624                 msm_hc_select_default(host);
625 }
626
627 static int sdhci_msm_cdclp533_calibration(struct sdhci_host *host)
628 {
629         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
630         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
631         u32 config, calib_done;
632         int ret;
633
634         pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
635
636         /*
637          * Retuning in HS400 (DDR mode) will fail, just reset the
638          * tuning block and restore the saved tuning phase.
639          */
640         ret = msm_init_cm_dll(host);
641         if (ret)
642                 goto out;
643
644         /* Set the selected phase in delay line hw block */
645         ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase);
646         if (ret)
647                 goto out;
648
649         config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
650         config |= CORE_CMD_DAT_TRACK_SEL;
651         writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
652
653         config = readl_relaxed(host->ioaddr + CORE_DDR_200_CFG);
654         config &= ~CORE_CDC_T4_DLY_SEL;
655         writel_relaxed(config, host->ioaddr + CORE_DDR_200_CFG);
656
657         config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG);
658         config &= ~CORE_CDC_SWITCH_BYPASS_OFF;
659         writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG);
660
661         config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG);
662         config |= CORE_CDC_SWITCH_RC_EN;
663         writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG);
664
665         config = readl_relaxed(host->ioaddr + CORE_DDR_200_CFG);
666         config &= ~CORE_START_CDC_TRAFFIC;
667         writel_relaxed(config, host->ioaddr + CORE_DDR_200_CFG);
668
669         /* Perform CDC Register Initialization Sequence */
670
671         writel_relaxed(0x11800EC, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
672         writel_relaxed(0x3011111, host->ioaddr + CORE_CSR_CDC_CTLR_CFG1);
673         writel_relaxed(0x1201000, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
674         writel_relaxed(0x4, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG1);
675         writel_relaxed(0xCB732020, host->ioaddr + CORE_CSR_CDC_REFCOUNT_CFG);
676         writel_relaxed(0xB19, host->ioaddr + CORE_CSR_CDC_COARSE_CAL_CFG);
677         writel_relaxed(0x4E2, host->ioaddr + CORE_CSR_CDC_DELAY_CFG);
678         writel_relaxed(0x0, host->ioaddr + CORE_CDC_OFFSET_CFG);
679         writel_relaxed(0x16334, host->ioaddr + CORE_CDC_SLAVE_DDA_CFG);
680
681         /* CDC HW Calibration */
682
683         config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
684         config |= CORE_SW_TRIG_FULL_CALIB;
685         writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
686
687         config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
688         config &= ~CORE_SW_TRIG_FULL_CALIB;
689         writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
690
691         config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
692         config |= CORE_HW_AUTOCAL_ENA;
693         writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
694
695         config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
696         config |= CORE_TIMER_ENA;
697         writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
698
699         ret = readl_relaxed_poll_timeout(host->ioaddr + CORE_CSR_CDC_STATUS0,
700                                          calib_done,
701                                          (calib_done & CORE_CALIBRATION_DONE),
702                                          1, 50);
703
704         if (ret == -ETIMEDOUT) {
705                 pr_err("%s: %s: CDC calibration was not completed\n",
706                        mmc_hostname(host->mmc), __func__);
707                 goto out;
708         }
709
710         ret = readl_relaxed(host->ioaddr + CORE_CSR_CDC_STATUS0)
711                         & CORE_CDC_ERROR_CODE_MASK;
712         if (ret) {
713                 pr_err("%s: %s: CDC error code %d\n",
714                        mmc_hostname(host->mmc), __func__, ret);
715                 ret = -EINVAL;
716                 goto out;
717         }
718
719         config = readl_relaxed(host->ioaddr + CORE_DDR_200_CFG);
720         config |= CORE_START_CDC_TRAFFIC;
721         writel_relaxed(config, host->ioaddr + CORE_DDR_200_CFG);
722 out:
723         pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
724                  __func__, ret);
725         return ret;
726 }
727
728 static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host *host)
729 {
730         struct mmc_host *mmc = host->mmc;
731         u32 dll_status, config;
732         int ret;
733
734         pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
735
736         /*
737          * Currently the CORE_DDR_CONFIG register defaults to desired
738          * configuration on reset. Currently reprogramming the power on
739          * reset (POR) value in case it might have been modified by
740          * bootloaders. In the future, if this changes, then the desired
741          * values will need to be programmed appropriately.
742          */
743         writel_relaxed(DDR_CONFIG_POR_VAL, host->ioaddr + CORE_DDR_CONFIG);
744
745         if (mmc->ios.enhanced_strobe) {
746                 config = readl_relaxed(host->ioaddr + CORE_DDR_200_CFG);
747                 config |= CORE_CMDIN_RCLK_EN;
748                 writel_relaxed(config, host->ioaddr + CORE_DDR_200_CFG);
749         }
750
751         config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2);
752         config |= CORE_DDR_CAL_EN;
753         writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG_2);
754
755         ret = readl_relaxed_poll_timeout(host->ioaddr + CORE_DLL_STATUS,
756                                          dll_status,
757                                          (dll_status & CORE_DDR_DLL_LOCK),
758                                          10, 1000);
759
760         if (ret == -ETIMEDOUT) {
761                 pr_err("%s: %s: CM_DLL_SDC4 calibration was not completed\n",
762                        mmc_hostname(host->mmc), __func__);
763                 goto out;
764         }
765
766         config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC3);
767         config |= CORE_PWRSAVE_DLL;
768         writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC3);
769
770         /*
771          * Drain writebuffer to ensure above DLL calibration
772          * and PWRSAVE DLL is enabled.
773          */
774         wmb();
775 out:
776         pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
777                  __func__, ret);
778         return ret;
779 }
780
781 static int sdhci_msm_hs400_dll_calibration(struct sdhci_host *host)
782 {
783         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
784         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
785         struct mmc_host *mmc = host->mmc;
786         int ret;
787         u32 config;
788
789         pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
790
791         /*
792          * Retuning in HS400 (DDR mode) will fail, just reset the
793          * tuning block and restore the saved tuning phase.
794          */
795         ret = msm_init_cm_dll(host);
796         if (ret)
797                 goto out;
798
799         if (!mmc->ios.enhanced_strobe) {
800                 /* Set the selected phase in delay line hw block */
801                 ret = msm_config_cm_dll_phase(host,
802                                               msm_host->saved_tuning_phase);
803                 if (ret)
804                         goto out;
805                 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
806                 config |= CORE_CMD_DAT_TRACK_SEL;
807                 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
808         }
809
810         if (msm_host->use_cdclp533)
811                 ret = sdhci_msm_cdclp533_calibration(host);
812         else
813                 ret = sdhci_msm_cm_dll_sdc4_calibration(host);
814 out:
815         pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
816                  __func__, ret);
817         return ret;
818 }
819
820 static void sdhci_msm_set_cdr(struct sdhci_host *host, bool enable)
821 {
822         u32 config, oldconfig = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
823
824         config = oldconfig;
825         if (enable) {
826                 config |= CORE_CDR_EN;
827                 config &= ~CORE_CDR_EXT_EN;
828         } else {
829                 config &= ~CORE_CDR_EN;
830                 config |= CORE_CDR_EXT_EN;
831         }
832
833         if (config != oldconfig)
834                 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
835 }
836
837 static int sdhci_msm_execute_tuning(struct mmc_host *mmc, u32 opcode)
838 {
839         struct sdhci_host *host = mmc_priv(mmc);
840         int tuning_seq_cnt = 10;
841         u8 phase, tuned_phases[16], tuned_phase_cnt = 0;
842         int rc;
843         struct mmc_ios ios = host->mmc->ios;
844         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
845         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
846
847         /*
848          * Tuning is required for SDR104, HS200 and HS400 cards and
849          * if clock frequency is greater than 100MHz in these modes.
850          */
851         if (host->clock <= CORE_FREQ_100MHZ ||
852             !(ios.timing == MMC_TIMING_MMC_HS400 ||
853             ios.timing == MMC_TIMING_MMC_HS200 ||
854             ios.timing == MMC_TIMING_UHS_SDR104)) {
855                 msm_host->use_cdr = false;
856                 sdhci_msm_set_cdr(host, false);
857                 return 0;
858         }
859
860         /* Clock-Data-Recovery used to dynamically adjust RX sampling point */
861         msm_host->use_cdr = true;
862
863         /*
864          * Clear tuning_done flag before tuning to ensure proper
865          * HS400 settings.
866          */
867         msm_host->tuning_done = 0;
868
869         /*
870          * For HS400 tuning in HS200 timing requires:
871          * - select MCLK/2 in VENDOR_SPEC
872          * - program MCLK to 400MHz (or nearest supported) in GCC
873          */
874         if (host->flags & SDHCI_HS400_TUNING) {
875                 sdhci_msm_hc_select_mode(host);
876                 msm_set_clock_rate_for_bus_mode(host, ios.clock);
877                 host->flags &= ~SDHCI_HS400_TUNING;
878         }
879
880 retry:
881         /* First of all reset the tuning block */
882         rc = msm_init_cm_dll(host);
883         if (rc)
884                 return rc;
885
886         phase = 0;
887         do {
888                 /* Set the phase in delay line hw block */
889                 rc = msm_config_cm_dll_phase(host, phase);
890                 if (rc)
891                         return rc;
892
893                 msm_host->saved_tuning_phase = phase;
894                 rc = mmc_send_tuning(mmc, opcode, NULL);
895                 if (!rc) {
896                         /* Tuning is successful at this tuning point */
897                         tuned_phases[tuned_phase_cnt++] = phase;
898                         dev_dbg(mmc_dev(mmc), "%s: Found good phase = %d\n",
899                                  mmc_hostname(mmc), phase);
900                 }
901         } while (++phase < ARRAY_SIZE(tuned_phases));
902
903         if (tuned_phase_cnt) {
904                 if (tuned_phase_cnt == ARRAY_SIZE(tuned_phases)) {
905                         /*
906                          * All phases valid is _almost_ as bad as no phases
907                          * valid.  Probably all phases are not really reliable
908                          * but we didn't detect where the unreliable place is.
909                          * That means we'll essentially be guessing and hoping
910                          * we get a good phase.  Better to try a few times.
911                          */
912                         dev_dbg(mmc_dev(mmc), "%s: All phases valid; try again\n",
913                                 mmc_hostname(mmc));
914                         if (--tuning_seq_cnt) {
915                                 tuned_phase_cnt = 0;
916                                 goto retry;
917                         }
918                 }
919
920                 rc = msm_find_most_appropriate_phase(host, tuned_phases,
921                                                      tuned_phase_cnt);
922                 if (rc < 0)
923                         return rc;
924                 else
925                         phase = rc;
926
927                 /*
928                  * Finally set the selected phase in delay
929                  * line hw block.
930                  */
931                 rc = msm_config_cm_dll_phase(host, phase);
932                 if (rc)
933                         return rc;
934                 dev_dbg(mmc_dev(mmc), "%s: Setting the tuning phase to %d\n",
935                          mmc_hostname(mmc), phase);
936         } else {
937                 if (--tuning_seq_cnt)
938                         goto retry;
939                 /* Tuning failed */
940                 dev_dbg(mmc_dev(mmc), "%s: No tuning point found\n",
941                        mmc_hostname(mmc));
942                 rc = -EIO;
943         }
944
945         if (!rc)
946                 msm_host->tuning_done = true;
947         return rc;
948 }
949
950 /*
951  * sdhci_msm_hs400 - Calibrate the DLL for HS400 bus speed mode operation.
952  * This needs to be done for both tuning and enhanced_strobe mode.
953  * DLL operation is only needed for clock > 100MHz. For clock <= 100MHz
954  * fixed feedback clock is used.
955  */
956 static void sdhci_msm_hs400(struct sdhci_host *host, struct mmc_ios *ios)
957 {
958         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
959         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
960         int ret;
961
962         if (host->clock > CORE_FREQ_100MHZ &&
963             (msm_host->tuning_done || ios->enhanced_strobe) &&
964             !msm_host->calibration_done) {
965                 ret = sdhci_msm_hs400_dll_calibration(host);
966                 if (!ret)
967                         msm_host->calibration_done = true;
968                 else
969                         pr_err("%s: Failed to calibrate DLL for hs400 mode (%d)\n",
970                                mmc_hostname(host->mmc), ret);
971         }
972 }
973
974 static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host,
975                                         unsigned int uhs)
976 {
977         struct mmc_host *mmc = host->mmc;
978         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
979         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
980         u16 ctrl_2;
981         u32 config;
982
983         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
984         /* Select Bus Speed Mode for host */
985         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
986         switch (uhs) {
987         case MMC_TIMING_UHS_SDR12:
988                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
989                 break;
990         case MMC_TIMING_UHS_SDR25:
991                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
992                 break;
993         case MMC_TIMING_UHS_SDR50:
994                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
995                 break;
996         case MMC_TIMING_MMC_HS400:
997         case MMC_TIMING_MMC_HS200:
998         case MMC_TIMING_UHS_SDR104:
999                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1000                 break;
1001         case MMC_TIMING_UHS_DDR50:
1002         case MMC_TIMING_MMC_DDR52:
1003                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1004                 break;
1005         }
1006
1007         /*
1008          * When clock frequency is less than 100MHz, the feedback clock must be
1009          * provided and DLL must not be used so that tuning can be skipped. To
1010          * provide feedback clock, the mode selection can be any value less
1011          * than 3'b011 in bits [2:0] of HOST CONTROL2 register.
1012          */
1013         if (host->clock <= CORE_FREQ_100MHZ) {
1014                 if (uhs == MMC_TIMING_MMC_HS400 ||
1015                     uhs == MMC_TIMING_MMC_HS200 ||
1016                     uhs == MMC_TIMING_UHS_SDR104)
1017                         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1018                 /*
1019                  * DLL is not required for clock <= 100MHz
1020                  * Thus, make sure DLL it is disabled when not required
1021                  */
1022                 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
1023                 config |= CORE_DLL_RST;
1024                 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
1025
1026                 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
1027                 config |= CORE_DLL_PDN;
1028                 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
1029
1030                 /*
1031                  * The DLL needs to be restored and CDCLP533 recalibrated
1032                  * when the clock frequency is set back to 400MHz.
1033                  */
1034                 msm_host->calibration_done = false;
1035         }
1036
1037         dev_dbg(mmc_dev(mmc), "%s: clock=%u uhs=%u ctrl_2=0x%x\n",
1038                 mmc_hostname(host->mmc), host->clock, uhs, ctrl_2);
1039         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1040
1041         if (mmc->ios.timing == MMC_TIMING_MMC_HS400)
1042                 sdhci_msm_hs400(host, &mmc->ios);
1043 }
1044
1045 static void sdhci_msm_voltage_switch(struct sdhci_host *host)
1046 {
1047         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1048         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1049         u32 irq_status, irq_ack = 0;
1050
1051         irq_status = readl_relaxed(msm_host->core_mem + CORE_PWRCTL_STATUS);
1052         irq_status &= INT_MASK;
1053
1054         writel_relaxed(irq_status, msm_host->core_mem + CORE_PWRCTL_CLEAR);
1055
1056         if (irq_status & (CORE_PWRCTL_BUS_ON | CORE_PWRCTL_BUS_OFF))
1057                 irq_ack |= CORE_PWRCTL_BUS_SUCCESS;
1058         if (irq_status & (CORE_PWRCTL_IO_LOW | CORE_PWRCTL_IO_HIGH))
1059                 irq_ack |= CORE_PWRCTL_IO_SUCCESS;
1060
1061         /*
1062          * The driver has to acknowledge the interrupt, switch voltages and
1063          * report back if it succeded or not to this register. The voltage
1064          * switches are handled by the sdhci core, so just report success.
1065          */
1066         writel_relaxed(irq_ack, msm_host->core_mem + CORE_PWRCTL_CTL);
1067 }
1068
1069 static irqreturn_t sdhci_msm_pwr_irq(int irq, void *data)
1070 {
1071         struct sdhci_host *host = (struct sdhci_host *)data;
1072
1073         sdhci_msm_voltage_switch(host);
1074
1075         return IRQ_HANDLED;
1076 }
1077
1078 static unsigned int sdhci_msm_get_max_clock(struct sdhci_host *host)
1079 {
1080         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1081         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1082
1083         return clk_round_rate(msm_host->clk, ULONG_MAX);
1084 }
1085
1086 static unsigned int sdhci_msm_get_min_clock(struct sdhci_host *host)
1087 {
1088         return SDHCI_MSM_MIN_CLOCK;
1089 }
1090
1091 /**
1092  * __sdhci_msm_set_clock - sdhci_msm clock control.
1093  *
1094  * Description:
1095  * MSM controller does not use internal divider and
1096  * instead directly control the GCC clock as per
1097  * HW recommendation.
1098  **/
1099 static void __sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
1100 {
1101         u16 clk;
1102         /*
1103          * Keep actual_clock as zero -
1104          * - since there is no divider used so no need of having actual_clock.
1105          * - MSM controller uses SDCLK for data timeout calculation. If
1106          *   actual_clock is zero, host->clock is taken for calculation.
1107          */
1108         host->mmc->actual_clock = 0;
1109
1110         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1111
1112         if (clock == 0)
1113                 return;
1114
1115         /*
1116          * MSM controller do not use clock divider.
1117          * Thus read SDHCI_CLOCK_CONTROL and only enable
1118          * clock with no divider value programmed.
1119          */
1120         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1121         sdhci_enable_clk(host, clk);
1122 }
1123
1124 /* sdhci_msm_set_clock - Called with (host->lock) spinlock held. */
1125 static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
1126 {
1127         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1128         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1129
1130         if (!clock) {
1131                 msm_host->clk_rate = clock;
1132                 goto out;
1133         }
1134
1135         sdhci_msm_hc_select_mode(host);
1136
1137         msm_set_clock_rate_for_bus_mode(host, clock);
1138 out:
1139         __sdhci_msm_set_clock(host, clock);
1140 }
1141
1142 static void sdhci_msm_write_w(struct sdhci_host *host, u16 val, int reg)
1143 {
1144         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1145         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1146
1147         switch (reg) {
1148         case SDHCI_TRANSFER_MODE:
1149                 msm_host->transfer_mode = val;
1150                 break;
1151         case SDHCI_COMMAND:
1152                 if (!msm_host->use_cdr)
1153                         break;
1154                 if ((msm_host->transfer_mode & SDHCI_TRNS_READ) &&
1155                     (SDHCI_GET_CMD(val) != MMC_SEND_TUNING_BLOCK_HS200) &&
1156                     (SDHCI_GET_CMD(val) != MMC_SEND_TUNING_BLOCK))
1157                         sdhci_msm_set_cdr(host, true);
1158                 else
1159                         sdhci_msm_set_cdr(host, false);
1160                 break;
1161         }
1162         writew(val, host->ioaddr + reg);
1163 }
1164
1165 static const struct of_device_id sdhci_msm_dt_match[] = {
1166         { .compatible = "qcom,sdhci-msm-v4" },
1167         {},
1168 };
1169
1170 MODULE_DEVICE_TABLE(of, sdhci_msm_dt_match);
1171
1172 static const struct sdhci_ops sdhci_msm_ops = {
1173         .reset = sdhci_reset,
1174         .set_clock = sdhci_msm_set_clock,
1175         .get_min_clock = sdhci_msm_get_min_clock,
1176         .get_max_clock = sdhci_msm_get_max_clock,
1177         .set_bus_width = sdhci_set_bus_width,
1178         .set_uhs_signaling = sdhci_msm_set_uhs_signaling,
1179         .voltage_switch = sdhci_msm_voltage_switch,
1180         .write_w = sdhci_msm_write_w,
1181 };
1182
1183 static const struct sdhci_pltfm_data sdhci_msm_pdata = {
1184         .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
1185                   SDHCI_QUIRK_NO_CARD_NO_RESET |
1186                   SDHCI_QUIRK_SINGLE_POWER_WRITE |
1187                   SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
1188                   SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
1189
1190         .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
1191         .ops = &sdhci_msm_ops,
1192 };
1193
1194 static int sdhci_msm_probe(struct platform_device *pdev)
1195 {
1196         struct sdhci_host *host;
1197         struct sdhci_pltfm_host *pltfm_host;
1198         struct sdhci_msm_host *msm_host;
1199         struct resource *core_memres;
1200         int ret;
1201         u16 host_version, core_minor;
1202         u32 core_version, config;
1203         u8 core_major;
1204
1205         host = sdhci_pltfm_init(pdev, &sdhci_msm_pdata, sizeof(*msm_host));
1206         if (IS_ERR(host))
1207                 return PTR_ERR(host);
1208
1209         host->sdma_boundary = 0;
1210         pltfm_host = sdhci_priv(host);
1211         msm_host = sdhci_pltfm_priv(pltfm_host);
1212         msm_host->mmc = host->mmc;
1213         msm_host->pdev = pdev;
1214
1215         ret = mmc_of_parse(host->mmc);
1216         if (ret)
1217                 goto pltfm_free;
1218
1219         sdhci_get_of_property(pdev);
1220
1221         msm_host->saved_tuning_phase = INVALID_TUNING_PHASE;
1222
1223         /* Setup SDCC bus voter clock. */
1224         msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus");
1225         if (!IS_ERR(msm_host->bus_clk)) {
1226                 /* Vote for max. clk rate for max. performance */
1227                 ret = clk_set_rate(msm_host->bus_clk, INT_MAX);
1228                 if (ret)
1229                         goto pltfm_free;
1230                 ret = clk_prepare_enable(msm_host->bus_clk);
1231                 if (ret)
1232                         goto pltfm_free;
1233         }
1234
1235         /* Setup main peripheral bus clock */
1236         msm_host->pclk = devm_clk_get(&pdev->dev, "iface");
1237         if (IS_ERR(msm_host->pclk)) {
1238                 ret = PTR_ERR(msm_host->pclk);
1239                 dev_err(&pdev->dev, "Peripheral clk setup failed (%d)\n", ret);
1240                 goto bus_clk_disable;
1241         }
1242
1243         ret = clk_prepare_enable(msm_host->pclk);
1244         if (ret)
1245                 goto bus_clk_disable;
1246
1247         /* Setup SDC MMC clock */
1248         msm_host->clk = devm_clk_get(&pdev->dev, "core");
1249         if (IS_ERR(msm_host->clk)) {
1250                 ret = PTR_ERR(msm_host->clk);
1251                 dev_err(&pdev->dev, "SDC MMC clk setup failed (%d)\n", ret);
1252                 goto pclk_disable;
1253         }
1254
1255         /*
1256          * xo clock is needed for FLL feature of cm_dll.
1257          * In case if xo clock is not mentioned in DT, warn and proceed.
1258          */
1259         msm_host->xo_clk = devm_clk_get(&pdev->dev, "xo");
1260         if (IS_ERR(msm_host->xo_clk)) {
1261                 ret = PTR_ERR(msm_host->xo_clk);
1262                 dev_warn(&pdev->dev, "TCXO clk not present (%d)\n", ret);
1263         }
1264
1265         /* Vote for maximum clock rate for maximum performance */
1266         ret = clk_set_rate(msm_host->clk, INT_MAX);
1267         if (ret)
1268                 dev_warn(&pdev->dev, "core clock boost failed\n");
1269
1270         ret = clk_prepare_enable(msm_host->clk);
1271         if (ret)
1272                 goto pclk_disable;
1273
1274         core_memres = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1275         msm_host->core_mem = devm_ioremap_resource(&pdev->dev, core_memres);
1276
1277         if (IS_ERR(msm_host->core_mem)) {
1278                 dev_err(&pdev->dev, "Failed to remap registers\n");
1279                 ret = PTR_ERR(msm_host->core_mem);
1280                 goto clk_disable;
1281         }
1282
1283         /* Reset the vendor spec register to power on reset state */
1284         writel_relaxed(CORE_VENDOR_SPEC_POR_VAL,
1285                        host->ioaddr + CORE_VENDOR_SPEC);
1286
1287         /* Set HC_MODE_EN bit in HC_MODE register */
1288         writel_relaxed(HC_MODE_EN, (msm_host->core_mem + CORE_HC_MODE));
1289
1290         config = readl_relaxed(msm_host->core_mem + CORE_HC_MODE);
1291         config |= FF_CLK_SW_RST_DIS;
1292         writel_relaxed(config, msm_host->core_mem + CORE_HC_MODE);
1293
1294         host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION));
1295         dev_dbg(&pdev->dev, "Host Version: 0x%x Vendor Version 0x%x\n",
1296                 host_version, ((host_version & SDHCI_VENDOR_VER_MASK) >>
1297                                SDHCI_VENDOR_VER_SHIFT));
1298
1299         core_version = readl_relaxed(msm_host->core_mem + CORE_MCI_VERSION);
1300         core_major = (core_version & CORE_VERSION_MAJOR_MASK) >>
1301                       CORE_VERSION_MAJOR_SHIFT;
1302         core_minor = core_version & CORE_VERSION_MINOR_MASK;
1303         dev_dbg(&pdev->dev, "MCI Version: 0x%08x, major: 0x%04x, minor: 0x%02x\n",
1304                 core_version, core_major, core_minor);
1305
1306         if (core_major == 1 && core_minor >= 0x42)
1307                 msm_host->use_14lpp_dll_reset = true;
1308
1309         /*
1310          * SDCC 5 controller with major version 1, minor version 0x34 and later
1311          * with HS 400 mode support will use CM DLL instead of CDC LP 533 DLL.
1312          */
1313         if (core_major == 1 && core_minor < 0x34)
1314                 msm_host->use_cdclp533 = true;
1315
1316         /*
1317          * Support for some capabilities is not advertised by newer
1318          * controller versions and must be explicitly enabled.
1319          */
1320         if (core_major >= 1 && core_minor != 0x11 && core_minor != 0x12) {
1321                 config = readl_relaxed(host->ioaddr + SDHCI_CAPABILITIES);
1322                 config |= SDHCI_CAN_VDD_300 | SDHCI_CAN_DO_8BIT;
1323                 writel_relaxed(config, host->ioaddr +
1324                                CORE_VENDOR_SPEC_CAPABILITIES0);
1325         }
1326
1327         /*
1328          * Power on reset state may trigger power irq if previous status of
1329          * PWRCTL was either BUS_ON or IO_HIGH_V. So before enabling pwr irq
1330          * interrupt in GIC, any pending power irq interrupt should be
1331          * acknowledged. Otherwise power irq interrupt handler would be
1332          * fired prematurely.
1333          */
1334         sdhci_msm_voltage_switch(host);
1335
1336         /*
1337          * Ensure that above writes are propogated before interrupt enablement
1338          * in GIC.
1339          */
1340         mb();
1341
1342         /* Setup IRQ for handling power/voltage tasks with PMIC */
1343         msm_host->pwr_irq = platform_get_irq_byname(pdev, "pwr_irq");
1344         if (msm_host->pwr_irq < 0) {
1345                 dev_err(&pdev->dev, "Get pwr_irq failed (%d)\n",
1346                         msm_host->pwr_irq);
1347                 ret = msm_host->pwr_irq;
1348                 goto clk_disable;
1349         }
1350
1351         /* Enable pwr irq interrupts */
1352         writel_relaxed(INT_MASK, msm_host->core_mem + CORE_PWRCTL_MASK);
1353
1354         ret = devm_request_threaded_irq(&pdev->dev, msm_host->pwr_irq, NULL,
1355                                         sdhci_msm_pwr_irq, IRQF_ONESHOT,
1356                                         dev_name(&pdev->dev), host);
1357         if (ret) {
1358                 dev_err(&pdev->dev, "Request IRQ failed (%d)\n", ret);
1359                 goto clk_disable;
1360         }
1361
1362         pm_runtime_get_noresume(&pdev->dev);
1363         pm_runtime_set_active(&pdev->dev);
1364         pm_runtime_enable(&pdev->dev);
1365         pm_runtime_set_autosuspend_delay(&pdev->dev,
1366                                          MSM_MMC_AUTOSUSPEND_DELAY_MS);
1367         pm_runtime_use_autosuspend(&pdev->dev);
1368
1369         host->mmc_host_ops.execute_tuning = sdhci_msm_execute_tuning;
1370         ret = sdhci_add_host(host);
1371         if (ret)
1372                 goto pm_runtime_disable;
1373
1374         pm_runtime_mark_last_busy(&pdev->dev);
1375         pm_runtime_put_autosuspend(&pdev->dev);
1376
1377         return 0;
1378
1379 pm_runtime_disable:
1380         pm_runtime_disable(&pdev->dev);
1381         pm_runtime_set_suspended(&pdev->dev);
1382         pm_runtime_put_noidle(&pdev->dev);
1383 clk_disable:
1384         clk_disable_unprepare(msm_host->clk);
1385 pclk_disable:
1386         clk_disable_unprepare(msm_host->pclk);
1387 bus_clk_disable:
1388         if (!IS_ERR(msm_host->bus_clk))
1389                 clk_disable_unprepare(msm_host->bus_clk);
1390 pltfm_free:
1391         sdhci_pltfm_free(pdev);
1392         return ret;
1393 }
1394
1395 static int sdhci_msm_remove(struct platform_device *pdev)
1396 {
1397         struct sdhci_host *host = platform_get_drvdata(pdev);
1398         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1399         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1400         int dead = (readl_relaxed(host->ioaddr + SDHCI_INT_STATUS) ==
1401                     0xffffffff);
1402
1403         sdhci_remove_host(host, dead);
1404
1405         pm_runtime_get_sync(&pdev->dev);
1406         pm_runtime_disable(&pdev->dev);
1407         pm_runtime_put_noidle(&pdev->dev);
1408
1409         clk_disable_unprepare(msm_host->clk);
1410         clk_disable_unprepare(msm_host->pclk);
1411         if (!IS_ERR(msm_host->bus_clk))
1412                 clk_disable_unprepare(msm_host->bus_clk);
1413         sdhci_pltfm_free(pdev);
1414         return 0;
1415 }
1416
1417 #ifdef CONFIG_PM
1418 static int sdhci_msm_runtime_suspend(struct device *dev)
1419 {
1420         struct sdhci_host *host = dev_get_drvdata(dev);
1421         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1422         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1423
1424         clk_disable_unprepare(msm_host->clk);
1425         clk_disable_unprepare(msm_host->pclk);
1426
1427         return 0;
1428 }
1429
1430 static int sdhci_msm_runtime_resume(struct device *dev)
1431 {
1432         struct sdhci_host *host = dev_get_drvdata(dev);
1433         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1434         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1435         int ret;
1436
1437         ret = clk_prepare_enable(msm_host->clk);
1438         if (ret) {
1439                 dev_err(dev, "clk_enable failed for core_clk: %d\n", ret);
1440                 return ret;
1441         }
1442         ret = clk_prepare_enable(msm_host->pclk);
1443         if (ret) {
1444                 dev_err(dev, "clk_enable failed for iface_clk: %d\n", ret);
1445                 clk_disable_unprepare(msm_host->clk);
1446                 return ret;
1447         }
1448
1449         return 0;
1450 }
1451 #endif
1452
1453 static const struct dev_pm_ops sdhci_msm_pm_ops = {
1454         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1455                                 pm_runtime_force_resume)
1456         SET_RUNTIME_PM_OPS(sdhci_msm_runtime_suspend,
1457                            sdhci_msm_runtime_resume,
1458                            NULL)
1459 };
1460
1461 static struct platform_driver sdhci_msm_driver = {
1462         .probe = sdhci_msm_probe,
1463         .remove = sdhci_msm_remove,
1464         .driver = {
1465                    .name = "sdhci_msm",
1466                    .of_match_table = sdhci_msm_dt_match,
1467                    .pm = &sdhci_msm_pm_ops,
1468         },
1469 };
1470
1471 module_platform_driver(sdhci_msm_driver);
1472
1473 MODULE_DESCRIPTION("Qualcomm Secure Digital Host Controller Interface driver");
1474 MODULE_LICENSE("GPL v2");