drivers/mmc/host/sdhci-msm.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver
   4  *
   5  * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
   6  */
   7
   8 #include <linux/module.h>
   9 #include <linux/of_device.h>
  10 #include <linux/delay.h>
  11 #include <linux/mmc/mmc.h>
  12 #include <linux/pm_runtime.h>
  13 #include <linux/pm_opp.h>
  14 #include <linux/slab.h>
  15 #include <linux/iopoll.h>
  16 #include <linux/regulator/consumer.h>
  17 #include <linux/interconnect.h>
  18 #include <linux/pinctrl/consumer.h>
  19 #include <linux/reset.h>
  20
  21 #include "sdhci-pltfm.h"
  22 #include "cqhci.h"
  23
  24 #define CORE_MCI_VERSION                0x50
  25 #define CORE_VERSION_MAJOR_SHIFT        28
  26 #define CORE_VERSION_MAJOR_MASK         (0xf << CORE_VERSION_MAJOR_SHIFT)
  27 #define CORE_VERSION_MINOR_MASK         0xff
  28
  29 #define CORE_MCI_GENERICS               0x70
  30 #define SWITCHABLE_SIGNALING_VOLTAGE    BIT(29)
  31
  32 #define HC_MODE_EN              0x1
  33 #define CORE_POWER              0x0
  34 #define CORE_SW_RST             BIT(7)
  35 #define FF_CLK_SW_RST_DIS       BIT(13)
  36
  37 #define CORE_PWRCTL_BUS_OFF     BIT(0)
  38 #define CORE_PWRCTL_BUS_ON      BIT(1)
  39 #define CORE_PWRCTL_IO_LOW      BIT(2)
  40 #define CORE_PWRCTL_IO_HIGH     BIT(3)
  41 #define CORE_PWRCTL_BUS_SUCCESS BIT(0)
  42 #define CORE_PWRCTL_BUS_FAIL    BIT(1)
  43 #define CORE_PWRCTL_IO_SUCCESS  BIT(2)
  44 #define CORE_PWRCTL_IO_FAIL     BIT(3)
  45 #define REQ_BUS_OFF             BIT(0)
  46 #define REQ_BUS_ON              BIT(1)
  47 #define REQ_IO_LOW              BIT(2)
  48 #define REQ_IO_HIGH             BIT(3)
  49 #define INT_MASK                0xf
  50 #define MAX_PHASES              16
  51 #define CORE_DLL_LOCK           BIT(7)
  52 #define CORE_DDR_DLL_LOCK       BIT(11)
  53 #define CORE_DLL_EN             BIT(16)
  54 #define CORE_CDR_EN             BIT(17)
  55 #define CORE_CK_OUT_EN          BIT(18)
  56 #define CORE_CDR_EXT_EN         BIT(19)
  57 #define CORE_DLL_PDN            BIT(29)
  58 #define CORE_DLL_RST            BIT(30)
  59 #define CORE_CMD_DAT_TRACK_SEL  BIT(0)
  60
  61 #define CORE_DDR_CAL_EN         BIT(0)
  62 #define CORE_FLL_CYCLE_CNT      BIT(18)
  63 #define CORE_DLL_CLOCK_DISABLE  BIT(21)
  64
  65 #define DLL_USR_CTL_POR_VAL     0x10800
  66 #define ENABLE_DLL_LOCK_STATUS  BIT(26)
  67 #define FINE_TUNE_MODE_EN       BIT(27)
  68 #define BIAS_OK_SIGNAL          BIT(29)
  69
  70 #define DLL_CONFIG_3_LOW_FREQ_VAL       0x08
  71 #define DLL_CONFIG_3_HIGH_FREQ_VAL      0x10
  72
  73 #define CORE_VENDOR_SPEC_POR_VAL 0xa9c
  74 #define CORE_CLK_PWRSAVE        BIT(1)
  75 #define CORE_HC_MCLK_SEL_DFLT   (2 << 8)
  76 #define CORE_HC_MCLK_SEL_HS400  (3 << 8)
  77 #define CORE_HC_MCLK_SEL_MASK   (3 << 8)
  78 #define CORE_IO_PAD_PWR_SWITCH_EN       BIT(15)
  79 #define CORE_IO_PAD_PWR_SWITCH  BIT(16)
  80 #define CORE_HC_SELECT_IN_EN    BIT(18)
  81 #define CORE_HC_SELECT_IN_HS400 (6 << 19)
  82 #define CORE_HC_SELECT_IN_MASK  (7 << 19)
  83
  84 #define CORE_3_0V_SUPPORT       BIT(25)
  85 #define CORE_1_8V_SUPPORT       BIT(26)
  86 #define CORE_VOLT_SUPPORT       (CORE_3_0V_SUPPORT | CORE_1_8V_SUPPORT)
  87
  88 #define CORE_CSR_CDC_CTLR_CFG0          0x130
  89 #define CORE_SW_TRIG_FULL_CALIB         BIT(16)
  90 #define CORE_HW_AUTOCAL_ENA             BIT(17)
  91
  92 #define CORE_CSR_CDC_CTLR_CFG1          0x134
  93 #define CORE_CSR_CDC_CAL_TIMER_CFG0     0x138
  94 #define CORE_TIMER_ENA                  BIT(16)
  95
  96 #define CORE_CSR_CDC_CAL_TIMER_CFG1     0x13C
  97 #define CORE_CSR_CDC_REFCOUNT_CFG       0x140
  98 #define CORE_CSR_CDC_COARSE_CAL_CFG     0x144
  99 #define CORE_CDC_OFFSET_CFG             0x14C
 100 #define CORE_CSR_CDC_DELAY_CFG          0x150
 101 #define CORE_CDC_SLAVE_DDA_CFG          0x160
 102 #define CORE_CSR_CDC_STATUS0            0x164
 103 #define CORE_CALIBRATION_DONE           BIT(0)
 104
 105 #define CORE_CDC_ERROR_CODE_MASK        0x7000000
 106
 107 #define CORE_CSR_CDC_GEN_CFG            0x178
 108 #define CORE_CDC_SWITCH_BYPASS_OFF      BIT(0)
 109 #define CORE_CDC_SWITCH_RC_EN           BIT(1)
 110
 111 #define CORE_CDC_T4_DLY_SEL             BIT(0)
 112 #define CORE_CMDIN_RCLK_EN              BIT(1)
 113 #define CORE_START_CDC_TRAFFIC          BIT(6)
 114
 115 #define CORE_PWRSAVE_DLL        BIT(3)
 116
 117 #define DDR_CONFIG_POR_VAL      0x80040873
 118
 119
 120 #define INVALID_TUNING_PHASE    -1
 121 #define SDHCI_MSM_MIN_CLOCK     400000
 122 #define CORE_FREQ_100MHZ        (100 * 1000 * 1000)
 123
 124 #define CDR_SELEXT_SHIFT        20
 125 #define CDR_SELEXT_MASK         (0xf << CDR_SELEXT_SHIFT)
 126 #define CMUX_SHIFT_PHASE_SHIFT  24
 127 #define CMUX_SHIFT_PHASE_MASK   (7 << CMUX_SHIFT_PHASE_SHIFT)
 128
 129 #define MSM_MMC_AUTOSUSPEND_DELAY_MS    50
 130
 131 /* Timeout value to avoid infinite waiting for pwr_irq */
 132 #define MSM_PWR_IRQ_TIMEOUT_MS 5000
 133
 134 /* Max load for eMMC Vdd-io supply */
 135 #define MMC_VQMMC_MAX_LOAD_UA   325000
 136
 137 #define msm_host_readl(msm_host, host, offset) \
 138         msm_host->var_ops->msm_readl_relaxed(host, offset)
 139
 140 #define msm_host_writel(msm_host, val, host, offset) \
 141         msm_host->var_ops->msm_writel_relaxed(val, host, offset)
 142
 143 /* CQHCI vendor specific registers */
 144 #define CQHCI_VENDOR_CFG1       0xA00
 145 #define CQHCI_VENDOR_DIS_RST_ON_CQ_EN   (0x3 << 13)
 146
 147 struct sdhci_msm_offset {
 148         u32 core_hc_mode;
 149         u32 core_mci_data_cnt;
 150         u32 core_mci_status;
 151         u32 core_mci_fifo_cnt;
 152         u32 core_mci_version;
 153         u32 core_generics;
 154         u32 core_testbus_config;
 155         u32 core_testbus_sel2_bit;
 156         u32 core_testbus_ena;
 157         u32 core_testbus_sel2;
 158         u32 core_pwrctl_status;
 159         u32 core_pwrctl_mask;
 160         u32 core_pwrctl_clear;
 161         u32 core_pwrctl_ctl;
 162         u32 core_sdcc_debug_reg;
 163         u32 core_dll_config;
 164         u32 core_dll_status;
 165         u32 core_vendor_spec;
 166         u32 core_vendor_spec_adma_err_addr0;
 167         u32 core_vendor_spec_adma_err_addr1;
 168         u32 core_vendor_spec_func2;
 169         u32 core_vendor_spec_capabilities0;
 170         u32 core_ddr_200_cfg;
 171         u32 core_vendor_spec3;
 172         u32 core_dll_config_2;
 173         u32 core_dll_config_3;
 174         u32 core_ddr_config_old; /* Applicable to sdcc minor ver < 0x49 */
 175         u32 core_ddr_config;
 176         u32 core_dll_usr_ctl; /* Present on SDCC5.1 onwards */
 177 };
 178
 179 static const struct sdhci_msm_offset sdhci_msm_v5_offset = {
 180         .core_mci_data_cnt = 0x35c,
 181         .core_mci_status = 0x324,
 182         .core_mci_fifo_cnt = 0x308,
 183         .core_mci_version = 0x318,
 184         .core_generics = 0x320,
 185         .core_testbus_config = 0x32c,
 186         .core_testbus_sel2_bit = 3,
 187         .core_testbus_ena = (1 << 31),
 188         .core_testbus_sel2 = (1 << 3),
 189         .core_pwrctl_status = 0x240,
 190         .core_pwrctl_mask = 0x244,
 191         .core_pwrctl_clear = 0x248,
 192         .core_pwrctl_ctl = 0x24c,
 193         .core_sdcc_debug_reg = 0x358,
 194         .core_dll_config = 0x200,
 195         .core_dll_status = 0x208,
 196         .core_vendor_spec = 0x20c,
 197         .core_vendor_spec_adma_err_addr0 = 0x214,
 198         .core_vendor_spec_adma_err_addr1 = 0x218,
 199         .core_vendor_spec_func2 = 0x210,
 200         .core_vendor_spec_capabilities0 = 0x21c,
 201         .core_ddr_200_cfg = 0x224,
 202         .core_vendor_spec3 = 0x250,
 203         .core_dll_config_2 = 0x254,
 204         .core_dll_config_3 = 0x258,
 205         .core_ddr_config = 0x25c,
 206         .core_dll_usr_ctl = 0x388,
 207 };
 208
 209 static const struct sdhci_msm_offset sdhci_msm_mci_offset = {
 210         .core_hc_mode = 0x78,
 211         .core_mci_data_cnt = 0x30,
 212         .core_mci_status = 0x34,
 213         .core_mci_fifo_cnt = 0x44,
 214         .core_mci_version = 0x050,
 215         .core_generics = 0x70,
 216         .core_testbus_config = 0x0cc,
 217         .core_testbus_sel2_bit = 4,
 218         .core_testbus_ena = (1 << 3),
 219         .core_testbus_sel2 = (1 << 4),
 220         .core_pwrctl_status = 0xdc,
 221         .core_pwrctl_mask = 0xe0,
 222         .core_pwrctl_clear = 0xe4,
 223         .core_pwrctl_ctl = 0xe8,
 224         .core_sdcc_debug_reg = 0x124,
 225         .core_dll_config = 0x100,
 226         .core_dll_status = 0x108,
 227         .core_vendor_spec = 0x10c,
 228         .core_vendor_spec_adma_err_addr0 = 0x114,
 229         .core_vendor_spec_adma_err_addr1 = 0x118,
 230         .core_vendor_spec_func2 = 0x110,
 231         .core_vendor_spec_capabilities0 = 0x11c,
 232         .core_ddr_200_cfg = 0x184,
 233         .core_vendor_spec3 = 0x1b0,
 234         .core_dll_config_2 = 0x1b4,
 235         .core_ddr_config_old = 0x1b8,
 236         .core_ddr_config = 0x1bc,
 237 };
 238
 239 struct sdhci_msm_variant_ops {
 240         u32 (*msm_readl_relaxed)(struct sdhci_host *host, u32 offset);
 241         void (*msm_writel_relaxed)(u32 val, struct sdhci_host *host,
 242                         u32 offset);
 243 };
 244
 245 /*
 246  * From V5, register spaces have changed. Wrap this info in a structure
 247  * and choose the data_structure based on version info mentioned in DT.
 248  */
 249 struct sdhci_msm_variant_info {
 250         bool mci_removed;
 251         bool restore_dll_config;
 252         bool uses_tassadar_dll;
 253         const struct sdhci_msm_variant_ops *var_ops;
 254         const struct sdhci_msm_offset *offset;
 255 };
 256
 257 struct sdhci_msm_host {
 258         struct platform_device *pdev;
 259         void __iomem *core_mem; /* MSM SDCC mapped address */
 260         int pwr_irq;            /* power irq */
 261         struct clk *bus_clk;    /* SDHC bus voter clock */
 262         struct clk *xo_clk;     /* TCXO clk needed for FLL feature of cm_dll*/
 263         struct clk_bulk_data bulk_clks[4]; /* core, iface, cal, sleep clocks */
 264         unsigned long clk_rate;
 265         struct mmc_host *mmc;
 266         struct opp_table *opp_table;
 267         bool use_14lpp_dll_reset;
 268         bool tuning_done;
 269         bool calibration_done;
 270         u8 saved_tuning_phase;
 271         bool use_cdclp533;
 272         u32 curr_pwr_state;
 273         u32 curr_io_level;
 274         wait_queue_head_t pwr_irq_wait;
 275         bool pwr_irq_flag;
 276         u32 caps_0;
 277         bool mci_removed;
 278         bool restore_dll_config;
 279         const struct sdhci_msm_variant_ops *var_ops;
 280         const struct sdhci_msm_offset *offset;
 281         bool use_cdr;
 282         u32 transfer_mode;
 283         bool updated_ddr_cfg;
 284         bool uses_tassadar_dll;
 285         u32 dll_config;
 286         u32 ddr_config;
 287         bool vqmmc_enabled;
 288 };
 289
 290 static const struct sdhci_msm_offset *sdhci_priv_msm_offset(struct sdhci_host *host)
 291 {
 292         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 293         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 294
 295         return msm_host->offset;
 296 }
 297
 298 /*
 299  * APIs to read/write to vendor specific registers which were there in the
 300  * core_mem region before MCI was removed.
 301  */
 302 static u32 sdhci_msm_mci_variant_readl_relaxed(struct sdhci_host *host,
 303                 u32 offset)
 304 {
 305         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 306         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 307
 308         return readl_relaxed(msm_host->core_mem + offset);
 309 }
 310
 311 static u32 sdhci_msm_v5_variant_readl_relaxed(struct sdhci_host *host,
 312                 u32 offset)
 313 {
 314         return readl_relaxed(host->ioaddr + offset);
 315 }
 316
 317 static void sdhci_msm_mci_variant_writel_relaxed(u32 val,
 318                 struct sdhci_host *host, u32 offset)
 319 {
 320         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 321         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 322
 323         writel_relaxed(val, msm_host->core_mem + offset);
 324 }
 325
 326 static void sdhci_msm_v5_variant_writel_relaxed(u32 val,
 327                 struct sdhci_host *host, u32 offset)
 328 {
 329         writel_relaxed(val, host->ioaddr + offset);
 330 }
 331
 332 static unsigned int msm_get_clock_rate_for_bus_mode(struct sdhci_host *host,
 333                                                     unsigned int clock)
 334 {
 335         struct mmc_ios ios = host->mmc->ios;
 336         /*
 337          * The SDHC requires internal clock frequency to be double the
 338          * actual clock that will be set for DDR mode. The controller
 339          * uses the faster clock(100/400MHz) for some of its parts and
 340          * send the actual required clock (50/200MHz) to the card.
 341          */
 342         if (ios.timing == MMC_TIMING_UHS_DDR50 ||
 343             ios.timing == MMC_TIMING_MMC_DDR52 ||
 344             ios.timing == MMC_TIMING_MMC_HS400 ||
 345             host->flags & SDHCI_HS400_TUNING)
 346                 clock *= 2;
 347         return clock;
 348 }
 349
 350 static void msm_set_clock_rate_for_bus_mode(struct sdhci_host *host,
 351                                             unsigned int clock)
 352 {
 353         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 354         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 355         struct mmc_ios curr_ios = host->mmc->ios;
 356         struct clk *core_clk = msm_host->bulk_clks[0].clk;
 357         int rc;
 358
 359         clock = msm_get_clock_rate_for_bus_mode(host, clock);
 360         rc = dev_pm_opp_set_rate(mmc_dev(host->mmc), clock);
 361         if (rc) {
 362                 pr_err("%s: Failed to set clock at rate %u at timing %d\n",
 363                        mmc_hostname(host->mmc), clock,
 364                        curr_ios.timing);
 365                 return;
 366         }
 367         msm_host->clk_rate = clock;
 368         pr_debug("%s: Setting clock at rate %lu at timing %d\n",
 369                  mmc_hostname(host->mmc), clk_get_rate(core_clk),
 370                  curr_ios.timing);
 371 }
 372
 373 /* Platform specific tuning */
 374 static inline int msm_dll_poll_ck_out_en(struct sdhci_host *host, u8 poll)
 375 {
 376         u32 wait_cnt = 50;
 377         u8 ck_out_en;
 378         struct mmc_host *mmc = host->mmc;
 379         const struct sdhci_msm_offset *msm_offset =
 380                                         sdhci_priv_msm_offset(host);
 381
 382         /* Poll for CK_OUT_EN bit.  max. poll time = 50us */
 383         ck_out_en = !!(readl_relaxed(host->ioaddr +
 384                         msm_offset->core_dll_config) & CORE_CK_OUT_EN);
 385
 386         while (ck_out_en != poll) {
 387                 if (--wait_cnt == 0) {
 388                         dev_err(mmc_dev(mmc), "%s: CK_OUT_EN bit is not %d\n",
 389                                mmc_hostname(mmc), poll);
 390                         return -ETIMEDOUT;
 391                 }
 392                 udelay(1);
 393
 394                 ck_out_en = !!(readl_relaxed(host->ioaddr +
 395                         msm_offset->core_dll_config) & CORE_CK_OUT_EN);
 396         }
 397
 398         return 0;
 399 }
 400
 401 static int msm_config_cm_dll_phase(struct sdhci_host *host, u8 phase)
 402 {
 403         int rc;
 404         static const u8 grey_coded_phase_table[] = {
 405                 0x0, 0x1, 0x3, 0x2, 0x6, 0x7, 0x5, 0x4,
 406                 0xc, 0xd, 0xf, 0xe, 0xa, 0xb, 0x9, 0x8
 407         };
 408         unsigned long flags;
 409         u32 config;
 410         struct mmc_host *mmc = host->mmc;
 411         const struct sdhci_msm_offset *msm_offset =
 412                                         sdhci_priv_msm_offset(host);
 413
 414         if (phase > 0xf)
 415                 return -EINVAL;
 416
 417         spin_lock_irqsave(&host->lock, flags);
 418
 419         config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
 420         config &= ~(CORE_CDR_EN | CORE_CK_OUT_EN);
 421         config |= (CORE_CDR_EXT_EN | CORE_DLL_EN);
 422         writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
 423
 424         /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '0' */
 425         rc = msm_dll_poll_ck_out_en(host, 0);
 426         if (rc)
 427                 goto err_out;
 428
 429         /*
 430          * Write the selected DLL clock output phase (0 ... 15)
 431          * to CDR_SELEXT bit field of DLL_CONFIG register.
 432          */
 433         config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
 434         config &= ~CDR_SELEXT_MASK;
 435         config |= grey_coded_phase_table[phase] << CDR_SELEXT_SHIFT;
 436         writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
 437
 438         config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
 439         config |= CORE_CK_OUT_EN;
 440         writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
 441
 442         /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '1' */
 443         rc = msm_dll_poll_ck_out_en(host, 1);
 444         if (rc)
 445                 goto err_out;
 446
 447         config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
 448         config |= CORE_CDR_EN;
 449         config &= ~CORE_CDR_EXT_EN;
 450         writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
 451         goto out;
 452
 453 err_out:
 454         dev_err(mmc_dev(mmc), "%s: Failed to set DLL phase: %d\n",
 455                mmc_hostname(mmc), phase);
 456 out:
 457         spin_unlock_irqrestore(&host->lock, flags);
 458         return rc;
 459 }
 460
 461 /*
 462  * Find out the greatest range of consecuitive selected
 463  * DLL clock output phases that can be used as sampling
 464  * setting for SD3.0 UHS-I card read operation (in SDR104
 465  * timing mode) or for eMMC4.5 card read operation (in
 466  * HS400/HS200 timing mode).
 467  * Select the 3/4 of the range and configure the DLL with the
 468  * selected DLL clock output phase.
 469  */
 470
 471 static int msm_find_most_appropriate_phase(struct sdhci_host *host,
 472                                            u8 *phase_table, u8 total_phases)
 473 {
 474         int ret;
 475         u8 ranges[MAX_PHASES][MAX_PHASES] = { {0}, {0} };
 476         u8 phases_per_row[MAX_PHASES] = { 0 };
 477         int row_index = 0, col_index = 0, selected_row_index = 0, curr_max = 0;
 478         int i, cnt, phase_0_raw_index = 0, phase_15_raw_index = 0;
 479         bool phase_0_found = false, phase_15_found = false;
 480         struct mmc_host *mmc = host->mmc;
 481
 482         if (!total_phases || (total_phases > MAX_PHASES)) {
 483                 dev_err(mmc_dev(mmc), "%s: Invalid argument: total_phases=%d\n",
 484                        mmc_hostname(mmc), total_phases);
 485                 return -EINVAL;
 486         }
 487
 488         for (cnt = 0; cnt < total_phases; cnt++) {
 489                 ranges[row_index][col_index] = phase_table[cnt];
 490                 phases_per_row[row_index] += 1;
 491                 col_index++;
 492
 493                 if ((cnt + 1) == total_phases) {
 494                         continue;
 495                 /* check if next phase in phase_table is consecutive or not */
 496                 } else if ((phase_table[cnt] + 1) != phase_table[cnt + 1]) {
 497                         row_index++;
 498                         col_index = 0;
 499                 }
 500         }
 501
 502         if (row_index >= MAX_PHASES)
 503                 return -EINVAL;
 504
 505         /* Check if phase-0 is present in first valid window? */
 506         if (!ranges[0][0]) {
 507                 phase_0_found = true;
 508                 phase_0_raw_index = 0;
 509                 /* Check if cycle exist between 2 valid windows */
 510                 for (cnt = 1; cnt <= row_index; cnt++) {
 511                         if (phases_per_row[cnt]) {
 512                                 for (i = 0; i < phases_per_row[cnt]; i++) {
 513                                         if (ranges[cnt][i] == 15) {
 514                                                 phase_15_found = true;
 515                                                 phase_15_raw_index = cnt;
 516                                                 break;
 517                                         }
 518                                 }
 519                         }
 520                 }
 521         }
 522
 523         /* If 2 valid windows form cycle then merge them as single window */
 524         if (phase_0_found && phase_15_found) {
 525                 /* number of phases in raw where phase 0 is present */
 526                 u8 phases_0 = phases_per_row[phase_0_raw_index];
 527                 /* number of phases in raw where phase 15 is present */
 528                 u8 phases_15 = phases_per_row[phase_15_raw_index];
 529
 530                 if (phases_0 + phases_15 >= MAX_PHASES)
 531                         /*
 532                          * If there are more than 1 phase windows then total
 533                          * number of phases in both the windows should not be
 534                          * more than or equal to MAX_PHASES.
 535                          */
 536                         return -EINVAL;
 537
 538                 /* Merge 2 cyclic windows */
 539                 i = phases_15;
 540                 for (cnt = 0; cnt < phases_0; cnt++) {
 541                         ranges[phase_15_raw_index][i] =
 542                             ranges[phase_0_raw_index][cnt];
 543                         if (++i >= MAX_PHASES)
 544                                 break;
 545                 }
 546
 547                 phases_per_row[phase_0_raw_index] = 0;
 548                 phases_per_row[phase_15_raw_index] = phases_15 + phases_0;
 549         }
 550
 551         for (cnt = 0; cnt <= row_index; cnt++) {
 552                 if (phases_per_row[cnt] > curr_max) {
 553                         curr_max = phases_per_row[cnt];
 554                         selected_row_index = cnt;
 555                 }
 556         }
 557
 558         i = (curr_max * 3) / 4;
 559         if (i)
 560                 i--;
 561
 562         ret = ranges[selected_row_index][i];
 563
 564         if (ret >= MAX_PHASES) {
 565                 ret = -EINVAL;
 566                 dev_err(mmc_dev(mmc), "%s: Invalid phase selected=%d\n",
 567                        mmc_hostname(mmc), ret);
 568         }
 569
 570         return ret;
 571 }
 572
 573 static inline void msm_cm_dll_set_freq(struct sdhci_host *host)
 574 {
 575         u32 mclk_freq = 0, config;
 576         const struct sdhci_msm_offset *msm_offset =
 577                                         sdhci_priv_msm_offset(host);
 578
 579         /* Program the MCLK value to MCLK_FREQ bit field */
 580         if (host->clock <= 112000000)
 581                 mclk_freq = 0;
 582         else if (host->clock <= 125000000)
 583                 mclk_freq = 1;
 584         else if (host->clock <= 137000000)
 585                 mclk_freq = 2;
 586         else if (host->clock <= 150000000)
 587                 mclk_freq = 3;
 588         else if (host->clock <= 162000000)
 589                 mclk_freq = 4;
 590         else if (host->clock <= 175000000)
 591                 mclk_freq = 5;
 592         else if (host->clock <= 187000000)
 593                 mclk_freq = 6;
 594         else if (host->clock <= 200000000)
 595                 mclk_freq = 7;
 596
 597         config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
 598         config &= ~CMUX_SHIFT_PHASE_MASK;
 599         config |= mclk_freq << CMUX_SHIFT_PHASE_SHIFT;
 600         writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
 601 }
 602
 603 /* Initialize the DLL (Programmable Delay Line) */
 604 static int msm_init_cm_dll(struct sdhci_host *host)
 605 {
 606         struct mmc_host *mmc = host->mmc;
 607         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 608         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 609         int wait_cnt = 50;
 610         unsigned long flags, xo_clk = 0;
 611         u32 config;
 612         const struct sdhci_msm_offset *msm_offset =
 613                                         msm_host->offset;
 614
 615         if (msm_host->use_14lpp_dll_reset && !IS_ERR_OR_NULL(msm_host->xo_clk))
 616                 xo_clk = clk_get_rate(msm_host->xo_clk);
 617
 618         spin_lock_irqsave(&host->lock, flags);
 619
 620         /*
 621          * Make sure that clock is always enabled when DLL
 622          * tuning is in progress. Keeping PWRSAVE ON may
 623          * turn off the clock.
 624          */
 625         config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
 626         config &= ~CORE_CLK_PWRSAVE;
 627         writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
 628
 629         if (msm_host->dll_config)
 630                 writel_relaxed(msm_host->dll_config,
 631                                 host->ioaddr + msm_offset->core_dll_config);
 632
 633         if (msm_host->use_14lpp_dll_reset) {
 634                 config = readl_relaxed(host->ioaddr +
 635                                 msm_offset->core_dll_config);
 636                 config &= ~CORE_CK_OUT_EN;
 637                 writel_relaxed(config, host->ioaddr +
 638                                 msm_offset->core_dll_config);
 639
 640                 config = readl_relaxed(host->ioaddr +
 641                                 msm_offset->core_dll_config_2);
 642                 config |= CORE_DLL_CLOCK_DISABLE;
 643                 writel_relaxed(config, host->ioaddr +
 644                                 msm_offset->core_dll_config_2);
 645         }
 646
 647         config = readl_relaxed(host->ioaddr +
 648                         msm_offset->core_dll_config);
 649         config |= CORE_DLL_RST;
 650         writel_relaxed(config, host->ioaddr +
 651                         msm_offset->core_dll_config);
 652
 653         config = readl_relaxed(host->ioaddr +
 654                         msm_offset->core_dll_config);
 655         config |= CORE_DLL_PDN;
 656         writel_relaxed(config, host->ioaddr +
 657                         msm_offset->core_dll_config);
 658
 659         if (!msm_host->dll_config)
 660                 msm_cm_dll_set_freq(host);
 661
 662         if (msm_host->use_14lpp_dll_reset &&
 663             !IS_ERR_OR_NULL(msm_host->xo_clk)) {
 664                 u32 mclk_freq = 0;
 665
 666                 config = readl_relaxed(host->ioaddr +
 667                                 msm_offset->core_dll_config_2);
 668                 config &= CORE_FLL_CYCLE_CNT;
 669                 if (config)
 670                         mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 8),
 671                                         xo_clk);
 672                 else
 673                         mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 4),
 674                                         xo_clk);
 675
 676                 config = readl_relaxed(host->ioaddr +
 677                                 msm_offset->core_dll_config_2);
 678                 config &= ~(0xFF << 10);
 679                 config |= mclk_freq << 10;
 680
 681                 writel_relaxed(config, host->ioaddr +
 682                                 msm_offset->core_dll_config_2);
 683                 /* wait for 5us before enabling DLL clock */
 684                 udelay(5);
 685         }
 686
 687         config = readl_relaxed(host->ioaddr +
 688                         msm_offset->core_dll_config);
 689         config &= ~CORE_DLL_RST;
 690         writel_relaxed(config, host->ioaddr +
 691                         msm_offset->core_dll_config);
 692
 693         config = readl_relaxed(host->ioaddr +
 694                         msm_offset->core_dll_config);
 695         config &= ~CORE_DLL_PDN;
 696         writel_relaxed(config, host->ioaddr +
 697                         msm_offset->core_dll_config);
 698
 699         if (msm_host->use_14lpp_dll_reset) {
 700                 if (!msm_host->dll_config)
 701                         msm_cm_dll_set_freq(host);
 702                 config = readl_relaxed(host->ioaddr +
 703                                 msm_offset->core_dll_config_2);
 704                 config &= ~CORE_DLL_CLOCK_DISABLE;
 705                 writel_relaxed(config, host->ioaddr +
 706                                 msm_offset->core_dll_config_2);
 707         }
 708
 709         /*
 710          * Configure DLL user control register to enable DLL status.
 711          * This setting is applicable to SDCC v5.1 onwards only.
 712          */
 713         if (msm_host->uses_tassadar_dll) {
 714                 config = DLL_USR_CTL_POR_VAL | FINE_TUNE_MODE_EN |
 715                         ENABLE_DLL_LOCK_STATUS | BIAS_OK_SIGNAL;
 716                 writel_relaxed(config, host->ioaddr +
 717                                 msm_offset->core_dll_usr_ctl);
 718
 719                 config = readl_relaxed(host->ioaddr +
 720                                 msm_offset->core_dll_config_3);
 721                 config &= ~0xFF;
 722                 if (msm_host->clk_rate < 150000000)
 723                         config |= DLL_CONFIG_3_LOW_FREQ_VAL;
 724                 else
 725                         config |= DLL_CONFIG_3_HIGH_FREQ_VAL;
 726                 writel_relaxed(config, host->ioaddr +
 727                         msm_offset->core_dll_config_3);
 728         }
 729
 730         config = readl_relaxed(host->ioaddr +
 731                         msm_offset->core_dll_config);
 732         config |= CORE_DLL_EN;
 733         writel_relaxed(config, host->ioaddr +
 734                         msm_offset->core_dll_config);
 735
 736         config = readl_relaxed(host->ioaddr +
 737                         msm_offset->core_dll_config);
 738         config |= CORE_CK_OUT_EN;
 739         writel_relaxed(config, host->ioaddr +
 740                         msm_offset->core_dll_config);
 741
 742         /* Wait until DLL_LOCK bit of DLL_STATUS register becomes '1' */
 743         while (!(readl_relaxed(host->ioaddr + msm_offset->core_dll_status) &
 744                  CORE_DLL_LOCK)) {
 745                 /* max. wait for 50us sec for LOCK bit to be set */
 746                 if (--wait_cnt == 0) {
 747                         dev_err(mmc_dev(mmc), "%s: DLL failed to LOCK\n",
 748                                mmc_hostname(mmc));
 749                         spin_unlock_irqrestore(&host->lock, flags);
 750                         return -ETIMEDOUT;
 751                 }
 752                 udelay(1);
 753         }
 754
 755         spin_unlock_irqrestore(&host->lock, flags);
 756         return 0;
 757 }
 758
 759 static void msm_hc_select_default(struct sdhci_host *host)
 760 {
 761         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 762         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 763         u32 config;
 764         const struct sdhci_msm_offset *msm_offset =
 765                                         msm_host->offset;
 766
 767         if (!msm_host->use_cdclp533) {
 768                 config = readl_relaxed(host->ioaddr +
 769                                 msm_offset->core_vendor_spec3);
 770                 config &= ~CORE_PWRSAVE_DLL;
 771                 writel_relaxed(config, host->ioaddr +
 772                                 msm_offset->core_vendor_spec3);
 773         }
 774
 775         config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
 776         config &= ~CORE_HC_MCLK_SEL_MASK;
 777         config |= CORE_HC_MCLK_SEL_DFLT;
 778         writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
 779
 780         /*
 781          * Disable HC_SELECT_IN to be able to use the UHS mode select
 782          * configuration from Host Control2 register for all other
 783          * modes.
 784          * Write 0 to HC_SELECT_IN and HC_SELECT_IN_EN field
 785          * in VENDOR_SPEC_FUNC
 786          */
 787         config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
 788         config &= ~CORE_HC_SELECT_IN_EN;
 789         config &= ~CORE_HC_SELECT_IN_MASK;
 790         writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
 791
 792         /*
 793          * Make sure above writes impacting free running MCLK are completed
 794          * before changing the clk_rate at GCC.
 795          */
 796         wmb();
 797 }
 798
 799 static void msm_hc_select_hs400(struct sdhci_host *host)
 800 {
 801         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 802         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 803         struct mmc_ios ios = host->mmc->ios;
 804         u32 config, dll_lock;
 805         int rc;
 806         const struct sdhci_msm_offset *msm_offset =
 807                                         msm_host->offset;
 808
 809         /* Select the divided clock (free running MCLK/2) */
 810         config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
 811         config &= ~CORE_HC_MCLK_SEL_MASK;
 812         config |= CORE_HC_MCLK_SEL_HS400;
 813
 814         writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
 815         /*
 816          * Select HS400 mode using the HC_SELECT_IN from VENDOR SPEC
 817          * register
 818          */
 819         if ((msm_host->tuning_done || ios.enhanced_strobe) &&
 820             !msm_host->calibration_done) {
 821                 config = readl_relaxed(host->ioaddr +
 822                                 msm_offset->core_vendor_spec);
 823                 config |= CORE_HC_SELECT_IN_HS400;
 824                 config |= CORE_HC_SELECT_IN_EN;
 825                 writel_relaxed(config, host->ioaddr +
 826                                 msm_offset->core_vendor_spec);
 827         }
 828         if (!msm_host->clk_rate && !msm_host->use_cdclp533) {
 829                 /*
 830                  * Poll on DLL_LOCK or DDR_DLL_LOCK bits in
 831                  * core_dll_status to be set. This should get set
 832                  * within 15 us at 200 MHz.
 833                  */
 834                 rc = readl_relaxed_poll_timeout(host->ioaddr +
 835                                                 msm_offset->core_dll_status,
 836                                                 dll_lock,
 837                                                 (dll_lock &
 838                                                 (CORE_DLL_LOCK |
 839                                                 CORE_DDR_DLL_LOCK)), 10,
 840                                                 1000);
 841                 if (rc == -ETIMEDOUT)
 842                         pr_err("%s: Unable to get DLL_LOCK/DDR_DLL_LOCK, dll_status: 0x%08x\n",
 843                                mmc_hostname(host->mmc), dll_lock);
 844         }
 845         /*
 846          * Make sure above writes impacting free running MCLK are completed
 847          * before changing the clk_rate at GCC.
 848          */
 849         wmb();
 850 }
 851
 852 /*
 853  * sdhci_msm_hc_select_mode :- In general all timing modes are
 854  * controlled via UHS mode select in Host Control2 register.
 855  * eMMC specific HS200/HS400 doesn't have their respective modes
 856  * defined here, hence we use these values.
 857  *
 858  * HS200 - SDR104 (Since they both are equivalent in functionality)
 859  * HS400 - This involves multiple configurations
 860  *              Initially SDR104 - when tuning is required as HS200
 861  *              Then when switching to DDR @ 400MHz (HS400) we use
 862  *              the vendor specific HC_SELECT_IN to control the mode.
 863  *
 864  * In addition to controlling the modes we also need to select the
 865  * correct input clock for DLL depending on the mode.
 866  *
 867  * HS400 - divided clock (free running MCLK/2)
 868  * All other modes - default (free running MCLK)
 869  */
 870 static void sdhci_msm_hc_select_mode(struct sdhci_host *host)
 871 {
 872         struct mmc_ios ios = host->mmc->ios;
 873
 874         if (ios.timing == MMC_TIMING_MMC_HS400 ||
 875             host->flags & SDHCI_HS400_TUNING)
 876                 msm_hc_select_hs400(host);
 877         else
 878                 msm_hc_select_default(host);
 879 }
 880
 881 static int sdhci_msm_cdclp533_calibration(struct sdhci_host *host)
 882 {
 883         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 884         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 885         u32 config, calib_done;
 886         int ret;
 887         const struct sdhci_msm_offset *msm_offset =
 888                                         msm_host->offset;
 889
 890         pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
 891
 892         /*
 893          * Retuning in HS400 (DDR mode) will fail, just reset the
 894          * tuning block and restore the saved tuning phase.
 895          */
 896         ret = msm_init_cm_dll(host);
 897         if (ret)
 898                 goto out;
 899
 900         /* Set the selected phase in delay line hw block */
 901         ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase);
 902         if (ret)
 903                 goto out;
 904
 905         config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
 906         config |= CORE_CMD_DAT_TRACK_SEL;
 907         writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
 908
 909         config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg);
 910         config &= ~CORE_CDC_T4_DLY_SEL;
 911         writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg);
 912
 913         config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG);
 914         config &= ~CORE_CDC_SWITCH_BYPASS_OFF;
 915         writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG);
 916
 917         config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG);
 918         config |= CORE_CDC_SWITCH_RC_EN;
 919         writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG);
 920
 921         config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg);
 922         config &= ~CORE_START_CDC_TRAFFIC;
 923         writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg);
 924
 925         /* Perform CDC Register Initialization Sequence */
 926
 927         writel_relaxed(0x11800EC, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
 928         writel_relaxed(0x3011111, host->ioaddr + CORE_CSR_CDC_CTLR_CFG1);
 929         writel_relaxed(0x1201000, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
 930         writel_relaxed(0x4, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG1);
 931         writel_relaxed(0xCB732020, host->ioaddr + CORE_CSR_CDC_REFCOUNT_CFG);
 932         writel_relaxed(0xB19, host->ioaddr + CORE_CSR_CDC_COARSE_CAL_CFG);
 933         writel_relaxed(0x4E2, host->ioaddr + CORE_CSR_CDC_DELAY_CFG);
 934         writel_relaxed(0x0, host->ioaddr + CORE_CDC_OFFSET_CFG);
 935         writel_relaxed(0x16334, host->ioaddr + CORE_CDC_SLAVE_DDA_CFG);
 936
 937         /* CDC HW Calibration */
 938
 939         config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
 940         config |= CORE_SW_TRIG_FULL_CALIB;
 941         writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
 942
 943         config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
 944         config &= ~CORE_SW_TRIG_FULL_CALIB;
 945         writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
 946
 947         config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
 948         config |= CORE_HW_AUTOCAL_ENA;
 949         writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
 950
 951         config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
 952         config |= CORE_TIMER_ENA;
 953         writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
 954
 955         ret = readl_relaxed_poll_timeout(host->ioaddr + CORE_CSR_CDC_STATUS0,
 956                                          calib_done,
 957                                          (calib_done & CORE_CALIBRATION_DONE),
 958                                          1, 50);
 959
 960         if (ret == -ETIMEDOUT) {
 961                 pr_err("%s: %s: CDC calibration was not completed\n",
 962                        mmc_hostname(host->mmc), __func__);
 963                 goto out;
 964         }
 965
 966         ret = readl_relaxed(host->ioaddr + CORE_CSR_CDC_STATUS0)
 967                         & CORE_CDC_ERROR_CODE_MASK;
 968         if (ret) {
 969                 pr_err("%s: %s: CDC error code %d\n",
 970                        mmc_hostname(host->mmc), __func__, ret);
 971                 ret = -EINVAL;
 972                 goto out;
 973         }
 974
 975         config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg);
 976         config |= CORE_START_CDC_TRAFFIC;
 977         writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg);
 978 out:
 979         pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
 980                  __func__, ret);
 981         return ret;
 982 }
 983
 984 static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host *host)
 985 {
 986         struct mmc_host *mmc = host->mmc;
 987         u32 dll_status, config, ddr_cfg_offset;
 988         int ret;
 989         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 990         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 991         const struct sdhci_msm_offset *msm_offset =
 992                                         sdhci_priv_msm_offset(host);
 993
 994         pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
 995
 996         /*
 997          * Currently the core_ddr_config register defaults to desired
 998          * configuration on reset. Currently reprogramming the power on
 999          * reset (POR) value in case it might have been modified by
1000          * bootloaders. In the future, if this changes, then the desired
1001          * values will need to be programmed appropriately.
1002          */
1003         if (msm_host->updated_ddr_cfg)
1004                 ddr_cfg_offset = msm_offset->core_ddr_config;
1005         else
1006                 ddr_cfg_offset = msm_offset->core_ddr_config_old;
1007         writel_relaxed(msm_host->ddr_config, host->ioaddr + ddr_cfg_offset);
1008
1009         if (mmc->ios.enhanced_strobe) {
1010                 config = readl_relaxed(host->ioaddr +
1011                                 msm_offset->core_ddr_200_cfg);
1012                 config |= CORE_CMDIN_RCLK_EN;
1013                 writel_relaxed(config, host->ioaddr +
1014                                 msm_offset->core_ddr_200_cfg);
1015         }
1016
1017         config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config_2);
1018         config |= CORE_DDR_CAL_EN;
1019         writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config_2);
1020
1021         ret = readl_relaxed_poll_timeout(host->ioaddr +
1022                                         msm_offset->core_dll_status,
1023                                         dll_status,
1024                                         (dll_status & CORE_DDR_DLL_LOCK),
1025                                         10, 1000);
1026
1027         if (ret == -ETIMEDOUT) {
1028                 pr_err("%s: %s: CM_DLL_SDC4 calibration was not completed\n",
1029                        mmc_hostname(host->mmc), __func__);
1030                 goto out;
1031         }
1032
1033         /*
1034          * Set CORE_PWRSAVE_DLL bit in CORE_VENDOR_SPEC3.
1035          * When MCLK is gated OFF, it is not gated for less than 0.5us
1036          * and MCLK must be switched on for at-least 1us before DATA
1037          * starts coming. Controllers with 14lpp and later tech DLL cannot
1038          * guarantee above requirement. So PWRSAVE_DLL should not be
1039          * turned on for host controllers using this DLL.
1040          */
1041         if (!msm_host->use_14lpp_dll_reset) {
1042                 config = readl_relaxed(host->ioaddr +
1043                                 msm_offset->core_vendor_spec3);
1044                 config |= CORE_PWRSAVE_DLL;
1045                 writel_relaxed(config, host->ioaddr +
1046                                 msm_offset->core_vendor_spec3);
1047         }
1048
1049         /*
1050          * Drain writebuffer to ensure above DLL calibration
1051          * and PWRSAVE DLL is enabled.
1052          */
1053         wmb();
1054 out:
1055         pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
1056                  __func__, ret);
1057         return ret;
1058 }
1059
1060 static int sdhci_msm_hs400_dll_calibration(struct sdhci_host *host)
1061 {
1062         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1063         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1064         struct mmc_host *mmc = host->mmc;
1065         int ret;
1066         u32 config;
1067         const struct sdhci_msm_offset *msm_offset =
1068                                         msm_host->offset;
1069
1070         pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
1071
1072         /*
1073          * Retuning in HS400 (DDR mode) will fail, just reset the
1074          * tuning block and restore the saved tuning phase.
1075          */
1076         ret = msm_init_cm_dll(host);
1077         if (ret)
1078                 goto out;
1079
1080         if (!mmc->ios.enhanced_strobe) {
1081                 /* Set the selected phase in delay line hw block */
1082                 ret = msm_config_cm_dll_phase(host,
1083                                               msm_host->saved_tuning_phase);
1084                 if (ret)
1085                         goto out;
1086                 config = readl_relaxed(host->ioaddr +
1087                                 msm_offset->core_dll_config);
1088                 config |= CORE_CMD_DAT_TRACK_SEL;
1089                 writel_relaxed(config, host->ioaddr +
1090                                 msm_offset->core_dll_config);
1091         }
1092
1093         if (msm_host->use_cdclp533)
1094                 ret = sdhci_msm_cdclp533_calibration(host);
1095         else
1096                 ret = sdhci_msm_cm_dll_sdc4_calibration(host);
1097 out:
1098         pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
1099                  __func__, ret);
1100         return ret;
1101 }
1102
1103 static bool sdhci_msm_is_tuning_needed(struct sdhci_host *host)
1104 {
1105         struct mmc_ios *ios = &host->mmc->ios;
1106
1107         /*
1108          * Tuning is required for SDR104, HS200 and HS400 cards and
1109          * if clock frequency is greater than 100MHz in these modes.
1110          */
1111         if (host->clock <= CORE_FREQ_100MHZ ||
1112             !(ios->timing == MMC_TIMING_MMC_HS400 ||
1113             ios->timing == MMC_TIMING_MMC_HS200 ||
1114             ios->timing == MMC_TIMING_UHS_SDR104) ||
1115             ios->enhanced_strobe)
1116                 return false;
1117
1118         return true;
1119 }
1120
1121 static int sdhci_msm_restore_sdr_dll_config(struct sdhci_host *host)
1122 {
1123         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1124         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1125         int ret;
1126
1127         /*
1128          * SDR DLL comes into picture only for timing modes which needs
1129          * tuning.
1130          */
1131         if (!sdhci_msm_is_tuning_needed(host))
1132                 return 0;
1133
1134         /* Reset the tuning block */
1135         ret = msm_init_cm_dll(host);
1136         if (ret)
1137                 return ret;
1138
1139         /* Restore the tuning block */
1140         ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase);
1141
1142         return ret;
1143 }
1144
1145 static void sdhci_msm_set_cdr(struct sdhci_host *host, bool enable)
1146 {
1147         const struct sdhci_msm_offset *msm_offset = sdhci_priv_msm_offset(host);
1148         u32 config, oldconfig = readl_relaxed(host->ioaddr +
1149                                               msm_offset->core_dll_config);
1150
1151         config = oldconfig;
1152         if (enable) {
1153                 config |= CORE_CDR_EN;
1154                 config &= ~CORE_CDR_EXT_EN;
1155         } else {
1156                 config &= ~CORE_CDR_EN;
1157                 config |= CORE_CDR_EXT_EN;
1158         }
1159
1160         if (config != oldconfig) {
1161                 writel_relaxed(config, host->ioaddr +
1162                                msm_offset->core_dll_config);
1163         }
1164 }
1165
1166 static int sdhci_msm_execute_tuning(struct mmc_host *mmc, u32 opcode)
1167 {
1168         struct sdhci_host *host = mmc_priv(mmc);
1169         int tuning_seq_cnt = 10;
1170         u8 phase, tuned_phases[16], tuned_phase_cnt = 0;
1171         int rc;
1172         struct mmc_ios ios = host->mmc->ios;
1173         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1174         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1175
1176         if (!sdhci_msm_is_tuning_needed(host)) {
1177                 msm_host->use_cdr = false;
1178                 sdhci_msm_set_cdr(host, false);
1179                 return 0;
1180         }
1181
1182         /* Clock-Data-Recovery used to dynamically adjust RX sampling point */
1183         msm_host->use_cdr = true;
1184
1185         /*
1186          * Clear tuning_done flag before tuning to ensure proper
1187          * HS400 settings.
1188          */
1189         msm_host->tuning_done = 0;
1190
1191         /*
1192          * For HS400 tuning in HS200 timing requires:
1193          * - select MCLK/2 in VENDOR_SPEC
1194          * - program MCLK to 400MHz (or nearest supported) in GCC
1195          */
1196         if (host->flags & SDHCI_HS400_TUNING) {
1197                 sdhci_msm_hc_select_mode(host);
1198                 msm_set_clock_rate_for_bus_mode(host, ios.clock);
1199                 host->flags &= ~SDHCI_HS400_TUNING;
1200         }
1201
1202 retry:
1203         /* First of all reset the tuning block */
1204         rc = msm_init_cm_dll(host);
1205         if (rc)
1206                 return rc;
1207
1208         phase = 0;
1209         do {
1210                 /* Set the phase in delay line hw block */
1211                 rc = msm_config_cm_dll_phase(host, phase);
1212                 if (rc)
1213                         return rc;
1214
1215                 rc = mmc_send_tuning(mmc, opcode, NULL);
1216                 if (!rc) {
1217                         /* Tuning is successful at this tuning point */
1218                         tuned_phases[tuned_phase_cnt++] = phase;
1219                         dev_dbg(mmc_dev(mmc), "%s: Found good phase = %d\n",
1220                                  mmc_hostname(mmc), phase);
1221                 }
1222         } while (++phase < ARRAY_SIZE(tuned_phases));
1223
1224         if (tuned_phase_cnt) {
1225                 if (tuned_phase_cnt == ARRAY_SIZE(tuned_phases)) {
1226                         /*
1227                          * All phases valid is _almost_ as bad as no phases
1228                          * valid.  Probably all phases are not really reliable
1229                          * but we didn't detect where the unreliable place is.
1230                          * That means we'll essentially be guessing and hoping
1231                          * we get a good phase.  Better to try a few times.
1232                          */
1233                         dev_dbg(mmc_dev(mmc), "%s: All phases valid; try again\n",
1234                                 mmc_hostname(mmc));
1235                         if (--tuning_seq_cnt) {
1236                                 tuned_phase_cnt = 0;
1237                                 goto retry;
1238                         }
1239                 }
1240
1241                 rc = msm_find_most_appropriate_phase(host, tuned_phases,
1242                                                      tuned_phase_cnt);
1243                 if (rc < 0)
1244                         return rc;
1245                 else
1246                         phase = rc;
1247
1248                 /*
1249                  * Finally set the selected phase in delay
1250                  * line hw block.
1251                  */
1252                 rc = msm_config_cm_dll_phase(host, phase);
1253                 if (rc)
1254                         return rc;
1255                 msm_host->saved_tuning_phase = phase;
1256                 dev_dbg(mmc_dev(mmc), "%s: Setting the tuning phase to %d\n",
1257                          mmc_hostname(mmc), phase);
1258         } else {
1259                 if (--tuning_seq_cnt)
1260                         goto retry;
1261                 /* Tuning failed */
1262                 dev_dbg(mmc_dev(mmc), "%s: No tuning point found\n",
1263                        mmc_hostname(mmc));
1264                 rc = -EIO;
1265         }
1266
1267         if (!rc)
1268                 msm_host->tuning_done = true;
1269         return rc;
1270 }
1271
1272 /*
1273  * sdhci_msm_hs400 - Calibrate the DLL for HS400 bus speed mode operation.
1274  * This needs to be done for both tuning and enhanced_strobe mode.
1275  * DLL operation is only needed for clock > 100MHz. For clock <= 100MHz
1276  * fixed feedback clock is used.
1277  */
1278 static void sdhci_msm_hs400(struct sdhci_host *host, struct mmc_ios *ios)
1279 {
1280         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1281         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1282         int ret;
1283
1284         if (host->clock > CORE_FREQ_100MHZ &&
1285             (msm_host->tuning_done || ios->enhanced_strobe) &&
1286             !msm_host->calibration_done) {
1287                 ret = sdhci_msm_hs400_dll_calibration(host);
1288                 if (!ret)
1289                         msm_host->calibration_done = true;
1290                 else
1291                         pr_err("%s: Failed to calibrate DLL for hs400 mode (%d)\n",
1292                                mmc_hostname(host->mmc), ret);
1293         }
1294 }
1295
1296 static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host,
1297                                         unsigned int uhs)
1298 {
1299         struct mmc_host *mmc = host->mmc;
1300         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1301         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1302         u16 ctrl_2;
1303         u32 config;
1304         const struct sdhci_msm_offset *msm_offset =
1305                                         msm_host->offset;
1306
1307         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1308         /* Select Bus Speed Mode for host */
1309         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1310         switch (uhs) {
1311         case MMC_TIMING_UHS_SDR12:
1312                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1313                 break;
1314         case MMC_TIMING_UHS_SDR25:
1315                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1316                 break;
1317         case MMC_TIMING_UHS_SDR50:
1318                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1319                 break;
1320         case MMC_TIMING_MMC_HS400:
1321         case MMC_TIMING_MMC_HS200:
1322         case MMC_TIMING_UHS_SDR104:
1323                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1324                 break;
1325         case MMC_TIMING_UHS_DDR50:
1326         case MMC_TIMING_MMC_DDR52:
1327                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1328                 break;
1329         }
1330
1331         /*
1332          * When clock frequency is less than 100MHz, the feedback clock must be
1333          * provided and DLL must not be used so that tuning can be skipped. To
1334          * provide feedback clock, the mode selection can be any value less
1335          * than 3'b011 in bits [2:0] of HOST CONTROL2 register.
1336          */
1337         if (host->clock <= CORE_FREQ_100MHZ) {
1338                 if (uhs == MMC_TIMING_MMC_HS400 ||
1339                     uhs == MMC_TIMING_MMC_HS200 ||
1340                     uhs == MMC_TIMING_UHS_SDR104)
1341                         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1342                 /*
1343                  * DLL is not required for clock <= 100MHz
1344                  * Thus, make sure DLL it is disabled when not required
1345                  */
1346                 config = readl_relaxed(host->ioaddr +
1347                                 msm_offset->core_dll_config);
1348                 config |= CORE_DLL_RST;
1349                 writel_relaxed(config, host->ioaddr +
1350                                 msm_offset->core_dll_config);
1351
1352                 config = readl_relaxed(host->ioaddr +
1353                                 msm_offset->core_dll_config);
1354                 config |= CORE_DLL_PDN;
1355                 writel_relaxed(config, host->ioaddr +
1356                                 msm_offset->core_dll_config);
1357
1358                 /*
1359                  * The DLL needs to be restored and CDCLP533 recalibrated
1360                  * when the clock frequency is set back to 400MHz.
1361                  */
1362                 msm_host->calibration_done = false;
1363         }
1364
1365         dev_dbg(mmc_dev(mmc), "%s: clock=%u uhs=%u ctrl_2=0x%x\n",
1366                 mmc_hostname(host->mmc), host->clock, uhs, ctrl_2);
1367         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1368
1369         if (mmc->ios.timing == MMC_TIMING_MMC_HS400)
1370                 sdhci_msm_hs400(host, &mmc->ios);
1371 }
1372
1373 static int sdhci_msm_set_pincfg(struct sdhci_msm_host *msm_host, bool level)
1374 {
1375         struct platform_device *pdev = msm_host->pdev;
1376         int ret;
1377
1378         if (level)
1379                 ret = pinctrl_pm_select_default_state(&pdev->dev);
1380         else
1381                 ret = pinctrl_pm_select_sleep_state(&pdev->dev);
1382
1383         return ret;
1384 }
1385
1386 static int sdhci_msm_set_vmmc(struct mmc_host *mmc)
1387 {
1388         if (IS_ERR(mmc->supply.vmmc))
1389                 return 0;
1390
1391         return mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, mmc->ios.vdd);
1392 }
1393
1394 static int msm_toggle_vqmmc(struct sdhci_msm_host *msm_host,
1395                               struct mmc_host *mmc, bool level)
1396 {
1397         int ret;
1398         struct mmc_ios ios;
1399
1400         if (msm_host->vqmmc_enabled == level)
1401                 return 0;
1402
1403         if (level) {
1404                 /* Set the IO voltage regulator to default voltage level */
1405                 if (msm_host->caps_0 & CORE_3_0V_SUPPORT)
1406                         ios.signal_voltage = MMC_SIGNAL_VOLTAGE_330;
1407                 else if (msm_host->caps_0 & CORE_1_8V_SUPPORT)
1408                         ios.signal_voltage = MMC_SIGNAL_VOLTAGE_180;
1409
1410                 if (msm_host->caps_0 & CORE_VOLT_SUPPORT) {
1411                         ret = mmc_regulator_set_vqmmc(mmc, &ios);
1412                         if (ret < 0) {
1413                                 dev_err(mmc_dev(mmc), "%s: vqmmc set volgate failed: %d\n",
1414                                         mmc_hostname(mmc), ret);
1415                                 goto out;
1416                         }
1417                 }
1418                 ret = regulator_enable(mmc->supply.vqmmc);
1419         } else {
1420                 ret = regulator_disable(mmc->supply.vqmmc);
1421         }
1422
1423         if (ret)
1424                 dev_err(mmc_dev(mmc), "%s: vqmm %sable failed: %d\n",
1425                         mmc_hostname(mmc), level ? "en":"dis", ret);
1426         else
1427                 msm_host->vqmmc_enabled = level;
1428 out:
1429         return ret;
1430 }
1431
1432 static int msm_config_vqmmc_mode(struct sdhci_msm_host *msm_host,
1433                               struct mmc_host *mmc, bool hpm)
1434 {
1435         int load, ret;
1436
1437         load = hpm ? MMC_VQMMC_MAX_LOAD_UA : 0;
1438         ret = regulator_set_load(mmc->supply.vqmmc, load);
1439         if (ret)
1440                 dev_err(mmc_dev(mmc), "%s: vqmmc set load failed: %d\n",
1441                         mmc_hostname(mmc), ret);
1442         return ret;
1443 }
1444
1445 static int sdhci_msm_set_vqmmc(struct sdhci_msm_host *msm_host,
1446                               struct mmc_host *mmc, bool level)
1447 {
1448         int ret;
1449         bool always_on;
1450
1451         if (IS_ERR(mmc->supply.vqmmc) ||
1452                         (mmc->ios.power_mode == MMC_POWER_UNDEFINED))
1453                 return 0;
1454         /*
1455          * For eMMC don't turn off Vqmmc, Instead just configure it in LPM
1456          * and HPM modes by setting the corresponding load.
1457          *
1458          * Till eMMC is initialized (i.e. always_on == 0), just turn on/off
1459          * Vqmmc. Vqmmc gets turned off only if init fails and mmc_power_off
1460          * gets invoked. Once eMMC is initialized (i.e. always_on == 1),
1461          * Vqmmc should remain ON, So just set the load instead of turning it
1462          * off/on.
1463          */
1464         always_on = !mmc_card_is_removable(mmc) &&
1465                         mmc->card && mmc_card_mmc(mmc->card);
1466
1467         if (always_on)
1468                 ret = msm_config_vqmmc_mode(msm_host, mmc, level);
1469         else
1470                 ret = msm_toggle_vqmmc(msm_host, mmc, level);
1471
1472         return ret;
1473 }
1474
1475 static inline void sdhci_msm_init_pwr_irq_wait(struct sdhci_msm_host *msm_host)
1476 {
1477         init_waitqueue_head(&msm_host->pwr_irq_wait);
1478 }
1479
1480 static inline void sdhci_msm_complete_pwr_irq_wait(
1481                 struct sdhci_msm_host *msm_host)
1482 {
1483         wake_up(&msm_host->pwr_irq_wait);
1484 }
1485
1486 /*
1487  * sdhci_msm_check_power_status API should be called when registers writes
1488  * which can toggle sdhci IO bus ON/OFF or change IO lines HIGH/LOW happens.
1489  * To what state the register writes will change the IO lines should be passed
1490  * as the argument req_type. This API will check whether the IO line's state
1491  * is already the expected state and will wait for power irq only if
1492  * power irq is expected to be triggered based on the current IO line state
1493  * and expected IO line state.
1494  */
1495 static void sdhci_msm_check_power_status(struct sdhci_host *host, u32 req_type)
1496 {
1497         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1498         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1499         bool done = false;
1500         u32 val = SWITCHABLE_SIGNALING_VOLTAGE;
1501         const struct sdhci_msm_offset *msm_offset =
1502                                         msm_host->offset;
1503
1504         pr_debug("%s: %s: request %d curr_pwr_state %x curr_io_level %x\n",
1505                         mmc_hostname(host->mmc), __func__, req_type,
1506                         msm_host->curr_pwr_state, msm_host->curr_io_level);
1507
1508         /*
1509          * The power interrupt will not be generated for signal voltage
1510          * switches if SWITCHABLE_SIGNALING_VOLTAGE in MCI_GENERICS is not set.
1511          * Since sdhci-msm-v5, this bit has been removed and SW must consider
1512          * it as always set.
1513          */
1514         if (!msm_host->mci_removed)
1515                 val = msm_host_readl(msm_host, host,
1516                                 msm_offset->core_generics);
1517         if ((req_type & REQ_IO_HIGH || req_type & REQ_IO_LOW) &&
1518             !(val & SWITCHABLE_SIGNALING_VOLTAGE)) {
1519                 return;
1520         }
1521
1522         /*
1523          * The IRQ for request type IO High/LOW will be generated when -
1524          * there is a state change in 1.8V enable bit (bit 3) of
1525          * SDHCI_HOST_CONTROL2 register. The reset state of that bit is 0
1526          * which indicates 3.3V IO voltage. So, when MMC core layer tries
1527          * to set it to 3.3V before card detection happens, the
1528          * IRQ doesn't get triggered as there is no state change in this bit.
1529          * The driver already handles this case by changing the IO voltage
1530          * level to high as part of controller power up sequence. Hence, check
1531          * for host->pwr to handle a case where IO voltage high request is
1532          * issued even before controller power up.
1533          */
1534         if ((req_type & REQ_IO_HIGH) && !host->pwr) {
1535                 pr_debug("%s: do not wait for power IRQ that never comes, req_type: %d\n",
1536                                 mmc_hostname(host->mmc), req_type);
1537                 return;
1538         }
1539         if ((req_type & msm_host->curr_pwr_state) ||
1540                         (req_type & msm_host->curr_io_level))
1541                 done = true;
1542         /*
1543          * This is needed here to handle cases where register writes will
1544          * not change the current bus state or io level of the controller.
1545          * In this case, no power irq will be triggerred and we should
1546          * not wait.
1547          */
1548         if (!done) {
1549                 if (!wait_event_timeout(msm_host->pwr_irq_wait,
1550                                 msm_host->pwr_irq_flag,
1551                                 msecs_to_jiffies(MSM_PWR_IRQ_TIMEOUT_MS)))
1552                         dev_warn(&msm_host->pdev->dev,
1553                                  "%s: pwr_irq for req: (%d) timed out\n",
1554                                  mmc_hostname(host->mmc), req_type);
1555         }
1556         pr_debug("%s: %s: request %d done\n", mmc_hostname(host->mmc),
1557                         __func__, req_type);
1558 }
1559
1560 static void sdhci_msm_dump_pwr_ctrl_regs(struct sdhci_host *host)
1561 {
1562         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1563         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1564         const struct sdhci_msm_offset *msm_offset =
1565                                         msm_host->offset;
1566
1567         pr_err("%s: PWRCTL_STATUS: 0x%08x | PWRCTL_MASK: 0x%08x | PWRCTL_CTL: 0x%08x\n",
1568                 mmc_hostname(host->mmc),
1569                 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_status),
1570                 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_mask),
1571                 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_ctl));
1572 }
1573
1574 static void sdhci_msm_handle_pwr_irq(struct sdhci_host *host, int irq)
1575 {
1576         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1577         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1578         struct mmc_host *mmc = host->mmc;
1579         u32 irq_status, irq_ack = 0;
1580         int retry = 10, ret;
1581         u32 pwr_state = 0, io_level = 0;
1582         u32 config;
1583         const struct sdhci_msm_offset *msm_offset = msm_host->offset;
1584
1585         irq_status = msm_host_readl(msm_host, host,
1586                         msm_offset->core_pwrctl_status);
1587         irq_status &= INT_MASK;
1588
1589         msm_host_writel(msm_host, irq_status, host,
1590                         msm_offset->core_pwrctl_clear);
1591
1592         /*
1593          * There is a rare HW scenario where the first clear pulse could be
1594          * lost when actual reset and clear/read of status register is
1595          * happening at a time. Hence, retry for at least 10 times to make
1596          * sure status register is cleared. Otherwise, this will result in
1597          * a spurious power IRQ resulting in system instability.
1598          */
1599         while (irq_status & msm_host_readl(msm_host, host,
1600                                 msm_offset->core_pwrctl_status)) {
1601                 if (retry == 0) {
1602                         pr_err("%s: Timedout clearing (0x%x) pwrctl status register\n",
1603                                         mmc_hostname(host->mmc), irq_status);
1604                         sdhci_msm_dump_pwr_ctrl_regs(host);
1605                         WARN_ON(1);
1606                         break;
1607                 }
1608                 msm_host_writel(msm_host, irq_status, host,
1609                         msm_offset->core_pwrctl_clear);
1610                 retry--;
1611                 udelay(10);
1612         }
1613
1614         /* Handle BUS ON/OFF*/
1615         if (irq_status & CORE_PWRCTL_BUS_ON) {
1616                 pwr_state = REQ_BUS_ON;
1617                 io_level = REQ_IO_HIGH;
1618         }
1619         if (irq_status & CORE_PWRCTL_BUS_OFF) {
1620                 pwr_state = REQ_BUS_OFF;
1621                 io_level = REQ_IO_LOW;
1622         }
1623
1624         if (pwr_state) {
1625                 ret = sdhci_msm_set_vmmc(mmc);
1626                 if (!ret)
1627                         ret = sdhci_msm_set_vqmmc(msm_host, mmc,
1628                                         pwr_state & REQ_BUS_ON);
1629                 if (!ret)
1630                         ret = sdhci_msm_set_pincfg(msm_host,
1631                                         pwr_state & REQ_BUS_ON);
1632                 if (!ret)
1633                         irq_ack |= CORE_PWRCTL_BUS_SUCCESS;
1634                 else
1635                         irq_ack |= CORE_PWRCTL_BUS_FAIL;
1636         }
1637
1638         /* Handle IO LOW/HIGH */
1639         if (irq_status & CORE_PWRCTL_IO_LOW)
1640                 io_level = REQ_IO_LOW;
1641
1642         if (irq_status & CORE_PWRCTL_IO_HIGH)
1643                 io_level = REQ_IO_HIGH;
1644
1645         if (io_level)
1646                 irq_ack |= CORE_PWRCTL_IO_SUCCESS;
1647
1648         if (io_level && !IS_ERR(mmc->supply.vqmmc) && !pwr_state) {
1649                 ret = mmc_regulator_set_vqmmc(mmc, &mmc->ios);
1650                 if (ret < 0) {
1651                         dev_err(mmc_dev(mmc), "%s: IO_level setting failed(%d). signal_voltage: %d, vdd: %d irq_status: 0x%08x\n",
1652                                         mmc_hostname(mmc), ret,
1653                                         mmc->ios.signal_voltage, mmc->ios.vdd,
1654                                         irq_status);
1655                         irq_ack |= CORE_PWRCTL_IO_FAIL;
1656                 }
1657         }
1658
1659         /*
1660          * The driver has to acknowledge the interrupt, switch voltages and
1661          * report back if it succeded or not to this register. The voltage
1662          * switches are handled by the sdhci core, so just report success.
1663          */
1664         msm_host_writel(msm_host, irq_ack, host,
1665                         msm_offset->core_pwrctl_ctl);
1666
1667         /*
1668          * If we don't have info regarding the voltage levels supported by
1669          * regulators, don't change the IO PAD PWR SWITCH.
1670          */
1671         if (msm_host->caps_0 & CORE_VOLT_SUPPORT) {
1672                 u32 new_config;
1673                 /*
1674                  * We should unset IO PAD PWR switch only if the register write
1675                  * can set IO lines high and the regulator also switches to 3 V.
1676                  * Else, we should keep the IO PAD PWR switch set.
1677                  * This is applicable to certain targets where eMMC vccq supply
1678                  * is only 1.8V. In such targets, even during REQ_IO_HIGH, the
1679                  * IO PAD PWR switch must be kept set to reflect actual
1680                  * regulator voltage. This way, during initialization of
1681                  * controllers with only 1.8V, we will set the IO PAD bit
1682                  * without waiting for a REQ_IO_LOW.
1683                  */
1684                 config = readl_relaxed(host->ioaddr +
1685                                 msm_offset->core_vendor_spec);
1686                 new_config = config;
1687
1688                 if ((io_level & REQ_IO_HIGH) &&
1689                                 (msm_host->caps_0 & CORE_3_0V_SUPPORT))
1690                         new_config &= ~CORE_IO_PAD_PWR_SWITCH;
1691                 else if ((io_level & REQ_IO_LOW) ||
1692                                 (msm_host->caps_0 & CORE_1_8V_SUPPORT))
1693                         new_config |= CORE_IO_PAD_PWR_SWITCH;
1694
1695                 if (config ^ new_config)
1696                         writel_relaxed(new_config, host->ioaddr +
1697                                         msm_offset->core_vendor_spec);
1698         }
1699
1700         if (pwr_state)
1701                 msm_host->curr_pwr_state = pwr_state;
1702         if (io_level)
1703                 msm_host->curr_io_level = io_level;
1704
1705         dev_dbg(mmc_dev(mmc), "%s: %s: Handled IRQ(%d), irq_status=0x%x, ack=0x%x\n",
1706                 mmc_hostname(msm_host->mmc), __func__, irq, irq_status,
1707                 irq_ack);
1708 }
1709
1710 static irqreturn_t sdhci_msm_pwr_irq(int irq, void *data)
1711 {
1712         struct sdhci_host *host = (struct sdhci_host *)data;
1713         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1714         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1715
1716         sdhci_msm_handle_pwr_irq(host, irq);
1717         msm_host->pwr_irq_flag = 1;
1718         sdhci_msm_complete_pwr_irq_wait(msm_host);
1719
1720
1721         return IRQ_HANDLED;
1722 }
1723
1724 static unsigned int sdhci_msm_get_max_clock(struct sdhci_host *host)
1725 {
1726         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1727         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1728         struct clk *core_clk = msm_host->bulk_clks[0].clk;
1729
1730         return clk_round_rate(core_clk, ULONG_MAX);
1731 }
1732
1733 static unsigned int sdhci_msm_get_min_clock(struct sdhci_host *host)
1734 {
1735         return SDHCI_MSM_MIN_CLOCK;
1736 }
1737
1738 /*
1739  * __sdhci_msm_set_clock - sdhci_msm clock control.
1740  *
1741  * Description:
1742  * MSM controller does not use internal divider and
1743  * instead directly control the GCC clock as per
1744  * HW recommendation.
1745  **/
1746 static void __sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
1747 {
1748         u16 clk;
1749         /*
1750          * Keep actual_clock as zero -
1751          * - since there is no divider used so no need of having actual_clock.
1752          * - MSM controller uses SDCLK for data timeout calculation. If
1753          *   actual_clock is zero, host->clock is taken for calculation.
1754          */
1755         host->mmc->actual_clock = 0;
1756
1757         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1758
1759         if (clock == 0)
1760                 return;
1761
1762         /*
1763          * MSM controller do not use clock divider.
1764          * Thus read SDHCI_CLOCK_CONTROL and only enable
1765          * clock with no divider value programmed.
1766          */
1767         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1768         sdhci_enable_clk(host, clk);
1769 }
1770
1771 /* sdhci_msm_set_clock - Called with (host->lock) spinlock held. */
1772 static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
1773 {
1774         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1775         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1776
1777         if (!clock) {
1778                 msm_host->clk_rate = clock;
1779                 goto out;
1780         }
1781
1782         sdhci_msm_hc_select_mode(host);
1783
1784         msm_set_clock_rate_for_bus_mode(host, clock);
1785 out:
1786         __sdhci_msm_set_clock(host, clock);
1787 }
1788
1789 /*****************************************************************************\
1790  *                                                                           *
1791  * MSM Command Queue Engine (CQE)                                            *
1792  *                                                                           *
1793 \*****************************************************************************/
1794
1795 static u32 sdhci_msm_cqe_irq(struct sdhci_host *host, u32 intmask)
1796 {
1797         int cmd_error = 0;
1798         int data_error = 0;
1799
1800         if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
1801                 return intmask;
1802
1803         cqhci_irq(host->mmc, intmask, cmd_error, data_error);
1804         return 0;
1805 }
1806
1807 static void sdhci_msm_cqe_disable(struct mmc_host *mmc, bool recovery)
1808 {
1809         struct sdhci_host *host = mmc_priv(mmc);
1810         unsigned long flags;
1811         u32 ctrl;
1812
1813         /*
1814          * When CQE is halted, the legacy SDHCI path operates only
1815          * on 16-byte descriptors in 64bit mode.
1816          */
1817         if (host->flags & SDHCI_USE_64_BIT_DMA)
1818                 host->desc_sz = 16;
1819
1820         spin_lock_irqsave(&host->lock, flags);
1821
1822         /*
1823          * During CQE command transfers, command complete bit gets latched.
1824          * So s/w should clear command complete interrupt status when CQE is
1825          * either halted or disabled. Otherwise unexpected SDCHI legacy
1826          * interrupt gets triggered when CQE is halted/disabled.
1827          */
1828         ctrl = sdhci_readl(host, SDHCI_INT_ENABLE);
1829         ctrl |= SDHCI_INT_RESPONSE;
1830         sdhci_writel(host,  ctrl, SDHCI_INT_ENABLE);
1831         sdhci_writel(host, SDHCI_INT_RESPONSE, SDHCI_INT_STATUS);
1832
1833         spin_unlock_irqrestore(&host->lock, flags);
1834
1835         sdhci_cqe_disable(mmc, recovery);
1836 }
1837
1838 static void sdhci_msm_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
1839 {
1840         u32 count, start = 15;
1841
1842         __sdhci_set_timeout(host, cmd);
1843         count = sdhci_readb(host, SDHCI_TIMEOUT_CONTROL);
1844         /*
1845          * Update software timeout value if its value is less than hardware data
1846          * timeout value. Qcom SoC hardware data timeout value was calculated
1847          * using 4 * MCLK * 2^(count + 13). where MCLK = 1 / host->clock.
1848          */
1849         if (cmd && cmd->data && host->clock > 400000 &&
1850             host->clock <= 50000000 &&
1851             ((1 << (count + start)) > (10 * host->clock)))
1852                 host->data_timeout = 22LL * NSEC_PER_SEC;
1853 }
1854
1855 static const struct cqhci_host_ops sdhci_msm_cqhci_ops = {
1856         .enable         = sdhci_cqe_enable,
1857         .disable        = sdhci_msm_cqe_disable,
1858 };
1859
1860 static int sdhci_msm_cqe_add_host(struct sdhci_host *host,
1861                                 struct platform_device *pdev)
1862 {
1863         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1864         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1865         struct cqhci_host *cq_host;
1866         bool dma64;
1867         u32 cqcfg;
1868         int ret;
1869
1870         /*
1871          * When CQE is halted, SDHC operates only on 16byte ADMA descriptors.
1872          * So ensure ADMA table is allocated for 16byte descriptors.
1873          */
1874         if (host->caps & SDHCI_CAN_64BIT)
1875                 host->alloc_desc_sz = 16;
1876
1877         ret = sdhci_setup_host(host);
1878         if (ret)
1879                 return ret;
1880
1881         cq_host = cqhci_pltfm_init(pdev);
1882         if (IS_ERR(cq_host)) {
1883                 ret = PTR_ERR(cq_host);
1884                 dev_err(&pdev->dev, "cqhci-pltfm init: failed: %d\n", ret);
1885                 goto cleanup;
1886         }
1887
1888         msm_host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
1889         cq_host->ops = &sdhci_msm_cqhci_ops;
1890
1891         dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
1892
1893         ret = cqhci_init(cq_host, host->mmc, dma64);
1894         if (ret) {
1895                 dev_err(&pdev->dev, "%s: CQE init: failed (%d)\n",
1896                                 mmc_hostname(host->mmc), ret);
1897                 goto cleanup;
1898         }
1899
1900         /* Disable cqe reset due to cqe enable signal */
1901         cqcfg = cqhci_readl(cq_host, CQHCI_VENDOR_CFG1);
1902         cqcfg |= CQHCI_VENDOR_DIS_RST_ON_CQ_EN;
1903         cqhci_writel(cq_host, cqcfg, CQHCI_VENDOR_CFG1);
1904
1905         /*
1906          * SDHC expects 12byte ADMA descriptors till CQE is enabled.
1907          * So limit desc_sz to 12 so that the data commands that are sent
1908          * during card initialization (before CQE gets enabled) would
1909          * get executed without any issues.
1910          */
1911         if (host->flags & SDHCI_USE_64_BIT_DMA)
1912                 host->desc_sz = 12;
1913
1914         ret = __sdhci_add_host(host);
1915         if (ret)
1916                 goto cleanup;
1917
1918         dev_info(&pdev->dev, "%s: CQE init: success\n",
1919                         mmc_hostname(host->mmc));
1920         return ret;
1921
1922 cleanup:
1923         sdhci_cleanup_host(host);
1924         return ret;
1925 }
1926
1927 /*
1928  * Platform specific register write functions. This is so that, if any
1929  * register write needs to be followed up by platform specific actions,
1930  * they can be added here. These functions can go to sleep when writes
1931  * to certain registers are done.
1932  * These functions are relying on sdhci_set_ios not using spinlock.
1933  */
1934 static int __sdhci_msm_check_write(struct sdhci_host *host, u16 val, int reg)
1935 {
1936         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1937         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1938         u32 req_type = 0;
1939
1940         switch (reg) {
1941         case SDHCI_HOST_CONTROL2:
1942                 req_type = (val & SDHCI_CTRL_VDD_180) ? REQ_IO_LOW :
1943                         REQ_IO_HIGH;
1944                 break;
1945         case SDHCI_SOFTWARE_RESET:
1946                 if (host->pwr && (val & SDHCI_RESET_ALL))
1947                         req_type = REQ_BUS_OFF;
1948                 break;
1949         case SDHCI_POWER_CONTROL:
1950                 req_type = !val ? REQ_BUS_OFF : REQ_BUS_ON;
1951                 break;
1952         case SDHCI_TRANSFER_MODE:
1953                 msm_host->transfer_mode = val;
1954                 break;
1955         case SDHCI_COMMAND:
1956                 if (!msm_host->use_cdr)
1957                         break;
1958                 if ((msm_host->transfer_mode & SDHCI_TRNS_READ) &&
1959                     SDHCI_GET_CMD(val) != MMC_SEND_TUNING_BLOCK_HS200 &&
1960                     SDHCI_GET_CMD(val) != MMC_SEND_TUNING_BLOCK)
1961                         sdhci_msm_set_cdr(host, true);
1962                 else
1963                         sdhci_msm_set_cdr(host, false);
1964                 break;
1965         }
1966
1967         if (req_type) {
1968                 msm_host->pwr_irq_flag = 0;
1969                 /*
1970                  * Since this register write may trigger a power irq, ensure
1971                  * all previous register writes are complete by this point.
1972                  */
1973                 mb();
1974         }
1975         return req_type;
1976 }
1977
1978 /* This function may sleep*/
1979 static void sdhci_msm_writew(struct sdhci_host *host, u16 val, int reg)
1980 {
1981         u32 req_type = 0;
1982
1983         req_type = __sdhci_msm_check_write(host, val, reg);
1984         writew_relaxed(val, host->ioaddr + reg);
1985
1986         if (req_type)
1987                 sdhci_msm_check_power_status(host, req_type);
1988 }
1989
1990 /* This function may sleep*/
1991 static void sdhci_msm_writeb(struct sdhci_host *host, u8 val, int reg)
1992 {
1993         u32 req_type = 0;
1994
1995         req_type = __sdhci_msm_check_write(host, val, reg);
1996
1997         writeb_relaxed(val, host->ioaddr + reg);
1998
1999         if (req_type)
2000                 sdhci_msm_check_power_status(host, req_type);
2001 }
2002
2003 static void sdhci_msm_set_regulator_caps(struct sdhci_msm_host *msm_host)
2004 {
2005         struct mmc_host *mmc = msm_host->mmc;
2006         struct regulator *supply = mmc->supply.vqmmc;
2007         u32 caps = 0, config;
2008         struct sdhci_host *host = mmc_priv(mmc);
2009         const struct sdhci_msm_offset *msm_offset = msm_host->offset;
2010
2011         if (!IS_ERR(mmc->supply.vqmmc)) {
2012                 if (regulator_is_supported_voltage(supply, 1700000, 1950000))
2013                         caps |= CORE_1_8V_SUPPORT;
2014                 if (regulator_is_supported_voltage(supply, 2700000, 3600000))
2015                         caps |= CORE_3_0V_SUPPORT;
2016
2017                 if (!caps)
2018                         pr_warn("%s: 1.8/3V not supported for vqmmc\n",
2019                                         mmc_hostname(mmc));
2020         }
2021
2022         if (caps) {
2023                 /*
2024                  * Set the PAD_PWR_SWITCH_EN bit so that the PAD_PWR_SWITCH
2025                  * bit can be used as required later on.
2026                  */
2027                 u32 io_level = msm_host->curr_io_level;
2028
2029                 config = readl_relaxed(host->ioaddr +
2030                                 msm_offset->core_vendor_spec);
2031                 config |= CORE_IO_PAD_PWR_SWITCH_EN;
2032
2033                 if ((io_level & REQ_IO_HIGH) && (caps & CORE_3_0V_SUPPORT))
2034                         config &= ~CORE_IO_PAD_PWR_SWITCH;
2035                 else if ((io_level & REQ_IO_LOW) || (caps & CORE_1_8V_SUPPORT))
2036                         config |= CORE_IO_PAD_PWR_SWITCH;
2037
2038                 writel_relaxed(config,
2039                                 host->ioaddr + msm_offset->core_vendor_spec);
2040         }
2041         msm_host->caps_0 |= caps;
2042         pr_debug("%s: supported caps: 0x%08x\n", mmc_hostname(mmc), caps);
2043 }
2044
2045 static void sdhci_msm_reset(struct sdhci_host *host, u8 mask)
2046 {
2047         if ((host->mmc->caps2 & MMC_CAP2_CQE) && (mask & SDHCI_RESET_ALL))
2048                 cqhci_deactivate(host->mmc);
2049         sdhci_reset(host, mask);
2050 }
2051
2052 static int sdhci_msm_register_vreg(struct sdhci_msm_host *msm_host)
2053 {
2054         int ret;
2055
2056         ret = mmc_regulator_get_supply(msm_host->mmc);
2057         if (ret)
2058                 return ret;
2059
2060         sdhci_msm_set_regulator_caps(msm_host);
2061
2062         return 0;
2063 }
2064
2065 static int sdhci_msm_start_signal_voltage_switch(struct mmc_host *mmc,
2066                                       struct mmc_ios *ios)
2067 {
2068         struct sdhci_host *host = mmc_priv(mmc);
2069         u16 ctrl, status;
2070
2071         /*
2072          * Signal Voltage Switching is only applicable for Host Controllers
2073          * v3.00 and above.
2074          */
2075         if (host->version < SDHCI_SPEC_300)
2076                 return 0;
2077
2078         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2079
2080         switch (ios->signal_voltage) {
2081         case MMC_SIGNAL_VOLTAGE_330:
2082                 if (!(host->flags & SDHCI_SIGNALING_330))
2083                         return -EINVAL;
2084
2085                 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
2086                 ctrl &= ~SDHCI_CTRL_VDD_180;
2087                 break;
2088         case MMC_SIGNAL_VOLTAGE_180:
2089                 if (!(host->flags & SDHCI_SIGNALING_180))
2090                         return -EINVAL;
2091
2092                 /* Enable 1.8V Signal Enable in the Host Control2 register */
2093                 ctrl |= SDHCI_CTRL_VDD_180;
2094                 break;
2095
2096         default:
2097                 return -EINVAL;
2098         }
2099
2100         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2101
2102         /* Wait for 5ms */
2103         usleep_range(5000, 5500);
2104
2105         /* regulator output should be stable within 5 ms */
2106         status = ctrl & SDHCI_CTRL_VDD_180;
2107         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2108         if ((ctrl & SDHCI_CTRL_VDD_180) == status)
2109                 return 0;
2110
2111         dev_warn(mmc_dev(mmc), "%s: Regulator output did not became stable\n",
2112                 mmc_hostname(mmc));
2113
2114         return -EAGAIN;
2115 }
2116
2117 #define DRIVER_NAME "sdhci_msm"
2118 #define SDHCI_MSM_DUMP(f, x...) \
2119         pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
2120
2121 static void sdhci_msm_dump_vendor_regs(struct sdhci_host *host)
2122 {
2123         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2124         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
2125         const struct sdhci_msm_offset *msm_offset = msm_host->offset;
2126
2127         SDHCI_MSM_DUMP("----------- VENDOR REGISTER DUMP -----------\n");
2128
2129         SDHCI_MSM_DUMP(
2130                         "DLL sts: 0x%08x | DLL cfg:  0x%08x | DLL cfg2: 0x%08x\n",
2131                 readl_relaxed(host->ioaddr + msm_offset->core_dll_status),
2132                 readl_relaxed(host->ioaddr + msm_offset->core_dll_config),
2133                 readl_relaxed(host->ioaddr + msm_offset->core_dll_config_2));
2134         SDHCI_MSM_DUMP(
2135                         "DLL cfg3: 0x%08x | DLL usr ctl:  0x%08x | DDR cfg: 0x%08x\n",
2136                 readl_relaxed(host->ioaddr + msm_offset->core_dll_config_3),
2137                 readl_relaxed(host->ioaddr + msm_offset->core_dll_usr_ctl),
2138                 readl_relaxed(host->ioaddr + msm_offset->core_ddr_config));
2139         SDHCI_MSM_DUMP(
2140                         "Vndr func: 0x%08x | Vndr func2 : 0x%08x Vndr func3: 0x%08x\n",
2141                 readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec),
2142                 readl_relaxed(host->ioaddr +
2143                         msm_offset->core_vendor_spec_func2),
2144                 readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec3));
2145 }
2146
2147 static const struct sdhci_msm_variant_ops mci_var_ops = {
2148         .msm_readl_relaxed = sdhci_msm_mci_variant_readl_relaxed,
2149         .msm_writel_relaxed = sdhci_msm_mci_variant_writel_relaxed,
2150 };
2151
2152 static const struct sdhci_msm_variant_ops v5_var_ops = {
2153         .msm_readl_relaxed = sdhci_msm_v5_variant_readl_relaxed,
2154         .msm_writel_relaxed = sdhci_msm_v5_variant_writel_relaxed,
2155 };
2156
2157 static const struct sdhci_msm_variant_info sdhci_msm_mci_var = {
2158         .var_ops = &mci_var_ops,
2159         .offset = &sdhci_msm_mci_offset,
2160 };
2161
2162 static const struct sdhci_msm_variant_info sdhci_msm_v5_var = {
2163         .mci_removed = true,
2164         .var_ops = &v5_var_ops,
2165         .offset = &sdhci_msm_v5_offset,
2166 };
2167
2168 static const struct sdhci_msm_variant_info sdm845_sdhci_var = {
2169         .mci_removed = true,
2170         .restore_dll_config = true,
2171         .var_ops = &v5_var_ops,
2172         .offset = &sdhci_msm_v5_offset,
2173 };
2174
2175 static const struct sdhci_msm_variant_info sm8250_sdhci_var = {
2176         .mci_removed = true,
2177         .uses_tassadar_dll = true,
2178         .var_ops = &v5_var_ops,
2179         .offset = &sdhci_msm_v5_offset,
2180 };
2181
2182 static const struct of_device_id sdhci_msm_dt_match[] = {
2183         {.compatible = "qcom,sdhci-msm-v4", .data = &sdhci_msm_mci_var},
2184         {.compatible = "qcom,sdhci-msm-v5", .data = &sdhci_msm_v5_var},
2185         {.compatible = "qcom,sdm670-sdhci", .data = &sdm845_sdhci_var},
2186         {.compatible = "qcom,sdm845-sdhci", .data = &sdm845_sdhci_var},
2187         {.compatible = "qcom,sm8250-sdhci", .data = &sm8250_sdhci_var},
2188         {.compatible = "qcom,sc7180-sdhci", .data = &sdm845_sdhci_var},
2189         {},
2190 };
2191
2192 MODULE_DEVICE_TABLE(of, sdhci_msm_dt_match);
2193
2194 static const struct sdhci_ops sdhci_msm_ops = {
2195         .reset = sdhci_msm_reset,
2196         .set_clock = sdhci_msm_set_clock,
2197         .get_min_clock = sdhci_msm_get_min_clock,
2198         .get_max_clock = sdhci_msm_get_max_clock,
2199         .set_bus_width = sdhci_set_bus_width,
2200         .set_uhs_signaling = sdhci_msm_set_uhs_signaling,
2201         .write_w = sdhci_msm_writew,
2202         .write_b = sdhci_msm_writeb,
2203         .irq    = sdhci_msm_cqe_irq,
2204         .dump_vendor_regs = sdhci_msm_dump_vendor_regs,
2205         .set_power = sdhci_set_power_noreg,
2206         .set_timeout = sdhci_msm_set_timeout,
2207 };
2208
2209 static const struct sdhci_pltfm_data sdhci_msm_pdata = {
2210         .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
2211                   SDHCI_QUIRK_SINGLE_POWER_WRITE |
2212                   SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
2213                   SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
2214
2215         .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
2216         .ops = &sdhci_msm_ops,
2217 };
2218
2219 static inline void sdhci_msm_get_of_property(struct platform_device *pdev,
2220                 struct sdhci_host *host)
2221 {
2222         struct device_node *node = pdev->dev.of_node;
2223         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2224         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
2225
2226         if (of_property_read_u32(node, "qcom,ddr-config",
2227                                 &msm_host->ddr_config))
2228                 msm_host->ddr_config = DDR_CONFIG_POR_VAL;
2229
2230         of_property_read_u32(node, "qcom,dll-config", &msm_host->dll_config);
2231
2232         if (of_device_is_compatible(node, "qcom,msm8916-sdhci"))
2233                 host->quirks2 |= SDHCI_QUIRK2_BROKEN_64_BIT_DMA;
2234 }
2235
2236 static int sdhci_msm_gcc_reset(struct device *dev, struct sdhci_host *host)
2237 {
2238         struct reset_control *reset;
2239         int ret = 0;
2240
2241         reset = reset_control_get_optional_exclusive(dev, NULL);
2242         if (IS_ERR(reset))
2243                 return dev_err_probe(dev, PTR_ERR(reset),
2244                                 "unable to acquire core_reset\n");
2245
2246         if (!reset)
2247                 return ret;
2248
2249         ret = reset_control_assert(reset);
2250         if (ret) {
2251                 reset_control_put(reset);
2252                 return dev_err_probe(dev, ret, "core_reset assert failed\n");
2253         }
2254
2255         /*
2256          * The hardware requirement for delay between assert/deassert
2257          * is at least 3-4 sleep clock (32.7KHz) cycles, which comes to
2258          * ~125us (4/32768). To be on the safe side add 200us delay.
2259          */
2260         usleep_range(200, 210);
2261
2262         ret = reset_control_deassert(reset);
2263         if (ret) {
2264                 reset_control_put(reset);
2265                 return dev_err_probe(dev, ret, "core_reset deassert failed\n");
2266         }
2267
2268         usleep_range(200, 210);
2269         reset_control_put(reset);
2270
2271         return ret;
2272 }
2273
2274 static int sdhci_msm_probe(struct platform_device *pdev)
2275 {
2276         struct sdhci_host *host;
2277         struct sdhci_pltfm_host *pltfm_host;
2278         struct sdhci_msm_host *msm_host;
2279         struct clk *clk;
2280         int ret;
2281         u16 host_version, core_minor;
2282         u32 core_version, config;
2283         u8 core_major;
2284         const struct sdhci_msm_offset *msm_offset;
2285         const struct sdhci_msm_variant_info *var_info;
2286         struct device_node *node = pdev->dev.of_node;
2287
2288         host = sdhci_pltfm_init(pdev, &sdhci_msm_pdata, sizeof(*msm_host));
2289         if (IS_ERR(host))
2290                 return PTR_ERR(host);
2291
2292         host->sdma_boundary = 0;
2293         pltfm_host = sdhci_priv(host);
2294         msm_host = sdhci_pltfm_priv(pltfm_host);
2295         msm_host->mmc = host->mmc;
2296         msm_host->pdev = pdev;
2297
2298         ret = mmc_of_parse(host->mmc);
2299         if (ret)
2300                 goto pltfm_free;
2301
2302         /*
2303          * Based on the compatible string, load the required msm host info from
2304          * the data associated with the version info.
2305          */
2306         var_info = of_device_get_match_data(&pdev->dev);
2307
2308         msm_host->mci_removed = var_info->mci_removed;
2309         msm_host->restore_dll_config = var_info->restore_dll_config;
2310         msm_host->var_ops = var_info->var_ops;
2311         msm_host->offset = var_info->offset;
2312         msm_host->uses_tassadar_dll = var_info->uses_tassadar_dll;
2313
2314         msm_offset = msm_host->offset;
2315
2316         sdhci_get_of_property(pdev);
2317         sdhci_msm_get_of_property(pdev, host);
2318
2319         msm_host->saved_tuning_phase = INVALID_TUNING_PHASE;
2320
2321         ret = sdhci_msm_gcc_reset(&pdev->dev, host);
2322         if (ret)
2323                 goto pltfm_free;
2324
2325         /* Setup SDCC bus voter clock. */
2326         msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus");
2327         if (!IS_ERR(msm_host->bus_clk)) {
2328                 /* Vote for max. clk rate for max. performance */
2329                 ret = clk_set_rate(msm_host->bus_clk, INT_MAX);
2330                 if (ret)
2331                         goto pltfm_free;
2332                 ret = clk_prepare_enable(msm_host->bus_clk);
2333                 if (ret)
2334                         goto pltfm_free;
2335         }
2336
2337         /* Setup main peripheral bus clock */
2338         clk = devm_clk_get(&pdev->dev, "iface");
2339         if (IS_ERR(clk)) {
2340                 ret = PTR_ERR(clk);
2341                 dev_err(&pdev->dev, "Peripheral clk setup failed (%d)\n", ret);
2342                 goto bus_clk_disable;
2343         }
2344         msm_host->bulk_clks[1].clk = clk;
2345
2346         /* Setup SDC MMC clock */
2347         clk = devm_clk_get(&pdev->dev, "core");
2348         if (IS_ERR(clk)) {
2349                 ret = PTR_ERR(clk);
2350                 dev_err(&pdev->dev, "SDC MMC clk setup failed (%d)\n", ret);
2351                 goto bus_clk_disable;
2352         }
2353         msm_host->bulk_clks[0].clk = clk;
2354
2355          /* Check for optional interconnect paths */
2356         ret = dev_pm_opp_of_find_icc_paths(&pdev->dev, NULL);
2357         if (ret)
2358                 goto bus_clk_disable;
2359
2360         msm_host->opp_table = dev_pm_opp_set_clkname(&pdev->dev, "core");
2361         if (IS_ERR(msm_host->opp_table)) {
2362                 ret = PTR_ERR(msm_host->opp_table);
2363                 goto bus_clk_disable;
2364         }
2365
2366         /* OPP table is optional */
2367         ret = dev_pm_opp_of_add_table(&pdev->dev);
2368         if (ret && ret != -ENODEV) {
2369                 dev_err(&pdev->dev, "Invalid OPP table in Device tree\n");
2370                 goto opp_put_clkname;
2371         }
2372
2373         /* Vote for maximum clock rate for maximum performance */
2374         ret = dev_pm_opp_set_rate(&pdev->dev, INT_MAX);
2375         if (ret)
2376                 dev_warn(&pdev->dev, "core clock boost failed\n");
2377
2378         clk = devm_clk_get(&pdev->dev, "cal");
2379         if (IS_ERR(clk))
2380                 clk = NULL;
2381         msm_host->bulk_clks[2].clk = clk;
2382
2383         clk = devm_clk_get(&pdev->dev, "sleep");
2384         if (IS_ERR(clk))
2385                 clk = NULL;
2386         msm_host->bulk_clks[3].clk = clk;
2387
2388         ret = clk_bulk_prepare_enable(ARRAY_SIZE(msm_host->bulk_clks),
2389                                       msm_host->bulk_clks);
2390         if (ret)
2391                 goto opp_cleanup;
2392
2393         /*
2394          * xo clock is needed for FLL feature of cm_dll.
2395          * In case if xo clock is not mentioned in DT, warn and proceed.
2396          */
2397         msm_host->xo_clk = devm_clk_get(&pdev->dev, "xo");
2398         if (IS_ERR(msm_host->xo_clk)) {
2399                 ret = PTR_ERR(msm_host->xo_clk);
2400                 dev_warn(&pdev->dev, "TCXO clk not present (%d)\n", ret);
2401         }
2402
2403         if (!msm_host->mci_removed) {
2404                 msm_host->core_mem = devm_platform_ioremap_resource(pdev, 1);
2405                 if (IS_ERR(msm_host->core_mem)) {
2406                         ret = PTR_ERR(msm_host->core_mem);
2407                         goto clk_disable;
2408                 }
2409         }
2410
2411         /* Reset the vendor spec register to power on reset state */
2412         writel_relaxed(CORE_VENDOR_SPEC_POR_VAL,
2413                         host->ioaddr + msm_offset->core_vendor_spec);
2414
2415         if (!msm_host->mci_removed) {
2416                 /* Set HC_MODE_EN bit in HC_MODE register */
2417                 msm_host_writel(msm_host, HC_MODE_EN, host,
2418                                 msm_offset->core_hc_mode);
2419                 config = msm_host_readl(msm_host, host,
2420                                 msm_offset->core_hc_mode);
2421                 config |= FF_CLK_SW_RST_DIS;
2422                 msm_host_writel(msm_host, config, host,
2423                                 msm_offset->core_hc_mode);
2424         }
2425
2426         host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION));
2427         dev_dbg(&pdev->dev, "Host Version: 0x%x Vendor Version 0x%x\n",
2428                 host_version, ((host_version & SDHCI_VENDOR_VER_MASK) >>
2429                                SDHCI_VENDOR_VER_SHIFT));
2430
2431         core_version = msm_host_readl(msm_host, host,
2432                         msm_offset->core_mci_version);
2433         core_major = (core_version & CORE_VERSION_MAJOR_MASK) >>
2434                       CORE_VERSION_MAJOR_SHIFT;
2435         core_minor = core_version & CORE_VERSION_MINOR_MASK;
2436         dev_dbg(&pdev->dev, "MCI Version: 0x%08x, major: 0x%04x, minor: 0x%02x\n",
2437                 core_version, core_major, core_minor);
2438
2439         if (core_major == 1 && core_minor >= 0x42)
2440                 msm_host->use_14lpp_dll_reset = true;
2441
2442         /*
2443          * SDCC 5 controller with major version 1, minor version 0x34 and later
2444          * with HS 400 mode support will use CM DLL instead of CDC LP 533 DLL.
2445          */
2446         if (core_major == 1 && core_minor < 0x34)
2447                 msm_host->use_cdclp533 = true;
2448
2449         /*
2450          * Support for some capabilities is not advertised by newer
2451          * controller versions and must be explicitly enabled.
2452          */
2453         if (core_major >= 1 && core_minor != 0x11 && core_minor != 0x12) {
2454                 config = readl_relaxed(host->ioaddr + SDHCI_CAPABILITIES);
2455                 config |= SDHCI_CAN_VDD_300 | SDHCI_CAN_DO_8BIT;
2456                 writel_relaxed(config, host->ioaddr +
2457                                 msm_offset->core_vendor_spec_capabilities0);
2458         }
2459
2460         if (core_major == 1 && core_minor >= 0x49)
2461                 msm_host->updated_ddr_cfg = true;
2462
2463         ret = sdhci_msm_register_vreg(msm_host);
2464         if (ret)
2465                 goto clk_disable;
2466
2467         /*
2468          * Power on reset state may trigger power irq if previous status of
2469          * PWRCTL was either BUS_ON or IO_HIGH_V. So before enabling pwr irq
2470          * interrupt in GIC, any pending power irq interrupt should be
2471          * acknowledged. Otherwise power irq interrupt handler would be
2472          * fired prematurely.
2473          */
2474         sdhci_msm_handle_pwr_irq(host, 0);
2475
2476         /*
2477          * Ensure that above writes are propogated before interrupt enablement
2478          * in GIC.
2479          */
2480         mb();
2481
2482         /* Setup IRQ for handling power/voltage tasks with PMIC */
2483         msm_host->pwr_irq = platform_get_irq_byname(pdev, "pwr_irq");
2484         if (msm_host->pwr_irq < 0) {
2485                 ret = msm_host->pwr_irq;
2486                 goto clk_disable;
2487         }
2488
2489         sdhci_msm_init_pwr_irq_wait(msm_host);
2490         /* Enable pwr irq interrupts */
2491         msm_host_writel(msm_host, INT_MASK, host,
2492                 msm_offset->core_pwrctl_mask);
2493
2494         ret = devm_request_threaded_irq(&pdev->dev, msm_host->pwr_irq, NULL,
2495                                         sdhci_msm_pwr_irq, IRQF_ONESHOT,
2496                                         dev_name(&pdev->dev), host);
2497         if (ret) {
2498                 dev_err(&pdev->dev, "Request IRQ failed (%d)\n", ret);
2499                 goto clk_disable;
2500         }
2501
2502         msm_host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_NEED_RSP_BUSY;
2503
2504         pm_runtime_get_noresume(&pdev->dev);
2505         pm_runtime_set_active(&pdev->dev);
2506         pm_runtime_enable(&pdev->dev);
2507         pm_runtime_set_autosuspend_delay(&pdev->dev,
2508                                          MSM_MMC_AUTOSUSPEND_DELAY_MS);
2509         pm_runtime_use_autosuspend(&pdev->dev);
2510
2511         host->mmc_host_ops.start_signal_voltage_switch =
2512                 sdhci_msm_start_signal_voltage_switch;
2513         host->mmc_host_ops.execute_tuning = sdhci_msm_execute_tuning;
2514         if (of_property_read_bool(node, "supports-cqe"))
2515                 ret = sdhci_msm_cqe_add_host(host, pdev);
2516         else
2517                 ret = sdhci_add_host(host);
2518         if (ret)
2519                 goto pm_runtime_disable;
2520
2521         pm_runtime_mark_last_busy(&pdev->dev);
2522         pm_runtime_put_autosuspend(&pdev->dev);
2523
2524         return 0;
2525
2526 pm_runtime_disable:
2527         pm_runtime_disable(&pdev->dev);
2528         pm_runtime_set_suspended(&pdev->dev);
2529         pm_runtime_put_noidle(&pdev->dev);
2530 clk_disable:
2531         clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks),
2532                                    msm_host->bulk_clks);
2533 opp_cleanup:
2534         dev_pm_opp_of_remove_table(&pdev->dev);
2535 opp_put_clkname:
2536         dev_pm_opp_put_clkname(msm_host->opp_table);
2537 bus_clk_disable:
2538         if (!IS_ERR(msm_host->bus_clk))
2539                 clk_disable_unprepare(msm_host->bus_clk);
2540 pltfm_free:
2541         sdhci_pltfm_free(pdev);
2542         return ret;
2543 }
2544
2545 static int sdhci_msm_remove(struct platform_device *pdev)
2546 {
2547         struct sdhci_host *host = platform_get_drvdata(pdev);
2548         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2549         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
2550         int dead = (readl_relaxed(host->ioaddr + SDHCI_INT_STATUS) ==
2551                     0xffffffff);
2552
2553         sdhci_remove_host(host, dead);
2554
2555         dev_pm_opp_of_remove_table(&pdev->dev);
2556         dev_pm_opp_put_clkname(msm_host->opp_table);
2557         pm_runtime_get_sync(&pdev->dev);
2558         pm_runtime_disable(&pdev->dev);
2559         pm_runtime_put_noidle(&pdev->dev);
2560
2561         clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks),
2562                                    msm_host->bulk_clks);
2563         if (!IS_ERR(msm_host->bus_clk))
2564                 clk_disable_unprepare(msm_host->bus_clk);
2565         sdhci_pltfm_free(pdev);
2566         return 0;
2567 }
2568
2569 static __maybe_unused int sdhci_msm_runtime_suspend(struct device *dev)
2570 {
2571         struct sdhci_host *host = dev_get_drvdata(dev);
2572         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2573         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
2574
2575         /* Drop the performance vote */
2576         dev_pm_opp_set_rate(dev, 0);
2577         clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks),
2578                                    msm_host->bulk_clks);
2579
2580         return 0;
2581 }
2582
2583 static __maybe_unused int sdhci_msm_runtime_resume(struct device *dev)
2584 {
2585         struct sdhci_host *host = dev_get_drvdata(dev);
2586         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2587         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
2588         int ret;
2589
2590         ret = clk_bulk_prepare_enable(ARRAY_SIZE(msm_host->bulk_clks),
2591                                        msm_host->bulk_clks);
2592         if (ret)
2593                 return ret;
2594         /*
2595          * Whenever core-clock is gated dynamically, it's needed to
2596          * restore the SDR DLL settings when the clock is ungated.
2597          */
2598         if (msm_host->restore_dll_config && msm_host->clk_rate)
2599                 ret = sdhci_msm_restore_sdr_dll_config(host);
2600
2601         dev_pm_opp_set_rate(dev, msm_host->clk_rate);
2602
2603         return ret;
2604 }
2605
2606 static const struct dev_pm_ops sdhci_msm_pm_ops = {
2607         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
2608                                 pm_runtime_force_resume)
2609         SET_RUNTIME_PM_OPS(sdhci_msm_runtime_suspend,
2610                            sdhci_msm_runtime_resume,
2611                            NULL)
2612 };
2613
2614 static struct platform_driver sdhci_msm_driver = {
2615         .probe = sdhci_msm_probe,
2616         .remove = sdhci_msm_remove,
2617         .driver = {
2618                    .name = "sdhci_msm",
2619                    .of_match_table = sdhci_msm_dt_match,
2620                    .pm = &sdhci_msm_pm_ops,
2621                    .probe_type = PROBE_PREFER_ASYNCHRONOUS,
2622         },
2623 };
2624
2625 module_platform_driver(sdhci_msm_driver);
2626
2627 MODULE_DESCRIPTION("Qualcomm Secure Digital Host Controller Interface driver");
2628 MODULE_LICENSE("GPL v2");