drivers/mmc/host/sdhci-esdhc-imx.c

   1 /*
   2  * Freescale eSDHC i.MX controller driver for the platform bus.
   3  *
   4  * derived from the OF-version.
   5  *
   6  * Copyright (c) 2010 Pengutronix e.K.
   7  *   Author: Wolfram Sang <kernel@pengutronix.de>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License.
  12  */
  13
  14 #include <linux/io.h>
  15 #include <linux/delay.h>
  16 #include <linux/err.h>
  17 #include <linux/clk.h>
  18 #include <linux/gpio.h>
  19 #include <linux/module.h>
  20 #include <linux/slab.h>
  21 #include <linux/mmc/host.h>
  22 #include <linux/mmc/mmc.h>
  23 #include <linux/mmc/sdio.h>
  24 #include <linux/mmc/slot-gpio.h>
  25 #include <linux/of.h>
  26 #include <linux/of_device.h>
  27 #include <linux/of_gpio.h>
  28 #include <linux/pinctrl/consumer.h>
  29 #include <linux/platform_data/mmc-esdhc-imx.h>
  30 #include <linux/pm_runtime.h>
  31 #include "sdhci-pltfm.h"
  32 #include "sdhci-esdhc.h"
  33
  34 #define ESDHC_SYS_CTRL_DTOCV_MASK       0x0f
  35 #define ESDHC_CTRL_D3CD                 0x08
  36 #define ESDHC_BURST_LEN_EN_INCR         (1 << 27)
  37 /* VENDOR SPEC register */
  38 #define ESDHC_VENDOR_SPEC               0xc0
  39 #define  ESDHC_VENDOR_SPEC_SDIO_QUIRK   (1 << 1)
  40 #define  ESDHC_VENDOR_SPEC_VSELECT      (1 << 1)
  41 #define  ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8)
  42 #define ESDHC_WTMK_LVL                  0x44
  43 #define  ESDHC_WTMK_DEFAULT_VAL         0x10401040
  44 #define ESDHC_MIX_CTRL                  0x48
  45 #define  ESDHC_MIX_CTRL_DDREN           (1 << 3)
  46 #define  ESDHC_MIX_CTRL_AC23EN          (1 << 7)
  47 #define  ESDHC_MIX_CTRL_EXE_TUNE        (1 << 22)
  48 #define  ESDHC_MIX_CTRL_SMPCLK_SEL      (1 << 23)
  49 #define  ESDHC_MIX_CTRL_AUTO_TUNE_EN    (1 << 24)
  50 #define  ESDHC_MIX_CTRL_FBCLK_SEL       (1 << 25)
  51 #define  ESDHC_MIX_CTRL_HS400_EN        (1 << 26)
  52 /* Bits 3 and 6 are not SDHCI standard definitions */
  53 #define  ESDHC_MIX_CTRL_SDHCI_MASK      0xb7
  54 /* Tuning bits */
  55 #define  ESDHC_MIX_CTRL_TUNING_MASK     0x03c00000
  56
  57 /* dll control register */
  58 #define ESDHC_DLL_CTRL                  0x60
  59 #define ESDHC_DLL_OVERRIDE_VAL_SHIFT    9
  60 #define ESDHC_DLL_OVERRIDE_EN_SHIFT     8
  61
  62 /* tune control register */
  63 #define ESDHC_TUNE_CTRL_STATUS          0x68
  64 #define  ESDHC_TUNE_CTRL_STEP           1
  65 #define  ESDHC_TUNE_CTRL_MIN            0
  66 #define  ESDHC_TUNE_CTRL_MAX            ((1 << 7) - 1)
  67
  68 /* strobe dll register */
  69 #define ESDHC_STROBE_DLL_CTRL           0x70
  70 #define ESDHC_STROBE_DLL_CTRL_ENABLE    (1 << 0)
  71 #define ESDHC_STROBE_DLL_CTRL_RESET     (1 << 1)
  72 #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT      3
  73
  74 #define ESDHC_STROBE_DLL_STATUS         0x74
  75 #define ESDHC_STROBE_DLL_STS_REF_LOCK   (1 << 1)
  76 #define ESDHC_STROBE_DLL_STS_SLV_LOCK   0x1
  77
  78 #define ESDHC_TUNING_CTRL               0xcc
  79 #define ESDHC_STD_TUNING_EN             (1 << 24)
  80 /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
  81 #define ESDHC_TUNING_START_TAP_DEFAULT  0x1
  82 #define ESDHC_TUNING_START_TAP_MASK     0x7f
  83 #define ESDHC_TUNING_STEP_MASK          0x00070000
  84 #define ESDHC_TUNING_STEP_SHIFT         16
  85
  86 /* pinctrl state */
  87 #define ESDHC_PINCTRL_STATE_100MHZ      "state_100mhz"
  88 #define ESDHC_PINCTRL_STATE_200MHZ      "state_200mhz"
  89
  90 /*
  91  * Our interpretation of the SDHCI_HOST_CONTROL register
  92  */
  93 #define ESDHC_CTRL_4BITBUS              (0x1 << 1)
  94 #define ESDHC_CTRL_8BITBUS              (0x2 << 1)
  95 #define ESDHC_CTRL_BUSWIDTH_MASK        (0x3 << 1)
  96
  97 /*
  98  * There is an INT DMA ERR mismatch between eSDHC and STD SDHC SPEC:
  99  * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design,
 100  * but bit28 is used as the INT DMA ERR in fsl eSDHC design.
 101  * Define this macro DMA error INT for fsl eSDHC
 102  */
 103 #define ESDHC_INT_VENDOR_SPEC_DMA_ERR   (1 << 28)
 104
 105 /*
 106  * The CMDTYPE of the CMD register (offset 0xE) should be set to
 107  * "11" when the STOP CMD12 is issued on imx53 to abort one
 108  * open ended multi-blk IO. Otherwise the TC INT wouldn't
 109  * be generated.
 110  * In exact block transfer, the controller doesn't complete the
 111  * operations automatically as required at the end of the
 112  * transfer and remains on hold if the abort command is not sent.
 113  * As a result, the TC flag is not asserted and SW received timeout
 114  * exception. Bit1 of Vendor Spec register is used to fix it.
 115  */
 116 #define ESDHC_FLAG_MULTIBLK_NO_INT      BIT(1)
 117 /*
 118  * The flag tells that the ESDHC controller is an USDHC block that is
 119  * integrated on the i.MX6 series.
 120  */
 121 #define ESDHC_FLAG_USDHC                BIT(3)
 122 /* The IP supports manual tuning process */
 123 #define ESDHC_FLAG_MAN_TUNING           BIT(4)
 124 /* The IP supports standard tuning process */
 125 #define ESDHC_FLAG_STD_TUNING           BIT(5)
 126 /* The IP has SDHCI_CAPABILITIES_1 register */
 127 #define ESDHC_FLAG_HAVE_CAP1            BIT(6)
 128 /*
 129  * The IP has erratum ERR004536
 130  * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow,
 131  * when reading data from the card
 132  * This flag is also set for i.MX25 and i.MX35 in order to get
 133  * SDHCI_QUIRK_BROKEN_ADMA, but for different reasons (ADMA capability bits).
 134  */
 135 #define ESDHC_FLAG_ERR004536            BIT(7)
 136 /* The IP supports HS200 mode */
 137 #define ESDHC_FLAG_HS200                BIT(8)
 138 /* The IP supports HS400 mode */
 139 #define ESDHC_FLAG_HS400                BIT(9)
 140
 141 /* A clock frequency higher than this rate requires strobe dll control */
 142 #define ESDHC_STROBE_DLL_CLK_FREQ       100000000
 143
 144 struct esdhc_soc_data {
 145         u32 flags;
 146 };
 147
 148 static struct esdhc_soc_data esdhc_imx25_data = {
 149         .flags = ESDHC_FLAG_ERR004536,
 150 };
 151
 152 static struct esdhc_soc_data esdhc_imx35_data = {
 153         .flags = ESDHC_FLAG_ERR004536,
 154 };
 155
 156 static struct esdhc_soc_data esdhc_imx51_data = {
 157         .flags = 0,
 158 };
 159
 160 static struct esdhc_soc_data esdhc_imx53_data = {
 161         .flags = ESDHC_FLAG_MULTIBLK_NO_INT,
 162 };
 163
 164 static struct esdhc_soc_data usdhc_imx6q_data = {
 165         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING,
 166 };
 167
 168 static struct esdhc_soc_data usdhc_imx6sl_data = {
 169         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 170                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536
 171                         | ESDHC_FLAG_HS200,
 172 };
 173
 174 static struct esdhc_soc_data usdhc_imx6sx_data = {
 175         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 176                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200,
 177 };
 178
 179 static struct esdhc_soc_data usdhc_imx7d_data = {
 180         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 181                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
 182                         | ESDHC_FLAG_HS400,
 183 };
 184
 185 struct pltfm_imx_data {
 186         u32 scratchpad;
 187         struct pinctrl *pinctrl;
 188         struct pinctrl_state *pins_default;
 189         struct pinctrl_state *pins_100mhz;
 190         struct pinctrl_state *pins_200mhz;
 191         const struct esdhc_soc_data *socdata;
 192         struct esdhc_platform_data boarddata;
 193         struct clk *clk_ipg;
 194         struct clk *clk_ahb;
 195         struct clk *clk_per;
 196         enum {
 197                 NO_CMD_PENDING,      /* no multiblock command pending */
 198                 MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */
 199                 WAIT_FOR_INT,        /* sent CMD12, waiting for response INT */
 200         } multiblock_status;
 201         u32 is_ddr;
 202 };
 203
 204 static const struct platform_device_id imx_esdhc_devtype[] = {
 205         {
 206                 .name = "sdhci-esdhc-imx25",
 207                 .driver_data = (kernel_ulong_t) &esdhc_imx25_data,
 208         }, {
 209                 .name = "sdhci-esdhc-imx35",
 210                 .driver_data = (kernel_ulong_t) &esdhc_imx35_data,
 211         }, {
 212                 .name = "sdhci-esdhc-imx51",
 213                 .driver_data = (kernel_ulong_t) &esdhc_imx51_data,
 214         }, {
 215                 /* sentinel */
 216         }
 217 };
 218 MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype);
 219
 220 static const struct of_device_id imx_esdhc_dt_ids[] = {
 221         { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, },
 222         { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, },
 223         { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, },
 224         { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, },
 225         { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, },
 226         { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, },
 227         { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, },
 228         { .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, },
 229         { /* sentinel */ }
 230 };
 231 MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids);
 232
 233 static inline int is_imx25_esdhc(struct pltfm_imx_data *data)
 234 {
 235         return data->socdata == &esdhc_imx25_data;
 236 }
 237
 238 static inline int is_imx53_esdhc(struct pltfm_imx_data *data)
 239 {
 240         return data->socdata == &esdhc_imx53_data;
 241 }
 242
 243 static inline int is_imx6q_usdhc(struct pltfm_imx_data *data)
 244 {
 245         return data->socdata == &usdhc_imx6q_data;
 246 }
 247
 248 static inline int esdhc_is_usdhc(struct pltfm_imx_data *data)
 249 {
 250         return !!(data->socdata->flags & ESDHC_FLAG_USDHC);
 251 }
 252
 253 static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
 254 {
 255         void __iomem *base = host->ioaddr + (reg & ~0x3);
 256         u32 shift = (reg & 0x3) * 8;
 257
 258         writel(((readl(base) & ~(mask << shift)) | (val << shift)), base);
 259 }
 260
 261 static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
 262 {
 263         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 264         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 265         u32 val = readl(host->ioaddr + reg);
 266
 267         if (unlikely(reg == SDHCI_PRESENT_STATE)) {
 268                 u32 fsl_prss = val;
 269                 /* save the least 20 bits */
 270                 val = fsl_prss & 0x000FFFFF;
 271                 /* move dat[0-3] bits */
 272                 val |= (fsl_prss & 0x0F000000) >> 4;
 273                 /* move cmd line bit */
 274                 val |= (fsl_prss & 0x00800000) << 1;
 275         }
 276
 277         if (unlikely(reg == SDHCI_CAPABILITIES)) {
 278                 /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */
 279                 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
 280                         val &= 0xffff0000;
 281
 282                 /* In FSL esdhc IC module, only bit20 is used to indicate the
 283                  * ADMA2 capability of esdhc, but this bit is messed up on
 284                  * some SOCs (e.g. on MX25, MX35 this bit is set, but they
 285                  * don't actually support ADMA2). So set the BROKEN_ADMA
 286                  * quirk on MX25/35 platforms.
 287                  */
 288
 289                 if (val & SDHCI_CAN_DO_ADMA1) {
 290                         val &= ~SDHCI_CAN_DO_ADMA1;
 291                         val |= SDHCI_CAN_DO_ADMA2;
 292                 }
 293         }
 294
 295         if (unlikely(reg == SDHCI_CAPABILITIES_1)) {
 296                 if (esdhc_is_usdhc(imx_data)) {
 297                         if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
 298                                 val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF;
 299                         else
 300                                 /* imx6q/dl does not have cap_1 register, fake one */
 301                                 val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104
 302                                         | SDHCI_SUPPORT_SDR50
 303                                         | SDHCI_USE_SDR50_TUNING
 304                                         | (SDHCI_TUNING_MODE_3 << SDHCI_RETUNING_MODE_SHIFT);
 305
 306                         if (imx_data->socdata->flags & ESDHC_FLAG_HS400)
 307                                 val |= SDHCI_SUPPORT_HS400;
 308
 309                         /*
 310                          * Do not advertise faster UHS modes if there are no
 311                          * pinctrl states for 100MHz/200MHz.
 312                          */
 313                         if (IS_ERR_OR_NULL(imx_data->pins_100mhz) ||
 314                             IS_ERR_OR_NULL(imx_data->pins_200mhz))
 315                                 val &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50
 316                                          | SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_HS400);
 317                 }
 318         }
 319
 320         if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) {
 321                 val = 0;
 322                 val |= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT;
 323                 val |= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT;
 324                 val |= 0xFF << SDHCI_MAX_CURRENT_180_SHIFT;
 325         }
 326
 327         if (unlikely(reg == SDHCI_INT_STATUS)) {
 328                 if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) {
 329                         val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR;
 330                         val |= SDHCI_INT_ADMA_ERROR;
 331                 }
 332
 333                 /*
 334                  * mask off the interrupt we get in response to the manually
 335                  * sent CMD12
 336                  */
 337                 if ((imx_data->multiblock_status == WAIT_FOR_INT) &&
 338                     ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) {
 339                         val &= ~SDHCI_INT_RESPONSE;
 340                         writel(SDHCI_INT_RESPONSE, host->ioaddr +
 341                                                    SDHCI_INT_STATUS);
 342                         imx_data->multiblock_status = NO_CMD_PENDING;
 343                 }
 344         }
 345
 346         return val;
 347 }
 348
 349 static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
 350 {
 351         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 352         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 353         u32 data;
 354
 355         if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE ||
 356                         reg == SDHCI_INT_STATUS)) {
 357                 if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) {
 358                         /*
 359                          * Clear and then set D3CD bit to avoid missing the
 360                          * card interrupt. This is an eSDHC controller problem
 361                          * so we need to apply the following workaround: clear
 362                          * and set D3CD bit will make eSDHC re-sample the card
 363                          * interrupt. In case a card interrupt was lost,
 364                          * re-sample it by the following steps.
 365                          */
 366                         data = readl(host->ioaddr + SDHCI_HOST_CONTROL);
 367                         data &= ~ESDHC_CTRL_D3CD;
 368                         writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
 369                         data |= ESDHC_CTRL_D3CD;
 370                         writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
 371                 }
 372
 373                 if (val & SDHCI_INT_ADMA_ERROR) {
 374                         val &= ~SDHCI_INT_ADMA_ERROR;
 375                         val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR;
 376                 }
 377         }
 378
 379         if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
 380                                 && (reg == SDHCI_INT_STATUS)
 381                                 && (val & SDHCI_INT_DATA_END))) {
 382                         u32 v;
 383                         v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 384                         v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK;
 385                         writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
 386
 387                         if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS)
 388                         {
 389                                 /* send a manual CMD12 with RESPTYP=none */
 390                                 data = MMC_STOP_TRANSMISSION << 24 |
 391                                        SDHCI_CMD_ABORTCMD << 16;
 392                                 writel(data, host->ioaddr + SDHCI_TRANSFER_MODE);
 393                                 imx_data->multiblock_status = WAIT_FOR_INT;
 394                         }
 395         }
 396
 397         writel(val, host->ioaddr + reg);
 398 }
 399
 400 static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
 401 {
 402         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 403         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 404         u16 ret = 0;
 405         u32 val;
 406
 407         if (unlikely(reg == SDHCI_HOST_VERSION)) {
 408                 reg ^= 2;
 409                 if (esdhc_is_usdhc(imx_data)) {
 410                         /*
 411                          * The usdhc register returns a wrong host version.
 412                          * Correct it here.
 413                          */
 414                         return SDHCI_SPEC_300;
 415                 }
 416         }
 417
 418         if (unlikely(reg == SDHCI_HOST_CONTROL2)) {
 419                 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 420                 if (val & ESDHC_VENDOR_SPEC_VSELECT)
 421                         ret |= SDHCI_CTRL_VDD_180;
 422
 423                 if (esdhc_is_usdhc(imx_data)) {
 424                         if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
 425                                 val = readl(host->ioaddr + ESDHC_MIX_CTRL);
 426                         else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING)
 427                                 /* the std tuning bits is in ACMD12_ERR for imx6sl */
 428                                 val = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
 429                 }
 430
 431                 if (val & ESDHC_MIX_CTRL_EXE_TUNE)
 432                         ret |= SDHCI_CTRL_EXEC_TUNING;
 433                 if (val & ESDHC_MIX_CTRL_SMPCLK_SEL)
 434                         ret |= SDHCI_CTRL_TUNED_CLK;
 435
 436                 ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
 437
 438                 return ret;
 439         }
 440
 441         if (unlikely(reg == SDHCI_TRANSFER_MODE)) {
 442                 if (esdhc_is_usdhc(imx_data)) {
 443                         u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
 444                         ret = m & ESDHC_MIX_CTRL_SDHCI_MASK;
 445                         /* Swap AC23 bit */
 446                         if (m & ESDHC_MIX_CTRL_AC23EN) {
 447                                 ret &= ~ESDHC_MIX_CTRL_AC23EN;
 448                                 ret |= SDHCI_TRNS_AUTO_CMD23;
 449                         }
 450                 } else {
 451                         ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE);
 452                 }
 453
 454                 return ret;
 455         }
 456
 457         return readw(host->ioaddr + reg);
 458 }
 459
 460 static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
 461 {
 462         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 463         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 464         u32 new_val = 0;
 465
 466         switch (reg) {
 467         case SDHCI_CLOCK_CONTROL:
 468                 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 469                 if (val & SDHCI_CLOCK_CARD_EN)
 470                         new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
 471                 else
 472                         new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
 473                 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
 474                 return;
 475         case SDHCI_HOST_CONTROL2:
 476                 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 477                 if (val & SDHCI_CTRL_VDD_180)
 478                         new_val |= ESDHC_VENDOR_SPEC_VSELECT;
 479                 else
 480                         new_val &= ~ESDHC_VENDOR_SPEC_VSELECT;
 481                 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
 482                 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
 483                         new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
 484                         if (val & SDHCI_CTRL_TUNED_CLK) {
 485                                 new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL;
 486                                 new_val |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
 487                         } else {
 488                                 new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
 489                                 new_val &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN;
 490                         }
 491                         writel(new_val , host->ioaddr + ESDHC_MIX_CTRL);
 492                 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
 493                         u32 v = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
 494                         u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
 495                         if (val & SDHCI_CTRL_TUNED_CLK) {
 496                                 v |= ESDHC_MIX_CTRL_SMPCLK_SEL;
 497                         } else {
 498                                 v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
 499                                 m &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
 500                                 m &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN;
 501                         }
 502
 503                         if (val & SDHCI_CTRL_EXEC_TUNING) {
 504                                 v |= ESDHC_MIX_CTRL_EXE_TUNE;
 505                                 m |= ESDHC_MIX_CTRL_FBCLK_SEL;
 506                                 m |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
 507                         } else {
 508                                 v &= ~ESDHC_MIX_CTRL_EXE_TUNE;
 509                         }
 510
 511                         writel(v, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
 512                         writel(m, host->ioaddr + ESDHC_MIX_CTRL);
 513                 }
 514                 return;
 515         case SDHCI_TRANSFER_MODE:
 516                 if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
 517                                 && (host->cmd->opcode == SD_IO_RW_EXTENDED)
 518                                 && (host->cmd->data->blocks > 1)
 519                                 && (host->cmd->data->flags & MMC_DATA_READ)) {
 520                         u32 v;
 521                         v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 522                         v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK;
 523                         writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
 524                 }
 525
 526                 if (esdhc_is_usdhc(imx_data)) {
 527                         u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
 528                         /* Swap AC23 bit */
 529                         if (val & SDHCI_TRNS_AUTO_CMD23) {
 530                                 val &= ~SDHCI_TRNS_AUTO_CMD23;
 531                                 val |= ESDHC_MIX_CTRL_AC23EN;
 532                         }
 533                         m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK);
 534                         writel(m, host->ioaddr + ESDHC_MIX_CTRL);
 535                 } else {
 536                         /*
 537                          * Postpone this write, we must do it together with a
 538                          * command write that is down below.
 539                          */
 540                         imx_data->scratchpad = val;
 541                 }
 542                 return;
 543         case SDHCI_COMMAND:
 544                 if (host->cmd->opcode == MMC_STOP_TRANSMISSION)
 545                         val |= SDHCI_CMD_ABORTCMD;
 546
 547                 if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) &&
 548                     (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
 549                         imx_data->multiblock_status = MULTIBLK_IN_PROCESS;
 550
 551                 if (esdhc_is_usdhc(imx_data))
 552                         writel(val << 16,
 553                                host->ioaddr + SDHCI_TRANSFER_MODE);
 554                 else
 555                         writel(val << 16 | imx_data->scratchpad,
 556                                host->ioaddr + SDHCI_TRANSFER_MODE);
 557                 return;
 558         case SDHCI_BLOCK_SIZE:
 559                 val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
 560                 break;
 561         }
 562         esdhc_clrset_le(host, 0xffff, val, reg);
 563 }
 564
 565 static u8 esdhc_readb_le(struct sdhci_host *host, int reg)
 566 {
 567         u8 ret;
 568         u32 val;
 569
 570         switch (reg) {
 571         case SDHCI_HOST_CONTROL:
 572                 val = readl(host->ioaddr + reg);
 573
 574                 ret = val & SDHCI_CTRL_LED;
 575                 ret |= (val >> 5) & SDHCI_CTRL_DMA_MASK;
 576                 ret |= (val & ESDHC_CTRL_4BITBUS);
 577                 ret |= (val & ESDHC_CTRL_8BITBUS) << 3;
 578                 return ret;
 579         }
 580
 581         return readb(host->ioaddr + reg);
 582 }
 583
 584 static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
 585 {
 586         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 587         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 588         u32 new_val = 0;
 589         u32 mask;
 590
 591         switch (reg) {
 592         case SDHCI_POWER_CONTROL:
 593                 /*
 594                  * FSL put some DMA bits here
 595                  * If your board has a regulator, code should be here
 596                  */
 597                 return;
 598         case SDHCI_HOST_CONTROL:
 599                 /* FSL messed up here, so we need to manually compose it. */
 600                 new_val = val & SDHCI_CTRL_LED;
 601                 /* ensure the endianness */
 602                 new_val |= ESDHC_HOST_CONTROL_LE;
 603                 /* bits 8&9 are reserved on mx25 */
 604                 if (!is_imx25_esdhc(imx_data)) {
 605                         /* DMA mode bits are shifted */
 606                         new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5;
 607                 }
 608
 609                 /*
 610                  * Do not touch buswidth bits here. This is done in
 611                  * esdhc_pltfm_bus_width.
 612                  * Do not touch the D3CD bit either which is used for the
 613                  * SDIO interrupt erratum workaround.
 614                  */
 615                 mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD);
 616
 617                 esdhc_clrset_le(host, mask, new_val, reg);
 618                 return;
 619         case SDHCI_SOFTWARE_RESET:
 620                 if (val & SDHCI_RESET_DATA)
 621                         new_val = readl(host->ioaddr + SDHCI_HOST_CONTROL);
 622                 break;
 623         }
 624         esdhc_clrset_le(host, 0xff, val, reg);
 625
 626         if (reg == SDHCI_SOFTWARE_RESET) {
 627                 if (val & SDHCI_RESET_ALL) {
 628                         /*
 629                          * The esdhc has a design violation to SDHC spec which
 630                          * tells that software reset should not affect card
 631                          * detection circuit. But esdhc clears its SYSCTL
 632                          * register bits [0..2] during the software reset. This
 633                          * will stop those clocks that card detection circuit
 634                          * relies on. To work around it, we turn the clocks on
 635                          * back to keep card detection circuit functional.
 636                          */
 637                         esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL);
 638                         /*
 639                          * The reset on usdhc fails to clear MIX_CTRL register.
 640                          * Do it manually here.
 641                          */
 642                         if (esdhc_is_usdhc(imx_data)) {
 643                                 /*
 644                                  * the tuning bits should be kept during reset
 645                                  */
 646                                 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
 647                                 writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK,
 648                                                 host->ioaddr + ESDHC_MIX_CTRL);
 649                                 imx_data->is_ddr = 0;
 650                         }
 651                 } else if (val & SDHCI_RESET_DATA) {
 652                         /*
 653                          * The eSDHC DAT line software reset clears at least the
 654                          * data transfer width on i.MX25, so make sure that the
 655                          * Host Control register is unaffected.
 656                          */
 657                         esdhc_clrset_le(host, 0xff, new_val,
 658                                         SDHCI_HOST_CONTROL);
 659                 }
 660         }
 661 }
 662
 663 static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host)
 664 {
 665         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 666
 667         return pltfm_host->clock;
 668 }
 669
 670 static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
 671 {
 672         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 673
 674         return pltfm_host->clock / 256 / 16;
 675 }
 676
 677 static inline void esdhc_pltfm_set_clock(struct sdhci_host *host,
 678                                          unsigned int clock)
 679 {
 680         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 681         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 682         unsigned int host_clock = pltfm_host->clock;
 683         int ddr_pre_div = imx_data->is_ddr ? 2 : 1;
 684         int pre_div = 1;
 685         int div = 1;
 686         u32 temp, val;
 687
 688         if (clock == 0) {
 689                 host->mmc->actual_clock = 0;
 690
 691                 if (esdhc_is_usdhc(imx_data)) {
 692                         val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 693                         writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
 694                                         host->ioaddr + ESDHC_VENDOR_SPEC);
 695                 }
 696                 return;
 697         }
 698
 699         /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
 700         if (is_imx53_esdhc(imx_data)) {
 701                 /*
 702                  * According to the i.MX53 reference manual, if DLLCTRL[10] can
 703                  * be set, then the controller is eSDHCv3, else it is eSDHCv2.
 704                  */
 705                 val = readl(host->ioaddr + ESDHC_DLL_CTRL);
 706                 writel(val | BIT(10), host->ioaddr + ESDHC_DLL_CTRL);
 707                 temp = readl(host->ioaddr + ESDHC_DLL_CTRL);
 708                 writel(val, host->ioaddr + ESDHC_DLL_CTRL);
 709                 if (temp & BIT(10))
 710                         pre_div = 2;
 711         }
 712
 713         temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
 714         temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
 715                 | ESDHC_CLOCK_MASK);
 716         sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
 717
 718         while (host_clock / (16 * pre_div * ddr_pre_div) > clock &&
 719                         pre_div < 256)
 720                 pre_div *= 2;
 721
 722         while (host_clock / (div * pre_div * ddr_pre_div) > clock && div < 16)
 723                 div++;
 724
 725         host->mmc->actual_clock = host_clock / (div * pre_div * ddr_pre_div);
 726         dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
 727                 clock, host->mmc->actual_clock);
 728
 729         pre_div >>= 1;
 730         div--;
 731
 732         temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
 733         temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
 734                 | (div << ESDHC_DIVIDER_SHIFT)
 735                 | (pre_div << ESDHC_PREDIV_SHIFT));
 736         sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
 737
 738         if (esdhc_is_usdhc(imx_data)) {
 739                 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 740                 writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
 741                 host->ioaddr + ESDHC_VENDOR_SPEC);
 742         }
 743
 744         mdelay(1);
 745 }
 746
 747 static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host)
 748 {
 749         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 750         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 751         struct esdhc_platform_data *boarddata = &imx_data->boarddata;
 752
 753         switch (boarddata->wp_type) {
 754         case ESDHC_WP_GPIO:
 755                 return mmc_gpio_get_ro(host->mmc);
 756         case ESDHC_WP_CONTROLLER:
 757                 return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
 758                                SDHCI_WRITE_PROTECT);
 759         case ESDHC_WP_NONE:
 760                 break;
 761         }
 762
 763         return -ENOSYS;
 764 }
 765
 766 static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
 767 {
 768         u32 ctrl;
 769
 770         switch (width) {
 771         case MMC_BUS_WIDTH_8:
 772                 ctrl = ESDHC_CTRL_8BITBUS;
 773                 break;
 774         case MMC_BUS_WIDTH_4:
 775                 ctrl = ESDHC_CTRL_4BITBUS;
 776                 break;
 777         default:
 778                 ctrl = 0;
 779                 break;
 780         }
 781
 782         esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl,
 783                         SDHCI_HOST_CONTROL);
 784 }
 785
 786 static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val)
 787 {
 788         u32 reg;
 789
 790         /* FIXME: delay a bit for card to be ready for next tuning due to errors */
 791         mdelay(1);
 792
 793         reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
 794         reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL |
 795                         ESDHC_MIX_CTRL_FBCLK_SEL;
 796         writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
 797         writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
 798         dev_dbg(mmc_dev(host->mmc),
 799                 "tuning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n",
 800                         val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS));
 801 }
 802
 803 static void esdhc_post_tuning(struct sdhci_host *host)
 804 {
 805         u32 reg;
 806
 807         reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
 808         reg &= ~ESDHC_MIX_CTRL_EXE_TUNE;
 809         reg |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
 810         writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
 811 }
 812
 813 static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode)
 814 {
 815         int min, max, avg, ret;
 816
 817         /* find the mininum delay first which can pass tuning */
 818         min = ESDHC_TUNE_CTRL_MIN;
 819         while (min < ESDHC_TUNE_CTRL_MAX) {
 820                 esdhc_prepare_tuning(host, min);
 821                 if (!mmc_send_tuning(host->mmc, opcode, NULL))
 822                         break;
 823                 min += ESDHC_TUNE_CTRL_STEP;
 824         }
 825
 826         /* find the maxinum delay which can not pass tuning */
 827         max = min + ESDHC_TUNE_CTRL_STEP;
 828         while (max < ESDHC_TUNE_CTRL_MAX) {
 829                 esdhc_prepare_tuning(host, max);
 830                 if (mmc_send_tuning(host->mmc, opcode, NULL)) {
 831                         max -= ESDHC_TUNE_CTRL_STEP;
 832                         break;
 833                 }
 834                 max += ESDHC_TUNE_CTRL_STEP;
 835         }
 836
 837         /* use average delay to get the best timing */
 838         avg = (min + max) / 2;
 839         esdhc_prepare_tuning(host, avg);
 840         ret = mmc_send_tuning(host->mmc, opcode, NULL);
 841         esdhc_post_tuning(host);
 842
 843         dev_dbg(mmc_dev(host->mmc), "tuning %s at 0x%x ret %d\n",
 844                 ret ? "failed" : "passed", avg, ret);
 845
 846         return ret;
 847 }
 848
 849 static int esdhc_change_pinstate(struct sdhci_host *host,
 850                                                 unsigned int uhs)
 851 {
 852         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 853         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 854         struct pinctrl_state *pinctrl;
 855
 856         dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs);
 857
 858         if (IS_ERR(imx_data->pinctrl) ||
 859                 IS_ERR(imx_data->pins_default) ||
 860                 IS_ERR(imx_data->pins_100mhz) ||
 861                 IS_ERR(imx_data->pins_200mhz))
 862                 return -EINVAL;
 863
 864         switch (uhs) {
 865         case MMC_TIMING_UHS_SDR50:
 866         case MMC_TIMING_UHS_DDR50:
 867                 pinctrl = imx_data->pins_100mhz;
 868                 break;
 869         case MMC_TIMING_UHS_SDR104:
 870         case MMC_TIMING_MMC_HS200:
 871         case MMC_TIMING_MMC_HS400:
 872                 pinctrl = imx_data->pins_200mhz;
 873                 break;
 874         default:
 875                 /* back to default state for other legacy timing */
 876                 pinctrl = imx_data->pins_default;
 877         }
 878
 879         return pinctrl_select_state(imx_data->pinctrl, pinctrl);
 880 }
 881
 882 /*
 883  * For HS400 eMMC, there is a data_strobe line. This signal is generated
 884  * by the device and used for data output and CRC status response output
 885  * in HS400 mode. The frequency of this signal follows the frequency of
 886  * CLK generated by host. The host receives the data which is aligned to the
 887  * edge of data_strobe line. Due to the time delay between CLK line and
 888  * data_strobe line, if the delay time is larger than one clock cycle,
 889  * then CLK and data_strobe line will be misaligned, read error shows up.
 890  * So when the CLK is higher than 100MHz, each clock cycle is short enough,
 891  * host should configure the delay target.
 892  */
 893 static void esdhc_set_strobe_dll(struct sdhci_host *host)
 894 {
 895         u32 v;
 896
 897         if (host->mmc->actual_clock > ESDHC_STROBE_DLL_CLK_FREQ) {
 898                 /* disable clock before enabling strobe dll */
 899                 writel(readl(host->ioaddr + ESDHC_VENDOR_SPEC) &
 900                        ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
 901                        host->ioaddr + ESDHC_VENDOR_SPEC);
 902
 903                 /* force a reset on strobe dll */
 904                 writel(ESDHC_STROBE_DLL_CTRL_RESET,
 905                         host->ioaddr + ESDHC_STROBE_DLL_CTRL);
 906                 /*
 907                  * enable strobe dll ctrl and adjust the delay target
 908                  * for the uSDHC loopback read clock
 909                  */
 910                 v = ESDHC_STROBE_DLL_CTRL_ENABLE |
 911                         (7 << ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
 912                 writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL);
 913                 /* wait 1us to make sure strobe dll status register stable */
 914                 udelay(1);
 915                 v = readl(host->ioaddr + ESDHC_STROBE_DLL_STATUS);
 916                 if (!(v & ESDHC_STROBE_DLL_STS_REF_LOCK))
 917                         dev_warn(mmc_dev(host->mmc),
 918                                 "warning! HS400 strobe DLL status REF not lock!\n");
 919                 if (!(v & ESDHC_STROBE_DLL_STS_SLV_LOCK))
 920                         dev_warn(mmc_dev(host->mmc),
 921                                 "warning! HS400 strobe DLL status SLV not lock!\n");
 922         }
 923 }
 924
 925 static void esdhc_reset_tuning(struct sdhci_host *host)
 926 {
 927         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 928         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 929         u32 ctrl;
 930
 931         /* Reset the tuning circuit */
 932         if (esdhc_is_usdhc(imx_data)) {
 933                 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
 934                         ctrl = readl(host->ioaddr + ESDHC_MIX_CTRL);
 935                         ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
 936                         ctrl &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
 937                         writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL);
 938                         writel(0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
 939                 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
 940                         ctrl = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
 941                         ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
 942                         writel(ctrl, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
 943                 }
 944         }
 945 }
 946
 947 static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
 948 {
 949         u32 m;
 950         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 951         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 952         struct esdhc_platform_data *boarddata = &imx_data->boarddata;
 953
 954         /* disable ddr mode and disable HS400 mode */
 955         m = readl(host->ioaddr + ESDHC_MIX_CTRL);
 956         m &= ~(ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN);
 957         imx_data->is_ddr = 0;
 958
 959         switch (timing) {
 960         case MMC_TIMING_UHS_SDR12:
 961         case MMC_TIMING_UHS_SDR25:
 962         case MMC_TIMING_UHS_SDR50:
 963         case MMC_TIMING_UHS_SDR104:
 964         case MMC_TIMING_MMC_HS:
 965         case MMC_TIMING_MMC_HS200:
 966                 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
 967                 break;
 968         case MMC_TIMING_UHS_DDR50:
 969         case MMC_TIMING_MMC_DDR52:
 970                 m |= ESDHC_MIX_CTRL_DDREN;
 971                 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
 972                 imx_data->is_ddr = 1;
 973                 if (boarddata->delay_line) {
 974                         u32 v;
 975                         v = boarddata->delay_line <<
 976                                 ESDHC_DLL_OVERRIDE_VAL_SHIFT |
 977                                 (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT);
 978                         if (is_imx53_esdhc(imx_data))
 979                                 v <<= 1;
 980                         writel(v, host->ioaddr + ESDHC_DLL_CTRL);
 981                 }
 982                 break;
 983         case MMC_TIMING_MMC_HS400:
 984                 m |= ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN;
 985                 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
 986                 imx_data->is_ddr = 1;
 987                 /* update clock after enable DDR for strobe DLL lock */
 988                 host->ops->set_clock(host, host->clock);
 989                 esdhc_set_strobe_dll(host);
 990                 break;
 991         case MMC_TIMING_LEGACY:
 992         default:
 993                 esdhc_reset_tuning(host);
 994                 break;
 995         }
 996
 997         esdhc_change_pinstate(host, timing);
 998 }
 999
1000 static void esdhc_reset(struct sdhci_host *host, u8 mask)
1001 {
1002         sdhci_reset(host, mask);
1003
1004         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1005         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1006 }
1007
1008 static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host)
1009 {
1010         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1011         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1012
1013         /* Doc Erratum: the uSDHC actual maximum timeout count is 1 << 29 */
1014         return esdhc_is_usdhc(imx_data) ? 1 << 29 : 1 << 27;
1015 }
1016
1017 static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
1018 {
1019         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1020         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1021
1022         /* use maximum timeout counter */
1023         esdhc_clrset_le(host, ESDHC_SYS_CTRL_DTOCV_MASK,
1024                         esdhc_is_usdhc(imx_data) ? 0xF : 0xE,
1025                         SDHCI_TIMEOUT_CONTROL);
1026 }
1027
1028 static struct sdhci_ops sdhci_esdhc_ops = {
1029         .read_l = esdhc_readl_le,
1030         .read_w = esdhc_readw_le,
1031         .read_b = esdhc_readb_le,
1032         .write_l = esdhc_writel_le,
1033         .write_w = esdhc_writew_le,
1034         .write_b = esdhc_writeb_le,
1035         .set_clock = esdhc_pltfm_set_clock,
1036         .get_max_clock = esdhc_pltfm_get_max_clock,
1037         .get_min_clock = esdhc_pltfm_get_min_clock,
1038         .get_max_timeout_count = esdhc_get_max_timeout_count,
1039         .get_ro = esdhc_pltfm_get_ro,
1040         .set_timeout = esdhc_set_timeout,
1041         .set_bus_width = esdhc_pltfm_set_bus_width,
1042         .set_uhs_signaling = esdhc_set_uhs_signaling,
1043         .reset = esdhc_reset,
1044 };
1045
1046 static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
1047         .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT
1048                         | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
1049                         | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
1050                         | SDHCI_QUIRK_BROKEN_CARD_DETECTION,
1051         .ops = &sdhci_esdhc_ops,
1052 };
1053
1054 static void sdhci_esdhc_imx_hwinit(struct sdhci_host *host)
1055 {
1056         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1057         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1058         int tmp;
1059
1060         if (esdhc_is_usdhc(imx_data)) {
1061                 /*
1062                  * The imx6q ROM code will change the default watermark
1063                  * level setting to something insane.  Change it back here.
1064                  */
1065                 writel(ESDHC_WTMK_DEFAULT_VAL, host->ioaddr + ESDHC_WTMK_LVL);
1066
1067                 /*
1068                  * ROM code will change the bit burst_length_enable setting
1069                  * to zero if this usdhc is chosen to boot system. Change
1070                  * it back here, otherwise it will impact the performance a
1071                  * lot. This bit is used to enable/disable the burst length
1072                  * for the external AHB2AXI bridge. It's useful especially
1073                  * for INCR transfer because without burst length indicator,
1074                  * the AHB2AXI bridge does not know the burst length in
1075                  * advance. And without burst length indicator, AHB INCR
1076                  * transfer can only be converted to singles on the AXI side.
1077                  */
1078                 writel(readl(host->ioaddr + SDHCI_HOST_CONTROL)
1079                         | ESDHC_BURST_LEN_EN_INCR,
1080                         host->ioaddr + SDHCI_HOST_CONTROL);
1081
1082                 /*
1083                  * erratum ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL
1084                  * TO1.1, it's harmless for MX6SL
1085                  */
1086                 writel(readl(host->ioaddr + 0x6c) & ~BIT(7),
1087                         host->ioaddr + 0x6c);
1088
1089                 /* disable DLL_CTRL delay line settings */
1090                 writel(0x0, host->ioaddr + ESDHC_DLL_CTRL);
1091
1092                 if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
1093                         tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL);
1094                         tmp |= ESDHC_STD_TUNING_EN |
1095                                 ESDHC_TUNING_START_TAP_DEFAULT;
1096                         if (imx_data->boarddata.tuning_start_tap) {
1097                                 tmp &= ~ESDHC_TUNING_START_TAP_MASK;
1098                                 tmp |= imx_data->boarddata.tuning_start_tap;
1099                         }
1100
1101                         if (imx_data->boarddata.tuning_step) {
1102                                 tmp &= ~ESDHC_TUNING_STEP_MASK;
1103                                 tmp |= imx_data->boarddata.tuning_step
1104                                         << ESDHC_TUNING_STEP_SHIFT;
1105                         }
1106                         writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL);
1107                 }
1108         }
1109 }
1110
1111 #ifdef CONFIG_OF
1112 static int
1113 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
1114                          struct sdhci_host *host,
1115                          struct pltfm_imx_data *imx_data)
1116 {
1117         struct device_node *np = pdev->dev.of_node;
1118         struct esdhc_platform_data *boarddata = &imx_data->boarddata;
1119         int ret;
1120
1121         if (of_get_property(np, "fsl,wp-controller", NULL))
1122                 boarddata->wp_type = ESDHC_WP_CONTROLLER;
1123
1124         boarddata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
1125         if (gpio_is_valid(boarddata->wp_gpio))
1126                 boarddata->wp_type = ESDHC_WP_GPIO;
1127
1128         of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step);
1129         of_property_read_u32(np, "fsl,tuning-start-tap",
1130                              &boarddata->tuning_start_tap);
1131
1132         if (of_find_property(np, "no-1-8-v", NULL))
1133                 boarddata->support_vsel = false;
1134         else
1135                 boarddata->support_vsel = true;
1136
1137         if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line))
1138                 boarddata->delay_line = 0;
1139
1140         mmc_of_parse_voltage(np, &host->ocr_mask);
1141
1142         /* sdr50 and sdr104 need work on 1.8v signal voltage */
1143         if ((boarddata->support_vsel) && esdhc_is_usdhc(imx_data) &&
1144             !IS_ERR(imx_data->pins_default)) {
1145                 imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl,
1146                                                 ESDHC_PINCTRL_STATE_100MHZ);
1147                 imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl,
1148                                                 ESDHC_PINCTRL_STATE_200MHZ);
1149         }
1150
1151         /* call to generic mmc_of_parse to support additional capabilities */
1152         ret = mmc_of_parse(host->mmc);
1153         if (ret)
1154                 return ret;
1155
1156         if (mmc_gpio_get_cd(host->mmc) >= 0)
1157                 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
1158
1159         return 0;
1160 }
1161 #else
1162 static inline int
1163 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
1164                          struct sdhci_host *host,
1165                          struct pltfm_imx_data *imx_data)
1166 {
1167         return -ENODEV;
1168 }
1169 #endif
1170
1171 static int sdhci_esdhc_imx_probe_nondt(struct platform_device *pdev,
1172                          struct sdhci_host *host,
1173                          struct pltfm_imx_data *imx_data)
1174 {
1175         struct esdhc_platform_data *boarddata = &imx_data->boarddata;
1176         int err;
1177
1178         if (!host->mmc->parent->platform_data) {
1179                 dev_err(mmc_dev(host->mmc), "no board data!\n");
1180                 return -EINVAL;
1181         }
1182
1183         imx_data->boarddata = *((struct esdhc_platform_data *)
1184                                 host->mmc->parent->platform_data);
1185         /* write_protect */
1186         if (boarddata->wp_type == ESDHC_WP_GPIO) {
1187                 err = mmc_gpio_request_ro(host->mmc, boarddata->wp_gpio);
1188                 if (err) {
1189                         dev_err(mmc_dev(host->mmc),
1190                                 "failed to request write-protect gpio!\n");
1191                         return err;
1192                 }
1193                 host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
1194         }
1195
1196         /* card_detect */
1197         switch (boarddata->cd_type) {
1198         case ESDHC_CD_GPIO:
1199                 err = mmc_gpio_request_cd(host->mmc, boarddata->cd_gpio, 0);
1200                 if (err) {
1201                         dev_err(mmc_dev(host->mmc),
1202                                 "failed to request card-detect gpio!\n");
1203                         return err;
1204                 }
1205                 /* fall through */
1206
1207         case ESDHC_CD_CONTROLLER:
1208                 /* we have a working card_detect back */
1209                 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
1210                 break;
1211
1212         case ESDHC_CD_PERMANENT:
1213                 host->mmc->caps |= MMC_CAP_NONREMOVABLE;
1214                 break;
1215
1216         case ESDHC_CD_NONE:
1217                 break;
1218         }
1219
1220         switch (boarddata->max_bus_width) {
1221         case 8:
1222                 host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA;
1223                 break;
1224         case 4:
1225                 host->mmc->caps |= MMC_CAP_4_BIT_DATA;
1226                 break;
1227         case 1:
1228         default:
1229                 host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA;
1230                 break;
1231         }
1232
1233         return 0;
1234 }
1235
1236 static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
1237 {
1238         const struct of_device_id *of_id =
1239                         of_match_device(imx_esdhc_dt_ids, &pdev->dev);
1240         struct sdhci_pltfm_host *pltfm_host;
1241         struct sdhci_host *host;
1242         int err;
1243         struct pltfm_imx_data *imx_data;
1244
1245         host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata,
1246                                 sizeof(*imx_data));
1247         if (IS_ERR(host))
1248                 return PTR_ERR(host);
1249
1250         pltfm_host = sdhci_priv(host);
1251
1252         imx_data = sdhci_pltfm_priv(pltfm_host);
1253
1254         imx_data->socdata = of_id ? of_id->data : (struct esdhc_soc_data *)
1255                                                   pdev->id_entry->driver_data;
1256
1257         imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1258         if (IS_ERR(imx_data->clk_ipg)) {
1259                 err = PTR_ERR(imx_data->clk_ipg);
1260                 goto free_sdhci;
1261         }
1262
1263         imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1264         if (IS_ERR(imx_data->clk_ahb)) {
1265                 err = PTR_ERR(imx_data->clk_ahb);
1266                 goto free_sdhci;
1267         }
1268
1269         imx_data->clk_per = devm_clk_get(&pdev->dev, "per");
1270         if (IS_ERR(imx_data->clk_per)) {
1271                 err = PTR_ERR(imx_data->clk_per);
1272                 goto free_sdhci;
1273         }
1274
1275         pltfm_host->clk = imx_data->clk_per;
1276         pltfm_host->clock = clk_get_rate(pltfm_host->clk);
1277         err = clk_prepare_enable(imx_data->clk_per);
1278         if (err)
1279                 goto free_sdhci;
1280         err = clk_prepare_enable(imx_data->clk_ipg);
1281         if (err)
1282                 goto disable_per_clk;
1283         err = clk_prepare_enable(imx_data->clk_ahb);
1284         if (err)
1285                 goto disable_ipg_clk;
1286
1287         imx_data->pinctrl = devm_pinctrl_get(&pdev->dev);
1288         if (IS_ERR(imx_data->pinctrl)) {
1289                 err = PTR_ERR(imx_data->pinctrl);
1290                 goto disable_ahb_clk;
1291         }
1292
1293         imx_data->pins_default = pinctrl_lookup_state(imx_data->pinctrl,
1294                                                 PINCTRL_STATE_DEFAULT);
1295         if (IS_ERR(imx_data->pins_default))
1296                 dev_warn(mmc_dev(host->mmc), "could not get default state\n");
1297
1298         if (esdhc_is_usdhc(imx_data)) {
1299                 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
1300                 host->mmc->caps |= MMC_CAP_1_8V_DDR;
1301                 if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200))
1302                         host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
1303
1304                 /* clear tuning bits in case ROM has set it already */
1305                 writel(0x0, host->ioaddr + ESDHC_MIX_CTRL);
1306                 writel(0x0, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
1307                 writel(0x0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
1308         }
1309
1310         if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
1311                 sdhci_esdhc_ops.platform_execute_tuning =
1312                                         esdhc_executing_tuning;
1313
1314         if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536)
1315                 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
1316
1317         if (imx_data->socdata->flags & ESDHC_FLAG_HS400)
1318                 host->quirks2 |= SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400;
1319
1320         if (of_id)
1321                 err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data);
1322         else
1323                 err = sdhci_esdhc_imx_probe_nondt(pdev, host, imx_data);
1324         if (err)
1325                 goto disable_ahb_clk;
1326
1327         sdhci_esdhc_imx_hwinit(host);
1328
1329         err = sdhci_add_host(host);
1330         if (err)
1331                 goto disable_ahb_clk;
1332
1333         pm_runtime_set_active(&pdev->dev);
1334         pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1335         pm_runtime_use_autosuspend(&pdev->dev);
1336         pm_suspend_ignore_children(&pdev->dev, 1);
1337         pm_runtime_enable(&pdev->dev);
1338
1339         return 0;
1340
1341 disable_ahb_clk:
1342         clk_disable_unprepare(imx_data->clk_ahb);
1343 disable_ipg_clk:
1344         clk_disable_unprepare(imx_data->clk_ipg);
1345 disable_per_clk:
1346         clk_disable_unprepare(imx_data->clk_per);
1347 free_sdhci:
1348         sdhci_pltfm_free(pdev);
1349         return err;
1350 }
1351
1352 static int sdhci_esdhc_imx_remove(struct platform_device *pdev)
1353 {
1354         struct sdhci_host *host = platform_get_drvdata(pdev);
1355         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1356         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1357         int dead;
1358
1359         pm_runtime_get_sync(&pdev->dev);
1360         dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
1361         pm_runtime_disable(&pdev->dev);
1362         pm_runtime_put_noidle(&pdev->dev);
1363
1364         sdhci_remove_host(host, dead);
1365
1366         clk_disable_unprepare(imx_data->clk_per);
1367         clk_disable_unprepare(imx_data->clk_ipg);
1368         clk_disable_unprepare(imx_data->clk_ahb);
1369
1370         sdhci_pltfm_free(pdev);
1371
1372         return 0;
1373 }
1374
1375 #ifdef CONFIG_PM_SLEEP
1376 static int sdhci_esdhc_suspend(struct device *dev)
1377 {
1378         struct sdhci_host *host = dev_get_drvdata(dev);
1379
1380         if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1381                 mmc_retune_needed(host->mmc);
1382
1383         return sdhci_suspend_host(host);
1384 }
1385
1386 static int sdhci_esdhc_resume(struct device *dev)
1387 {
1388         struct sdhci_host *host = dev_get_drvdata(dev);
1389
1390         /* re-initialize hw state in case it's lost in low power mode */
1391         sdhci_esdhc_imx_hwinit(host);
1392
1393         return sdhci_resume_host(host);
1394 }
1395 #endif
1396
1397 #ifdef CONFIG_PM
1398 static int sdhci_esdhc_runtime_suspend(struct device *dev)
1399 {
1400         struct sdhci_host *host = dev_get_drvdata(dev);
1401         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1402         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1403         int ret;
1404
1405         ret = sdhci_runtime_suspend_host(host);
1406
1407         if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1408                 mmc_retune_needed(host->mmc);
1409
1410         if (!sdhci_sdio_irq_enabled(host)) {
1411                 clk_disable_unprepare(imx_data->clk_per);
1412                 clk_disable_unprepare(imx_data->clk_ipg);
1413         }
1414         clk_disable_unprepare(imx_data->clk_ahb);
1415
1416         return ret;
1417 }
1418
1419 static int sdhci_esdhc_runtime_resume(struct device *dev)
1420 {
1421         struct sdhci_host *host = dev_get_drvdata(dev);
1422         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1423         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1424         int err;
1425
1426         if (!sdhci_sdio_irq_enabled(host)) {
1427                 err = clk_prepare_enable(imx_data->clk_per);
1428                 if (err)
1429                         return err;
1430                 err = clk_prepare_enable(imx_data->clk_ipg);
1431                 if (err)
1432                         goto disable_per_clk;
1433         }
1434         err = clk_prepare_enable(imx_data->clk_ahb);
1435         if (err)
1436                 goto disable_ipg_clk;
1437         err = sdhci_runtime_resume_host(host);
1438         if (err)
1439                 goto disable_ahb_clk;
1440
1441         return 0;
1442
1443 disable_ahb_clk:
1444         clk_disable_unprepare(imx_data->clk_ahb);
1445 disable_ipg_clk:
1446         if (!sdhci_sdio_irq_enabled(host))
1447                 clk_disable_unprepare(imx_data->clk_ipg);
1448 disable_per_clk:
1449         if (!sdhci_sdio_irq_enabled(host))
1450                 clk_disable_unprepare(imx_data->clk_per);
1451         return err;
1452 }
1453 #endif
1454
1455 static const struct dev_pm_ops sdhci_esdhc_pmops = {
1456         SET_SYSTEM_SLEEP_PM_OPS(sdhci_esdhc_suspend, sdhci_esdhc_resume)
1457         SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend,
1458                                 sdhci_esdhc_runtime_resume, NULL)
1459 };
1460
1461 static struct platform_driver sdhci_esdhc_imx_driver = {
1462         .driver         = {
1463                 .name   = "sdhci-esdhc-imx",
1464                 .of_match_table = imx_esdhc_dt_ids,
1465                 .pm     = &sdhci_esdhc_pmops,
1466         },
1467         .id_table       = imx_esdhc_devtype,
1468         .probe          = sdhci_esdhc_imx_probe,
1469         .remove         = sdhci_esdhc_imx_remove,
1470 };
1471
1472 module_platform_driver(sdhci_esdhc_imx_driver);
1473
1474 MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC");
1475 MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>");
1476 MODULE_LICENSE("GPL v2");