drivers/mmc/host/sdhci-esdhc-imx.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Freescale eSDHC i.MX controller driver for the platform bus.
   4  *
   5  * derived from the OF-version.
   6  *
   7  * Copyright (c) 2010 Pengutronix e.K.
   8  *   Author: Wolfram Sang <kernel@pengutronix.de>
   9  */
  10
  11 #include <linux/bitfield.h>
  12 #include <linux/io.h>
  13 #include <linux/iopoll.h>
  14 #include <linux/delay.h>
  15 #include <linux/err.h>
  16 #include <linux/clk.h>
  17 #include <linux/module.h>
  18 #include <linux/slab.h>
  19 #include <linux/pm_qos.h>
  20 #include <linux/mmc/host.h>
  21 #include <linux/mmc/mmc.h>
  22 #include <linux/mmc/sdio.h>
  23 #include <linux/mmc/slot-gpio.h>
  24 #include <linux/of.h>
  25 #include <linux/of_device.h>
  26 #include <linux/pinctrl/consumer.h>
  27 #include <linux/platform_data/mmc-esdhc-imx.h>
  28 #include <linux/pm_runtime.h>
  29 #include "sdhci-cqhci.h"
  30 #include "sdhci-pltfm.h"
  31 #include "sdhci-esdhc.h"
  32 #include "cqhci.h"
  33
  34 #define ESDHC_SYS_CTRL_DTOCV_MASK       0x0f
  35 #define ESDHC_CTRL_D3CD                 0x08
  36 #define ESDHC_BURST_LEN_EN_INCR         (1 << 27)
  37 /* VENDOR SPEC register */
  38 #define ESDHC_VENDOR_SPEC               0xc0
  39 #define  ESDHC_VENDOR_SPEC_SDIO_QUIRK   (1 << 1)
  40 #define  ESDHC_VENDOR_SPEC_VSELECT      (1 << 1)
  41 #define  ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8)
  42 #define ESDHC_DEBUG_SEL_AND_STATUS_REG          0xc2
  43 #define ESDHC_DEBUG_SEL_REG                     0xc3
  44 #define ESDHC_DEBUG_SEL_MASK                    0xf
  45 #define ESDHC_DEBUG_SEL_CMD_STATE               1
  46 #define ESDHC_DEBUG_SEL_DATA_STATE              2
  47 #define ESDHC_DEBUG_SEL_TRANS_STATE             3
  48 #define ESDHC_DEBUG_SEL_DMA_STATE               4
  49 #define ESDHC_DEBUG_SEL_ADMA_STATE              5
  50 #define ESDHC_DEBUG_SEL_FIFO_STATE              6
  51 #define ESDHC_DEBUG_SEL_ASYNC_FIFO_STATE        7
  52 #define ESDHC_WTMK_LVL                  0x44
  53 #define  ESDHC_WTMK_DEFAULT_VAL         0x10401040
  54 #define  ESDHC_WTMK_LVL_RD_WML_MASK     0x000000FF
  55 #define  ESDHC_WTMK_LVL_RD_WML_SHIFT    0
  56 #define  ESDHC_WTMK_LVL_WR_WML_MASK     0x00FF0000
  57 #define  ESDHC_WTMK_LVL_WR_WML_SHIFT    16
  58 #define  ESDHC_WTMK_LVL_WML_VAL_DEF     64
  59 #define  ESDHC_WTMK_LVL_WML_VAL_MAX     128
  60 #define ESDHC_MIX_CTRL                  0x48
  61 #define  ESDHC_MIX_CTRL_DDREN           (1 << 3)
  62 #define  ESDHC_MIX_CTRL_AC23EN          (1 << 7)
  63 #define  ESDHC_MIX_CTRL_EXE_TUNE        (1 << 22)
  64 #define  ESDHC_MIX_CTRL_SMPCLK_SEL      (1 << 23)
  65 #define  ESDHC_MIX_CTRL_AUTO_TUNE_EN    (1 << 24)
  66 #define  ESDHC_MIX_CTRL_FBCLK_SEL       (1 << 25)
  67 #define  ESDHC_MIX_CTRL_HS400_EN        (1 << 26)
  68 #define  ESDHC_MIX_CTRL_HS400_ES_EN     (1 << 27)
  69 /* Bits 3 and 6 are not SDHCI standard definitions */
  70 #define  ESDHC_MIX_CTRL_SDHCI_MASK      0xb7
  71 /* Tuning bits */
  72 #define  ESDHC_MIX_CTRL_TUNING_MASK     0x03c00000
  73
  74 /* dll control register */
  75 #define ESDHC_DLL_CTRL                  0x60
  76 #define ESDHC_DLL_OVERRIDE_VAL_SHIFT    9
  77 #define ESDHC_DLL_OVERRIDE_EN_SHIFT     8
  78
  79 /* tune control register */
  80 #define ESDHC_TUNE_CTRL_STATUS          0x68
  81 #define  ESDHC_TUNE_CTRL_STEP           1
  82 #define  ESDHC_TUNE_CTRL_MIN            0
  83 #define  ESDHC_TUNE_CTRL_MAX            ((1 << 7) - 1)
  84
  85 /* strobe dll register */
  86 #define ESDHC_STROBE_DLL_CTRL           0x70
  87 #define ESDHC_STROBE_DLL_CTRL_ENABLE    (1 << 0)
  88 #define ESDHC_STROBE_DLL_CTRL_RESET     (1 << 1)
  89 #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT    0x7
  90 #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT      3
  91 #define ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT    (4 << 20)
  92
  93 #define ESDHC_STROBE_DLL_STATUS         0x74
  94 #define ESDHC_STROBE_DLL_STS_REF_LOCK   (1 << 1)
  95 #define ESDHC_STROBE_DLL_STS_SLV_LOCK   0x1
  96
  97 #define ESDHC_VEND_SPEC2                0xc8
  98 #define ESDHC_VEND_SPEC2_EN_BUSY_IRQ    (1 << 8)
  99
 100 #define ESDHC_TUNING_CTRL               0xcc
 101 #define ESDHC_STD_TUNING_EN             (1 << 24)
 102 /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
 103 #define ESDHC_TUNING_START_TAP_DEFAULT  0x1
 104 #define ESDHC_TUNING_START_TAP_MASK     0x7f
 105 #define ESDHC_TUNING_CMD_CRC_CHECK_DISABLE      (1 << 7)
 106 #define ESDHC_TUNING_STEP_DEFAULT       0x1
 107 #define ESDHC_TUNING_STEP_MASK          0x00070000
 108 #define ESDHC_TUNING_STEP_SHIFT         16
 109
 110 /* pinctrl state */
 111 #define ESDHC_PINCTRL_STATE_100MHZ      "state_100mhz"
 112 #define ESDHC_PINCTRL_STATE_200MHZ      "state_200mhz"
 113
 114 /*
 115  * Our interpretation of the SDHCI_HOST_CONTROL register
 116  */
 117 #define ESDHC_CTRL_4BITBUS              (0x1 << 1)
 118 #define ESDHC_CTRL_8BITBUS              (0x2 << 1)
 119 #define ESDHC_CTRL_BUSWIDTH_MASK        (0x3 << 1)
 120
 121 /*
 122  * There is an INT DMA ERR mismatch between eSDHC and STD SDHC SPEC:
 123  * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design,
 124  * but bit28 is used as the INT DMA ERR in fsl eSDHC design.
 125  * Define this macro DMA error INT for fsl eSDHC
 126  */
 127 #define ESDHC_INT_VENDOR_SPEC_DMA_ERR   (1 << 28)
 128
 129 /* the address offset of CQHCI */
 130 #define ESDHC_CQHCI_ADDR_OFFSET         0x100
 131
 132 /*
 133  * The CMDTYPE of the CMD register (offset 0xE) should be set to
 134  * "11" when the STOP CMD12 is issued on imx53 to abort one
 135  * open ended multi-blk IO. Otherwise the TC INT wouldn't
 136  * be generated.
 137  * In exact block transfer, the controller doesn't complete the
 138  * operations automatically as required at the end of the
 139  * transfer and remains on hold if the abort command is not sent.
 140  * As a result, the TC flag is not asserted and SW received timeout
 141  * exception. Bit1 of Vendor Spec register is used to fix it.
 142  */
 143 #define ESDHC_FLAG_MULTIBLK_NO_INT      BIT(1)
 144 /*
 145  * The flag tells that the ESDHC controller is an USDHC block that is
 146  * integrated on the i.MX6 series.
 147  */
 148 #define ESDHC_FLAG_USDHC                BIT(3)
 149 /* The IP supports manual tuning process */
 150 #define ESDHC_FLAG_MAN_TUNING           BIT(4)
 151 /* The IP supports standard tuning process */
 152 #define ESDHC_FLAG_STD_TUNING           BIT(5)
 153 /* The IP has SDHCI_CAPABILITIES_1 register */
 154 #define ESDHC_FLAG_HAVE_CAP1            BIT(6)
 155 /*
 156  * The IP has erratum ERR004536
 157  * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow,
 158  * when reading data from the card
 159  * This flag is also set for i.MX25 and i.MX35 in order to get
 160  * SDHCI_QUIRK_BROKEN_ADMA, but for different reasons (ADMA capability bits).
 161  */
 162 #define ESDHC_FLAG_ERR004536            BIT(7)
 163 /* The IP supports HS200 mode */
 164 #define ESDHC_FLAG_HS200                BIT(8)
 165 /* The IP supports HS400 mode */
 166 #define ESDHC_FLAG_HS400                BIT(9)
 167 /*
 168  * The IP has errata ERR010450
 169  * uSDHC: At 1.8V due to the I/O timing limit, for SDR mode, SD card
 170  * clock can't exceed 150MHz, for DDR mode, SD card clock can't exceed 45MHz.
 171  */
 172 #define ESDHC_FLAG_ERR010450            BIT(10)
 173 /* The IP supports HS400ES mode */
 174 #define ESDHC_FLAG_HS400_ES             BIT(11)
 175 /* The IP has Host Controller Interface for Command Queuing */
 176 #define ESDHC_FLAG_CQHCI                BIT(12)
 177 /* need request pmqos during low power */
 178 #define ESDHC_FLAG_PMQOS                BIT(13)
 179 /* The IP state got lost in low power mode */
 180 #define ESDHC_FLAG_STATE_LOST_IN_LPMODE         BIT(14)
 181 /* The IP lost clock rate in PM_RUNTIME */
 182 #define ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME  BIT(15)
 183 /*
 184  * The IP do not support the ACMD23 feature completely when use ADMA mode.
 185  * In ADMA mode, it only use the 16 bit block count of the register 0x4
 186  * (BLOCK_ATT) as the CMD23's argument for ACMD23 mode, which means it will
 187  * ignore the upper 16 bit of the CMD23's argument. This will block the reliable
 188  * write operation in RPMB, because RPMB reliable write need to set the bit31
 189  * of the CMD23's argument.
 190  * imx6qpdl/imx6sx/imx6sl/imx7d has this limitation only for ADMA mode, SDMA
 191  * do not has this limitation. so when these SoC use ADMA mode, it need to
 192  * disable the ACMD23 feature.
 193  */
 194 #define ESDHC_FLAG_BROKEN_AUTO_CMD23    BIT(16)
 195
 196 struct esdhc_soc_data {
 197         u32 flags;
 198 };
 199
 200 static const struct esdhc_soc_data esdhc_imx25_data = {
 201         .flags = ESDHC_FLAG_ERR004536,
 202 };
 203
 204 static const struct esdhc_soc_data esdhc_imx35_data = {
 205         .flags = ESDHC_FLAG_ERR004536,
 206 };
 207
 208 static const struct esdhc_soc_data esdhc_imx51_data = {
 209         .flags = 0,
 210 };
 211
 212 static const struct esdhc_soc_data esdhc_imx53_data = {
 213         .flags = ESDHC_FLAG_MULTIBLK_NO_INT,
 214 };
 215
 216 static const struct esdhc_soc_data usdhc_imx6q_data = {
 217         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING
 218                         | ESDHC_FLAG_BROKEN_AUTO_CMD23,
 219 };
 220
 221 static const struct esdhc_soc_data usdhc_imx6sl_data = {
 222         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 223                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536
 224                         | ESDHC_FLAG_HS200
 225                         | ESDHC_FLAG_BROKEN_AUTO_CMD23,
 226 };
 227
 228 static const struct esdhc_soc_data usdhc_imx6sll_data = {
 229         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 230                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
 231                         | ESDHC_FLAG_HS400
 232                         | ESDHC_FLAG_STATE_LOST_IN_LPMODE,
 233 };
 234
 235 static const struct esdhc_soc_data usdhc_imx6sx_data = {
 236         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 237                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
 238                         | ESDHC_FLAG_STATE_LOST_IN_LPMODE
 239                         | ESDHC_FLAG_BROKEN_AUTO_CMD23,
 240 };
 241
 242 static const struct esdhc_soc_data usdhc_imx6ull_data = {
 243         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 244                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
 245                         | ESDHC_FLAG_ERR010450
 246                         | ESDHC_FLAG_STATE_LOST_IN_LPMODE,
 247 };
 248
 249 static const struct esdhc_soc_data usdhc_imx7d_data = {
 250         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 251                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
 252                         | ESDHC_FLAG_HS400
 253                         | ESDHC_FLAG_STATE_LOST_IN_LPMODE
 254                         | ESDHC_FLAG_BROKEN_AUTO_CMD23,
 255 };
 256
 257 static struct esdhc_soc_data usdhc_imx7ulp_data = {
 258         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 259                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
 260                         | ESDHC_FLAG_PMQOS | ESDHC_FLAG_HS400
 261                         | ESDHC_FLAG_STATE_LOST_IN_LPMODE,
 262 };
 263
 264 static struct esdhc_soc_data usdhc_imx8qxp_data = {
 265         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 266                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
 267                         | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES
 268                         | ESDHC_FLAG_STATE_LOST_IN_LPMODE
 269                         | ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME,
 270 };
 271
 272 static struct esdhc_soc_data usdhc_imx8mm_data = {
 273         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 274                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
 275                         | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES
 276                         | ESDHC_FLAG_STATE_LOST_IN_LPMODE,
 277 };
 278
 279 struct pltfm_imx_data {
 280         u32 scratchpad;
 281         struct pinctrl *pinctrl;
 282         struct pinctrl_state *pins_100mhz;
 283         struct pinctrl_state *pins_200mhz;
 284         const struct esdhc_soc_data *socdata;
 285         struct esdhc_platform_data boarddata;
 286         struct clk *clk_ipg;
 287         struct clk *clk_ahb;
 288         struct clk *clk_per;
 289         unsigned int actual_clock;
 290         enum {
 291                 NO_CMD_PENDING,      /* no multiblock command pending */
 292                 MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */
 293                 WAIT_FOR_INT,        /* sent CMD12, waiting for response INT */
 294         } multiblock_status;
 295         u32 is_ddr;
 296         struct pm_qos_request pm_qos_req;
 297 };
 298
 299 static const struct of_device_id imx_esdhc_dt_ids[] = {
 300         { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, },
 301         { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, },
 302         { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, },
 303         { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, },
 304         { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, },
 305         { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, },
 306         { .compatible = "fsl,imx6sll-usdhc", .data = &usdhc_imx6sll_data, },
 307         { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, },
 308         { .compatible = "fsl,imx6ull-usdhc", .data = &usdhc_imx6ull_data, },
 309         { .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, },
 310         { .compatible = "fsl,imx7ulp-usdhc", .data = &usdhc_imx7ulp_data, },
 311         { .compatible = "fsl,imx8qxp-usdhc", .data = &usdhc_imx8qxp_data, },
 312         { .compatible = "fsl,imx8mm-usdhc", .data = &usdhc_imx8mm_data, },
 313         { /* sentinel */ }
 314 };
 315 MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids);
 316
 317 static inline int is_imx25_esdhc(struct pltfm_imx_data *data)
 318 {
 319         return data->socdata == &esdhc_imx25_data;
 320 }
 321
 322 static inline int is_imx53_esdhc(struct pltfm_imx_data *data)
 323 {
 324         return data->socdata == &esdhc_imx53_data;
 325 }
 326
 327 static inline int is_imx6q_usdhc(struct pltfm_imx_data *data)
 328 {
 329         return data->socdata == &usdhc_imx6q_data;
 330 }
 331
 332 static inline int esdhc_is_usdhc(struct pltfm_imx_data *data)
 333 {
 334         return !!(data->socdata->flags & ESDHC_FLAG_USDHC);
 335 }
 336
 337 static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
 338 {
 339         void __iomem *base = host->ioaddr + (reg & ~0x3);
 340         u32 shift = (reg & 0x3) * 8;
 341
 342         writel(((readl(base) & ~(mask << shift)) | (val << shift)), base);
 343 }
 344
 345 #define DRIVER_NAME "sdhci-esdhc-imx"
 346 #define ESDHC_IMX_DUMP(f, x...) \
 347         pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
 348 static void esdhc_dump_debug_regs(struct sdhci_host *host)
 349 {
 350         int i;
 351         char *debug_status[7] = {
 352                                  "cmd debug status",
 353                                  "data debug status",
 354                                  "trans debug status",
 355                                  "dma debug status",
 356                                  "adma debug status",
 357                                  "fifo debug status",
 358                                  "async fifo debug status"
 359         };
 360
 361         ESDHC_IMX_DUMP("========= ESDHC IMX DEBUG STATUS DUMP =========\n");
 362         for (i = 0; i < 7; i++) {
 363                 esdhc_clrset_le(host, ESDHC_DEBUG_SEL_MASK,
 364                         ESDHC_DEBUG_SEL_CMD_STATE + i, ESDHC_DEBUG_SEL_REG);
 365                 ESDHC_IMX_DUMP("%s:  0x%04x\n", debug_status[i],
 366                         readw(host->ioaddr + ESDHC_DEBUG_SEL_AND_STATUS_REG));
 367         }
 368
 369         esdhc_clrset_le(host, ESDHC_DEBUG_SEL_MASK, 0, ESDHC_DEBUG_SEL_REG);
 370
 371 }
 372
 373 static inline void esdhc_wait_for_card_clock_gate_off(struct sdhci_host *host)
 374 {
 375         u32 present_state;
 376         int ret;
 377
 378         ret = readl_poll_timeout(host->ioaddr + ESDHC_PRSSTAT, present_state,
 379                                 (present_state & ESDHC_CLOCK_GATE_OFF), 2, 100);
 380         if (ret == -ETIMEDOUT)
 381                 dev_warn(mmc_dev(host->mmc), "%s: card clock still not gate off in 100us!.\n", __func__);
 382 }
 383
 384 static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
 385 {
 386         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 387         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 388         u32 val = readl(host->ioaddr + reg);
 389
 390         if (unlikely(reg == SDHCI_PRESENT_STATE)) {
 391                 u32 fsl_prss = val;
 392                 /* save the least 20 bits */
 393                 val = fsl_prss & 0x000FFFFF;
 394                 /* move dat[0-3] bits */
 395                 val |= (fsl_prss & 0x0F000000) >> 4;
 396                 /* move cmd line bit */
 397                 val |= (fsl_prss & 0x00800000) << 1;
 398         }
 399
 400         if (unlikely(reg == SDHCI_CAPABILITIES)) {
 401                 /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */
 402                 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
 403                         val &= 0xffff0000;
 404
 405                 /* In FSL esdhc IC module, only bit20 is used to indicate the
 406                  * ADMA2 capability of esdhc, but this bit is messed up on
 407                  * some SOCs (e.g. on MX25, MX35 this bit is set, but they
 408                  * don't actually support ADMA2). So set the BROKEN_ADMA
 409                  * quirk on MX25/35 platforms.
 410                  */
 411
 412                 if (val & SDHCI_CAN_DO_ADMA1) {
 413                         val &= ~SDHCI_CAN_DO_ADMA1;
 414                         val |= SDHCI_CAN_DO_ADMA2;
 415                 }
 416         }
 417
 418         if (unlikely(reg == SDHCI_CAPABILITIES_1)) {
 419                 if (esdhc_is_usdhc(imx_data)) {
 420                         if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
 421                                 val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF;
 422                         else
 423                                 /* imx6q/dl does not have cap_1 register, fake one */
 424                                 val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104
 425                                         | SDHCI_SUPPORT_SDR50
 426                                         | SDHCI_USE_SDR50_TUNING
 427                                         | FIELD_PREP(SDHCI_RETUNING_MODE_MASK,
 428                                                      SDHCI_TUNING_MODE_3);
 429
 430                         if (imx_data->socdata->flags & ESDHC_FLAG_HS400)
 431                                 val |= SDHCI_SUPPORT_HS400;
 432
 433                         /*
 434                          * Do not advertise faster UHS modes if there are no
 435                          * pinctrl states for 100MHz/200MHz.
 436                          */
 437                         if (IS_ERR_OR_NULL(imx_data->pins_100mhz) ||
 438                             IS_ERR_OR_NULL(imx_data->pins_200mhz))
 439                                 val &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50
 440                                          | SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_HS400);
 441                 }
 442         }
 443
 444         if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) {
 445                 val = 0;
 446                 val |= FIELD_PREP(SDHCI_MAX_CURRENT_330_MASK, 0xFF);
 447                 val |= FIELD_PREP(SDHCI_MAX_CURRENT_300_MASK, 0xFF);
 448                 val |= FIELD_PREP(SDHCI_MAX_CURRENT_180_MASK, 0xFF);
 449         }
 450
 451         if (unlikely(reg == SDHCI_INT_STATUS)) {
 452                 if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) {
 453                         val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR;
 454                         val |= SDHCI_INT_ADMA_ERROR;
 455                 }
 456
 457                 /*
 458                  * mask off the interrupt we get in response to the manually
 459                  * sent CMD12
 460                  */
 461                 if ((imx_data->multiblock_status == WAIT_FOR_INT) &&
 462                     ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) {
 463                         val &= ~SDHCI_INT_RESPONSE;
 464                         writel(SDHCI_INT_RESPONSE, host->ioaddr +
 465                                                    SDHCI_INT_STATUS);
 466                         imx_data->multiblock_status = NO_CMD_PENDING;
 467                 }
 468         }
 469
 470         return val;
 471 }
 472
 473 static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
 474 {
 475         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 476         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 477         u32 data;
 478
 479         if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE ||
 480                         reg == SDHCI_INT_STATUS)) {
 481                 if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) {
 482                         /*
 483                          * Clear and then set D3CD bit to avoid missing the
 484                          * card interrupt. This is an eSDHC controller problem
 485                          * so we need to apply the following workaround: clear
 486                          * and set D3CD bit will make eSDHC re-sample the card
 487                          * interrupt. In case a card interrupt was lost,
 488                          * re-sample it by the following steps.
 489                          */
 490                         data = readl(host->ioaddr + SDHCI_HOST_CONTROL);
 491                         data &= ~ESDHC_CTRL_D3CD;
 492                         writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
 493                         data |= ESDHC_CTRL_D3CD;
 494                         writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
 495                 }
 496
 497                 if (val & SDHCI_INT_ADMA_ERROR) {
 498                         val &= ~SDHCI_INT_ADMA_ERROR;
 499                         val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR;
 500                 }
 501         }
 502
 503         if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
 504                                 && (reg == SDHCI_INT_STATUS)
 505                                 && (val & SDHCI_INT_DATA_END))) {
 506                         u32 v;
 507                         v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 508                         v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK;
 509                         writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
 510
 511                         if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS)
 512                         {
 513                                 /* send a manual CMD12 with RESPTYP=none */
 514                                 data = MMC_STOP_TRANSMISSION << 24 |
 515                                        SDHCI_CMD_ABORTCMD << 16;
 516                                 writel(data, host->ioaddr + SDHCI_TRANSFER_MODE);
 517                                 imx_data->multiblock_status = WAIT_FOR_INT;
 518                         }
 519         }
 520
 521         writel(val, host->ioaddr + reg);
 522 }
 523
 524 static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
 525 {
 526         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 527         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 528         u16 ret = 0;
 529         u32 val;
 530
 531         if (unlikely(reg == SDHCI_HOST_VERSION)) {
 532                 reg ^= 2;
 533                 if (esdhc_is_usdhc(imx_data)) {
 534                         /*
 535                          * The usdhc register returns a wrong host version.
 536                          * Correct it here.
 537                          */
 538                         return SDHCI_SPEC_300;
 539                 }
 540         }
 541
 542         if (unlikely(reg == SDHCI_HOST_CONTROL2)) {
 543                 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 544                 if (val & ESDHC_VENDOR_SPEC_VSELECT)
 545                         ret |= SDHCI_CTRL_VDD_180;
 546
 547                 if (esdhc_is_usdhc(imx_data)) {
 548                         if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
 549                                 val = readl(host->ioaddr + ESDHC_MIX_CTRL);
 550                         else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING)
 551                                 /* the std tuning bits is in ACMD12_ERR for imx6sl */
 552                                 val = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
 553                 }
 554
 555                 if (val & ESDHC_MIX_CTRL_EXE_TUNE)
 556                         ret |= SDHCI_CTRL_EXEC_TUNING;
 557                 if (val & ESDHC_MIX_CTRL_SMPCLK_SEL)
 558                         ret |= SDHCI_CTRL_TUNED_CLK;
 559
 560                 ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
 561
 562                 return ret;
 563         }
 564
 565         if (unlikely(reg == SDHCI_TRANSFER_MODE)) {
 566                 if (esdhc_is_usdhc(imx_data)) {
 567                         u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
 568                         ret = m & ESDHC_MIX_CTRL_SDHCI_MASK;
 569                         /* Swap AC23 bit */
 570                         if (m & ESDHC_MIX_CTRL_AC23EN) {
 571                                 ret &= ~ESDHC_MIX_CTRL_AC23EN;
 572                                 ret |= SDHCI_TRNS_AUTO_CMD23;
 573                         }
 574                 } else {
 575                         ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE);
 576                 }
 577
 578                 return ret;
 579         }
 580
 581         return readw(host->ioaddr + reg);
 582 }
 583
 584 static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
 585 {
 586         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 587         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 588         u32 new_val = 0;
 589
 590         switch (reg) {
 591         case SDHCI_CLOCK_CONTROL:
 592                 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 593                 if (val & SDHCI_CLOCK_CARD_EN)
 594                         new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
 595                 else
 596                         new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
 597                 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
 598                 if (!(new_val & ESDHC_VENDOR_SPEC_FRC_SDCLK_ON))
 599                         esdhc_wait_for_card_clock_gate_off(host);
 600                 return;
 601         case SDHCI_HOST_CONTROL2:
 602                 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 603                 if (val & SDHCI_CTRL_VDD_180)
 604                         new_val |= ESDHC_VENDOR_SPEC_VSELECT;
 605                 else
 606                         new_val &= ~ESDHC_VENDOR_SPEC_VSELECT;
 607                 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
 608                 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
 609                         new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
 610                         if (val & SDHCI_CTRL_TUNED_CLK) {
 611                                 new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL;
 612                                 new_val |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
 613                         } else {
 614                                 new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
 615                                 new_val &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN;
 616                         }
 617                         writel(new_val , host->ioaddr + ESDHC_MIX_CTRL);
 618                 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
 619                         u32 v = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
 620                         u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
 621                         if (val & SDHCI_CTRL_TUNED_CLK) {
 622                                 v |= ESDHC_MIX_CTRL_SMPCLK_SEL;
 623                         } else {
 624                                 v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
 625                                 m &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
 626                                 m &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN;
 627                         }
 628
 629                         if (val & SDHCI_CTRL_EXEC_TUNING) {
 630                                 v |= ESDHC_MIX_CTRL_EXE_TUNE;
 631                                 m |= ESDHC_MIX_CTRL_FBCLK_SEL;
 632                                 m |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
 633                         } else {
 634                                 v &= ~ESDHC_MIX_CTRL_EXE_TUNE;
 635                         }
 636
 637                         writel(v, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
 638                         writel(m, host->ioaddr + ESDHC_MIX_CTRL);
 639                 }
 640                 return;
 641         case SDHCI_TRANSFER_MODE:
 642                 if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
 643                                 && (host->cmd->opcode == SD_IO_RW_EXTENDED)
 644                                 && (host->cmd->data->blocks > 1)
 645                                 && (host->cmd->data->flags & MMC_DATA_READ)) {
 646                         u32 v;
 647                         v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 648                         v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK;
 649                         writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
 650                 }
 651
 652                 if (esdhc_is_usdhc(imx_data)) {
 653                         u32 wml;
 654                         u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
 655                         /* Swap AC23 bit */
 656                         if (val & SDHCI_TRNS_AUTO_CMD23) {
 657                                 val &= ~SDHCI_TRNS_AUTO_CMD23;
 658                                 val |= ESDHC_MIX_CTRL_AC23EN;
 659                         }
 660                         m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK);
 661                         writel(m, host->ioaddr + ESDHC_MIX_CTRL);
 662
 663                         /* Set watermark levels for PIO access to maximum value
 664                          * (128 words) to accommodate full 512 bytes buffer.
 665                          * For DMA access restore the levels to default value.
 666                          */
 667                         m = readl(host->ioaddr + ESDHC_WTMK_LVL);
 668                         if (val & SDHCI_TRNS_DMA) {
 669                                 wml = ESDHC_WTMK_LVL_WML_VAL_DEF;
 670                         } else {
 671                                 u8 ctrl;
 672                                 wml = ESDHC_WTMK_LVL_WML_VAL_MAX;
 673
 674                                 /*
 675                                  * Since already disable DMA mode, so also need
 676                                  * to clear the DMASEL. Otherwise, for standard
 677                                  * tuning, when send tuning command, usdhc will
 678                                  * still prefetch the ADMA script from wrong
 679                                  * DMA address, then we will see IOMMU report
 680                                  * some error which show lack of TLB mapping.
 681                                  */
 682                                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 683                                 ctrl &= ~SDHCI_CTRL_DMA_MASK;
 684                                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 685                         }
 686                         m &= ~(ESDHC_WTMK_LVL_RD_WML_MASK |
 687                                ESDHC_WTMK_LVL_WR_WML_MASK);
 688                         m |= (wml << ESDHC_WTMK_LVL_RD_WML_SHIFT) |
 689                              (wml << ESDHC_WTMK_LVL_WR_WML_SHIFT);
 690                         writel(m, host->ioaddr + ESDHC_WTMK_LVL);
 691                 } else {
 692                         /*
 693                          * Postpone this write, we must do it together with a
 694                          * command write that is down below.
 695                          */
 696                         imx_data->scratchpad = val;
 697                 }
 698                 return;
 699         case SDHCI_COMMAND:
 700                 if (host->cmd->opcode == MMC_STOP_TRANSMISSION)
 701                         val |= SDHCI_CMD_ABORTCMD;
 702
 703                 if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) &&
 704                     (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
 705                         imx_data->multiblock_status = MULTIBLK_IN_PROCESS;
 706
 707                 if (esdhc_is_usdhc(imx_data))
 708                         writel(val << 16,
 709                                host->ioaddr + SDHCI_TRANSFER_MODE);
 710                 else
 711                         writel(val << 16 | imx_data->scratchpad,
 712                                host->ioaddr + SDHCI_TRANSFER_MODE);
 713                 return;
 714         case SDHCI_BLOCK_SIZE:
 715                 val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
 716                 break;
 717         }
 718         esdhc_clrset_le(host, 0xffff, val, reg);
 719 }
 720
 721 static u8 esdhc_readb_le(struct sdhci_host *host, int reg)
 722 {
 723         u8 ret;
 724         u32 val;
 725
 726         switch (reg) {
 727         case SDHCI_HOST_CONTROL:
 728                 val = readl(host->ioaddr + reg);
 729
 730                 ret = val & SDHCI_CTRL_LED;
 731                 ret |= (val >> 5) & SDHCI_CTRL_DMA_MASK;
 732                 ret |= (val & ESDHC_CTRL_4BITBUS);
 733                 ret |= (val & ESDHC_CTRL_8BITBUS) << 3;
 734                 return ret;
 735         }
 736
 737         return readb(host->ioaddr + reg);
 738 }
 739
 740 static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
 741 {
 742         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 743         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 744         u32 new_val = 0;
 745         u32 mask;
 746
 747         switch (reg) {
 748         case SDHCI_POWER_CONTROL:
 749                 /*
 750                  * FSL put some DMA bits here
 751                  * If your board has a regulator, code should be here
 752                  */
 753                 return;
 754         case SDHCI_HOST_CONTROL:
 755                 /* FSL messed up here, so we need to manually compose it. */
 756                 new_val = val & SDHCI_CTRL_LED;
 757                 /* ensure the endianness */
 758                 new_val |= ESDHC_HOST_CONTROL_LE;
 759                 /* bits 8&9 are reserved on mx25 */
 760                 if (!is_imx25_esdhc(imx_data)) {
 761                         /* DMA mode bits are shifted */
 762                         new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5;
 763                 }
 764
 765                 /*
 766                  * Do not touch buswidth bits here. This is done in
 767                  * esdhc_pltfm_bus_width.
 768                  * Do not touch the D3CD bit either which is used for the
 769                  * SDIO interrupt erratum workaround.
 770                  */
 771                 mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD);
 772
 773                 esdhc_clrset_le(host, mask, new_val, reg);
 774                 return;
 775         case SDHCI_SOFTWARE_RESET:
 776                 if (val & SDHCI_RESET_DATA)
 777                         new_val = readl(host->ioaddr + SDHCI_HOST_CONTROL);
 778                 break;
 779         }
 780         esdhc_clrset_le(host, 0xff, val, reg);
 781
 782         if (reg == SDHCI_SOFTWARE_RESET) {
 783                 if (val & SDHCI_RESET_ALL) {
 784                         /*
 785                          * The esdhc has a design violation to SDHC spec which
 786                          * tells that software reset should not affect card
 787                          * detection circuit. But esdhc clears its SYSCTL
 788                          * register bits [0..2] during the software reset. This
 789                          * will stop those clocks that card detection circuit
 790                          * relies on. To work around it, we turn the clocks on
 791                          * back to keep card detection circuit functional.
 792                          */
 793                         esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL);
 794                         /*
 795                          * The reset on usdhc fails to clear MIX_CTRL register.
 796                          * Do it manually here.
 797                          */
 798                         if (esdhc_is_usdhc(imx_data)) {
 799                                 /*
 800                                  * the tuning bits should be kept during reset
 801                                  */
 802                                 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
 803                                 writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK,
 804                                                 host->ioaddr + ESDHC_MIX_CTRL);
 805                                 imx_data->is_ddr = 0;
 806                         }
 807                 } else if (val & SDHCI_RESET_DATA) {
 808                         /*
 809                          * The eSDHC DAT line software reset clears at least the
 810                          * data transfer width on i.MX25, so make sure that the
 811                          * Host Control register is unaffected.
 812                          */
 813                         esdhc_clrset_le(host, 0xff, new_val,
 814                                         SDHCI_HOST_CONTROL);
 815                 }
 816         }
 817 }
 818
 819 static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host)
 820 {
 821         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 822
 823         return pltfm_host->clock;
 824 }
 825
 826 static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
 827 {
 828         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 829
 830         return pltfm_host->clock / 256 / 16;
 831 }
 832
 833 static inline void esdhc_pltfm_set_clock(struct sdhci_host *host,
 834                                          unsigned int clock)
 835 {
 836         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 837         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 838         unsigned int host_clock = pltfm_host->clock;
 839         int ddr_pre_div = imx_data->is_ddr ? 2 : 1;
 840         int pre_div = 1;
 841         int div = 1;
 842         int ret;
 843         u32 temp, val;
 844
 845         if (esdhc_is_usdhc(imx_data)) {
 846                 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 847                 writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
 848                         host->ioaddr + ESDHC_VENDOR_SPEC);
 849                 esdhc_wait_for_card_clock_gate_off(host);
 850         }
 851
 852         if (clock == 0) {
 853                 host->mmc->actual_clock = 0;
 854                 return;
 855         }
 856
 857         /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
 858         if (is_imx53_esdhc(imx_data)) {
 859                 /*
 860                  * According to the i.MX53 reference manual, if DLLCTRL[10] can
 861                  * be set, then the controller is eSDHCv3, else it is eSDHCv2.
 862                  */
 863                 val = readl(host->ioaddr + ESDHC_DLL_CTRL);
 864                 writel(val | BIT(10), host->ioaddr + ESDHC_DLL_CTRL);
 865                 temp = readl(host->ioaddr + ESDHC_DLL_CTRL);
 866                 writel(val, host->ioaddr + ESDHC_DLL_CTRL);
 867                 if (temp & BIT(10))
 868                         pre_div = 2;
 869         }
 870
 871         temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
 872         temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
 873                 | ESDHC_CLOCK_MASK);
 874         sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
 875
 876         if ((imx_data->socdata->flags & ESDHC_FLAG_ERR010450) &&
 877             (!(host->quirks2 & SDHCI_QUIRK2_NO_1_8_V))) {
 878                 unsigned int max_clock;
 879
 880                 max_clock = imx_data->is_ddr ? 45000000 : 150000000;
 881
 882                 clock = min(clock, max_clock);
 883         }
 884
 885         while (host_clock / (16 * pre_div * ddr_pre_div) > clock &&
 886                         pre_div < 256)
 887                 pre_div *= 2;
 888
 889         while (host_clock / (div * pre_div * ddr_pre_div) > clock && div < 16)
 890                 div++;
 891
 892         host->mmc->actual_clock = host_clock / (div * pre_div * ddr_pre_div);
 893         dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
 894                 clock, host->mmc->actual_clock);
 895
 896         pre_div >>= 1;
 897         div--;
 898
 899         temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
 900         temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
 901                 | (div << ESDHC_DIVIDER_SHIFT)
 902                 | (pre_div << ESDHC_PREDIV_SHIFT));
 903         sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
 904
 905         /* need to wait the bit 3 of the PRSSTAT to be set, make sure card clock is stable */
 906         ret = readl_poll_timeout(host->ioaddr + ESDHC_PRSSTAT, temp,
 907                                 (temp & ESDHC_CLOCK_STABLE), 2, 100);
 908         if (ret == -ETIMEDOUT)
 909                 dev_warn(mmc_dev(host->mmc), "card clock still not stable in 100us!.\n");
 910
 911         if (esdhc_is_usdhc(imx_data)) {
 912                 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 913                 writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
 914                         host->ioaddr + ESDHC_VENDOR_SPEC);
 915         }
 916
 917 }
 918
 919 static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host)
 920 {
 921         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 922         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 923         struct esdhc_platform_data *boarddata = &imx_data->boarddata;
 924
 925         switch (boarddata->wp_type) {
 926         case ESDHC_WP_GPIO:
 927                 return mmc_gpio_get_ro(host->mmc);
 928         case ESDHC_WP_CONTROLLER:
 929                 return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
 930                                SDHCI_WRITE_PROTECT);
 931         case ESDHC_WP_NONE:
 932                 break;
 933         }
 934
 935         return -ENOSYS;
 936 }
 937
 938 static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
 939 {
 940         u32 ctrl;
 941
 942         switch (width) {
 943         case MMC_BUS_WIDTH_8:
 944                 ctrl = ESDHC_CTRL_8BITBUS;
 945                 break;
 946         case MMC_BUS_WIDTH_4:
 947                 ctrl = ESDHC_CTRL_4BITBUS;
 948                 break;
 949         default:
 950                 ctrl = 0;
 951                 break;
 952         }
 953
 954         esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl,
 955                         SDHCI_HOST_CONTROL);
 956 }
 957
 958 static int usdhc_execute_tuning(struct mmc_host *mmc, u32 opcode)
 959 {
 960         struct sdhci_host *host = mmc_priv(mmc);
 961
 962         /*
 963          * i.MX uSDHC internally already uses a fixed optimized timing for
 964          * DDR50, normally does not require tuning for DDR50 mode.
 965          */
 966         if (host->timing == MMC_TIMING_UHS_DDR50)
 967                 return 0;
 968
 969         return sdhci_execute_tuning(mmc, opcode);
 970 }
 971
 972 static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val)
 973 {
 974         u32 reg;
 975         u8 sw_rst;
 976         int ret;
 977
 978         /* FIXME: delay a bit for card to be ready for next tuning due to errors */
 979         mdelay(1);
 980
 981         /* IC suggest to reset USDHC before every tuning command */
 982         esdhc_clrset_le(host, 0xff, SDHCI_RESET_ALL, SDHCI_SOFTWARE_RESET);
 983         ret = readb_poll_timeout(host->ioaddr + SDHCI_SOFTWARE_RESET, sw_rst,
 984                                 !(sw_rst & SDHCI_RESET_ALL), 10, 100);
 985         if (ret == -ETIMEDOUT)
 986                 dev_warn(mmc_dev(host->mmc),
 987                 "warning! RESET_ALL never complete before sending tuning command\n");
 988
 989         reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
 990         reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL |
 991                         ESDHC_MIX_CTRL_FBCLK_SEL;
 992         writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
 993         writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
 994         dev_dbg(mmc_dev(host->mmc),
 995                 "tuning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n",
 996                         val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS));
 997 }
 998
 999 static void esdhc_post_tuning(struct sdhci_host *host)
1000 {
1001         u32 reg;
1002
1003         reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
1004         reg &= ~ESDHC_MIX_CTRL_EXE_TUNE;
1005         reg |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
1006         writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
1007 }
1008
1009 static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode)
1010 {
1011         int min, max, avg, ret;
1012
1013         /* find the mininum delay first which can pass tuning */
1014         min = ESDHC_TUNE_CTRL_MIN;
1015         while (min < ESDHC_TUNE_CTRL_MAX) {
1016                 esdhc_prepare_tuning(host, min);
1017                 if (!mmc_send_tuning(host->mmc, opcode, NULL))
1018                         break;
1019                 min += ESDHC_TUNE_CTRL_STEP;
1020         }
1021
1022         /* find the maxinum delay which can not pass tuning */
1023         max = min + ESDHC_TUNE_CTRL_STEP;
1024         while (max < ESDHC_TUNE_CTRL_MAX) {
1025                 esdhc_prepare_tuning(host, max);
1026                 if (mmc_send_tuning(host->mmc, opcode, NULL)) {
1027                         max -= ESDHC_TUNE_CTRL_STEP;
1028                         break;
1029                 }
1030                 max += ESDHC_TUNE_CTRL_STEP;
1031         }
1032
1033         /* use average delay to get the best timing */
1034         avg = (min + max) / 2;
1035         esdhc_prepare_tuning(host, avg);
1036         ret = mmc_send_tuning(host->mmc, opcode, NULL);
1037         esdhc_post_tuning(host);
1038
1039         dev_dbg(mmc_dev(host->mmc), "tuning %s at 0x%x ret %d\n",
1040                 ret ? "failed" : "passed", avg, ret);
1041
1042         return ret;
1043 }
1044
1045 static void esdhc_hs400_enhanced_strobe(struct mmc_host *mmc, struct mmc_ios *ios)
1046 {
1047         struct sdhci_host *host = mmc_priv(mmc);
1048         u32 m;
1049
1050         m = readl(host->ioaddr + ESDHC_MIX_CTRL);
1051         if (ios->enhanced_strobe)
1052                 m |= ESDHC_MIX_CTRL_HS400_ES_EN;
1053         else
1054                 m &= ~ESDHC_MIX_CTRL_HS400_ES_EN;
1055         writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1056 }
1057
1058 static int esdhc_change_pinstate(struct sdhci_host *host,
1059                                                 unsigned int uhs)
1060 {
1061         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1062         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1063         struct pinctrl_state *pinctrl;
1064
1065         dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs);
1066
1067         if (IS_ERR(imx_data->pinctrl) ||
1068                 IS_ERR(imx_data->pins_100mhz) ||
1069                 IS_ERR(imx_data->pins_200mhz))
1070                 return -EINVAL;
1071
1072         switch (uhs) {
1073         case MMC_TIMING_UHS_SDR50:
1074         case MMC_TIMING_UHS_DDR50:
1075                 pinctrl = imx_data->pins_100mhz;
1076                 break;
1077         case MMC_TIMING_UHS_SDR104:
1078         case MMC_TIMING_MMC_HS200:
1079         case MMC_TIMING_MMC_HS400:
1080                 pinctrl = imx_data->pins_200mhz;
1081                 break;
1082         default:
1083                 /* back to default state for other legacy timing */
1084                 return pinctrl_select_default_state(mmc_dev(host->mmc));
1085         }
1086
1087         return pinctrl_select_state(imx_data->pinctrl, pinctrl);
1088 }
1089
1090 /*
1091  * For HS400 eMMC, there is a data_strobe line. This signal is generated
1092  * by the device and used for data output and CRC status response output
1093  * in HS400 mode. The frequency of this signal follows the frequency of
1094  * CLK generated by host. The host receives the data which is aligned to the
1095  * edge of data_strobe line. Due to the time delay between CLK line and
1096  * data_strobe line, if the delay time is larger than one clock cycle,
1097  * then CLK and data_strobe line will be misaligned, read error shows up.
1098  */
1099 static void esdhc_set_strobe_dll(struct sdhci_host *host)
1100 {
1101         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1102         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1103         u32 strobe_delay;
1104         u32 v;
1105         int ret;
1106
1107         /* disable clock before enabling strobe dll */
1108         writel(readl(host->ioaddr + ESDHC_VENDOR_SPEC) &
1109                 ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
1110                 host->ioaddr + ESDHC_VENDOR_SPEC);
1111         esdhc_wait_for_card_clock_gate_off(host);
1112
1113         /* force a reset on strobe dll */
1114         writel(ESDHC_STROBE_DLL_CTRL_RESET,
1115                 host->ioaddr + ESDHC_STROBE_DLL_CTRL);
1116         /* clear the reset bit on strobe dll before any setting */
1117         writel(0, host->ioaddr + ESDHC_STROBE_DLL_CTRL);
1118
1119         /*
1120          * enable strobe dll ctrl and adjust the delay target
1121          * for the uSDHC loopback read clock
1122          */
1123         if (imx_data->boarddata.strobe_dll_delay_target)
1124                 strobe_delay = imx_data->boarddata.strobe_dll_delay_target;
1125         else
1126                 strobe_delay = ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT;
1127         v = ESDHC_STROBE_DLL_CTRL_ENABLE |
1128                 ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT |
1129                 (strobe_delay << ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
1130         writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL);
1131
1132         /* wait max 50us to get the REF/SLV lock */
1133         ret = readl_poll_timeout(host->ioaddr + ESDHC_STROBE_DLL_STATUS, v,
1134                 ((v & ESDHC_STROBE_DLL_STS_REF_LOCK) && (v & ESDHC_STROBE_DLL_STS_SLV_LOCK)), 1, 50);
1135         if (ret == -ETIMEDOUT)
1136                 dev_warn(mmc_dev(host->mmc),
1137                 "warning! HS400 strobe DLL status REF/SLV not lock in 50us, STROBE DLL status is %x!\n", v);
1138 }
1139
1140 static void esdhc_reset_tuning(struct sdhci_host *host)
1141 {
1142         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1143         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1144         u32 ctrl;
1145         int ret;
1146
1147         /* Reset the tuning circuit */
1148         if (esdhc_is_usdhc(imx_data)) {
1149                 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
1150                         ctrl = readl(host->ioaddr + ESDHC_MIX_CTRL);
1151                         ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
1152                         ctrl &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
1153                         writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL);
1154                         writel(0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
1155                 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
1156                         ctrl = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
1157                         ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
1158                         ctrl &= ~ESDHC_MIX_CTRL_EXE_TUNE;
1159                         writel(ctrl, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
1160                         /* Make sure ESDHC_MIX_CTRL_EXE_TUNE cleared */
1161                         ret = readl_poll_timeout(host->ioaddr + SDHCI_AUTO_CMD_STATUS,
1162                                 ctrl, !(ctrl & ESDHC_MIX_CTRL_EXE_TUNE), 1, 50);
1163                         if (ret == -ETIMEDOUT)
1164                                 dev_warn(mmc_dev(host->mmc),
1165                                  "Warning! clear execute tuning bit failed\n");
1166                         /*
1167                          * SDHCI_INT_DATA_AVAIL is W1C bit, set this bit will clear the
1168                          * usdhc IP internal logic flag execute_tuning_with_clr_buf, which
1169                          * will finally make sure the normal data transfer logic correct.
1170                          */
1171                         ctrl = readl(host->ioaddr + SDHCI_INT_STATUS);
1172                         ctrl |= SDHCI_INT_DATA_AVAIL;
1173                         writel(ctrl, host->ioaddr + SDHCI_INT_STATUS);
1174                 }
1175         }
1176 }
1177
1178 static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1179 {
1180         u32 m;
1181         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1182         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1183         struct esdhc_platform_data *boarddata = &imx_data->boarddata;
1184
1185         /* disable ddr mode and disable HS400 mode */
1186         m = readl(host->ioaddr + ESDHC_MIX_CTRL);
1187         m &= ~(ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN);
1188         imx_data->is_ddr = 0;
1189
1190         switch (timing) {
1191         case MMC_TIMING_UHS_SDR12:
1192         case MMC_TIMING_UHS_SDR25:
1193         case MMC_TIMING_UHS_SDR50:
1194         case MMC_TIMING_UHS_SDR104:
1195         case MMC_TIMING_MMC_HS:
1196         case MMC_TIMING_MMC_HS200:
1197                 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1198                 break;
1199         case MMC_TIMING_UHS_DDR50:
1200         case MMC_TIMING_MMC_DDR52:
1201                 m |= ESDHC_MIX_CTRL_DDREN;
1202                 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1203                 imx_data->is_ddr = 1;
1204                 if (boarddata->delay_line) {
1205                         u32 v;
1206                         v = boarddata->delay_line <<
1207                                 ESDHC_DLL_OVERRIDE_VAL_SHIFT |
1208                                 (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT);
1209                         if (is_imx53_esdhc(imx_data))
1210                                 v <<= 1;
1211                         writel(v, host->ioaddr + ESDHC_DLL_CTRL);
1212                 }
1213                 break;
1214         case MMC_TIMING_MMC_HS400:
1215                 m |= ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN;
1216                 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1217                 imx_data->is_ddr = 1;
1218                 /* update clock after enable DDR for strobe DLL lock */
1219                 host->ops->set_clock(host, host->clock);
1220                 esdhc_set_strobe_dll(host);
1221                 break;
1222         case MMC_TIMING_LEGACY:
1223         default:
1224                 esdhc_reset_tuning(host);
1225                 break;
1226         }
1227
1228         esdhc_change_pinstate(host, timing);
1229 }
1230
1231 static void esdhc_reset(struct sdhci_host *host, u8 mask)
1232 {
1233         sdhci_and_cqhci_reset(host, mask);
1234
1235         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1236         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1237 }
1238
1239 static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host)
1240 {
1241         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1242         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1243
1244         /* Doc Erratum: the uSDHC actual maximum timeout count is 1 << 29 */
1245         return esdhc_is_usdhc(imx_data) ? 1 << 29 : 1 << 27;
1246 }
1247
1248 static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
1249 {
1250         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1251         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1252
1253         /* use maximum timeout counter */
1254         esdhc_clrset_le(host, ESDHC_SYS_CTRL_DTOCV_MASK,
1255                         esdhc_is_usdhc(imx_data) ? 0xF : 0xE,
1256                         SDHCI_TIMEOUT_CONTROL);
1257 }
1258
1259 static u32 esdhc_cqhci_irq(struct sdhci_host *host, u32 intmask)
1260 {
1261         int cmd_error = 0;
1262         int data_error = 0;
1263
1264         if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
1265                 return intmask;
1266
1267         cqhci_irq(host->mmc, intmask, cmd_error, data_error);
1268
1269         return 0;
1270 }
1271
1272 static struct sdhci_ops sdhci_esdhc_ops = {
1273         .read_l = esdhc_readl_le,
1274         .read_w = esdhc_readw_le,
1275         .read_b = esdhc_readb_le,
1276         .write_l = esdhc_writel_le,
1277         .write_w = esdhc_writew_le,
1278         .write_b = esdhc_writeb_le,
1279         .set_clock = esdhc_pltfm_set_clock,
1280         .get_max_clock = esdhc_pltfm_get_max_clock,
1281         .get_min_clock = esdhc_pltfm_get_min_clock,
1282         .get_max_timeout_count = esdhc_get_max_timeout_count,
1283         .get_ro = esdhc_pltfm_get_ro,
1284         .set_timeout = esdhc_set_timeout,
1285         .set_bus_width = esdhc_pltfm_set_bus_width,
1286         .set_uhs_signaling = esdhc_set_uhs_signaling,
1287         .reset = esdhc_reset,
1288         .irq = esdhc_cqhci_irq,
1289         .dump_vendor_regs = esdhc_dump_debug_regs,
1290 };
1291
1292 static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
1293         .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT
1294                         | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
1295                         | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
1296                         | SDHCI_QUIRK_BROKEN_CARD_DETECTION,
1297         .ops = &sdhci_esdhc_ops,
1298 };
1299
1300 static void sdhci_esdhc_imx_hwinit(struct sdhci_host *host)
1301 {
1302         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1303         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1304         struct cqhci_host *cq_host = host->mmc->cqe_private;
1305         u32 tmp;
1306
1307         if (esdhc_is_usdhc(imx_data)) {
1308                 /*
1309                  * The imx6q ROM code will change the default watermark
1310                  * level setting to something insane.  Change it back here.
1311                  */
1312                 writel(ESDHC_WTMK_DEFAULT_VAL, host->ioaddr + ESDHC_WTMK_LVL);
1313
1314                 /*
1315                  * ROM code will change the bit burst_length_enable setting
1316                  * to zero if this usdhc is chosen to boot system. Change
1317                  * it back here, otherwise it will impact the performance a
1318                  * lot. This bit is used to enable/disable the burst length
1319                  * for the external AHB2AXI bridge. It's useful especially
1320                  * for INCR transfer because without burst length indicator,
1321                  * the AHB2AXI bridge does not know the burst length in
1322                  * advance. And without burst length indicator, AHB INCR
1323                  * transfer can only be converted to singles on the AXI side.
1324                  */
1325                 writel(readl(host->ioaddr + SDHCI_HOST_CONTROL)
1326                         | ESDHC_BURST_LEN_EN_INCR,
1327                         host->ioaddr + SDHCI_HOST_CONTROL);
1328
1329                 /*
1330                  * erratum ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL
1331                  * TO1.1, it's harmless for MX6SL
1332                  */
1333                 writel(readl(host->ioaddr + 0x6c) & ~BIT(7),
1334                         host->ioaddr + 0x6c);
1335
1336                 /* disable DLL_CTRL delay line settings */
1337                 writel(0x0, host->ioaddr + ESDHC_DLL_CTRL);
1338
1339                 /*
1340                  * For the case of command with busy, if set the bit
1341                  * ESDHC_VEND_SPEC2_EN_BUSY_IRQ, USDHC will generate a
1342                  * transfer complete interrupt when busy is deasserted.
1343                  * When CQHCI use DCMD to send a CMD need R1b respons,
1344                  * CQHCI require to set ESDHC_VEND_SPEC2_EN_BUSY_IRQ,
1345                  * otherwise DCMD will always meet timeout waiting for
1346                  * hardware interrupt issue.
1347                  */
1348                 if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) {
1349                         tmp = readl(host->ioaddr + ESDHC_VEND_SPEC2);
1350                         tmp |= ESDHC_VEND_SPEC2_EN_BUSY_IRQ;
1351                         writel(tmp, host->ioaddr + ESDHC_VEND_SPEC2);
1352
1353                         host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ;
1354                 }
1355
1356                 if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
1357                         tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL);
1358                         tmp |= ESDHC_STD_TUNING_EN;
1359
1360                         /*
1361                          * ROM code or bootloader may config the start tap
1362                          * and step, unmask them first.
1363                          */
1364                         tmp &= ~(ESDHC_TUNING_START_TAP_MASK | ESDHC_TUNING_STEP_MASK);
1365                         if (imx_data->boarddata.tuning_start_tap)
1366                                 tmp |= imx_data->boarddata.tuning_start_tap;
1367                         else
1368                                 tmp |= ESDHC_TUNING_START_TAP_DEFAULT;
1369
1370                         if (imx_data->boarddata.tuning_step) {
1371                                 tmp |= imx_data->boarddata.tuning_step
1372                                         << ESDHC_TUNING_STEP_SHIFT;
1373                         } else {
1374                                 tmp |= ESDHC_TUNING_STEP_DEFAULT
1375                                         << ESDHC_TUNING_STEP_SHIFT;
1376                         }
1377
1378                         /* Disable the CMD CRC check for tuning, if not, need to
1379                          * add some delay after every tuning command, because
1380                          * hardware standard tuning logic will directly go to next
1381                          * step once it detect the CMD CRC error, will not wait for
1382                          * the card side to finally send out the tuning data, trigger
1383                          * the buffer read ready interrupt immediately. If usdhc send
1384                          * the next tuning command some eMMC card will stuck, can't
1385                          * response, block the tuning procedure or the first command
1386                          * after the whole tuning procedure always can't get any response.
1387                          */
1388                         tmp |= ESDHC_TUNING_CMD_CRC_CHECK_DISABLE;
1389                         writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL);
1390                 } else if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
1391                         /*
1392                          * ESDHC_STD_TUNING_EN may be configed in bootloader
1393                          * or ROM code, so clear this bit here to make sure
1394                          * the manual tuning can work.
1395                          */
1396                         tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL);
1397                         tmp &= ~ESDHC_STD_TUNING_EN;
1398                         writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL);
1399                 }
1400
1401                 /*
1402                  * On i.MX8MM, we are running Dual Linux OS, with 1st Linux using SD Card
1403                  * as rootfs storage, 2nd Linux using eMMC as rootfs storage. We let the
1404                  * the 1st linux configure power/clock for the 2nd Linux.
1405                  *
1406                  * When the 2nd Linux is booting into rootfs stage, we let the 1st Linux
1407                  * to destroy the 2nd linux, then restart the 2nd linux, we met SDHCI dump.
1408                  * After we clear the pending interrupt and halt CQCTL, issue gone.
1409                  */
1410                 if (cq_host) {
1411                         tmp = cqhci_readl(cq_host, CQHCI_IS);
1412                         cqhci_writel(cq_host, tmp, CQHCI_IS);
1413                         cqhci_writel(cq_host, CQHCI_HALT, CQHCI_CTL);
1414                 }
1415         }
1416 }
1417
1418 static void esdhc_cqe_enable(struct mmc_host *mmc)
1419 {
1420         struct sdhci_host *host = mmc_priv(mmc);
1421         struct cqhci_host *cq_host = mmc->cqe_private;
1422         u32 reg;
1423         u16 mode;
1424         int count = 10;
1425
1426         /*
1427          * CQE gets stuck if it sees Buffer Read Enable bit set, which can be
1428          * the case after tuning, so ensure the buffer is drained.
1429          */
1430         reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
1431         while (reg & SDHCI_DATA_AVAILABLE) {
1432                 sdhci_readl(host, SDHCI_BUFFER);
1433                 reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
1434                 if (count-- == 0) {
1435                         dev_warn(mmc_dev(host->mmc),
1436                                 "CQE may get stuck because the Buffer Read Enable bit is set\n");
1437                         break;
1438                 }
1439                 mdelay(1);
1440         }
1441
1442         /*
1443          * Runtime resume will reset the entire host controller, which
1444          * will also clear the DMAEN/BCEN of register ESDHC_MIX_CTRL.
1445          * Here set DMAEN and BCEN when enable CMDQ.
1446          */
1447         mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
1448         if (host->flags & SDHCI_REQ_USE_DMA)
1449                 mode |= SDHCI_TRNS_DMA;
1450         if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
1451                 mode |= SDHCI_TRNS_BLK_CNT_EN;
1452         sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
1453
1454         /*
1455          * Though Runtime resume reset the entire host controller,
1456          * but do not impact the CQHCI side, need to clear the
1457          * HALT bit, avoid CQHCI stuck in the first request when
1458          * system resume back.
1459          */
1460         cqhci_writel(cq_host, 0, CQHCI_CTL);
1461         if (cqhci_readl(cq_host, CQHCI_CTL) & CQHCI_HALT)
1462                 dev_err(mmc_dev(host->mmc),
1463                         "failed to exit halt state when enable CQE\n");
1464
1465
1466         sdhci_cqe_enable(mmc);
1467 }
1468
1469 static void esdhc_sdhci_dumpregs(struct mmc_host *mmc)
1470 {
1471         sdhci_dumpregs(mmc_priv(mmc));
1472 }
1473
1474 static const struct cqhci_host_ops esdhc_cqhci_ops = {
1475         .enable         = esdhc_cqe_enable,
1476         .disable        = sdhci_cqe_disable,
1477         .dumpregs       = esdhc_sdhci_dumpregs,
1478 };
1479
1480 #ifdef CONFIG_OF
1481 static int
1482 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
1483                          struct sdhci_host *host,
1484                          struct pltfm_imx_data *imx_data)
1485 {
1486         struct device_node *np = pdev->dev.of_node;
1487         struct esdhc_platform_data *boarddata = &imx_data->boarddata;
1488         int ret;
1489
1490         if (of_get_property(np, "fsl,wp-controller", NULL))
1491                 boarddata->wp_type = ESDHC_WP_CONTROLLER;
1492
1493         /*
1494          * If we have this property, then activate WP check.
1495          * Retrieveing and requesting the actual WP GPIO will happen
1496          * in the call to mmc_of_parse().
1497          */
1498         if (of_property_read_bool(np, "wp-gpios"))
1499                 boarddata->wp_type = ESDHC_WP_GPIO;
1500
1501         of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step);
1502         of_property_read_u32(np, "fsl,tuning-start-tap",
1503                              &boarddata->tuning_start_tap);
1504
1505         of_property_read_u32(np, "fsl,strobe-dll-delay-target",
1506                                 &boarddata->strobe_dll_delay_target);
1507         if (of_find_property(np, "no-1-8-v", NULL))
1508                 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1509
1510         if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line))
1511                 boarddata->delay_line = 0;
1512
1513         mmc_of_parse_voltage(np, &host->ocr_mask);
1514
1515         if (esdhc_is_usdhc(imx_data) && !IS_ERR(imx_data->pinctrl)) {
1516                 imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl,
1517                                                 ESDHC_PINCTRL_STATE_100MHZ);
1518                 imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl,
1519                                                 ESDHC_PINCTRL_STATE_200MHZ);
1520         }
1521
1522         /* call to generic mmc_of_parse to support additional capabilities */
1523         ret = mmc_of_parse(host->mmc);
1524         if (ret)
1525                 return ret;
1526
1527         if (mmc_gpio_get_cd(host->mmc) >= 0)
1528                 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
1529
1530         return 0;
1531 }
1532 #else
1533 static inline int
1534 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
1535                          struct sdhci_host *host,
1536                          struct pltfm_imx_data *imx_data)
1537 {
1538         return -ENODEV;
1539 }
1540 #endif
1541
1542 static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
1543 {
1544         const struct of_device_id *of_id =
1545                         of_match_device(imx_esdhc_dt_ids, &pdev->dev);
1546         struct sdhci_pltfm_host *pltfm_host;
1547         struct sdhci_host *host;
1548         struct cqhci_host *cq_host;
1549         int err;
1550         struct pltfm_imx_data *imx_data;
1551
1552         host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata,
1553                                 sizeof(*imx_data));
1554         if (IS_ERR(host))
1555                 return PTR_ERR(host);
1556
1557         pltfm_host = sdhci_priv(host);
1558
1559         imx_data = sdhci_pltfm_priv(pltfm_host);
1560
1561         imx_data->socdata = of_id->data;
1562
1563         if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1564                 cpu_latency_qos_add_request(&imx_data->pm_qos_req, 0);
1565
1566         imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1567         if (IS_ERR(imx_data->clk_ipg)) {
1568                 err = PTR_ERR(imx_data->clk_ipg);
1569                 goto free_sdhci;
1570         }
1571
1572         imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1573         if (IS_ERR(imx_data->clk_ahb)) {
1574                 err = PTR_ERR(imx_data->clk_ahb);
1575                 goto free_sdhci;
1576         }
1577
1578         imx_data->clk_per = devm_clk_get(&pdev->dev, "per");
1579         if (IS_ERR(imx_data->clk_per)) {
1580                 err = PTR_ERR(imx_data->clk_per);
1581                 goto free_sdhci;
1582         }
1583
1584         pltfm_host->clk = imx_data->clk_per;
1585         pltfm_host->clock = clk_get_rate(pltfm_host->clk);
1586         err = clk_prepare_enable(imx_data->clk_per);
1587         if (err)
1588                 goto free_sdhci;
1589         err = clk_prepare_enable(imx_data->clk_ipg);
1590         if (err)
1591                 goto disable_per_clk;
1592         err = clk_prepare_enable(imx_data->clk_ahb);
1593         if (err)
1594                 goto disable_ipg_clk;
1595
1596         imx_data->pinctrl = devm_pinctrl_get(&pdev->dev);
1597         if (IS_ERR(imx_data->pinctrl))
1598                 dev_warn(mmc_dev(host->mmc), "could not get pinctrl\n");
1599
1600         if (esdhc_is_usdhc(imx_data)) {
1601                 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
1602                 host->mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR;
1603
1604                 /* GPIO CD can be set as a wakeup source */
1605                 host->mmc->caps |= MMC_CAP_CD_WAKE;
1606
1607                 if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200))
1608                         host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
1609
1610                 /* clear tuning bits in case ROM has set it already */
1611                 writel(0x0, host->ioaddr + ESDHC_MIX_CTRL);
1612                 writel(0x0, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
1613                 writel(0x0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
1614
1615                 /*
1616                  * Link usdhc specific mmc_host_ops execute_tuning function,
1617                  * to replace the standard one in sdhci_ops.
1618                  */
1619                 host->mmc_host_ops.execute_tuning = usdhc_execute_tuning;
1620         }
1621
1622         err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data);
1623         if (err)
1624                 goto disable_ahb_clk;
1625
1626         if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
1627                 sdhci_esdhc_ops.platform_execute_tuning =
1628                                         esdhc_executing_tuning;
1629
1630         if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536)
1631                 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
1632
1633         if (host->mmc->caps & MMC_CAP_8_BIT_DATA &&
1634             imx_data->socdata->flags & ESDHC_FLAG_HS400)
1635                 host->quirks2 |= SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400;
1636
1637         if (imx_data->socdata->flags & ESDHC_FLAG_BROKEN_AUTO_CMD23)
1638                 host->quirks2 |= SDHCI_QUIRK2_ACMD23_BROKEN;
1639
1640         if (host->mmc->caps & MMC_CAP_8_BIT_DATA &&
1641             imx_data->socdata->flags & ESDHC_FLAG_HS400_ES) {
1642                 host->mmc->caps2 |= MMC_CAP2_HS400_ES;
1643                 host->mmc_host_ops.hs400_enhanced_strobe =
1644                                         esdhc_hs400_enhanced_strobe;
1645         }
1646
1647         if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) {
1648                 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
1649                 cq_host = devm_kzalloc(&pdev->dev, sizeof(*cq_host), GFP_KERNEL);
1650                 if (!cq_host) {
1651                         err = -ENOMEM;
1652                         goto disable_ahb_clk;
1653                 }
1654
1655                 cq_host->mmio = host->ioaddr + ESDHC_CQHCI_ADDR_OFFSET;
1656                 cq_host->ops = &esdhc_cqhci_ops;
1657
1658                 err = cqhci_init(cq_host, host->mmc, false);
1659                 if (err)
1660                         goto disable_ahb_clk;
1661         }
1662
1663         sdhci_esdhc_imx_hwinit(host);
1664
1665         err = sdhci_add_host(host);
1666         if (err)
1667                 goto disable_ahb_clk;
1668
1669         pm_runtime_set_active(&pdev->dev);
1670         pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1671         pm_runtime_use_autosuspend(&pdev->dev);
1672         pm_suspend_ignore_children(&pdev->dev, 1);
1673         pm_runtime_enable(&pdev->dev);
1674
1675         return 0;
1676
1677 disable_ahb_clk:
1678         clk_disable_unprepare(imx_data->clk_ahb);
1679 disable_ipg_clk:
1680         clk_disable_unprepare(imx_data->clk_ipg);
1681 disable_per_clk:
1682         clk_disable_unprepare(imx_data->clk_per);
1683 free_sdhci:
1684         if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1685                 cpu_latency_qos_remove_request(&imx_data->pm_qos_req);
1686         sdhci_pltfm_free(pdev);
1687         return err;
1688 }
1689
1690 static int sdhci_esdhc_imx_remove(struct platform_device *pdev)
1691 {
1692         struct sdhci_host *host = platform_get_drvdata(pdev);
1693         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1694         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1695         int dead;
1696
1697         pm_runtime_get_sync(&pdev->dev);
1698         dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
1699         pm_runtime_disable(&pdev->dev);
1700         pm_runtime_put_noidle(&pdev->dev);
1701
1702         sdhci_remove_host(host, dead);
1703
1704         clk_disable_unprepare(imx_data->clk_per);
1705         clk_disable_unprepare(imx_data->clk_ipg);
1706         clk_disable_unprepare(imx_data->clk_ahb);
1707
1708         if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1709                 cpu_latency_qos_remove_request(&imx_data->pm_qos_req);
1710
1711         sdhci_pltfm_free(pdev);
1712
1713         return 0;
1714 }
1715
1716 #ifdef CONFIG_PM_SLEEP
1717 static int sdhci_esdhc_suspend(struct device *dev)
1718 {
1719         struct sdhci_host *host = dev_get_drvdata(dev);
1720         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1721         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1722         int ret;
1723
1724         if (host->mmc->caps2 & MMC_CAP2_CQE) {
1725                 ret = cqhci_suspend(host->mmc);
1726                 if (ret)
1727                         return ret;
1728         }
1729
1730         if ((imx_data->socdata->flags & ESDHC_FLAG_STATE_LOST_IN_LPMODE) &&
1731                 (host->tuning_mode != SDHCI_TUNING_MODE_1)) {
1732                 mmc_retune_timer_stop(host->mmc);
1733                 mmc_retune_needed(host->mmc);
1734         }
1735
1736         if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1737                 mmc_retune_needed(host->mmc);
1738
1739         ret = sdhci_suspend_host(host);
1740         if (ret)
1741                 return ret;
1742
1743         ret = pinctrl_pm_select_sleep_state(dev);
1744         if (ret)
1745                 return ret;
1746
1747         ret = mmc_gpio_set_cd_wake(host->mmc, true);
1748
1749         return ret;
1750 }
1751
1752 static int sdhci_esdhc_resume(struct device *dev)
1753 {
1754         struct sdhci_host *host = dev_get_drvdata(dev);
1755         int ret;
1756
1757         ret = pinctrl_pm_select_default_state(dev);
1758         if (ret)
1759                 return ret;
1760
1761         /* re-initialize hw state in case it's lost in low power mode */
1762         sdhci_esdhc_imx_hwinit(host);
1763
1764         ret = sdhci_resume_host(host);
1765         if (ret)
1766                 return ret;
1767
1768         if (host->mmc->caps2 & MMC_CAP2_CQE)
1769                 ret = cqhci_resume(host->mmc);
1770
1771         if (!ret)
1772                 ret = mmc_gpio_set_cd_wake(host->mmc, false);
1773
1774         return ret;
1775 }
1776 #endif
1777
1778 #ifdef CONFIG_PM
1779 static int sdhci_esdhc_runtime_suspend(struct device *dev)
1780 {
1781         struct sdhci_host *host = dev_get_drvdata(dev);
1782         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1783         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1784         int ret;
1785
1786         if (host->mmc->caps2 & MMC_CAP2_CQE) {
1787                 ret = cqhci_suspend(host->mmc);
1788                 if (ret)
1789                         return ret;
1790         }
1791
1792         ret = sdhci_runtime_suspend_host(host);
1793         if (ret)
1794                 return ret;
1795
1796         if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1797                 mmc_retune_needed(host->mmc);
1798
1799         imx_data->actual_clock = host->mmc->actual_clock;
1800         esdhc_pltfm_set_clock(host, 0);
1801         clk_disable_unprepare(imx_data->clk_per);
1802         clk_disable_unprepare(imx_data->clk_ipg);
1803         clk_disable_unprepare(imx_data->clk_ahb);
1804
1805         if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1806                 cpu_latency_qos_remove_request(&imx_data->pm_qos_req);
1807
1808         return ret;
1809 }
1810
1811 static int sdhci_esdhc_runtime_resume(struct device *dev)
1812 {
1813         struct sdhci_host *host = dev_get_drvdata(dev);
1814         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1815         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1816         int err;
1817
1818         if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1819                 cpu_latency_qos_add_request(&imx_data->pm_qos_req, 0);
1820
1821         if (imx_data->socdata->flags & ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME)
1822                 clk_set_rate(imx_data->clk_per, pltfm_host->clock);
1823
1824         err = clk_prepare_enable(imx_data->clk_ahb);
1825         if (err)
1826                 goto remove_pm_qos_request;
1827
1828         err = clk_prepare_enable(imx_data->clk_per);
1829         if (err)
1830                 goto disable_ahb_clk;
1831
1832         err = clk_prepare_enable(imx_data->clk_ipg);
1833         if (err)
1834                 goto disable_per_clk;
1835
1836         esdhc_pltfm_set_clock(host, imx_data->actual_clock);
1837
1838         err = sdhci_runtime_resume_host(host, 0);
1839         if (err)
1840                 goto disable_ipg_clk;
1841
1842         if (host->mmc->caps2 & MMC_CAP2_CQE)
1843                 err = cqhci_resume(host->mmc);
1844
1845         return err;
1846
1847 disable_ipg_clk:
1848         clk_disable_unprepare(imx_data->clk_ipg);
1849 disable_per_clk:
1850         clk_disable_unprepare(imx_data->clk_per);
1851 disable_ahb_clk:
1852         clk_disable_unprepare(imx_data->clk_ahb);
1853 remove_pm_qos_request:
1854         if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1855                 cpu_latency_qos_remove_request(&imx_data->pm_qos_req);
1856         return err;
1857 }
1858 #endif
1859
1860 static const struct dev_pm_ops sdhci_esdhc_pmops = {
1861         SET_SYSTEM_SLEEP_PM_OPS(sdhci_esdhc_suspend, sdhci_esdhc_resume)
1862         SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend,
1863                                 sdhci_esdhc_runtime_resume, NULL)
1864 };
1865
1866 static struct platform_driver sdhci_esdhc_imx_driver = {
1867         .driver         = {
1868                 .name   = "sdhci-esdhc-imx",
1869                 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1870                 .of_match_table = imx_esdhc_dt_ids,
1871                 .pm     = &sdhci_esdhc_pmops,
1872         },
1873         .probe          = sdhci_esdhc_imx_probe,
1874         .remove         = sdhci_esdhc_imx_remove,
1875 };
1876
1877 module_platform_driver(sdhci_esdhc_imx_driver);
1878
1879 MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC");
1880 MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>");
1881 MODULE_LICENSE("GPL v2");