2 * Freescale eSDHC i.MX controller driver for the platform bus.
4 * derived from the OF-version.
6 * Copyright (c) 2010 Pengutronix e.K.
7 * Author: Wolfram Sang <kernel@pengutronix.de>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
15 #include <linux/delay.h>
16 #include <linux/err.h>
17 #include <linux/clk.h>
18 #include <linux/gpio.h>
19 #include <linux/module.h>
20 #include <linux/slab.h>
21 #include <linux/mmc/host.h>
22 #include <linux/mmc/mmc.h>
23 #include <linux/mmc/sdio.h>
24 #include <linux/mmc/slot-gpio.h>
26 #include <linux/of_device.h>
27 #include <linux/of_gpio.h>
28 #include <linux/pinctrl/consumer.h>
29 #include <linux/platform_data/mmc-esdhc-imx.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/iopoll.h>
32 #include "sdhci-pltfm.h"
33 #include "sdhci-esdhc.h"
35 #define ESDHC_SYS_CTRL_DTOCV_MASK 0x0f
36 #define ESDHC_CTRL_D3CD 0x08
37 #define ESDHC_BURST_LEN_EN_INCR (1 << 27)
38 /* VENDOR SPEC register */
39 #define ESDHC_VENDOR_SPEC 0xc0
40 #define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1)
41 #define ESDHC_VENDOR_SPEC_VSELECT (1 << 1)
42 #define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8)
43 #define ESDHC_WTMK_LVL 0x44
44 #define ESDHC_WTMK_DEFAULT_VAL 0x10401040
45 #define ESDHC_MIX_CTRL 0x48
46 #define ESDHC_MIX_CTRL_DDREN (1 << 3)
47 #define ESDHC_MIX_CTRL_AC23EN (1 << 7)
48 #define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22)
49 #define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23)
50 #define ESDHC_MIX_CTRL_AUTO_TUNE_EN (1 << 24)
51 #define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25)
52 #define ESDHC_MIX_CTRL_HS400_EN (1 << 26)
53 /* Bits 3 and 6 are not SDHCI standard definitions */
54 #define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7
56 #define ESDHC_MIX_CTRL_TUNING_MASK 0x03c00000
58 /* dll control register */
59 #define ESDHC_DLL_CTRL 0x60
60 #define ESDHC_DLL_OVERRIDE_VAL_SHIFT 9
61 #define ESDHC_DLL_OVERRIDE_EN_SHIFT 8
63 /* tune control register */
64 #define ESDHC_TUNE_CTRL_STATUS 0x68
65 #define ESDHC_TUNE_CTRL_STEP 1
66 #define ESDHC_TUNE_CTRL_MIN 0
67 #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1)
69 /* strobe dll register */
70 #define ESDHC_STROBE_DLL_CTRL 0x70
71 #define ESDHC_STROBE_DLL_CTRL_ENABLE (1 << 0)
72 #define ESDHC_STROBE_DLL_CTRL_RESET (1 << 1)
73 #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3
75 #define ESDHC_STROBE_DLL_STATUS 0x74
76 #define ESDHC_STROBE_DLL_STS_REF_LOCK (1 << 1)
77 #define ESDHC_STROBE_DLL_STS_SLV_LOCK 0x1
79 #define ESDHC_TUNING_CTRL 0xcc
80 #define ESDHC_STD_TUNING_EN (1 << 24)
81 /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
82 #define ESDHC_TUNING_START_TAP_DEFAULT 0x1
83 #define ESDHC_TUNING_START_TAP_MASK 0x7f
84 #define ESDHC_TUNING_STEP_MASK 0x00070000
85 #define ESDHC_TUNING_STEP_SHIFT 16
88 #define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz"
89 #define ESDHC_PINCTRL_STATE_200MHZ "state_200mhz"
92 * Our interpretation of the SDHCI_HOST_CONTROL register
94 #define ESDHC_CTRL_4BITBUS (0x1 << 1)
95 #define ESDHC_CTRL_8BITBUS (0x2 << 1)
96 #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1)
99 * There is an INT DMA ERR mismatch between eSDHC and STD SDHC SPEC:
100 * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design,
101 * but bit28 is used as the INT DMA ERR in fsl eSDHC design.
102 * Define this macro DMA error INT for fsl eSDHC
104 #define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28)
107 * The CMDTYPE of the CMD register (offset 0xE) should be set to
108 * "11" when the STOP CMD12 is issued on imx53 to abort one
109 * open ended multi-blk IO. Otherwise the TC INT wouldn't
111 * In exact block transfer, the controller doesn't complete the
112 * operations automatically as required at the end of the
113 * transfer and remains on hold if the abort command is not sent.
114 * As a result, the TC flag is not asserted and SW received timeout
115 * exception. Bit1 of Vendor Spec register is used to fix it.
117 #define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1)
119 * The flag tells that the ESDHC controller is an USDHC block that is
120 * integrated on the i.MX6 series.
122 #define ESDHC_FLAG_USDHC BIT(3)
123 /* The IP supports manual tuning process */
124 #define ESDHC_FLAG_MAN_TUNING BIT(4)
125 /* The IP supports standard tuning process */
126 #define ESDHC_FLAG_STD_TUNING BIT(5)
127 /* The IP has SDHCI_CAPABILITIES_1 register */
128 #define ESDHC_FLAG_HAVE_CAP1 BIT(6)
130 * The IP has erratum ERR004536
131 * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow,
132 * when reading data from the card
133 * This flag is also set for i.MX25 and i.MX35 in order to get
134 * SDHCI_QUIRK_BROKEN_ADMA, but for different reasons (ADMA capability bits).
136 #define ESDHC_FLAG_ERR004536 BIT(7)
137 /* The IP supports HS200 mode */
138 #define ESDHC_FLAG_HS200 BIT(8)
139 /* The IP supports HS400 mode */
140 #define ESDHC_FLAG_HS400 BIT(9)
142 /* A clock frequency higher than this rate requires strobe dll control */
143 #define ESDHC_STROBE_DLL_CLK_FREQ 100000000
145 struct esdhc_soc_data {
149 static struct esdhc_soc_data esdhc_imx25_data = {
150 .flags = ESDHC_FLAG_ERR004536,
153 static struct esdhc_soc_data esdhc_imx35_data = {
154 .flags = ESDHC_FLAG_ERR004536,
157 static struct esdhc_soc_data esdhc_imx51_data = {
161 static struct esdhc_soc_data esdhc_imx53_data = {
162 .flags = ESDHC_FLAG_MULTIBLK_NO_INT,
165 static struct esdhc_soc_data usdhc_imx6q_data = {
166 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING,
169 static struct esdhc_soc_data usdhc_imx6sl_data = {
170 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
171 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536
175 static struct esdhc_soc_data usdhc_imx6sx_data = {
176 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
177 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200,
180 static struct esdhc_soc_data usdhc_imx7d_data = {
181 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
182 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
186 struct pltfm_imx_data {
188 struct pinctrl *pinctrl;
189 struct pinctrl_state *pins_default;
190 struct pinctrl_state *pins_100mhz;
191 struct pinctrl_state *pins_200mhz;
192 const struct esdhc_soc_data *socdata;
193 struct esdhc_platform_data boarddata;
198 NO_CMD_PENDING, /* no multiblock command pending */
199 MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */
200 WAIT_FOR_INT, /* sent CMD12, waiting for response INT */
205 static const struct platform_device_id imx_esdhc_devtype[] = {
207 .name = "sdhci-esdhc-imx25",
208 .driver_data = (kernel_ulong_t) &esdhc_imx25_data,
210 .name = "sdhci-esdhc-imx35",
211 .driver_data = (kernel_ulong_t) &esdhc_imx35_data,
213 .name = "sdhci-esdhc-imx51",
214 .driver_data = (kernel_ulong_t) &esdhc_imx51_data,
219 MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype);
221 static const struct of_device_id imx_esdhc_dt_ids[] = {
222 { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, },
223 { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, },
224 { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, },
225 { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, },
226 { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, },
227 { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, },
228 { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, },
229 { .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, },
232 MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids);
234 static inline int is_imx25_esdhc(struct pltfm_imx_data *data)
236 return data->socdata == &esdhc_imx25_data;
239 static inline int is_imx53_esdhc(struct pltfm_imx_data *data)
241 return data->socdata == &esdhc_imx53_data;
244 static inline int is_imx6q_usdhc(struct pltfm_imx_data *data)
246 return data->socdata == &usdhc_imx6q_data;
249 static inline int esdhc_is_usdhc(struct pltfm_imx_data *data)
251 return !!(data->socdata->flags & ESDHC_FLAG_USDHC);
254 static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
256 void __iomem *base = host->ioaddr + (reg & ~0x3);
257 u32 shift = (reg & 0x3) * 8;
259 writel(((readl(base) & ~(mask << shift)) | (val << shift)), base);
262 static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
264 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
265 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
266 u32 val = readl(host->ioaddr + reg);
268 if (unlikely(reg == SDHCI_PRESENT_STATE)) {
270 /* save the least 20 bits */
271 val = fsl_prss & 0x000FFFFF;
272 /* move dat[0-3] bits */
273 val |= (fsl_prss & 0x0F000000) >> 4;
274 /* move cmd line bit */
275 val |= (fsl_prss & 0x00800000) << 1;
278 if (unlikely(reg == SDHCI_CAPABILITIES)) {
279 /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */
280 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
283 /* In FSL esdhc IC module, only bit20 is used to indicate the
284 * ADMA2 capability of esdhc, but this bit is messed up on
285 * some SOCs (e.g. on MX25, MX35 this bit is set, but they
286 * don't actually support ADMA2). So set the BROKEN_ADMA
287 * quirk on MX25/35 platforms.
290 if (val & SDHCI_CAN_DO_ADMA1) {
291 val &= ~SDHCI_CAN_DO_ADMA1;
292 val |= SDHCI_CAN_DO_ADMA2;
296 if (unlikely(reg == SDHCI_CAPABILITIES_1)) {
297 if (esdhc_is_usdhc(imx_data)) {
298 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
299 val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF;
301 /* imx6q/dl does not have cap_1 register, fake one */
302 val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104
303 | SDHCI_SUPPORT_SDR50
304 | SDHCI_USE_SDR50_TUNING
305 | (SDHCI_TUNING_MODE_3 << SDHCI_RETUNING_MODE_SHIFT);
307 if (imx_data->socdata->flags & ESDHC_FLAG_HS400)
308 val |= SDHCI_SUPPORT_HS400;
311 * Do not advertise faster UHS modes if there are no
312 * pinctrl states for 100MHz/200MHz.
314 if (IS_ERR_OR_NULL(imx_data->pins_100mhz) ||
315 IS_ERR_OR_NULL(imx_data->pins_200mhz))
316 val &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50
317 | SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_HS400);
321 if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) {
323 val |= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT;
324 val |= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT;
325 val |= 0xFF << SDHCI_MAX_CURRENT_180_SHIFT;
328 if (unlikely(reg == SDHCI_INT_STATUS)) {
329 if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) {
330 val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR;
331 val |= SDHCI_INT_ADMA_ERROR;
335 * mask off the interrupt we get in response to the manually
338 if ((imx_data->multiblock_status == WAIT_FOR_INT) &&
339 ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) {
340 val &= ~SDHCI_INT_RESPONSE;
341 writel(SDHCI_INT_RESPONSE, host->ioaddr +
343 imx_data->multiblock_status = NO_CMD_PENDING;
350 static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
352 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
353 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
356 if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE ||
357 reg == SDHCI_INT_STATUS)) {
358 if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) {
360 * Clear and then set D3CD bit to avoid missing the
361 * card interrupt. This is an eSDHC controller problem
362 * so we need to apply the following workaround: clear
363 * and set D3CD bit will make eSDHC re-sample the card
364 * interrupt. In case a card interrupt was lost,
365 * re-sample it by the following steps.
367 data = readl(host->ioaddr + SDHCI_HOST_CONTROL);
368 data &= ~ESDHC_CTRL_D3CD;
369 writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
370 data |= ESDHC_CTRL_D3CD;
371 writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
374 if (val & SDHCI_INT_ADMA_ERROR) {
375 val &= ~SDHCI_INT_ADMA_ERROR;
376 val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR;
380 if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
381 && (reg == SDHCI_INT_STATUS)
382 && (val & SDHCI_INT_DATA_END))) {
384 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
385 v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK;
386 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
388 if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS)
390 /* send a manual CMD12 with RESPTYP=none */
391 data = MMC_STOP_TRANSMISSION << 24 |
392 SDHCI_CMD_ABORTCMD << 16;
393 writel(data, host->ioaddr + SDHCI_TRANSFER_MODE);
394 imx_data->multiblock_status = WAIT_FOR_INT;
398 writel(val, host->ioaddr + reg);
401 static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
403 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
404 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
408 if (unlikely(reg == SDHCI_HOST_VERSION)) {
410 if (esdhc_is_usdhc(imx_data)) {
412 * The usdhc register returns a wrong host version.
415 return SDHCI_SPEC_300;
419 if (unlikely(reg == SDHCI_HOST_CONTROL2)) {
420 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
421 if (val & ESDHC_VENDOR_SPEC_VSELECT)
422 ret |= SDHCI_CTRL_VDD_180;
424 if (esdhc_is_usdhc(imx_data)) {
425 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
426 val = readl(host->ioaddr + ESDHC_MIX_CTRL);
427 else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING)
428 /* the std tuning bits is in ACMD12_ERR for imx6sl */
429 val = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
432 if (val & ESDHC_MIX_CTRL_EXE_TUNE)
433 ret |= SDHCI_CTRL_EXEC_TUNING;
434 if (val & ESDHC_MIX_CTRL_SMPCLK_SEL)
435 ret |= SDHCI_CTRL_TUNED_CLK;
437 ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
442 if (unlikely(reg == SDHCI_TRANSFER_MODE)) {
443 if (esdhc_is_usdhc(imx_data)) {
444 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
445 ret = m & ESDHC_MIX_CTRL_SDHCI_MASK;
447 if (m & ESDHC_MIX_CTRL_AC23EN) {
448 ret &= ~ESDHC_MIX_CTRL_AC23EN;
449 ret |= SDHCI_TRNS_AUTO_CMD23;
452 ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE);
458 return readw(host->ioaddr + reg);
461 static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
463 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
464 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
468 case SDHCI_CLOCK_CONTROL:
469 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
470 if (val & SDHCI_CLOCK_CARD_EN)
471 new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
473 new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
474 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
476 case SDHCI_HOST_CONTROL2:
477 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
478 if (val & SDHCI_CTRL_VDD_180)
479 new_val |= ESDHC_VENDOR_SPEC_VSELECT;
481 new_val &= ~ESDHC_VENDOR_SPEC_VSELECT;
482 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
483 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
484 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
485 if (val & SDHCI_CTRL_TUNED_CLK) {
486 new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL;
487 new_val |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
489 new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
490 new_val &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN;
492 writel(new_val , host->ioaddr + ESDHC_MIX_CTRL);
493 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
494 u32 v = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
495 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
496 if (val & SDHCI_CTRL_TUNED_CLK) {
497 v |= ESDHC_MIX_CTRL_SMPCLK_SEL;
499 v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
500 m &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
501 m &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN;
504 if (val & SDHCI_CTRL_EXEC_TUNING) {
505 v |= ESDHC_MIX_CTRL_EXE_TUNE;
506 m |= ESDHC_MIX_CTRL_FBCLK_SEL;
507 m |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
509 v &= ~ESDHC_MIX_CTRL_EXE_TUNE;
512 writel(v, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
513 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
516 case SDHCI_TRANSFER_MODE:
517 if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
518 && (host->cmd->opcode == SD_IO_RW_EXTENDED)
519 && (host->cmd->data->blocks > 1)
520 && (host->cmd->data->flags & MMC_DATA_READ)) {
522 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
523 v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK;
524 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
527 if (esdhc_is_usdhc(imx_data)) {
528 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
530 if (val & SDHCI_TRNS_AUTO_CMD23) {
531 val &= ~SDHCI_TRNS_AUTO_CMD23;
532 val |= ESDHC_MIX_CTRL_AC23EN;
534 m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK);
535 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
538 * Postpone this write, we must do it together with a
539 * command write that is down below.
541 imx_data->scratchpad = val;
545 if (host->cmd->opcode == MMC_STOP_TRANSMISSION)
546 val |= SDHCI_CMD_ABORTCMD;
548 if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) &&
549 (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
550 imx_data->multiblock_status = MULTIBLK_IN_PROCESS;
552 if (esdhc_is_usdhc(imx_data))
554 host->ioaddr + SDHCI_TRANSFER_MODE);
556 writel(val << 16 | imx_data->scratchpad,
557 host->ioaddr + SDHCI_TRANSFER_MODE);
559 case SDHCI_BLOCK_SIZE:
560 val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
563 esdhc_clrset_le(host, 0xffff, val, reg);
566 static u8 esdhc_readb_le(struct sdhci_host *host, int reg)
572 case SDHCI_HOST_CONTROL:
573 val = readl(host->ioaddr + reg);
575 ret = val & SDHCI_CTRL_LED;
576 ret |= (val >> 5) & SDHCI_CTRL_DMA_MASK;
577 ret |= (val & ESDHC_CTRL_4BITBUS);
578 ret |= (val & ESDHC_CTRL_8BITBUS) << 3;
582 return readb(host->ioaddr + reg);
585 static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
587 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
588 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
593 case SDHCI_POWER_CONTROL:
595 * FSL put some DMA bits here
596 * If your board has a regulator, code should be here
599 case SDHCI_HOST_CONTROL:
600 /* FSL messed up here, so we need to manually compose it. */
601 new_val = val & SDHCI_CTRL_LED;
602 /* ensure the endianness */
603 new_val |= ESDHC_HOST_CONTROL_LE;
604 /* bits 8&9 are reserved on mx25 */
605 if (!is_imx25_esdhc(imx_data)) {
606 /* DMA mode bits are shifted */
607 new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5;
611 * Do not touch buswidth bits here. This is done in
612 * esdhc_pltfm_bus_width.
613 * Do not touch the D3CD bit either which is used for the
614 * SDIO interrupt erratum workaround.
616 mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD);
618 esdhc_clrset_le(host, mask, new_val, reg);
620 case SDHCI_SOFTWARE_RESET:
621 if (val & SDHCI_RESET_DATA)
622 new_val = readl(host->ioaddr + SDHCI_HOST_CONTROL);
625 esdhc_clrset_le(host, 0xff, val, reg);
627 if (reg == SDHCI_SOFTWARE_RESET) {
628 if (val & SDHCI_RESET_ALL) {
630 * The esdhc has a design violation to SDHC spec which
631 * tells that software reset should not affect card
632 * detection circuit. But esdhc clears its SYSCTL
633 * register bits [0..2] during the software reset. This
634 * will stop those clocks that card detection circuit
635 * relies on. To work around it, we turn the clocks on
636 * back to keep card detection circuit functional.
638 esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL);
640 * The reset on usdhc fails to clear MIX_CTRL register.
641 * Do it manually here.
643 if (esdhc_is_usdhc(imx_data)) {
645 * the tuning bits should be kept during reset
647 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
648 writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK,
649 host->ioaddr + ESDHC_MIX_CTRL);
650 imx_data->is_ddr = 0;
652 } else if (val & SDHCI_RESET_DATA) {
654 * The eSDHC DAT line software reset clears at least the
655 * data transfer width on i.MX25, so make sure that the
656 * Host Control register is unaffected.
658 esdhc_clrset_le(host, 0xff, new_val,
664 static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host)
666 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
668 return pltfm_host->clock;
671 static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
673 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
675 return pltfm_host->clock / 256 / 16;
678 static inline void esdhc_pltfm_set_clock(struct sdhci_host *host,
681 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
682 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
683 unsigned int host_clock = pltfm_host->clock;
684 int ddr_pre_div = imx_data->is_ddr ? 2 : 1;
690 host->mmc->actual_clock = 0;
692 if (esdhc_is_usdhc(imx_data)) {
693 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
694 writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
695 host->ioaddr + ESDHC_VENDOR_SPEC);
700 /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
701 if (is_imx53_esdhc(imx_data)) {
703 * According to the i.MX53 reference manual, if DLLCTRL[10] can
704 * be set, then the controller is eSDHCv3, else it is eSDHCv2.
706 val = readl(host->ioaddr + ESDHC_DLL_CTRL);
707 writel(val | BIT(10), host->ioaddr + ESDHC_DLL_CTRL);
708 temp = readl(host->ioaddr + ESDHC_DLL_CTRL);
709 writel(val, host->ioaddr + ESDHC_DLL_CTRL);
714 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
715 temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
717 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
719 while (host_clock / (16 * pre_div * ddr_pre_div) > clock &&
723 while (host_clock / (div * pre_div * ddr_pre_div) > clock && div < 16)
726 host->mmc->actual_clock = host_clock / (div * pre_div * ddr_pre_div);
727 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
728 clock, host->mmc->actual_clock);
733 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
734 temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
735 | (div << ESDHC_DIVIDER_SHIFT)
736 | (pre_div << ESDHC_PREDIV_SHIFT));
737 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
739 if (esdhc_is_usdhc(imx_data)) {
740 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
741 writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
742 host->ioaddr + ESDHC_VENDOR_SPEC);
748 static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host)
750 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
751 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
752 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
754 switch (boarddata->wp_type) {
756 return mmc_gpio_get_ro(host->mmc);
757 case ESDHC_WP_CONTROLLER:
758 return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
759 SDHCI_WRITE_PROTECT);
767 static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
772 case MMC_BUS_WIDTH_8:
773 ctrl = ESDHC_CTRL_8BITBUS;
775 case MMC_BUS_WIDTH_4:
776 ctrl = ESDHC_CTRL_4BITBUS;
783 esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl,
787 static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val)
791 /* FIXME: delay a bit for card to be ready for next tuning due to errors */
794 reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
795 reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL |
796 ESDHC_MIX_CTRL_FBCLK_SEL;
797 writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
798 writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
799 dev_dbg(mmc_dev(host->mmc),
800 "tuning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n",
801 val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS));
804 static void esdhc_post_tuning(struct sdhci_host *host)
808 reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
809 reg &= ~ESDHC_MIX_CTRL_EXE_TUNE;
810 reg |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
811 writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
814 static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode)
816 int min, max, avg, ret;
818 /* find the mininum delay first which can pass tuning */
819 min = ESDHC_TUNE_CTRL_MIN;
820 while (min < ESDHC_TUNE_CTRL_MAX) {
821 esdhc_prepare_tuning(host, min);
822 if (!mmc_send_tuning(host->mmc, opcode, NULL))
824 min += ESDHC_TUNE_CTRL_STEP;
827 /* find the maxinum delay which can not pass tuning */
828 max = min + ESDHC_TUNE_CTRL_STEP;
829 while (max < ESDHC_TUNE_CTRL_MAX) {
830 esdhc_prepare_tuning(host, max);
831 if (mmc_send_tuning(host->mmc, opcode, NULL)) {
832 max -= ESDHC_TUNE_CTRL_STEP;
835 max += ESDHC_TUNE_CTRL_STEP;
838 /* use average delay to get the best timing */
839 avg = (min + max) / 2;
840 esdhc_prepare_tuning(host, avg);
841 ret = mmc_send_tuning(host->mmc, opcode, NULL);
842 esdhc_post_tuning(host);
844 dev_dbg(mmc_dev(host->mmc), "tuning %s at 0x%x ret %d\n",
845 ret ? "failed" : "passed", avg, ret);
850 static int esdhc_change_pinstate(struct sdhci_host *host,
853 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
854 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
855 struct pinctrl_state *pinctrl;
857 dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs);
859 if (IS_ERR(imx_data->pinctrl) ||
860 IS_ERR(imx_data->pins_default) ||
861 IS_ERR(imx_data->pins_100mhz) ||
862 IS_ERR(imx_data->pins_200mhz))
866 case MMC_TIMING_UHS_SDR50:
867 case MMC_TIMING_UHS_DDR50:
868 pinctrl = imx_data->pins_100mhz;
870 case MMC_TIMING_UHS_SDR104:
871 case MMC_TIMING_MMC_HS200:
872 case MMC_TIMING_MMC_HS400:
873 pinctrl = imx_data->pins_200mhz;
876 /* back to default state for other legacy timing */
877 pinctrl = imx_data->pins_default;
880 return pinctrl_select_state(imx_data->pinctrl, pinctrl);
884 * For HS400 eMMC, there is a data_strobe line. This signal is generated
885 * by the device and used for data output and CRC status response output
886 * in HS400 mode. The frequency of this signal follows the frequency of
887 * CLK generated by host. The host receives the data which is aligned to the
888 * edge of data_strobe line. Due to the time delay between CLK line and
889 * data_strobe line, if the delay time is larger than one clock cycle,
890 * then CLK and data_strobe line will be misaligned, read error shows up.
891 * So when the CLK is higher than 100MHz, each clock cycle is short enough,
892 * host should configure the delay target.
894 static void esdhc_set_strobe_dll(struct sdhci_host *host)
898 if (host->mmc->actual_clock > ESDHC_STROBE_DLL_CLK_FREQ) {
899 /* disable clock before enabling strobe dll */
900 writel(readl(host->ioaddr + ESDHC_VENDOR_SPEC) &
901 ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
902 host->ioaddr + ESDHC_VENDOR_SPEC);
904 /* force a reset on strobe dll */
905 writel(ESDHC_STROBE_DLL_CTRL_RESET,
906 host->ioaddr + ESDHC_STROBE_DLL_CTRL);
908 * enable strobe dll ctrl and adjust the delay target
909 * for the uSDHC loopback read clock
911 v = ESDHC_STROBE_DLL_CTRL_ENABLE |
912 (7 << ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
913 writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL);
914 /* wait 1us to make sure strobe dll status register stable */
916 v = readl(host->ioaddr + ESDHC_STROBE_DLL_STATUS);
917 if (!(v & ESDHC_STROBE_DLL_STS_REF_LOCK))
918 dev_warn(mmc_dev(host->mmc),
919 "warning! HS400 strobe DLL status REF not lock!\n");
920 if (!(v & ESDHC_STROBE_DLL_STS_SLV_LOCK))
921 dev_warn(mmc_dev(host->mmc),
922 "warning! HS400 strobe DLL status SLV not lock!\n");
926 static void esdhc_reset_tuning(struct sdhci_host *host)
928 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
929 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
933 /* Reset the tuning circuit */
934 if (esdhc_is_usdhc(imx_data)) {
935 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
936 ctrl = readl(host->ioaddr + ESDHC_MIX_CTRL);
937 ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
938 ctrl &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
939 writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL);
940 writel(0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
941 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
942 ctrl = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
943 ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
944 ctrl &= ~ESDHC_MIX_CTRL_EXE_TUNE;
945 writel(ctrl, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
946 /* Make sure ESDHC_MIX_CTRL_EXE_TUNE cleared */
947 ret = readl_poll_timeout(host->ioaddr + SDHCI_AUTO_CMD_STATUS,
948 ctrl, !(ctrl & ESDHC_MIX_CTRL_EXE_TUNE), 1, 50);
949 if (ret == -ETIMEDOUT)
950 dev_warn(mmc_dev(host->mmc),
951 "Warning! clear execute tuning bit failed\n");
953 * SDHCI_INT_DATA_AVAIL is W1C bit, set this bit will clear the
954 * usdhc IP internal logic flag execute_tuning_with_clr_buf, which
955 * will finally make sure the normal data transfer logic correct.
957 ctrl = readl(host->ioaddr + SDHCI_INT_STATUS);
958 ctrl |= SDHCI_INT_DATA_AVAIL;
959 writel(ctrl, host->ioaddr + SDHCI_INT_STATUS);
964 static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
967 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
968 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
969 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
971 /* disable ddr mode and disable HS400 mode */
972 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
973 m &= ~(ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN);
974 imx_data->is_ddr = 0;
977 case MMC_TIMING_UHS_SDR12:
978 case MMC_TIMING_UHS_SDR25:
979 case MMC_TIMING_UHS_SDR50:
980 case MMC_TIMING_UHS_SDR104:
981 case MMC_TIMING_MMC_HS:
982 case MMC_TIMING_MMC_HS200:
983 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
985 case MMC_TIMING_UHS_DDR50:
986 case MMC_TIMING_MMC_DDR52:
987 m |= ESDHC_MIX_CTRL_DDREN;
988 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
989 imx_data->is_ddr = 1;
990 if (boarddata->delay_line) {
992 v = boarddata->delay_line <<
993 ESDHC_DLL_OVERRIDE_VAL_SHIFT |
994 (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT);
995 if (is_imx53_esdhc(imx_data))
997 writel(v, host->ioaddr + ESDHC_DLL_CTRL);
1000 case MMC_TIMING_MMC_HS400:
1001 m |= ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN;
1002 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1003 imx_data->is_ddr = 1;
1004 /* update clock after enable DDR for strobe DLL lock */
1005 host->ops->set_clock(host, host->clock);
1006 esdhc_set_strobe_dll(host);
1008 case MMC_TIMING_LEGACY:
1010 esdhc_reset_tuning(host);
1014 esdhc_change_pinstate(host, timing);
1017 static void esdhc_reset(struct sdhci_host *host, u8 mask)
1019 sdhci_reset(host, mask);
1021 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1022 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1025 static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host)
1027 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1028 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1030 /* Doc Erratum: the uSDHC actual maximum timeout count is 1 << 29 */
1031 return esdhc_is_usdhc(imx_data) ? 1 << 29 : 1 << 27;
1034 static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
1036 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1037 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1039 /* use maximum timeout counter */
1040 esdhc_clrset_le(host, ESDHC_SYS_CTRL_DTOCV_MASK,
1041 esdhc_is_usdhc(imx_data) ? 0xF : 0xE,
1042 SDHCI_TIMEOUT_CONTROL);
1045 static struct sdhci_ops sdhci_esdhc_ops = {
1046 .read_l = esdhc_readl_le,
1047 .read_w = esdhc_readw_le,
1048 .read_b = esdhc_readb_le,
1049 .write_l = esdhc_writel_le,
1050 .write_w = esdhc_writew_le,
1051 .write_b = esdhc_writeb_le,
1052 .set_clock = esdhc_pltfm_set_clock,
1053 .get_max_clock = esdhc_pltfm_get_max_clock,
1054 .get_min_clock = esdhc_pltfm_get_min_clock,
1055 .get_max_timeout_count = esdhc_get_max_timeout_count,
1056 .get_ro = esdhc_pltfm_get_ro,
1057 .set_timeout = esdhc_set_timeout,
1058 .set_bus_width = esdhc_pltfm_set_bus_width,
1059 .set_uhs_signaling = esdhc_set_uhs_signaling,
1060 .reset = esdhc_reset,
1063 static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
1064 .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT
1065 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
1066 | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
1067 | SDHCI_QUIRK_BROKEN_CARD_DETECTION,
1068 .ops = &sdhci_esdhc_ops,
1071 static void sdhci_esdhc_imx_hwinit(struct sdhci_host *host)
1073 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1074 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1077 if (esdhc_is_usdhc(imx_data)) {
1079 * The imx6q ROM code will change the default watermark
1080 * level setting to something insane. Change it back here.
1082 writel(ESDHC_WTMK_DEFAULT_VAL, host->ioaddr + ESDHC_WTMK_LVL);
1085 * ROM code will change the bit burst_length_enable setting
1086 * to zero if this usdhc is chosen to boot system. Change
1087 * it back here, otherwise it will impact the performance a
1088 * lot. This bit is used to enable/disable the burst length
1089 * for the external AHB2AXI bridge. It's useful especially
1090 * for INCR transfer because without burst length indicator,
1091 * the AHB2AXI bridge does not know the burst length in
1092 * advance. And without burst length indicator, AHB INCR
1093 * transfer can only be converted to singles on the AXI side.
1095 writel(readl(host->ioaddr + SDHCI_HOST_CONTROL)
1096 | ESDHC_BURST_LEN_EN_INCR,
1097 host->ioaddr + SDHCI_HOST_CONTROL);
1100 * erratum ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL
1101 * TO1.1, it's harmless for MX6SL
1103 writel(readl(host->ioaddr + 0x6c) & ~BIT(7),
1104 host->ioaddr + 0x6c);
1106 /* disable DLL_CTRL delay line settings */
1107 writel(0x0, host->ioaddr + ESDHC_DLL_CTRL);
1109 if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
1110 tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL);
1111 tmp |= ESDHC_STD_TUNING_EN |
1112 ESDHC_TUNING_START_TAP_DEFAULT;
1113 if (imx_data->boarddata.tuning_start_tap) {
1114 tmp &= ~ESDHC_TUNING_START_TAP_MASK;
1115 tmp |= imx_data->boarddata.tuning_start_tap;
1118 if (imx_data->boarddata.tuning_step) {
1119 tmp &= ~ESDHC_TUNING_STEP_MASK;
1120 tmp |= imx_data->boarddata.tuning_step
1121 << ESDHC_TUNING_STEP_SHIFT;
1123 writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL);
1130 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
1131 struct sdhci_host *host,
1132 struct pltfm_imx_data *imx_data)
1134 struct device_node *np = pdev->dev.of_node;
1135 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
1138 if (of_get_property(np, "fsl,wp-controller", NULL))
1139 boarddata->wp_type = ESDHC_WP_CONTROLLER;
1141 boarddata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
1142 if (gpio_is_valid(boarddata->wp_gpio))
1143 boarddata->wp_type = ESDHC_WP_GPIO;
1145 of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step);
1146 of_property_read_u32(np, "fsl,tuning-start-tap",
1147 &boarddata->tuning_start_tap);
1149 if (of_find_property(np, "no-1-8-v", NULL))
1150 boarddata->support_vsel = false;
1152 boarddata->support_vsel = true;
1154 if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line))
1155 boarddata->delay_line = 0;
1157 mmc_of_parse_voltage(np, &host->ocr_mask);
1159 /* sdr50 and sdr104 need work on 1.8v signal voltage */
1160 if ((boarddata->support_vsel) && esdhc_is_usdhc(imx_data) &&
1161 !IS_ERR(imx_data->pins_default)) {
1162 imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl,
1163 ESDHC_PINCTRL_STATE_100MHZ);
1164 imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl,
1165 ESDHC_PINCTRL_STATE_200MHZ);
1168 /* call to generic mmc_of_parse to support additional capabilities */
1169 ret = mmc_of_parse(host->mmc);
1173 if (mmc_gpio_get_cd(host->mmc) >= 0)
1174 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
1180 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
1181 struct sdhci_host *host,
1182 struct pltfm_imx_data *imx_data)
1188 static int sdhci_esdhc_imx_probe_nondt(struct platform_device *pdev,
1189 struct sdhci_host *host,
1190 struct pltfm_imx_data *imx_data)
1192 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
1195 if (!host->mmc->parent->platform_data) {
1196 dev_err(mmc_dev(host->mmc), "no board data!\n");
1200 imx_data->boarddata = *((struct esdhc_platform_data *)
1201 host->mmc->parent->platform_data);
1203 if (boarddata->wp_type == ESDHC_WP_GPIO) {
1204 err = mmc_gpio_request_ro(host->mmc, boarddata->wp_gpio);
1206 dev_err(mmc_dev(host->mmc),
1207 "failed to request write-protect gpio!\n");
1210 host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
1214 switch (boarddata->cd_type) {
1216 err = mmc_gpio_request_cd(host->mmc, boarddata->cd_gpio, 0);
1218 dev_err(mmc_dev(host->mmc),
1219 "failed to request card-detect gpio!\n");
1224 case ESDHC_CD_CONTROLLER:
1225 /* we have a working card_detect back */
1226 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
1229 case ESDHC_CD_PERMANENT:
1230 host->mmc->caps |= MMC_CAP_NONREMOVABLE;
1237 switch (boarddata->max_bus_width) {
1239 host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA;
1242 host->mmc->caps |= MMC_CAP_4_BIT_DATA;
1246 host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA;
1253 static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
1255 const struct of_device_id *of_id =
1256 of_match_device(imx_esdhc_dt_ids, &pdev->dev);
1257 struct sdhci_pltfm_host *pltfm_host;
1258 struct sdhci_host *host;
1260 struct pltfm_imx_data *imx_data;
1262 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata,
1265 return PTR_ERR(host);
1267 pltfm_host = sdhci_priv(host);
1269 imx_data = sdhci_pltfm_priv(pltfm_host);
1271 imx_data->socdata = of_id ? of_id->data : (struct esdhc_soc_data *)
1272 pdev->id_entry->driver_data;
1274 imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1275 if (IS_ERR(imx_data->clk_ipg)) {
1276 err = PTR_ERR(imx_data->clk_ipg);
1280 imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1281 if (IS_ERR(imx_data->clk_ahb)) {
1282 err = PTR_ERR(imx_data->clk_ahb);
1286 imx_data->clk_per = devm_clk_get(&pdev->dev, "per");
1287 if (IS_ERR(imx_data->clk_per)) {
1288 err = PTR_ERR(imx_data->clk_per);
1292 pltfm_host->clk = imx_data->clk_per;
1293 pltfm_host->clock = clk_get_rate(pltfm_host->clk);
1294 err = clk_prepare_enable(imx_data->clk_per);
1297 err = clk_prepare_enable(imx_data->clk_ipg);
1299 goto disable_per_clk;
1300 err = clk_prepare_enable(imx_data->clk_ahb);
1302 goto disable_ipg_clk;
1304 imx_data->pinctrl = devm_pinctrl_get(&pdev->dev);
1305 if (IS_ERR(imx_data->pinctrl)) {
1306 err = PTR_ERR(imx_data->pinctrl);
1307 goto disable_ahb_clk;
1310 imx_data->pins_default = pinctrl_lookup_state(imx_data->pinctrl,
1311 PINCTRL_STATE_DEFAULT);
1312 if (IS_ERR(imx_data->pins_default))
1313 dev_warn(mmc_dev(host->mmc), "could not get default state\n");
1315 if (esdhc_is_usdhc(imx_data)) {
1316 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
1317 host->mmc->caps |= MMC_CAP_1_8V_DDR;
1318 if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200))
1319 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
1321 /* clear tuning bits in case ROM has set it already */
1322 writel(0x0, host->ioaddr + ESDHC_MIX_CTRL);
1323 writel(0x0, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
1324 writel(0x0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
1327 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
1328 sdhci_esdhc_ops.platform_execute_tuning =
1329 esdhc_executing_tuning;
1331 if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536)
1332 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
1334 if (imx_data->socdata->flags & ESDHC_FLAG_HS400)
1335 host->quirks2 |= SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400;
1338 err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data);
1340 err = sdhci_esdhc_imx_probe_nondt(pdev, host, imx_data);
1342 goto disable_ahb_clk;
1344 sdhci_esdhc_imx_hwinit(host);
1346 err = sdhci_add_host(host);
1348 goto disable_ahb_clk;
1350 pm_runtime_set_active(&pdev->dev);
1351 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1352 pm_runtime_use_autosuspend(&pdev->dev);
1353 pm_suspend_ignore_children(&pdev->dev, 1);
1354 pm_runtime_enable(&pdev->dev);
1359 clk_disable_unprepare(imx_data->clk_ahb);
1361 clk_disable_unprepare(imx_data->clk_ipg);
1363 clk_disable_unprepare(imx_data->clk_per);
1365 sdhci_pltfm_free(pdev);
1369 static int sdhci_esdhc_imx_remove(struct platform_device *pdev)
1371 struct sdhci_host *host = platform_get_drvdata(pdev);
1372 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1373 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1376 pm_runtime_get_sync(&pdev->dev);
1377 dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
1378 pm_runtime_disable(&pdev->dev);
1379 pm_runtime_put_noidle(&pdev->dev);
1381 sdhci_remove_host(host, dead);
1383 clk_disable_unprepare(imx_data->clk_per);
1384 clk_disable_unprepare(imx_data->clk_ipg);
1385 clk_disable_unprepare(imx_data->clk_ahb);
1387 sdhci_pltfm_free(pdev);
1392 #ifdef CONFIG_PM_SLEEP
1393 static int sdhci_esdhc_suspend(struct device *dev)
1395 struct sdhci_host *host = dev_get_drvdata(dev);
1397 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1398 mmc_retune_needed(host->mmc);
1400 return sdhci_suspend_host(host);
1403 static int sdhci_esdhc_resume(struct device *dev)
1405 struct sdhci_host *host = dev_get_drvdata(dev);
1407 /* re-initialize hw state in case it's lost in low power mode */
1408 sdhci_esdhc_imx_hwinit(host);
1410 return sdhci_resume_host(host);
1415 static int sdhci_esdhc_runtime_suspend(struct device *dev)
1417 struct sdhci_host *host = dev_get_drvdata(dev);
1418 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1419 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1422 ret = sdhci_runtime_suspend_host(host);
1424 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1425 mmc_retune_needed(host->mmc);
1427 if (!sdhci_sdio_irq_enabled(host)) {
1428 clk_disable_unprepare(imx_data->clk_per);
1429 clk_disable_unprepare(imx_data->clk_ipg);
1431 clk_disable_unprepare(imx_data->clk_ahb);
1436 static int sdhci_esdhc_runtime_resume(struct device *dev)
1438 struct sdhci_host *host = dev_get_drvdata(dev);
1439 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1440 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1443 if (!sdhci_sdio_irq_enabled(host)) {
1444 err = clk_prepare_enable(imx_data->clk_per);
1447 err = clk_prepare_enable(imx_data->clk_ipg);
1449 goto disable_per_clk;
1451 err = clk_prepare_enable(imx_data->clk_ahb);
1453 goto disable_ipg_clk;
1454 err = sdhci_runtime_resume_host(host);
1456 goto disable_ahb_clk;
1461 clk_disable_unprepare(imx_data->clk_ahb);
1463 if (!sdhci_sdio_irq_enabled(host))
1464 clk_disable_unprepare(imx_data->clk_ipg);
1466 if (!sdhci_sdio_irq_enabled(host))
1467 clk_disable_unprepare(imx_data->clk_per);
1472 static const struct dev_pm_ops sdhci_esdhc_pmops = {
1473 SET_SYSTEM_SLEEP_PM_OPS(sdhci_esdhc_suspend, sdhci_esdhc_resume)
1474 SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend,
1475 sdhci_esdhc_runtime_resume, NULL)
1478 static struct platform_driver sdhci_esdhc_imx_driver = {
1480 .name = "sdhci-esdhc-imx",
1481 .of_match_table = imx_esdhc_dt_ids,
1482 .pm = &sdhci_esdhc_pmops,
1484 .id_table = imx_esdhc_devtype,
1485 .probe = sdhci_esdhc_imx_probe,
1486 .remove = sdhci_esdhc_imx_remove,
1489 module_platform_driver(sdhci_esdhc_imx_driver);
1491 MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC");
1492 MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>");
1493 MODULE_LICENSE("GPL v2");