2 * linux/drivers/mmc/s3cmci.h - Samsung S3C MCI driver
4 * Copyright (C) 2004-2006 maintech GmbH, Thomas Kleffel <tk@maintech.de>
6 * Current driver maintained by Ben Dooks and Simtec Electronics
7 * Copyright (C) 2008 Simtec Electronics <ben-linux@fluff.org>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/module.h>
15 #include <linux/dmaengine.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/clk.h>
18 #include <linux/mmc/host.h>
19 #include <linux/platform_device.h>
20 #include <linux/cpufreq.h>
21 #include <linux/debugfs.h>
22 #include <linux/seq_file.h>
23 #include <linux/gpio.h>
24 #include <linux/interrupt.h>
25 #include <linux/irq.h>
28 #include <plat/gpio-cfg.h>
30 #include <mach/gpio-samsung.h>
32 #include <linux/platform_data/dma-s3c24xx.h>
33 #include <linux/platform_data/mmc-s3cmci.h>
37 #define DRIVER_NAME "s3c-mci"
39 #define S3C2410_SDICON (0x00)
40 #define S3C2410_SDIPRE (0x04)
41 #define S3C2410_SDICMDARG (0x08)
42 #define S3C2410_SDICMDCON (0x0C)
43 #define S3C2410_SDICMDSTAT (0x10)
44 #define S3C2410_SDIRSP0 (0x14)
45 #define S3C2410_SDIRSP1 (0x18)
46 #define S3C2410_SDIRSP2 (0x1C)
47 #define S3C2410_SDIRSP3 (0x20)
48 #define S3C2410_SDITIMER (0x24)
49 #define S3C2410_SDIBSIZE (0x28)
50 #define S3C2410_SDIDCON (0x2C)
51 #define S3C2410_SDIDCNT (0x30)
52 #define S3C2410_SDIDSTA (0x34)
53 #define S3C2410_SDIFSTA (0x38)
55 #define S3C2410_SDIDATA (0x3C)
56 #define S3C2410_SDIIMSK (0x40)
58 #define S3C2440_SDIDATA (0x40)
59 #define S3C2440_SDIIMSK (0x3C)
61 #define S3C2440_SDICON_SDRESET (1 << 8)
62 #define S3C2410_SDICON_SDIOIRQ (1 << 3)
63 #define S3C2410_SDICON_FIFORESET (1 << 1)
64 #define S3C2410_SDICON_CLOCKTYPE (1 << 0)
66 #define S3C2410_SDICMDCON_LONGRSP (1 << 10)
67 #define S3C2410_SDICMDCON_WAITRSP (1 << 9)
68 #define S3C2410_SDICMDCON_CMDSTART (1 << 8)
69 #define S3C2410_SDICMDCON_SENDERHOST (1 << 6)
70 #define S3C2410_SDICMDCON_INDEX (0x3f)
72 #define S3C2410_SDICMDSTAT_CRCFAIL (1 << 12)
73 #define S3C2410_SDICMDSTAT_CMDSENT (1 << 11)
74 #define S3C2410_SDICMDSTAT_CMDTIMEOUT (1 << 10)
75 #define S3C2410_SDICMDSTAT_RSPFIN (1 << 9)
77 #define S3C2440_SDIDCON_DS_WORD (2 << 22)
78 #define S3C2410_SDIDCON_TXAFTERRESP (1 << 20)
79 #define S3C2410_SDIDCON_RXAFTERCMD (1 << 19)
80 #define S3C2410_SDIDCON_BLOCKMODE (1 << 17)
81 #define S3C2410_SDIDCON_WIDEBUS (1 << 16)
82 #define S3C2410_SDIDCON_DMAEN (1 << 15)
83 #define S3C2410_SDIDCON_STOP (1 << 14)
84 #define S3C2440_SDIDCON_DATSTART (1 << 14)
86 #define S3C2410_SDIDCON_XFER_RXSTART (2 << 12)
87 #define S3C2410_SDIDCON_XFER_TXSTART (3 << 12)
89 #define S3C2410_SDIDCON_BLKNUM_MASK (0xFFF)
91 #define S3C2410_SDIDSTA_SDIOIRQDETECT (1 << 9)
92 #define S3C2410_SDIDSTA_FIFOFAIL (1 << 8)
93 #define S3C2410_SDIDSTA_CRCFAIL (1 << 7)
94 #define S3C2410_SDIDSTA_RXCRCFAIL (1 << 6)
95 #define S3C2410_SDIDSTA_DATATIMEOUT (1 << 5)
96 #define S3C2410_SDIDSTA_XFERFINISH (1 << 4)
97 #define S3C2410_SDIDSTA_TXDATAON (1 << 1)
98 #define S3C2410_SDIDSTA_RXDATAON (1 << 0)
100 #define S3C2440_SDIFSTA_FIFORESET (1 << 16)
101 #define S3C2440_SDIFSTA_FIFOFAIL (3 << 14)
102 #define S3C2410_SDIFSTA_TFDET (1 << 13)
103 #define S3C2410_SDIFSTA_RFDET (1 << 12)
104 #define S3C2410_SDIFSTA_COUNTMASK (0x7f)
106 #define S3C2410_SDIIMSK_RESPONSECRC (1 << 17)
107 #define S3C2410_SDIIMSK_CMDSENT (1 << 16)
108 #define S3C2410_SDIIMSK_CMDTIMEOUT (1 << 15)
109 #define S3C2410_SDIIMSK_RESPONSEND (1 << 14)
110 #define S3C2410_SDIIMSK_SDIOIRQ (1 << 12)
111 #define S3C2410_SDIIMSK_FIFOFAIL (1 << 11)
112 #define S3C2410_SDIIMSK_CRCSTATUS (1 << 10)
113 #define S3C2410_SDIIMSK_DATACRC (1 << 9)
114 #define S3C2410_SDIIMSK_DATATIMEOUT (1 << 8)
115 #define S3C2410_SDIIMSK_DATAFINISH (1 << 7)
116 #define S3C2410_SDIIMSK_TXFIFOHALF (1 << 4)
117 #define S3C2410_SDIIMSK_RXFIFOLAST (1 << 2)
118 #define S3C2410_SDIIMSK_RXFIFOHALF (1 << 0)
122 dbg_debug = (1 << 1),
132 static const int dbgmap_err = dbg_fail;
133 static const int dbgmap_info = dbg_info | dbg_conf;
134 static const int dbgmap_debug = dbg_err | dbg_debug;
136 #define dbg(host, channels, args...) \
138 if (dbgmap_err & channels) \
139 dev_err(&host->pdev->dev, args); \
140 else if (dbgmap_info & channels) \
141 dev_info(&host->pdev->dev, args); \
142 else if (dbgmap_debug & channels) \
143 dev_dbg(&host->pdev->dev, args); \
146 static void finalize_request(struct s3cmci_host *host);
147 static void s3cmci_send_request(struct mmc_host *mmc);
148 static void s3cmci_reset(struct s3cmci_host *host);
150 #ifdef CONFIG_MMC_DEBUG
152 static void dbg_dumpregs(struct s3cmci_host *host, char *prefix)
154 u32 con, pre, cmdarg, cmdcon, cmdsta, r0, r1, r2, r3, timer, bsize;
155 u32 datcon, datcnt, datsta, fsta, imask;
157 con = readl(host->base + S3C2410_SDICON);
158 pre = readl(host->base + S3C2410_SDIPRE);
159 cmdarg = readl(host->base + S3C2410_SDICMDARG);
160 cmdcon = readl(host->base + S3C2410_SDICMDCON);
161 cmdsta = readl(host->base + S3C2410_SDICMDSTAT);
162 r0 = readl(host->base + S3C2410_SDIRSP0);
163 r1 = readl(host->base + S3C2410_SDIRSP1);
164 r2 = readl(host->base + S3C2410_SDIRSP2);
165 r3 = readl(host->base + S3C2410_SDIRSP3);
166 timer = readl(host->base + S3C2410_SDITIMER);
167 bsize = readl(host->base + S3C2410_SDIBSIZE);
168 datcon = readl(host->base + S3C2410_SDIDCON);
169 datcnt = readl(host->base + S3C2410_SDIDCNT);
170 datsta = readl(host->base + S3C2410_SDIDSTA);
171 fsta = readl(host->base + S3C2410_SDIFSTA);
172 imask = readl(host->base + host->sdiimsk);
174 dbg(host, dbg_debug, "%s CON:[%08x] PRE:[%08x] TMR:[%08x]\n",
175 prefix, con, pre, timer);
177 dbg(host, dbg_debug, "%s CCON:[%08x] CARG:[%08x] CSTA:[%08x]\n",
178 prefix, cmdcon, cmdarg, cmdsta);
180 dbg(host, dbg_debug, "%s DCON:[%08x] FSTA:[%08x]"
181 " DSTA:[%08x] DCNT:[%08x]\n",
182 prefix, datcon, fsta, datsta, datcnt);
184 dbg(host, dbg_debug, "%s R0:[%08x] R1:[%08x]"
185 " R2:[%08x] R3:[%08x]\n",
186 prefix, r0, r1, r2, r3);
189 static void prepare_dbgmsg(struct s3cmci_host *host, struct mmc_command *cmd,
192 snprintf(host->dbgmsg_cmd, 300,
193 "#%u%s op:%i arg:0x%08x flags:0x08%x retries:%u",
194 host->ccnt, (stop ? " (STOP)" : ""),
195 cmd->opcode, cmd->arg, cmd->flags, cmd->retries);
198 snprintf(host->dbgmsg_dat, 300,
199 "#%u bsize:%u blocks:%u bytes:%u",
200 host->dcnt, cmd->data->blksz,
202 cmd->data->blocks * cmd->data->blksz);
204 host->dbgmsg_dat[0] = '\0';
208 static void dbg_dumpcmd(struct s3cmci_host *host, struct mmc_command *cmd,
211 unsigned int dbglvl = fail ? dbg_fail : dbg_debug;
216 if (cmd->error == 0) {
217 dbg(host, dbglvl, "CMD[OK] %s R0:0x%08x\n",
218 host->dbgmsg_cmd, cmd->resp[0]);
220 dbg(host, dbglvl, "CMD[ERR %i] %s Status:%s\n",
221 cmd->error, host->dbgmsg_cmd, host->status);
227 if (cmd->data->error == 0) {
228 dbg(host, dbglvl, "DAT[OK] %s\n", host->dbgmsg_dat);
230 dbg(host, dbglvl, "DAT[ERR %i] %s DCNT:0x%08x\n",
231 cmd->data->error, host->dbgmsg_dat,
232 readl(host->base + S3C2410_SDIDCNT));
236 static void dbg_dumpcmd(struct s3cmci_host *host,
237 struct mmc_command *cmd, int fail) { }
239 static void prepare_dbgmsg(struct s3cmci_host *host, struct mmc_command *cmd,
242 static void dbg_dumpregs(struct s3cmci_host *host, char *prefix) { }
244 #endif /* CONFIG_MMC_DEBUG */
247 * s3cmci_host_usedma - return whether the host is using dma or pio
248 * @host: The host state
250 * Return true if the host is using DMA to transfer data, else false
251 * to use PIO mode. Will return static data depending on the driver
254 static inline bool s3cmci_host_usedma(struct s3cmci_host *host)
256 #ifdef CONFIG_MMC_S3C_PIO
258 #else /* CONFIG_MMC_S3C_DMA */
263 static inline u32 enable_imask(struct s3cmci_host *host, u32 imask)
267 newmask = readl(host->base + host->sdiimsk);
270 writel(newmask, host->base + host->sdiimsk);
275 static inline u32 disable_imask(struct s3cmci_host *host, u32 imask)
279 newmask = readl(host->base + host->sdiimsk);
282 writel(newmask, host->base + host->sdiimsk);
287 static inline void clear_imask(struct s3cmci_host *host)
289 u32 mask = readl(host->base + host->sdiimsk);
291 /* preserve the SDIO IRQ mask state */
292 mask &= S3C2410_SDIIMSK_SDIOIRQ;
293 writel(mask, host->base + host->sdiimsk);
297 * s3cmci_check_sdio_irq - test whether the SDIO IRQ is being signalled
298 * @host: The host to check.
300 * Test to see if the SDIO interrupt is being signalled in case the
301 * controller has failed to re-detect a card interrupt. Read GPE8 and
302 * see if it is low and if so, signal a SDIO interrupt.
304 * This is currently called if a request is finished (we assume that the
305 * bus is now idle) and when the SDIO IRQ is enabled in case the IRQ is
306 * already being indicated.
308 static void s3cmci_check_sdio_irq(struct s3cmci_host *host)
310 if (host->sdio_irqen) {
311 if (gpio_get_value(S3C2410_GPE(8)) == 0) {
312 pr_debug("%s: signalling irq\n", __func__);
313 mmc_signal_sdio_irq(host->mmc);
318 static inline int get_data_buffer(struct s3cmci_host *host,
319 u32 *bytes, u32 **pointer)
321 struct scatterlist *sg;
323 if (host->pio_active == XFER_NONE)
326 if ((!host->mrq) || (!host->mrq->data))
329 if (host->pio_sgptr >= host->mrq->data->sg_len) {
330 dbg(host, dbg_debug, "no more buffers (%i/%i)\n",
331 host->pio_sgptr, host->mrq->data->sg_len);
334 sg = &host->mrq->data->sg[host->pio_sgptr];
337 *pointer = sg_virt(sg);
341 dbg(host, dbg_sg, "new buffer (%i/%i)\n",
342 host->pio_sgptr, host->mrq->data->sg_len);
347 static inline u32 fifo_count(struct s3cmci_host *host)
349 u32 fifostat = readl(host->base + S3C2410_SDIFSTA);
351 fifostat &= S3C2410_SDIFSTA_COUNTMASK;
355 static inline u32 fifo_free(struct s3cmci_host *host)
357 u32 fifostat = readl(host->base + S3C2410_SDIFSTA);
359 fifostat &= S3C2410_SDIFSTA_COUNTMASK;
360 return 63 - fifostat;
364 * s3cmci_enable_irq - enable IRQ, after having disabled it.
365 * @host: The device state.
366 * @more: True if more IRQs are expected from transfer.
368 * Enable the main IRQ if needed after it has been disabled.
370 * The IRQ can be one of the following states:
371 * - disabled during IDLE
372 * - disabled whilst processing data
373 * - enabled during transfer
374 * - enabled whilst awaiting SDIO interrupt detection
376 static void s3cmci_enable_irq(struct s3cmci_host *host, bool more)
381 local_irq_save(flags);
383 host->irq_enabled = more;
384 host->irq_disabled = false;
386 enable = more | host->sdio_irqen;
388 if (host->irq_state != enable) {
389 host->irq_state = enable;
392 enable_irq(host->irq);
394 disable_irq(host->irq);
397 local_irq_restore(flags);
403 static void s3cmci_disable_irq(struct s3cmci_host *host, bool transfer)
407 local_irq_save(flags);
409 /* pr_debug("%s: transfer %d\n", __func__, transfer); */
411 host->irq_disabled = transfer;
413 if (transfer && host->irq_state) {
414 host->irq_state = false;
415 disable_irq(host->irq);
418 local_irq_restore(flags);
421 static void do_pio_read(struct s3cmci_host *host)
427 void __iomem *from_ptr;
429 /* write real prescaler to host, it might be set slow to fix */
430 writel(host->prescaler, host->base + S3C2410_SDIPRE);
432 from_ptr = host->base + host->sdidata;
434 while ((fifo = fifo_count(host))) {
435 if (!host->pio_bytes) {
436 res = get_data_buffer(host, &host->pio_bytes,
439 host->pio_active = XFER_NONE;
440 host->complete_what = COMPLETION_FINALIZE;
442 dbg(host, dbg_pio, "pio_read(): "
443 "complete (no more data).\n");
448 "pio_read(): new target: [%i]@[%p]\n",
449 host->pio_bytes, host->pio_ptr);
453 "pio_read(): fifo:[%02i] buffer:[%03i] dcnt:[%08X]\n",
454 fifo, host->pio_bytes,
455 readl(host->base + S3C2410_SDIDCNT));
457 /* If we have reached the end of the block, we can
458 * read a word and get 1 to 3 bytes. If we in the
459 * middle of the block, we have to read full words,
460 * otherwise we will write garbage, so round down to
461 * an even multiple of 4. */
462 if (fifo >= host->pio_bytes)
463 fifo = host->pio_bytes;
467 host->pio_bytes -= fifo;
468 host->pio_count += fifo;
470 fifo_words = fifo >> 2;
473 *ptr++ = readl(from_ptr);
478 u32 data = readl(from_ptr);
479 u8 *p = (u8 *)host->pio_ptr;
488 if (!host->pio_bytes) {
489 res = get_data_buffer(host, &host->pio_bytes, &host->pio_ptr);
492 "pio_read(): complete (no more buffers).\n");
493 host->pio_active = XFER_NONE;
494 host->complete_what = COMPLETION_FINALIZE;
501 S3C2410_SDIIMSK_RXFIFOHALF | S3C2410_SDIIMSK_RXFIFOLAST);
504 static void do_pio_write(struct s3cmci_host *host)
506 void __iomem *to_ptr;
511 to_ptr = host->base + host->sdidata;
513 while ((fifo = fifo_free(host)) > 3) {
514 if (!host->pio_bytes) {
515 res = get_data_buffer(host, &host->pio_bytes,
519 "pio_write(): complete (no more data).\n");
520 host->pio_active = XFER_NONE;
526 "pio_write(): new source: [%i]@[%p]\n",
527 host->pio_bytes, host->pio_ptr);
531 /* If we have reached the end of the block, we have to
532 * write exactly the remaining number of bytes. If we
533 * in the middle of the block, we have to write full
534 * words, so round down to an even multiple of 4. */
535 if (fifo >= host->pio_bytes)
536 fifo = host->pio_bytes;
540 host->pio_bytes -= fifo;
541 host->pio_count += fifo;
543 fifo = (fifo + 3) >> 2;
546 writel(*ptr++, to_ptr);
550 enable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
553 static void pio_tasklet(unsigned long data)
555 struct s3cmci_host *host = (struct s3cmci_host *) data;
557 s3cmci_disable_irq(host, true);
559 if (host->pio_active == XFER_WRITE)
562 if (host->pio_active == XFER_READ)
565 if (host->complete_what == COMPLETION_FINALIZE) {
567 if (host->pio_active != XFER_NONE) {
568 dbg(host, dbg_err, "unfinished %s "
569 "- pio_count:[%u] pio_bytes:[%u]\n",
570 (host->pio_active == XFER_READ) ? "read" : "write",
571 host->pio_count, host->pio_bytes);
574 host->mrq->data->error = -EINVAL;
577 s3cmci_enable_irq(host, false);
578 finalize_request(host);
580 s3cmci_enable_irq(host, true);
584 * ISR for SDI Interface IRQ
585 * Communication between driver and ISR works as follows:
586 * host->mrq points to current request
587 * host->complete_what Indicates when the request is considered done
588 * COMPLETION_CMDSENT when the command was sent
589 * COMPLETION_RSPFIN when a response was received
590 * COMPLETION_XFERFINISH when the data transfer is finished
591 * COMPLETION_XFERFINISH_RSPFIN both of the above.
592 * host->complete_request is the completion-object the driver waits for
594 * 1) Driver sets up host->mrq and host->complete_what
595 * 2) Driver prepares the transfer
596 * 3) Driver enables interrupts
597 * 4) Driver starts transfer
598 * 5) Driver waits for host->complete_rquest
599 * 6) ISR checks for request status (errors and success)
600 * 6) ISR sets host->mrq->cmd->error and host->mrq->data->error
601 * 7) ISR completes host->complete_request
602 * 8) ISR disables interrupts
603 * 9) Driver wakes up and takes care of the request
605 * Note: "->error"-fields are expected to be set to 0 before the request
606 * was issued by mmc.c - therefore they are only set, when an error
610 static irqreturn_t s3cmci_irq(int irq, void *dev_id)
612 struct s3cmci_host *host = dev_id;
613 struct mmc_command *cmd;
614 u32 mci_csta, mci_dsta, mci_fsta, mci_dcnt, mci_imsk;
615 u32 mci_cclear = 0, mci_dclear;
616 unsigned long iflags;
618 mci_dsta = readl(host->base + S3C2410_SDIDSTA);
619 mci_imsk = readl(host->base + host->sdiimsk);
621 if (mci_dsta & S3C2410_SDIDSTA_SDIOIRQDETECT) {
622 if (mci_imsk & S3C2410_SDIIMSK_SDIOIRQ) {
623 mci_dclear = S3C2410_SDIDSTA_SDIOIRQDETECT;
624 writel(mci_dclear, host->base + S3C2410_SDIDSTA);
626 mmc_signal_sdio_irq(host->mmc);
631 spin_lock_irqsave(&host->complete_lock, iflags);
633 mci_csta = readl(host->base + S3C2410_SDICMDSTAT);
634 mci_dcnt = readl(host->base + S3C2410_SDIDCNT);
635 mci_fsta = readl(host->base + S3C2410_SDIFSTA);
638 if ((host->complete_what == COMPLETION_NONE) ||
639 (host->complete_what == COMPLETION_FINALIZE)) {
640 host->status = "nothing to complete";
646 host->status = "no active mrq";
651 cmd = host->cmd_is_stop ? host->mrq->stop : host->mrq->cmd;
654 host->status = "no active cmd";
659 if (!s3cmci_host_usedma(host)) {
660 if ((host->pio_active == XFER_WRITE) &&
661 (mci_fsta & S3C2410_SDIFSTA_TFDET)) {
663 disable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
664 tasklet_schedule(&host->pio_tasklet);
665 host->status = "pio tx";
668 if ((host->pio_active == XFER_READ) &&
669 (mci_fsta & S3C2410_SDIFSTA_RFDET)) {
672 S3C2410_SDIIMSK_RXFIFOHALF |
673 S3C2410_SDIIMSK_RXFIFOLAST);
675 tasklet_schedule(&host->pio_tasklet);
676 host->status = "pio rx";
680 if (mci_csta & S3C2410_SDICMDSTAT_CMDTIMEOUT) {
681 dbg(host, dbg_err, "CMDSTAT: error CMDTIMEOUT\n");
682 cmd->error = -ETIMEDOUT;
683 host->status = "error: command timeout";
687 if (mci_csta & S3C2410_SDICMDSTAT_CMDSENT) {
688 if (host->complete_what == COMPLETION_CMDSENT) {
689 host->status = "ok: command sent";
693 mci_cclear |= S3C2410_SDICMDSTAT_CMDSENT;
696 if (mci_csta & S3C2410_SDICMDSTAT_CRCFAIL) {
697 if (cmd->flags & MMC_RSP_CRC) {
698 if (host->mrq->cmd->flags & MMC_RSP_136) {
700 "fixup: ignore CRC fail with long rsp\n");
702 /* note, we used to fail the transfer
703 * here, but it seems that this is just
704 * the hardware getting it wrong.
706 * cmd->error = -EILSEQ;
707 * host->status = "error: bad command crc";
708 * goto fail_transfer;
713 mci_cclear |= S3C2410_SDICMDSTAT_CRCFAIL;
716 if (mci_csta & S3C2410_SDICMDSTAT_RSPFIN) {
717 if (host->complete_what == COMPLETION_RSPFIN) {
718 host->status = "ok: command response received";
722 if (host->complete_what == COMPLETION_XFERFINISH_RSPFIN)
723 host->complete_what = COMPLETION_XFERFINISH;
725 mci_cclear |= S3C2410_SDICMDSTAT_RSPFIN;
728 /* errors handled after this point are only relevant
729 when a data transfer is in progress */
732 goto clear_status_bits;
734 /* Check for FIFO failure */
736 if (mci_fsta & S3C2440_SDIFSTA_FIFOFAIL) {
737 dbg(host, dbg_err, "FIFO failure\n");
738 host->mrq->data->error = -EILSEQ;
739 host->status = "error: 2440 fifo failure";
743 if (mci_dsta & S3C2410_SDIDSTA_FIFOFAIL) {
744 dbg(host, dbg_err, "FIFO failure\n");
745 cmd->data->error = -EILSEQ;
746 host->status = "error: fifo failure";
751 if (mci_dsta & S3C2410_SDIDSTA_RXCRCFAIL) {
752 dbg(host, dbg_err, "bad data crc (outgoing)\n");
753 cmd->data->error = -EILSEQ;
754 host->status = "error: bad data crc (outgoing)";
758 if (mci_dsta & S3C2410_SDIDSTA_CRCFAIL) {
759 dbg(host, dbg_err, "bad data crc (incoming)\n");
760 cmd->data->error = -EILSEQ;
761 host->status = "error: bad data crc (incoming)";
765 if (mci_dsta & S3C2410_SDIDSTA_DATATIMEOUT) {
766 dbg(host, dbg_err, "data timeout\n");
767 cmd->data->error = -ETIMEDOUT;
768 host->status = "error: data timeout";
772 if (mci_dsta & S3C2410_SDIDSTA_XFERFINISH) {
773 if (host->complete_what == COMPLETION_XFERFINISH) {
774 host->status = "ok: data transfer completed";
778 if (host->complete_what == COMPLETION_XFERFINISH_RSPFIN)
779 host->complete_what = COMPLETION_RSPFIN;
781 mci_dclear |= S3C2410_SDIDSTA_XFERFINISH;
785 writel(mci_cclear, host->base + S3C2410_SDICMDSTAT);
786 writel(mci_dclear, host->base + S3C2410_SDIDSTA);
791 host->pio_active = XFER_NONE;
794 host->complete_what = COMPLETION_FINALIZE;
797 tasklet_schedule(&host->pio_tasklet);
803 "csta:0x%08x dsta:0x%08x fsta:0x%08x dcnt:0x%08x status:%s.\n",
804 mci_csta, mci_dsta, mci_fsta, mci_dcnt, host->status);
806 spin_unlock_irqrestore(&host->complete_lock, iflags);
812 * ISR for the CardDetect Pin
815 static irqreturn_t s3cmci_irq_cd(int irq, void *dev_id)
817 struct s3cmci_host *host = (struct s3cmci_host *)dev_id;
819 dbg(host, dbg_irq, "card detect\n");
821 mmc_detect_change(host->mmc, msecs_to_jiffies(500));
826 static void s3cmci_dma_done_callback(void *arg)
828 struct s3cmci_host *host = arg;
829 unsigned long iflags;
832 BUG_ON(!host->mrq->data);
834 spin_lock_irqsave(&host->complete_lock, iflags);
836 dbg(host, dbg_dma, "DMA FINISHED\n");
838 host->dma_complete = 1;
839 host->complete_what = COMPLETION_FINALIZE;
841 tasklet_schedule(&host->pio_tasklet);
842 spin_unlock_irqrestore(&host->complete_lock, iflags);
846 static void finalize_request(struct s3cmci_host *host)
848 struct mmc_request *mrq = host->mrq;
849 struct mmc_command *cmd;
850 int debug_as_failure = 0;
852 if (host->complete_what != COMPLETION_FINALIZE)
857 cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd;
859 if (cmd->data && (cmd->error == 0) &&
860 (cmd->data->error == 0)) {
861 if (s3cmci_host_usedma(host) && (!host->dma_complete)) {
862 dbg(host, dbg_dma, "DMA Missing (%d)!\n",
868 /* Read response from controller. */
869 cmd->resp[0] = readl(host->base + S3C2410_SDIRSP0);
870 cmd->resp[1] = readl(host->base + S3C2410_SDIRSP1);
871 cmd->resp[2] = readl(host->base + S3C2410_SDIRSP2);
872 cmd->resp[3] = readl(host->base + S3C2410_SDIRSP3);
874 writel(host->prescaler, host->base + S3C2410_SDIPRE);
877 debug_as_failure = 1;
879 if (cmd->data && cmd->data->error)
880 debug_as_failure = 1;
882 dbg_dumpcmd(host, cmd, debug_as_failure);
884 /* Cleanup controller */
885 writel(0, host->base + S3C2410_SDICMDARG);
886 writel(S3C2410_SDIDCON_STOP, host->base + S3C2410_SDIDCON);
887 writel(0, host->base + S3C2410_SDICMDCON);
890 if (cmd->data && cmd->error)
891 cmd->data->error = cmd->error;
893 if (cmd->data && cmd->data->stop && (!host->cmd_is_stop)) {
894 host->cmd_is_stop = 1;
895 s3cmci_send_request(host->mmc);
899 /* If we have no data transfer we are finished here */
903 /* Calculate the amout of bytes transfer if there was no error */
904 if (mrq->data->error == 0) {
905 mrq->data->bytes_xfered =
906 (mrq->data->blocks * mrq->data->blksz);
908 mrq->data->bytes_xfered = 0;
911 /* If we had an error while transferring data we flush the
912 * DMA channel and the fifo to clear out any garbage. */
913 if (mrq->data->error != 0) {
914 if (s3cmci_host_usedma(host))
915 dmaengine_terminate_all(host->dma);
918 /* Clear failure register and reset fifo. */
919 writel(S3C2440_SDIFSTA_FIFORESET |
920 S3C2440_SDIFSTA_FIFOFAIL,
921 host->base + S3C2410_SDIFSTA);
926 mci_con = readl(host->base + S3C2410_SDICON);
927 mci_con |= S3C2410_SDICON_FIFORESET;
929 writel(mci_con, host->base + S3C2410_SDICON);
934 host->complete_what = COMPLETION_NONE;
937 s3cmci_check_sdio_irq(host);
938 mmc_request_done(host->mmc, mrq);
941 static void s3cmci_send_command(struct s3cmci_host *host,
942 struct mmc_command *cmd)
946 imsk = S3C2410_SDIIMSK_CRCSTATUS | S3C2410_SDIIMSK_CMDTIMEOUT |
947 S3C2410_SDIIMSK_RESPONSEND | S3C2410_SDIIMSK_CMDSENT |
948 S3C2410_SDIIMSK_RESPONSECRC;
950 enable_imask(host, imsk);
953 host->complete_what = COMPLETION_XFERFINISH_RSPFIN;
954 else if (cmd->flags & MMC_RSP_PRESENT)
955 host->complete_what = COMPLETION_RSPFIN;
957 host->complete_what = COMPLETION_CMDSENT;
959 writel(cmd->arg, host->base + S3C2410_SDICMDARG);
961 ccon = cmd->opcode & S3C2410_SDICMDCON_INDEX;
962 ccon |= S3C2410_SDICMDCON_SENDERHOST | S3C2410_SDICMDCON_CMDSTART;
964 if (cmd->flags & MMC_RSP_PRESENT)
965 ccon |= S3C2410_SDICMDCON_WAITRSP;
967 if (cmd->flags & MMC_RSP_136)
968 ccon |= S3C2410_SDICMDCON_LONGRSP;
970 writel(ccon, host->base + S3C2410_SDICMDCON);
973 static int s3cmci_setup_data(struct s3cmci_host *host, struct mmc_data *data)
975 u32 dcon, imsk, stoptries = 3;
977 /* write DCON register */
980 writel(0, host->base + S3C2410_SDIDCON);
984 if ((data->blksz & 3) != 0) {
985 /* We cannot deal with unaligned blocks with more than
986 * one block being transferred. */
988 if (data->blocks > 1) {
989 pr_warn("%s: can't do non-word sized block transfers (blksz %d)\n",
990 __func__, data->blksz);
995 while (readl(host->base + S3C2410_SDIDSTA) &
996 (S3C2410_SDIDSTA_TXDATAON | S3C2410_SDIDSTA_RXDATAON)) {
999 "mci_setup_data() transfer stillin progress.\n");
1001 writel(S3C2410_SDIDCON_STOP, host->base + S3C2410_SDIDCON);
1004 if ((stoptries--) == 0) {
1005 dbg_dumpregs(host, "DRF");
1010 dcon = data->blocks & S3C2410_SDIDCON_BLKNUM_MASK;
1012 if (s3cmci_host_usedma(host))
1013 dcon |= S3C2410_SDIDCON_DMAEN;
1015 if (host->bus_width == MMC_BUS_WIDTH_4)
1016 dcon |= S3C2410_SDIDCON_WIDEBUS;
1018 dcon |= S3C2410_SDIDCON_BLOCKMODE;
1020 if (data->flags & MMC_DATA_WRITE) {
1021 dcon |= S3C2410_SDIDCON_TXAFTERRESP;
1022 dcon |= S3C2410_SDIDCON_XFER_TXSTART;
1025 if (data->flags & MMC_DATA_READ) {
1026 dcon |= S3C2410_SDIDCON_RXAFTERCMD;
1027 dcon |= S3C2410_SDIDCON_XFER_RXSTART;
1031 dcon |= S3C2440_SDIDCON_DS_WORD;
1032 dcon |= S3C2440_SDIDCON_DATSTART;
1035 writel(dcon, host->base + S3C2410_SDIDCON);
1037 /* write BSIZE register */
1039 writel(data->blksz, host->base + S3C2410_SDIBSIZE);
1041 /* add to IMASK register */
1042 imsk = S3C2410_SDIIMSK_FIFOFAIL | S3C2410_SDIIMSK_DATACRC |
1043 S3C2410_SDIIMSK_DATATIMEOUT | S3C2410_SDIIMSK_DATAFINISH;
1045 enable_imask(host, imsk);
1047 /* write TIMER register */
1050 writel(0x007FFFFF, host->base + S3C2410_SDITIMER);
1052 writel(0x0000FFFF, host->base + S3C2410_SDITIMER);
1054 /* FIX: set slow clock to prevent timeouts on read */
1055 if (data->flags & MMC_DATA_READ)
1056 writel(0xFF, host->base + S3C2410_SDIPRE);
1062 #define BOTH_DIR (MMC_DATA_WRITE | MMC_DATA_READ)
1064 static int s3cmci_prepare_pio(struct s3cmci_host *host, struct mmc_data *data)
1066 int rw = (data->flags & MMC_DATA_WRITE) ? 1 : 0;
1068 BUG_ON((data->flags & BOTH_DIR) == BOTH_DIR);
1070 host->pio_sgptr = 0;
1071 host->pio_bytes = 0;
1072 host->pio_count = 0;
1073 host->pio_active = rw ? XFER_WRITE : XFER_READ;
1077 enable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
1079 enable_imask(host, S3C2410_SDIIMSK_RXFIFOHALF
1080 | S3C2410_SDIIMSK_RXFIFOLAST);
1086 static int s3cmci_prepare_dma(struct s3cmci_host *host, struct mmc_data *data)
1088 int rw = data->flags & MMC_DATA_WRITE;
1089 struct dma_async_tx_descriptor *desc;
1090 struct dma_slave_config conf = {
1091 .src_addr = host->mem->start + host->sdidata,
1092 .dst_addr = host->mem->start + host->sdidata,
1093 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
1094 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
1097 BUG_ON((data->flags & BOTH_DIR) == BOTH_DIR);
1099 /* Restore prescaler value */
1100 writel(host->prescaler, host->base + S3C2410_SDIPRE);
1103 conf.direction = DMA_DEV_TO_MEM;
1105 conf.direction = DMA_MEM_TO_DEV;
1107 dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1108 rw ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1110 dmaengine_slave_config(host->dma, &conf);
1111 desc = dmaengine_prep_slave_sg(host->dma, data->sg, data->sg_len,
1113 DMA_CTRL_ACK | DMA_PREP_INTERRUPT);
1116 desc->callback = s3cmci_dma_done_callback;
1117 desc->callback_param = host;
1118 dmaengine_submit(desc);
1119 dma_async_issue_pending(host->dma);
1124 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1125 rw ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1129 static void s3cmci_send_request(struct mmc_host *mmc)
1131 struct s3cmci_host *host = mmc_priv(mmc);
1132 struct mmc_request *mrq = host->mrq;
1133 struct mmc_command *cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd;
1136 prepare_dbgmsg(host, cmd, host->cmd_is_stop);
1138 /* Clear command, data and fifo status registers
1139 Fifo clear only necessary on 2440, but doesn't hurt on 2410
1141 writel(0xFFFFFFFF, host->base + S3C2410_SDICMDSTAT);
1142 writel(0xFFFFFFFF, host->base + S3C2410_SDIDSTA);
1143 writel(0xFFFFFFFF, host->base + S3C2410_SDIFSTA);
1146 int res = s3cmci_setup_data(host, cmd->data);
1151 dbg(host, dbg_err, "setup data error %d\n", res);
1153 cmd->data->error = res;
1155 mmc_request_done(mmc, mrq);
1159 if (s3cmci_host_usedma(host))
1160 res = s3cmci_prepare_dma(host, cmd->data);
1162 res = s3cmci_prepare_pio(host, cmd->data);
1165 dbg(host, dbg_err, "data prepare error %d\n", res);
1167 cmd->data->error = res;
1169 mmc_request_done(mmc, mrq);
1175 s3cmci_send_command(host, cmd);
1177 /* Enable Interrupt */
1178 s3cmci_enable_irq(host, true);
1181 static int s3cmci_card_present(struct mmc_host *mmc)
1183 struct s3cmci_host *host = mmc_priv(mmc);
1184 struct s3c24xx_mci_pdata *pdata = host->pdata;
1187 if (pdata->no_detect)
1190 ret = gpio_get_value(pdata->gpio_detect) ? 0 : 1;
1191 return ret ^ pdata->detect_invert;
1194 static void s3cmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1196 struct s3cmci_host *host = mmc_priv(mmc);
1198 host->status = "mmc request";
1199 host->cmd_is_stop = 0;
1202 if (s3cmci_card_present(mmc) == 0) {
1203 dbg(host, dbg_err, "%s: no medium present\n", __func__);
1204 host->mrq->cmd->error = -ENOMEDIUM;
1205 mmc_request_done(mmc, mrq);
1207 s3cmci_send_request(mmc);
1210 static void s3cmci_set_clk(struct s3cmci_host *host, struct mmc_ios *ios)
1215 for (mci_psc = 0; mci_psc < 255; mci_psc++) {
1216 host->real_rate = host->clk_rate / (host->clk_div*(mci_psc+1));
1218 if (host->real_rate <= ios->clock)
1225 host->prescaler = mci_psc;
1226 writel(host->prescaler, host->base + S3C2410_SDIPRE);
1228 /* If requested clock is 0, real_rate will be 0, too */
1229 if (ios->clock == 0)
1230 host->real_rate = 0;
1233 static void s3cmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1235 struct s3cmci_host *host = mmc_priv(mmc);
1238 /* Set the power state */
1240 mci_con = readl(host->base + S3C2410_SDICON);
1242 switch (ios->power_mode) {
1245 /* Configure GPE5...GPE10 pins in SD mode */
1246 s3c_gpio_cfgall_range(S3C2410_GPE(5), 6, S3C_GPIO_SFN(2),
1247 S3C_GPIO_PULL_NONE);
1249 if (host->pdata->set_power)
1250 host->pdata->set_power(ios->power_mode, ios->vdd);
1253 mci_con |= S3C2410_SDICON_FIFORESET;
1259 gpio_direction_output(S3C2410_GPE(5), 0);
1262 mci_con |= S3C2440_SDICON_SDRESET;
1264 if (host->pdata->set_power)
1265 host->pdata->set_power(ios->power_mode, ios->vdd);
1270 s3cmci_set_clk(host, ios);
1272 /* Set CLOCK_ENABLE */
1274 mci_con |= S3C2410_SDICON_CLOCKTYPE;
1276 mci_con &= ~S3C2410_SDICON_CLOCKTYPE;
1278 writel(mci_con, host->base + S3C2410_SDICON);
1280 if ((ios->power_mode == MMC_POWER_ON) ||
1281 (ios->power_mode == MMC_POWER_UP)) {
1282 dbg(host, dbg_conf, "running at %lukHz (requested: %ukHz).\n",
1283 host->real_rate/1000, ios->clock/1000);
1285 dbg(host, dbg_conf, "powered down.\n");
1288 host->bus_width = ios->bus_width;
1291 static void s3cmci_reset(struct s3cmci_host *host)
1293 u32 con = readl(host->base + S3C2410_SDICON);
1295 con |= S3C2440_SDICON_SDRESET;
1296 writel(con, host->base + S3C2410_SDICON);
1299 static int s3cmci_get_ro(struct mmc_host *mmc)
1301 struct s3cmci_host *host = mmc_priv(mmc);
1302 struct s3c24xx_mci_pdata *pdata = host->pdata;
1305 if (pdata->no_wprotect)
1308 ret = gpio_get_value(pdata->gpio_wprotect) ? 1 : 0;
1309 ret ^= pdata->wprotect_invert;
1314 static void s3cmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1316 struct s3cmci_host *host = mmc_priv(mmc);
1317 unsigned long flags;
1320 local_irq_save(flags);
1322 con = readl(host->base + S3C2410_SDICON);
1323 host->sdio_irqen = enable;
1325 if (enable == host->sdio_irqen)
1329 con |= S3C2410_SDICON_SDIOIRQ;
1330 enable_imask(host, S3C2410_SDIIMSK_SDIOIRQ);
1332 if (!host->irq_state && !host->irq_disabled) {
1333 host->irq_state = true;
1334 enable_irq(host->irq);
1337 disable_imask(host, S3C2410_SDIIMSK_SDIOIRQ);
1338 con &= ~S3C2410_SDICON_SDIOIRQ;
1340 if (!host->irq_enabled && host->irq_state) {
1341 disable_irq_nosync(host->irq);
1342 host->irq_state = false;
1346 writel(con, host->base + S3C2410_SDICON);
1349 local_irq_restore(flags);
1351 s3cmci_check_sdio_irq(host);
1354 static struct mmc_host_ops s3cmci_ops = {
1355 .request = s3cmci_request,
1356 .set_ios = s3cmci_set_ios,
1357 .get_ro = s3cmci_get_ro,
1358 .get_cd = s3cmci_card_present,
1359 .enable_sdio_irq = s3cmci_enable_sdio_irq,
1362 static struct s3c24xx_mci_pdata s3cmci_def_pdata = {
1363 /* This is currently here to avoid a number of if (host->pdata)
1364 * checks. Any zero fields to ensure reasonable defaults are picked. */
1369 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ
1371 static int s3cmci_cpufreq_transition(struct notifier_block *nb,
1372 unsigned long val, void *data)
1374 struct s3cmci_host *host;
1375 struct mmc_host *mmc;
1376 unsigned long newclk;
1377 unsigned long flags;
1379 host = container_of(nb, struct s3cmci_host, freq_transition);
1380 newclk = clk_get_rate(host->clk);
1383 if ((val == CPUFREQ_PRECHANGE && newclk > host->clk_rate) ||
1384 (val == CPUFREQ_POSTCHANGE && newclk < host->clk_rate)) {
1385 spin_lock_irqsave(&mmc->lock, flags);
1387 host->clk_rate = newclk;
1389 if (mmc->ios.power_mode != MMC_POWER_OFF &&
1390 mmc->ios.clock != 0)
1391 s3cmci_set_clk(host, &mmc->ios);
1393 spin_unlock_irqrestore(&mmc->lock, flags);
1399 static inline int s3cmci_cpufreq_register(struct s3cmci_host *host)
1401 host->freq_transition.notifier_call = s3cmci_cpufreq_transition;
1403 return cpufreq_register_notifier(&host->freq_transition,
1404 CPUFREQ_TRANSITION_NOTIFIER);
1407 static inline void s3cmci_cpufreq_deregister(struct s3cmci_host *host)
1409 cpufreq_unregister_notifier(&host->freq_transition,
1410 CPUFREQ_TRANSITION_NOTIFIER);
1414 static inline int s3cmci_cpufreq_register(struct s3cmci_host *host)
1419 static inline void s3cmci_cpufreq_deregister(struct s3cmci_host *host)
1425 #ifdef CONFIG_DEBUG_FS
1427 static int s3cmci_state_show(struct seq_file *seq, void *v)
1429 struct s3cmci_host *host = seq->private;
1431 seq_printf(seq, "Register base = 0x%08x\n", (u32)host->base);
1432 seq_printf(seq, "Clock rate = %ld\n", host->clk_rate);
1433 seq_printf(seq, "Prescale = %d\n", host->prescaler);
1434 seq_printf(seq, "is2440 = %d\n", host->is2440);
1435 seq_printf(seq, "IRQ = %d\n", host->irq);
1436 seq_printf(seq, "IRQ enabled = %d\n", host->irq_enabled);
1437 seq_printf(seq, "IRQ disabled = %d\n", host->irq_disabled);
1438 seq_printf(seq, "IRQ state = %d\n", host->irq_state);
1439 seq_printf(seq, "CD IRQ = %d\n", host->irq_cd);
1440 seq_printf(seq, "Do DMA = %d\n", s3cmci_host_usedma(host));
1441 seq_printf(seq, "SDIIMSK at %d\n", host->sdiimsk);
1442 seq_printf(seq, "SDIDATA at %d\n", host->sdidata);
1447 static int s3cmci_state_open(struct inode *inode, struct file *file)
1449 return single_open(file, s3cmci_state_show, inode->i_private);
1452 static const struct file_operations s3cmci_fops_state = {
1453 .owner = THIS_MODULE,
1454 .open = s3cmci_state_open,
1456 .llseek = seq_lseek,
1457 .release = single_release,
1460 #define DBG_REG(_r) { .addr = S3C2410_SDI##_r, .name = #_r }
1463 unsigned short addr;
1464 unsigned char *name;
1484 static int s3cmci_regs_show(struct seq_file *seq, void *v)
1486 struct s3cmci_host *host = seq->private;
1487 struct s3cmci_reg *rptr = debug_regs;
1489 for (; rptr->name; rptr++)
1490 seq_printf(seq, "SDI%s\t=0x%08x\n", rptr->name,
1491 readl(host->base + rptr->addr));
1493 seq_printf(seq, "SDIIMSK\t=0x%08x\n", readl(host->base + host->sdiimsk));
1498 static int s3cmci_regs_open(struct inode *inode, struct file *file)
1500 return single_open(file, s3cmci_regs_show, inode->i_private);
1503 static const struct file_operations s3cmci_fops_regs = {
1504 .owner = THIS_MODULE,
1505 .open = s3cmci_regs_open,
1507 .llseek = seq_lseek,
1508 .release = single_release,
1511 static void s3cmci_debugfs_attach(struct s3cmci_host *host)
1513 struct device *dev = &host->pdev->dev;
1515 host->debug_root = debugfs_create_dir(dev_name(dev), NULL);
1516 if (IS_ERR(host->debug_root)) {
1517 dev_err(dev, "failed to create debugfs root\n");
1521 host->debug_state = debugfs_create_file("state", 0444,
1522 host->debug_root, host,
1523 &s3cmci_fops_state);
1525 if (IS_ERR(host->debug_state))
1526 dev_err(dev, "failed to create debug state file\n");
1528 host->debug_regs = debugfs_create_file("regs", 0444,
1529 host->debug_root, host,
1532 if (IS_ERR(host->debug_regs))
1533 dev_err(dev, "failed to create debug regs file\n");
1536 static void s3cmci_debugfs_remove(struct s3cmci_host *host)
1538 debugfs_remove(host->debug_regs);
1539 debugfs_remove(host->debug_state);
1540 debugfs_remove(host->debug_root);
1544 static inline void s3cmci_debugfs_attach(struct s3cmci_host *host) { }
1545 static inline void s3cmci_debugfs_remove(struct s3cmci_host *host) { }
1547 #endif /* CONFIG_DEBUG_FS */
1549 static int s3cmci_probe(struct platform_device *pdev)
1551 struct s3cmci_host *host;
1552 struct mmc_host *mmc;
1557 is2440 = platform_get_device_id(pdev)->driver_data;
1559 mmc = mmc_alloc_host(sizeof(struct s3cmci_host), &pdev->dev);
1565 for (i = S3C2410_GPE(5); i <= S3C2410_GPE(10); i++) {
1566 ret = gpio_request(i, dev_name(&pdev->dev));
1568 dev_err(&pdev->dev, "failed to get gpio %d\n", i);
1570 for (i--; i >= S3C2410_GPE(5); i--)
1573 goto probe_free_host;
1577 host = mmc_priv(mmc);
1580 host->is2440 = is2440;
1582 host->pdata = pdev->dev.platform_data;
1584 pdev->dev.platform_data = &s3cmci_def_pdata;
1585 host->pdata = &s3cmci_def_pdata;
1588 spin_lock_init(&host->complete_lock);
1589 tasklet_init(&host->pio_tasklet, pio_tasklet, (unsigned long) host);
1592 host->sdiimsk = S3C2440_SDIIMSK;
1593 host->sdidata = S3C2440_SDIDATA;
1596 host->sdiimsk = S3C2410_SDIIMSK;
1597 host->sdidata = S3C2410_SDIDATA;
1601 host->complete_what = COMPLETION_NONE;
1602 host->pio_active = XFER_NONE;
1604 host->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1607 "failed to get io memory region resource.\n");
1610 goto probe_free_gpio;
1613 host->mem = request_mem_region(host->mem->start,
1614 resource_size(host->mem), pdev->name);
1617 dev_err(&pdev->dev, "failed to request io memory region.\n");
1619 goto probe_free_gpio;
1622 host->base = ioremap(host->mem->start, resource_size(host->mem));
1624 dev_err(&pdev->dev, "failed to ioremap() io memory region.\n");
1626 goto probe_free_mem_region;
1629 host->irq = platform_get_irq(pdev, 0);
1630 if (host->irq == 0) {
1631 dev_err(&pdev->dev, "failed to get interrupt resource.\n");
1636 if (request_irq(host->irq, s3cmci_irq, 0, DRIVER_NAME, host)) {
1637 dev_err(&pdev->dev, "failed to request mci interrupt.\n");
1642 /* We get spurious interrupts even when we have set the IMSK
1643 * register to ignore everything, so use disable_irq() to make
1644 * ensure we don't lock the system with un-serviceable requests. */
1646 disable_irq(host->irq);
1647 host->irq_state = false;
1649 if (!host->pdata->no_detect) {
1650 ret = gpio_request(host->pdata->gpio_detect, "s3cmci detect");
1652 dev_err(&pdev->dev, "failed to get detect gpio\n");
1653 goto probe_free_irq;
1656 host->irq_cd = gpio_to_irq(host->pdata->gpio_detect);
1658 if (host->irq_cd >= 0) {
1659 if (request_irq(host->irq_cd, s3cmci_irq_cd,
1660 IRQF_TRIGGER_RISING |
1661 IRQF_TRIGGER_FALLING,
1662 DRIVER_NAME, host)) {
1664 "can't get card detect irq.\n");
1666 goto probe_free_gpio_cd;
1669 dev_warn(&pdev->dev,
1670 "host detect has no irq available\n");
1671 gpio_direction_input(host->pdata->gpio_detect);
1676 if (!host->pdata->no_wprotect) {
1677 ret = gpio_request(host->pdata->gpio_wprotect, "s3cmci wp");
1679 dev_err(&pdev->dev, "failed to get writeprotect\n");
1680 goto probe_free_irq_cd;
1683 gpio_direction_input(host->pdata->gpio_wprotect);
1686 /* depending on the dma state, get a dma channel to use. */
1688 if (s3cmci_host_usedma(host)) {
1689 dma_cap_mask_t mask;
1692 dma_cap_set(DMA_SLAVE, mask);
1694 host->dma = dma_request_slave_channel_compat(mask,
1695 s3c24xx_dma_filter, (void *)DMACH_SDI, &pdev->dev, "rx-tx");
1697 dev_err(&pdev->dev, "cannot get DMA channel.\n");
1699 goto probe_free_gpio_wp;
1703 host->clk = clk_get(&pdev->dev, "sdi");
1704 if (IS_ERR(host->clk)) {
1705 dev_err(&pdev->dev, "failed to find clock source.\n");
1706 ret = PTR_ERR(host->clk);
1708 goto probe_free_dma;
1711 ret = clk_prepare_enable(host->clk);
1713 dev_err(&pdev->dev, "failed to enable clock source.\n");
1717 host->clk_rate = clk_get_rate(host->clk);
1719 mmc->ops = &s3cmci_ops;
1720 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1721 #ifdef CONFIG_MMC_S3C_HW_SDIO_IRQ
1722 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
1724 mmc->caps = MMC_CAP_4_BIT_DATA;
1726 mmc->f_min = host->clk_rate / (host->clk_div * 256);
1727 mmc->f_max = host->clk_rate / host->clk_div;
1729 if (host->pdata->ocr_avail)
1730 mmc->ocr_avail = host->pdata->ocr_avail;
1732 mmc->max_blk_count = 4095;
1733 mmc->max_blk_size = 4095;
1734 mmc->max_req_size = 4095 * 512;
1735 mmc->max_seg_size = mmc->max_req_size;
1737 mmc->max_segs = 128;
1739 dbg(host, dbg_debug,
1740 "probe: mode:%s mapped mci_base:%p irq:%u irq_cd:%u dma:%p.\n",
1741 (host->is2440?"2440":""),
1742 host->base, host->irq, host->irq_cd, host->dma);
1744 ret = s3cmci_cpufreq_register(host);
1746 dev_err(&pdev->dev, "failed to register cpufreq\n");
1750 ret = mmc_add_host(mmc);
1752 dev_err(&pdev->dev, "failed to add mmc host.\n");
1756 s3cmci_debugfs_attach(host);
1758 platform_set_drvdata(pdev, mmc);
1759 dev_info(&pdev->dev, "%s - using %s, %s SDIO IRQ\n", mmc_hostname(mmc),
1760 s3cmci_host_usedma(host) ? "dma" : "pio",
1761 mmc->caps & MMC_CAP_SDIO_IRQ ? "hw" : "sw");
1766 s3cmci_cpufreq_deregister(host);
1769 clk_disable_unprepare(host->clk);
1775 if (s3cmci_host_usedma(host))
1776 dma_release_channel(host->dma);
1779 if (!host->pdata->no_wprotect)
1780 gpio_free(host->pdata->gpio_wprotect);
1783 if (!host->pdata->no_detect)
1784 gpio_free(host->pdata->gpio_detect);
1787 if (host->irq_cd >= 0)
1788 free_irq(host->irq_cd, host);
1791 free_irq(host->irq, host);
1794 iounmap(host->base);
1796 probe_free_mem_region:
1797 release_mem_region(host->mem->start, resource_size(host->mem));
1800 for (i = S3C2410_GPE(5); i <= S3C2410_GPE(10); i++)
1810 static void s3cmci_shutdown(struct platform_device *pdev)
1812 struct mmc_host *mmc = platform_get_drvdata(pdev);
1813 struct s3cmci_host *host = mmc_priv(mmc);
1815 if (host->irq_cd >= 0)
1816 free_irq(host->irq_cd, host);
1818 s3cmci_debugfs_remove(host);
1819 s3cmci_cpufreq_deregister(host);
1820 mmc_remove_host(mmc);
1821 clk_disable_unprepare(host->clk);
1824 static int s3cmci_remove(struct platform_device *pdev)
1826 struct mmc_host *mmc = platform_get_drvdata(pdev);
1827 struct s3cmci_host *host = mmc_priv(mmc);
1828 struct s3c24xx_mci_pdata *pd = host->pdata;
1831 s3cmci_shutdown(pdev);
1835 tasklet_disable(&host->pio_tasklet);
1837 if (s3cmci_host_usedma(host))
1838 dma_release_channel(host->dma);
1840 free_irq(host->irq, host);
1842 if (!pd->no_wprotect)
1843 gpio_free(pd->gpio_wprotect);
1846 gpio_free(pd->gpio_detect);
1848 for (i = S3C2410_GPE(5); i <= S3C2410_GPE(10); i++)
1852 iounmap(host->base);
1853 release_mem_region(host->mem->start, resource_size(host->mem));
1859 static const struct platform_device_id s3cmci_driver_ids[] = {
1861 .name = "s3c2410-sdi",
1864 .name = "s3c2412-sdi",
1867 .name = "s3c2440-sdi",
1873 MODULE_DEVICE_TABLE(platform, s3cmci_driver_ids);
1875 static struct platform_driver s3cmci_driver = {
1879 .id_table = s3cmci_driver_ids,
1880 .probe = s3cmci_probe,
1881 .remove = s3cmci_remove,
1882 .shutdown = s3cmci_shutdown,
1885 module_platform_driver(s3cmci_driver);
1887 MODULE_DESCRIPTION("Samsung S3C MMC/SD Card Interface driver");
1888 MODULE_LICENSE("GPL v2");
1889 MODULE_AUTHOR("Thomas Kleffel <tk@maintech.de>, Ben Dooks <ben-linux@fluff.org>");