drivers/mmc/host/rtsx_pci_sdmmc.c

   1 /* Realtek PCI-Express SD/MMC Card Interface driver
   2  *
   3  * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2, or (at your option) any
   8  * later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program; if not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * Author:
  19  *   Wei WANG <wei_wang@realsil.com.cn>
  20  */
  21
  22 #include <linux/module.h>
  23 #include <linux/slab.h>
  24 #include <linux/highmem.h>
  25 #include <linux/delay.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/workqueue.h>
  28 #include <linux/mmc/host.h>
  29 #include <linux/mmc/mmc.h>
  30 #include <linux/mmc/sd.h>
  31 #include <linux/mmc/sdio.h>
  32 #include <linux/mmc/card.h>
  33 #include <linux/mfd/rtsx_pci.h>
  34 #include <asm/unaligned.h>
  35
  36 struct realtek_pci_sdmmc {
  37         struct platform_device  *pdev;
  38         struct rtsx_pcr         *pcr;
  39         struct mmc_host         *mmc;
  40         struct mmc_request      *mrq;
  41 #define SDMMC_WORKQ_NAME        "rtsx_pci_sdmmc_workq"
  42
  43         struct work_struct      work;
  44         struct mutex            host_mutex;
  45
  46         u8                      ssc_depth;
  47         unsigned int            clock;
  48         bool                    vpclk;
  49         bool                    double_clk;
  50         bool                    eject;
  51         bool                    initial_mode;
  52         int                     power_state;
  53 #define SDMMC_POWER_ON          1
  54 #define SDMMC_POWER_OFF         0
  55
  56         int                     sg_count;
  57         s32                     cookie;
  58         int                     cookie_sg_count;
  59         bool                    using_cookie;
  60 };
  61
  62 static inline struct device *sdmmc_dev(struct realtek_pci_sdmmc *host)
  63 {
  64         return &(host->pdev->dev);
  65 }
  66
  67 static inline void sd_clear_error(struct realtek_pci_sdmmc *host)
  68 {
  69         rtsx_pci_write_register(host->pcr, CARD_STOP,
  70                         SD_STOP | SD_CLR_ERR, SD_STOP | SD_CLR_ERR);
  71 }
  72
  73 #ifdef DEBUG
  74 static void dump_reg_range(struct realtek_pci_sdmmc *host, u16 start, u16 end)
  75 {
  76         u16 len = end - start + 1;
  77         int i;
  78         u8 data[8];
  79
  80         for (i = 0; i < len; i += 8) {
  81                 int j;
  82                 int n = min(8, len - i);
  83
  84                 memset(&data, 0, sizeof(data));
  85                 for (j = 0; j < n; j++)
  86                         rtsx_pci_read_register(host->pcr, start + i + j,
  87                                 data + j);
  88                 dev_dbg(sdmmc_dev(host), "0x%04X(%d): %8ph\n",
  89                         start + i, n, data);
  90         }
  91 }
  92
  93 static void sd_print_debug_regs(struct realtek_pci_sdmmc *host)
  94 {
  95         dump_reg_range(host, 0xFDA0, 0xFDB3);
  96         dump_reg_range(host, 0xFD52, 0xFD69);
  97 }
  98 #else
  99 #define sd_print_debug_regs(host)
 100 #endif /* DEBUG */
 101
 102 static inline int sd_get_cd_int(struct realtek_pci_sdmmc *host)
 103 {
 104         return rtsx_pci_readl(host->pcr, RTSX_BIPR) & SD_EXIST;
 105 }
 106
 107 static void sd_cmd_set_sd_cmd(struct rtsx_pcr *pcr, struct mmc_command *cmd)
 108 {
 109         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0, 0xFF,
 110                 SD_CMD_START | cmd->opcode);
 111         rtsx_pci_write_be32(pcr, SD_CMD1, cmd->arg);
 112 }
 113
 114 static void sd_cmd_set_data_len(struct rtsx_pcr *pcr, u16 blocks, u16 blksz)
 115 {
 116         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, blocks);
 117         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, blocks >> 8);
 118         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, blksz);
 119         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, blksz >> 8);
 120 }
 121
 122 static int sd_response_type(struct mmc_command *cmd)
 123 {
 124         switch (mmc_resp_type(cmd)) {
 125         case MMC_RSP_NONE:
 126                 return SD_RSP_TYPE_R0;
 127         case MMC_RSP_R1:
 128                 return SD_RSP_TYPE_R1;
 129         case MMC_RSP_R1_NO_CRC:
 130                 return SD_RSP_TYPE_R1 | SD_NO_CHECK_CRC7;
 131         case MMC_RSP_R1B:
 132                 return SD_RSP_TYPE_R1b;
 133         case MMC_RSP_R2:
 134                 return SD_RSP_TYPE_R2;
 135         case MMC_RSP_R3:
 136                 return SD_RSP_TYPE_R3;
 137         default:
 138                 return -EINVAL;
 139         }
 140 }
 141
 142 static int sd_status_index(int resp_type)
 143 {
 144         if (resp_type == SD_RSP_TYPE_R0)
 145                 return 0;
 146         else if (resp_type == SD_RSP_TYPE_R2)
 147                 return 16;
 148
 149         return 5;
 150 }
 151 /*
 152  * sd_pre_dma_transfer - do dma_map_sg() or using cookie
 153  *
 154  * @pre: if called in pre_req()
 155  * return:
 156  *      0 - do dma_map_sg()
 157  *      1 - using cookie
 158  */
 159 static int sd_pre_dma_transfer(struct realtek_pci_sdmmc *host,
 160                 struct mmc_data *data, bool pre)
 161 {
 162         struct rtsx_pcr *pcr = host->pcr;
 163         int read = data->flags & MMC_DATA_READ;
 164         int count = 0;
 165         int using_cookie = 0;
 166
 167         if (!pre && data->host_cookie && data->host_cookie != host->cookie) {
 168                 dev_err(sdmmc_dev(host),
 169                         "error: data->host_cookie = %d, host->cookie = %d\n",
 170                         data->host_cookie, host->cookie);
 171                 data->host_cookie = 0;
 172         }
 173
 174         if (pre || data->host_cookie != host->cookie) {
 175                 count = rtsx_pci_dma_map_sg(pcr, data->sg, data->sg_len, read);
 176         } else {
 177                 count = host->cookie_sg_count;
 178                 using_cookie = 1;
 179         }
 180
 181         if (pre) {
 182                 host->cookie_sg_count = count;
 183                 if (++host->cookie < 0)
 184                         host->cookie = 1;
 185                 data->host_cookie = host->cookie;
 186         } else {
 187                 host->sg_count = count;
 188         }
 189
 190         return using_cookie;
 191 }
 192
 193 static void sdmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
 194                 bool is_first_req)
 195 {
 196         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
 197         struct mmc_data *data = mrq->data;
 198
 199         if (data->host_cookie) {
 200                 dev_err(sdmmc_dev(host),
 201                         "error: reset data->host_cookie = %d\n",
 202                         data->host_cookie);
 203                 data->host_cookie = 0;
 204         }
 205
 206         sd_pre_dma_transfer(host, data, true);
 207         dev_dbg(sdmmc_dev(host), "pre dma sg: %d\n", host->cookie_sg_count);
 208 }
 209
 210 static void sdmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
 211                 int err)
 212 {
 213         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
 214         struct rtsx_pcr *pcr = host->pcr;
 215         struct mmc_data *data = mrq->data;
 216         int read = data->flags & MMC_DATA_READ;
 217
 218         rtsx_pci_dma_unmap_sg(pcr, data->sg, data->sg_len, read);
 219         data->host_cookie = 0;
 220 }
 221
 222 static void sd_send_cmd_get_rsp(struct realtek_pci_sdmmc *host,
 223                 struct mmc_command *cmd)
 224 {
 225         struct rtsx_pcr *pcr = host->pcr;
 226         u8 cmd_idx = (u8)cmd->opcode;
 227         u32 arg = cmd->arg;
 228         int err = 0;
 229         int timeout = 100;
 230         int i;
 231         u8 *ptr;
 232         int rsp_type;
 233         int stat_idx;
 234         bool clock_toggled = false;
 235
 236         dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
 237                         __func__, cmd_idx, arg);
 238
 239         rsp_type = sd_response_type(cmd);
 240         if (rsp_type < 0)
 241                 goto out;
 242
 243         stat_idx = sd_status_index(rsp_type);
 244
 245         if (rsp_type == SD_RSP_TYPE_R1b)
 246                 timeout = cmd->busy_timeout ? cmd->busy_timeout : 3000;
 247
 248         if (cmd->opcode == SD_SWITCH_VOLTAGE) {
 249                 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
 250                                 0xFF, SD_CLK_TOGGLE_EN);
 251                 if (err < 0)
 252                         goto out;
 253
 254                 clock_toggled = true;
 255         }
 256
 257         rtsx_pci_init_cmd(pcr);
 258         sd_cmd_set_sd_cmd(pcr, cmd);
 259         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, rsp_type);
 260         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
 261                         0x01, PINGPONG_BUFFER);
 262         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
 263                         0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START);
 264         rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
 265                      SD_TRANSFER_END | SD_STAT_IDLE,
 266                      SD_TRANSFER_END | SD_STAT_IDLE);
 267
 268         if (rsp_type == SD_RSP_TYPE_R2) {
 269                 /* Read data from ping-pong buffer */
 270                 for (i = PPBUF_BASE2; i < PPBUF_BASE2 + 16; i++)
 271                         rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
 272         } else if (rsp_type != SD_RSP_TYPE_R0) {
 273                 /* Read data from SD_CMDx registers */
 274                 for (i = SD_CMD0; i <= SD_CMD4; i++)
 275                         rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
 276         }
 277
 278         rtsx_pci_add_cmd(pcr, READ_REG_CMD, SD_STAT1, 0, 0);
 279
 280         err = rtsx_pci_send_cmd(pcr, timeout);
 281         if (err < 0) {
 282                 sd_print_debug_regs(host);
 283                 sd_clear_error(host);
 284                 dev_dbg(sdmmc_dev(host),
 285                         "rtsx_pci_send_cmd error (err = %d)\n", err);
 286                 goto out;
 287         }
 288
 289         if (rsp_type == SD_RSP_TYPE_R0) {
 290                 err = 0;
 291                 goto out;
 292         }
 293
 294         /* Eliminate returned value of CHECK_REG_CMD */
 295         ptr = rtsx_pci_get_cmd_data(pcr) + 1;
 296
 297         /* Check (Start,Transmission) bit of Response */
 298         if ((ptr[0] & 0xC0) != 0) {
 299                 err = -EILSEQ;
 300                 dev_dbg(sdmmc_dev(host), "Invalid response bit\n");
 301                 goto out;
 302         }
 303
 304         /* Check CRC7 */
 305         if (!(rsp_type & SD_NO_CHECK_CRC7)) {
 306                 if (ptr[stat_idx] & SD_CRC7_ERR) {
 307                         err = -EILSEQ;
 308                         dev_dbg(sdmmc_dev(host), "CRC7 error\n");
 309                         goto out;
 310                 }
 311         }
 312
 313         if (rsp_type == SD_RSP_TYPE_R2) {
 314                 /*
 315                  * The controller offloads the last byte {CRC-7, end bit 1'b1}
 316                  * of response type R2. Assign dummy CRC, 0, and end bit to the
 317                  * byte(ptr[16], goes into the LSB of resp[3] later).
 318                  */
 319                 ptr[16] = 1;
 320
 321                 for (i = 0; i < 4; i++) {
 322                         cmd->resp[i] = get_unaligned_be32(ptr + 1 + i * 4);
 323                         dev_dbg(sdmmc_dev(host), "cmd->resp[%d] = 0x%08x\n",
 324                                         i, cmd->resp[i]);
 325                 }
 326         } else {
 327                 cmd->resp[0] = get_unaligned_be32(ptr + 1);
 328                 dev_dbg(sdmmc_dev(host), "cmd->resp[0] = 0x%08x\n",
 329                                 cmd->resp[0]);
 330         }
 331
 332 out:
 333         cmd->error = err;
 334
 335         if (err && clock_toggled)
 336                 rtsx_pci_write_register(pcr, SD_BUS_STAT,
 337                                 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
 338 }
 339
 340 static int sd_read_data(struct realtek_pci_sdmmc *host, struct mmc_command *cmd,
 341         u16 byte_cnt, u8 *buf, int buf_len, int timeout)
 342 {
 343         struct rtsx_pcr *pcr = host->pcr;
 344         int err;
 345         u8 trans_mode;
 346
 347         dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
 348                 __func__, cmd->opcode, cmd->arg);
 349
 350         if (!buf)
 351                 buf_len = 0;
 352
 353         if (cmd->opcode == MMC_SEND_TUNING_BLOCK)
 354                 trans_mode = SD_TM_AUTO_TUNING;
 355         else
 356                 trans_mode = SD_TM_NORMAL_READ;
 357
 358         rtsx_pci_init_cmd(pcr);
 359         sd_cmd_set_sd_cmd(pcr, cmd);
 360         sd_cmd_set_data_len(pcr, 1, byte_cnt);
 361         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
 362                         SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
 363                         SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6);
 364         if (trans_mode != SD_TM_AUTO_TUNING)
 365                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
 366                                 CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
 367
 368         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
 369                         0xFF, trans_mode | SD_TRANSFER_START);
 370         rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
 371                         SD_TRANSFER_END, SD_TRANSFER_END);
 372
 373         err = rtsx_pci_send_cmd(pcr, timeout);
 374         if (err < 0) {
 375                 sd_print_debug_regs(host);
 376                 dev_dbg(sdmmc_dev(host),
 377                         "rtsx_pci_send_cmd fail (err = %d)\n", err);
 378                 return err;
 379         }
 380
 381         if (buf && buf_len) {
 382                 err = rtsx_pci_read_ppbuf(pcr, buf, buf_len);
 383                 if (err < 0) {
 384                         dev_dbg(sdmmc_dev(host),
 385                                 "rtsx_pci_read_ppbuf fail (err = %d)\n", err);
 386                         return err;
 387                 }
 388         }
 389
 390         return 0;
 391 }
 392
 393 static int sd_write_data(struct realtek_pci_sdmmc *host,
 394         struct mmc_command *cmd, u16 byte_cnt, u8 *buf, int buf_len,
 395         int timeout)
 396 {
 397         struct rtsx_pcr *pcr = host->pcr;
 398         int err;
 399
 400         dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
 401                 __func__, cmd->opcode, cmd->arg);
 402
 403         if (!buf)
 404                 buf_len = 0;
 405
 406         sd_send_cmd_get_rsp(host, cmd);
 407         if (cmd->error)
 408                 return cmd->error;
 409
 410         if (buf && buf_len) {
 411                 err = rtsx_pci_write_ppbuf(pcr, buf, buf_len);
 412                 if (err < 0) {
 413                         dev_dbg(sdmmc_dev(host),
 414                                 "rtsx_pci_write_ppbuf fail (err = %d)\n", err);
 415                         return err;
 416                 }
 417         }
 418
 419         rtsx_pci_init_cmd(pcr);
 420         sd_cmd_set_data_len(pcr, 1, byte_cnt);
 421         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
 422                 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
 423                 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_0);
 424         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
 425                         SD_TRANSFER_START | SD_TM_AUTO_WRITE_3);
 426         rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
 427                         SD_TRANSFER_END, SD_TRANSFER_END);
 428
 429         err = rtsx_pci_send_cmd(pcr, timeout);
 430         if (err < 0) {
 431                 sd_print_debug_regs(host);
 432                 dev_dbg(sdmmc_dev(host),
 433                         "rtsx_pci_send_cmd fail (err = %d)\n", err);
 434                 return err;
 435         }
 436
 437         return 0;
 438 }
 439
 440 static int sd_read_long_data(struct realtek_pci_sdmmc *host,
 441         struct mmc_request *mrq)
 442 {
 443         struct rtsx_pcr *pcr = host->pcr;
 444         struct mmc_host *mmc = host->mmc;
 445         struct mmc_card *card = mmc->card;
 446         struct mmc_command *cmd = mrq->cmd;
 447         struct mmc_data *data = mrq->data;
 448         int uhs = mmc_card_uhs(card);
 449         u8 cfg2 = 0;
 450         int err;
 451         int resp_type;
 452         size_t data_len = data->blksz * data->blocks;
 453
 454         dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
 455                 __func__, cmd->opcode, cmd->arg);
 456
 457         resp_type = sd_response_type(cmd);
 458         if (resp_type < 0)
 459                 return resp_type;
 460
 461         if (!uhs)
 462                 cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
 463
 464         rtsx_pci_init_cmd(pcr);
 465         sd_cmd_set_sd_cmd(pcr, cmd);
 466         sd_cmd_set_data_len(pcr, data->blocks, data->blksz);
 467         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
 468                         DMA_DONE_INT, DMA_DONE_INT);
 469         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3,
 470                 0xFF, (u8)(data_len >> 24));
 471         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2,
 472                 0xFF, (u8)(data_len >> 16));
 473         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1,
 474                 0xFF, (u8)(data_len >> 8));
 475         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len);
 476         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
 477                 0x03 | DMA_PACK_SIZE_MASK,
 478                 DMA_DIR_FROM_CARD | DMA_EN | DMA_512);
 479         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
 480                         0x01, RING_BUFFER);
 481         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2 | resp_type);
 482         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
 483                         SD_TRANSFER_START | SD_TM_AUTO_READ_2);
 484         rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
 485                         SD_TRANSFER_END, SD_TRANSFER_END);
 486         rtsx_pci_send_cmd_no_wait(pcr);
 487
 488         err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, 1, 10000);
 489         if (err < 0) {
 490                 sd_print_debug_regs(host);
 491                 sd_clear_error(host);
 492                 return err;
 493         }
 494
 495         return 0;
 496 }
 497
 498 static int sd_write_long_data(struct realtek_pci_sdmmc *host,
 499         struct mmc_request *mrq)
 500 {
 501         struct rtsx_pcr *pcr = host->pcr;
 502         struct mmc_host *mmc = host->mmc;
 503         struct mmc_card *card = mmc->card;
 504         struct mmc_command *cmd = mrq->cmd;
 505         struct mmc_data *data = mrq->data;
 506         int uhs = mmc_card_uhs(card);
 507         u8 cfg2;
 508         int err;
 509         size_t data_len = data->blksz * data->blocks;
 510
 511         sd_send_cmd_get_rsp(host, cmd);
 512         if (cmd->error)
 513                 return cmd->error;
 514
 515         dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
 516                 __func__, cmd->opcode, cmd->arg);
 517
 518         cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 |
 519                 SD_NO_WAIT_BUSY_END | SD_NO_CHECK_CRC7 | SD_RSP_LEN_0;
 520
 521         if (!uhs)
 522                 cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
 523
 524         rtsx_pci_init_cmd(pcr);
 525         sd_cmd_set_data_len(pcr, data->blocks, data->blksz);
 526         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
 527                         DMA_DONE_INT, DMA_DONE_INT);
 528         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3,
 529                 0xFF, (u8)(data_len >> 24));
 530         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2,
 531                 0xFF, (u8)(data_len >> 16));
 532         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1,
 533                 0xFF, (u8)(data_len >> 8));
 534         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len);
 535         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
 536                 0x03 | DMA_PACK_SIZE_MASK,
 537                 DMA_DIR_TO_CARD | DMA_EN | DMA_512);
 538         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
 539                         0x01, RING_BUFFER);
 540         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2);
 541         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
 542                         SD_TRANSFER_START | SD_TM_AUTO_WRITE_3);
 543         rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
 544                         SD_TRANSFER_END, SD_TRANSFER_END);
 545         rtsx_pci_send_cmd_no_wait(pcr);
 546         err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, 0, 10000);
 547         if (err < 0) {
 548                 sd_clear_error(host);
 549                 return err;
 550         }
 551
 552         return 0;
 553 }
 554
 555 static inline void sd_enable_initial_mode(struct realtek_pci_sdmmc *host)
 556 {
 557         rtsx_pci_write_register(host->pcr, SD_CFG1,
 558                         SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_128);
 559 }
 560
 561 static inline void sd_disable_initial_mode(struct realtek_pci_sdmmc *host)
 562 {
 563         rtsx_pci_write_register(host->pcr, SD_CFG1,
 564                         SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_0);
 565 }
 566
 567 static int sd_rw_multi(struct realtek_pci_sdmmc *host, struct mmc_request *mrq)
 568 {
 569         struct mmc_data *data = mrq->data;
 570         int err;
 571
 572         if (host->sg_count < 0) {
 573                 data->error = host->sg_count;
 574                 dev_dbg(sdmmc_dev(host), "%s: sg_count = %d is invalid\n",
 575                         __func__, host->sg_count);
 576                 return data->error;
 577         }
 578
 579         if (data->flags & MMC_DATA_READ) {
 580                 if (host->initial_mode)
 581                         sd_disable_initial_mode(host);
 582
 583                 err = sd_read_long_data(host, mrq);
 584
 585                 if (host->initial_mode)
 586                         sd_enable_initial_mode(host);
 587
 588                 return err;
 589         }
 590
 591         return sd_write_long_data(host, mrq);
 592 }
 593
 594 static void sd_normal_rw(struct realtek_pci_sdmmc *host,
 595                 struct mmc_request *mrq)
 596 {
 597         struct mmc_command *cmd = mrq->cmd;
 598         struct mmc_data *data = mrq->data;
 599         u8 *buf;
 600
 601         buf = kzalloc(data->blksz, GFP_NOIO);
 602         if (!buf) {
 603                 cmd->error = -ENOMEM;
 604                 return;
 605         }
 606
 607         if (data->flags & MMC_DATA_READ) {
 608                 if (host->initial_mode)
 609                         sd_disable_initial_mode(host);
 610
 611                 cmd->error = sd_read_data(host, cmd, (u16)data->blksz, buf,
 612                                 data->blksz, 200);
 613
 614                 if (host->initial_mode)
 615                         sd_enable_initial_mode(host);
 616
 617                 sg_copy_from_buffer(data->sg, data->sg_len, buf, data->blksz);
 618         } else {
 619                 sg_copy_to_buffer(data->sg, data->sg_len, buf, data->blksz);
 620
 621                 cmd->error = sd_write_data(host, cmd, (u16)data->blksz, buf,
 622                                 data->blksz, 200);
 623         }
 624
 625         kfree(buf);
 626 }
 627
 628 static int sd_change_phase(struct realtek_pci_sdmmc *host,
 629                 u8 sample_point, bool rx)
 630 {
 631         struct rtsx_pcr *pcr = host->pcr;
 632         int err;
 633
 634         dev_dbg(sdmmc_dev(host), "%s(%s): sample_point = %d\n",
 635                         __func__, rx ? "RX" : "TX", sample_point);
 636
 637         rtsx_pci_init_cmd(pcr);
 638
 639         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, CHANGE_CLK);
 640         if (rx)
 641                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
 642                                 SD_VPRX_CTL, 0x1F, sample_point);
 643         else
 644                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
 645                                 SD_VPTX_CTL, 0x1F, sample_point);
 646         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0);
 647         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
 648                         PHASE_NOT_RESET, PHASE_NOT_RESET);
 649         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, 0);
 650         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
 651
 652         err = rtsx_pci_send_cmd(pcr, 100);
 653         if (err < 0)
 654                 return err;
 655
 656         return 0;
 657 }
 658
 659 static inline u32 test_phase_bit(u32 phase_map, unsigned int bit)
 660 {
 661         bit %= RTSX_PHASE_MAX;
 662         return phase_map & (1 << bit);
 663 }
 664
 665 static int sd_get_phase_len(u32 phase_map, unsigned int start_bit)
 666 {
 667         int i;
 668
 669         for (i = 0; i < RTSX_PHASE_MAX; i++) {
 670                 if (test_phase_bit(phase_map, start_bit + i) == 0)
 671                         return i;
 672         }
 673         return RTSX_PHASE_MAX;
 674 }
 675
 676 static u8 sd_search_final_phase(struct realtek_pci_sdmmc *host, u32 phase_map)
 677 {
 678         int start = 0, len = 0;
 679         int start_final = 0, len_final = 0;
 680         u8 final_phase = 0xFF;
 681
 682         if (phase_map == 0) {
 683                 dev_err(sdmmc_dev(host), "phase error: [map:%x]\n", phase_map);
 684                 return final_phase;
 685         }
 686
 687         while (start < RTSX_PHASE_MAX) {
 688                 len = sd_get_phase_len(phase_map, start);
 689                 if (len_final < len) {
 690                         start_final = start;
 691                         len_final = len;
 692                 }
 693                 start += len ? len : 1;
 694         }
 695
 696         final_phase = (start_final + len_final / 2) % RTSX_PHASE_MAX;
 697         dev_dbg(sdmmc_dev(host), "phase: [map:%x] [maxlen:%d] [final:%d]\n",
 698                 phase_map, len_final, final_phase);
 699
 700         return final_phase;
 701 }
 702
 703 static void sd_wait_data_idle(struct realtek_pci_sdmmc *host)
 704 {
 705         int err, i;
 706         u8 val = 0;
 707
 708         for (i = 0; i < 100; i++) {
 709                 err = rtsx_pci_read_register(host->pcr, SD_DATA_STATE, &val);
 710                 if (val & SD_DATA_IDLE)
 711                         return;
 712
 713                 udelay(100);
 714         }
 715 }
 716
 717 static int sd_tuning_rx_cmd(struct realtek_pci_sdmmc *host,
 718                 u8 opcode, u8 sample_point)
 719 {
 720         int err;
 721         struct mmc_command cmd = {0};
 722
 723         err = sd_change_phase(host, sample_point, true);
 724         if (err < 0)
 725                 return err;
 726
 727         cmd.opcode = opcode;
 728         err = sd_read_data(host, &cmd, 0x40, NULL, 0, 100);
 729         if (err < 0) {
 730                 /* Wait till SD DATA IDLE */
 731                 sd_wait_data_idle(host);
 732                 sd_clear_error(host);
 733                 return err;
 734         }
 735
 736         return 0;
 737 }
 738
 739 static int sd_tuning_phase(struct realtek_pci_sdmmc *host,
 740                 u8 opcode, u32 *phase_map)
 741 {
 742         int err, i;
 743         u32 raw_phase_map = 0;
 744
 745         for (i = 0; i < RTSX_PHASE_MAX; i++) {
 746                 err = sd_tuning_rx_cmd(host, opcode, (u8)i);
 747                 if (err == 0)
 748                         raw_phase_map |= 1 << i;
 749         }
 750
 751         if (phase_map)
 752                 *phase_map = raw_phase_map;
 753
 754         return 0;
 755 }
 756
 757 static int sd_tuning_rx(struct realtek_pci_sdmmc *host, u8 opcode)
 758 {
 759         int err, i;
 760         u32 raw_phase_map[RX_TUNING_CNT] = {0}, phase_map;
 761         u8 final_phase;
 762
 763         for (i = 0; i < RX_TUNING_CNT; i++) {
 764                 err = sd_tuning_phase(host, opcode, &(raw_phase_map[i]));
 765                 if (err < 0)
 766                         return err;
 767
 768                 if (raw_phase_map[i] == 0)
 769                         break;
 770         }
 771
 772         phase_map = 0xFFFFFFFF;
 773         for (i = 0; i < RX_TUNING_CNT; i++) {
 774                 dev_dbg(sdmmc_dev(host), "RX raw_phase_map[%d] = 0x%08x\n",
 775                                 i, raw_phase_map[i]);
 776                 phase_map &= raw_phase_map[i];
 777         }
 778         dev_dbg(sdmmc_dev(host), "RX phase_map = 0x%08x\n", phase_map);
 779
 780         if (phase_map) {
 781                 final_phase = sd_search_final_phase(host, phase_map);
 782                 if (final_phase == 0xFF)
 783                         return -EINVAL;
 784
 785                 err = sd_change_phase(host, final_phase, true);
 786                 if (err < 0)
 787                         return err;
 788         } else {
 789                 return -EINVAL;
 790         }
 791
 792         return 0;
 793 }
 794
 795 static inline int sdio_extblock_cmd(struct mmc_command *cmd,
 796         struct mmc_data *data)
 797 {
 798         return (cmd->opcode == SD_IO_RW_EXTENDED) && (data->blksz == 512);
 799 }
 800
 801 static inline int sd_rw_cmd(struct mmc_command *cmd)
 802 {
 803         return mmc_op_multi(cmd->opcode) ||
 804                 (cmd->opcode == MMC_READ_SINGLE_BLOCK) ||
 805                 (cmd->opcode == MMC_WRITE_BLOCK);
 806 }
 807
 808 static void sd_request(struct work_struct *work)
 809 {
 810         struct realtek_pci_sdmmc *host = container_of(work,
 811                         struct realtek_pci_sdmmc, work);
 812         struct rtsx_pcr *pcr = host->pcr;
 813
 814         struct mmc_host *mmc = host->mmc;
 815         struct mmc_request *mrq = host->mrq;
 816         struct mmc_command *cmd = mrq->cmd;
 817         struct mmc_data *data = mrq->data;
 818
 819         unsigned int data_size = 0;
 820         int err;
 821
 822         if (host->eject || !sd_get_cd_int(host)) {
 823                 cmd->error = -ENOMEDIUM;
 824                 goto finish;
 825         }
 826
 827         err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
 828         if (err) {
 829                 cmd->error = err;
 830                 goto finish;
 831         }
 832
 833         mutex_lock(&pcr->pcr_mutex);
 834
 835         rtsx_pci_start_run(pcr);
 836
 837         rtsx_pci_switch_clock(pcr, host->clock, host->ssc_depth,
 838                         host->initial_mode, host->double_clk, host->vpclk);
 839         rtsx_pci_write_register(pcr, CARD_SELECT, 0x07, SD_MOD_SEL);
 840         rtsx_pci_write_register(pcr, CARD_SHARE_MODE,
 841                         CARD_SHARE_MASK, CARD_SHARE_48_SD);
 842
 843         mutex_lock(&host->host_mutex);
 844         host->mrq = mrq;
 845         mutex_unlock(&host->host_mutex);
 846
 847         if (mrq->data)
 848                 data_size = data->blocks * data->blksz;
 849
 850         if (!data_size) {
 851                 sd_send_cmd_get_rsp(host, cmd);
 852         } else if (sd_rw_cmd(cmd) || sdio_extblock_cmd(cmd, data)) {
 853                 cmd->error = sd_rw_multi(host, mrq);
 854                 if (!host->using_cookie)
 855                         sdmmc_post_req(host->mmc, host->mrq, 0);
 856
 857                 if (mmc_op_multi(cmd->opcode) && mrq->stop)
 858                         sd_send_cmd_get_rsp(host, mrq->stop);
 859         } else {
 860                 sd_normal_rw(host, mrq);
 861         }
 862
 863         if (mrq->data) {
 864                 if (cmd->error || data->error)
 865                         data->bytes_xfered = 0;
 866                 else
 867                         data->bytes_xfered = data->blocks * data->blksz;
 868         }
 869
 870         mutex_unlock(&pcr->pcr_mutex);
 871
 872 finish:
 873         if (cmd->error) {
 874                 dev_dbg(sdmmc_dev(host), "CMD %d 0x%08x error(%d)\n",
 875                         cmd->opcode, cmd->arg, cmd->error);
 876         }
 877
 878         mutex_lock(&host->host_mutex);
 879         host->mrq = NULL;
 880         mutex_unlock(&host->host_mutex);
 881
 882         mmc_request_done(mmc, mrq);
 883 }
 884
 885 static void sdmmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
 886 {
 887         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
 888         struct mmc_data *data = mrq->data;
 889
 890         mutex_lock(&host->host_mutex);
 891         host->mrq = mrq;
 892         mutex_unlock(&host->host_mutex);
 893
 894         if (sd_rw_cmd(mrq->cmd) || sdio_extblock_cmd(mrq->cmd, data))
 895                 host->using_cookie = sd_pre_dma_transfer(host, data, false);
 896
 897         schedule_work(&host->work);
 898 }
 899
 900 static int sd_set_bus_width(struct realtek_pci_sdmmc *host,
 901                 unsigned char bus_width)
 902 {
 903         int err = 0;
 904         u8 width[] = {
 905                 [MMC_BUS_WIDTH_1] = SD_BUS_WIDTH_1BIT,
 906                 [MMC_BUS_WIDTH_4] = SD_BUS_WIDTH_4BIT,
 907                 [MMC_BUS_WIDTH_8] = SD_BUS_WIDTH_8BIT,
 908         };
 909
 910         if (bus_width <= MMC_BUS_WIDTH_8)
 911                 err = rtsx_pci_write_register(host->pcr, SD_CFG1,
 912                                 0x03, width[bus_width]);
 913
 914         return err;
 915 }
 916
 917 static int sd_power_on(struct realtek_pci_sdmmc *host)
 918 {
 919         struct rtsx_pcr *pcr = host->pcr;
 920         int err;
 921
 922         if (host->power_state == SDMMC_POWER_ON)
 923                 return 0;
 924
 925         rtsx_pci_init_cmd(pcr);
 926         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SELECT, 0x07, SD_MOD_SEL);
 927         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SHARE_MODE,
 928                         CARD_SHARE_MASK, CARD_SHARE_48_SD);
 929         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN,
 930                         SD_CLK_EN, SD_CLK_EN);
 931         err = rtsx_pci_send_cmd(pcr, 100);
 932         if (err < 0)
 933                 return err;
 934
 935         err = rtsx_pci_card_pull_ctl_enable(pcr, RTSX_SD_CARD);
 936         if (err < 0)
 937                 return err;
 938
 939         err = rtsx_pci_card_power_on(pcr, RTSX_SD_CARD);
 940         if (err < 0)
 941                 return err;
 942
 943         err = rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN);
 944         if (err < 0)
 945                 return err;
 946
 947         host->power_state = SDMMC_POWER_ON;
 948         return 0;
 949 }
 950
 951 static int sd_power_off(struct realtek_pci_sdmmc *host)
 952 {
 953         struct rtsx_pcr *pcr = host->pcr;
 954         int err;
 955
 956         host->power_state = SDMMC_POWER_OFF;
 957
 958         rtsx_pci_init_cmd(pcr);
 959
 960         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, 0);
 961         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0);
 962
 963         err = rtsx_pci_send_cmd(pcr, 100);
 964         if (err < 0)
 965                 return err;
 966
 967         err = rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);
 968         if (err < 0)
 969                 return err;
 970
 971         return rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD);
 972 }
 973
 974 static int sd_set_power_mode(struct realtek_pci_sdmmc *host,
 975                 unsigned char power_mode)
 976 {
 977         int err;
 978
 979         if (power_mode == MMC_POWER_OFF)
 980                 err = sd_power_off(host);
 981         else
 982                 err = sd_power_on(host);
 983
 984         return err;
 985 }
 986
 987 static int sd_set_timing(struct realtek_pci_sdmmc *host, unsigned char timing)
 988 {
 989         struct rtsx_pcr *pcr = host->pcr;
 990         int err = 0;
 991
 992         rtsx_pci_init_cmd(pcr);
 993
 994         switch (timing) {
 995         case MMC_TIMING_UHS_SDR104:
 996         case MMC_TIMING_UHS_SDR50:
 997                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
 998                                 0x0C | SD_ASYNC_FIFO_NOT_RST,
 999                                 SD_30_MODE | SD_ASYNC_FIFO_NOT_RST);
1000                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1001                                 CLK_LOW_FREQ, CLK_LOW_FREQ);
1002                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1003                                 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
1004                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1005                 break;
1006
1007         case MMC_TIMING_MMC_DDR52:
1008         case MMC_TIMING_UHS_DDR50:
1009                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
1010                                 0x0C | SD_ASYNC_FIFO_NOT_RST,
1011                                 SD_DDR_MODE | SD_ASYNC_FIFO_NOT_RST);
1012                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1013                                 CLK_LOW_FREQ, CLK_LOW_FREQ);
1014                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1015                                 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
1016                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1017                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
1018                                 DDR_VAR_TX_CMD_DAT, DDR_VAR_TX_CMD_DAT);
1019                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
1020                                 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD,
1021                                 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD);
1022                 break;
1023
1024         case MMC_TIMING_MMC_HS:
1025         case MMC_TIMING_SD_HS:
1026                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
1027                                 0x0C, SD_20_MODE);
1028                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1029                                 CLK_LOW_FREQ, CLK_LOW_FREQ);
1030                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1031                                 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
1032                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1033                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
1034                                 SD20_TX_SEL_MASK, SD20_TX_14_AHEAD);
1035                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
1036                                 SD20_RX_SEL_MASK, SD20_RX_14_DELAY);
1037                 break;
1038
1039         default:
1040                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
1041                                 SD_CFG1, 0x0C, SD_20_MODE);
1042                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1043                                 CLK_LOW_FREQ, CLK_LOW_FREQ);
1044                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1045                                 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
1046                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1047                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
1048                                 SD_PUSH_POINT_CTL, 0xFF, 0);
1049                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
1050                                 SD20_RX_SEL_MASK, SD20_RX_POS_EDGE);
1051                 break;
1052         }
1053
1054         err = rtsx_pci_send_cmd(pcr, 100);
1055
1056         return err;
1057 }
1058
1059 static void sdmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1060 {
1061         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1062         struct rtsx_pcr *pcr = host->pcr;
1063
1064         if (host->eject)
1065                 return;
1066
1067         if (rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD))
1068                 return;
1069
1070         mutex_lock(&pcr->pcr_mutex);
1071
1072         rtsx_pci_start_run(pcr);
1073
1074         sd_set_bus_width(host, ios->bus_width);
1075         sd_set_power_mode(host, ios->power_mode);
1076         sd_set_timing(host, ios->timing);
1077
1078         host->vpclk = false;
1079         host->double_clk = true;
1080
1081         switch (ios->timing) {
1082         case MMC_TIMING_UHS_SDR104:
1083         case MMC_TIMING_UHS_SDR50:
1084                 host->ssc_depth = RTSX_SSC_DEPTH_2M;
1085                 host->vpclk = true;
1086                 host->double_clk = false;
1087                 break;
1088         case MMC_TIMING_MMC_DDR52:
1089         case MMC_TIMING_UHS_DDR50:
1090         case MMC_TIMING_UHS_SDR25:
1091                 host->ssc_depth = RTSX_SSC_DEPTH_1M;
1092                 break;
1093         default:
1094                 host->ssc_depth = RTSX_SSC_DEPTH_500K;
1095                 break;
1096         }
1097
1098         host->initial_mode = (ios->clock <= 1000000) ? true : false;
1099
1100         host->clock = ios->clock;
1101         rtsx_pci_switch_clock(pcr, ios->clock, host->ssc_depth,
1102                         host->initial_mode, host->double_clk, host->vpclk);
1103
1104         mutex_unlock(&pcr->pcr_mutex);
1105 }
1106
1107 static int sdmmc_get_ro(struct mmc_host *mmc)
1108 {
1109         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1110         struct rtsx_pcr *pcr = host->pcr;
1111         int ro = 0;
1112         u32 val;
1113
1114         if (host->eject)
1115                 return -ENOMEDIUM;
1116
1117         mutex_lock(&pcr->pcr_mutex);
1118
1119         rtsx_pci_start_run(pcr);
1120
1121         /* Check SD mechanical write-protect switch */
1122         val = rtsx_pci_readl(pcr, RTSX_BIPR);
1123         dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val);
1124         if (val & SD_WRITE_PROTECT)
1125                 ro = 1;
1126
1127         mutex_unlock(&pcr->pcr_mutex);
1128
1129         return ro;
1130 }
1131
1132 static int sdmmc_get_cd(struct mmc_host *mmc)
1133 {
1134         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1135         struct rtsx_pcr *pcr = host->pcr;
1136         int cd = 0;
1137         u32 val;
1138
1139         if (host->eject)
1140                 return cd;
1141
1142         mutex_lock(&pcr->pcr_mutex);
1143
1144         rtsx_pci_start_run(pcr);
1145
1146         /* Check SD card detect */
1147         val = rtsx_pci_card_exist(pcr);
1148         dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val);
1149         if (val & SD_EXIST)
1150                 cd = 1;
1151
1152         mutex_unlock(&pcr->pcr_mutex);
1153
1154         return cd;
1155 }
1156
1157 static int sd_wait_voltage_stable_1(struct realtek_pci_sdmmc *host)
1158 {
1159         struct rtsx_pcr *pcr = host->pcr;
1160         int err;
1161         u8 stat;
1162
1163         /* Reference to Signal Voltage Switch Sequence in SD spec.
1164          * Wait for a period of time so that the card can drive SD_CMD and
1165          * SD_DAT[3:0] to low after sending back CMD11 response.
1166          */
1167         mdelay(1);
1168
1169         /* SD_CMD, SD_DAT[3:0] should be driven to low by card;
1170          * If either one of SD_CMD,SD_DAT[3:0] is not low,
1171          * abort the voltage switch sequence;
1172          */
1173         err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1174         if (err < 0)
1175                 return err;
1176
1177         if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1178                                 SD_DAT1_STATUS | SD_DAT0_STATUS))
1179                 return -EINVAL;
1180
1181         /* Stop toggle SD clock */
1182         err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1183                         0xFF, SD_CLK_FORCE_STOP);
1184         if (err < 0)
1185                 return err;
1186
1187         return 0;
1188 }
1189
1190 static int sd_wait_voltage_stable_2(struct realtek_pci_sdmmc *host)
1191 {
1192         struct rtsx_pcr *pcr = host->pcr;
1193         int err;
1194         u8 stat, mask, val;
1195
1196         /* Wait 1.8V output of voltage regulator in card stable */
1197         msleep(50);
1198
1199         /* Toggle SD clock again */
1200         err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN);
1201         if (err < 0)
1202                 return err;
1203
1204         /* Wait for a period of time so that the card can drive
1205          * SD_DAT[3:0] to high at 1.8V
1206          */
1207         msleep(20);
1208
1209         /* SD_CMD, SD_DAT[3:0] should be pulled high by host */
1210         err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1211         if (err < 0)
1212                 return err;
1213
1214         mask = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1215                 SD_DAT1_STATUS | SD_DAT0_STATUS;
1216         val = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1217                 SD_DAT1_STATUS | SD_DAT0_STATUS;
1218         if ((stat & mask) != val) {
1219                 dev_dbg(sdmmc_dev(host),
1220                         "%s: SD_BUS_STAT = 0x%x\n", __func__, stat);
1221                 rtsx_pci_write_register(pcr, SD_BUS_STAT,
1222                                 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
1223                 rtsx_pci_write_register(pcr, CARD_CLK_EN, 0xFF, 0);
1224                 return -EINVAL;
1225         }
1226
1227         return 0;
1228 }
1229
1230 static int sdmmc_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1231 {
1232         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1233         struct rtsx_pcr *pcr = host->pcr;
1234         int err = 0;
1235         u8 voltage;
1236
1237         dev_dbg(sdmmc_dev(host), "%s: signal_voltage = %d\n",
1238                         __func__, ios->signal_voltage);
1239
1240         if (host->eject)
1241                 return -ENOMEDIUM;
1242
1243         err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
1244         if (err)
1245                 return err;
1246
1247         mutex_lock(&pcr->pcr_mutex);
1248
1249         rtsx_pci_start_run(pcr);
1250
1251         if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1252                 voltage = OUTPUT_3V3;
1253         else
1254                 voltage = OUTPUT_1V8;
1255
1256         if (voltage == OUTPUT_1V8) {
1257                 err = sd_wait_voltage_stable_1(host);
1258                 if (err < 0)
1259                         goto out;
1260         }
1261
1262         err = rtsx_pci_switch_output_voltage(pcr, voltage);
1263         if (err < 0)
1264                 goto out;
1265
1266         if (voltage == OUTPUT_1V8) {
1267                 err = sd_wait_voltage_stable_2(host);
1268                 if (err < 0)
1269                         goto out;
1270         }
1271
1272 out:
1273         /* Stop toggle SD clock in idle */
1274         err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1275                         SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
1276
1277         mutex_unlock(&pcr->pcr_mutex);
1278
1279         return err;
1280 }
1281
1282 static int sdmmc_execute_tuning(struct mmc_host *mmc, u32 opcode)
1283 {
1284         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1285         struct rtsx_pcr *pcr = host->pcr;
1286         int err = 0;
1287
1288         if (host->eject)
1289                 return -ENOMEDIUM;
1290
1291         err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
1292         if (err)
1293                 return err;
1294
1295         mutex_lock(&pcr->pcr_mutex);
1296
1297         rtsx_pci_start_run(pcr);
1298
1299         /* Set initial TX phase */
1300         switch (mmc->ios.timing) {
1301         case MMC_TIMING_UHS_SDR104:
1302                 err = sd_change_phase(host, SDR104_TX_PHASE(pcr), false);
1303                 break;
1304
1305         case MMC_TIMING_UHS_SDR50:
1306                 err = sd_change_phase(host, SDR50_TX_PHASE(pcr), false);
1307                 break;
1308
1309         case MMC_TIMING_UHS_DDR50:
1310                 err = sd_change_phase(host, DDR50_TX_PHASE(pcr), false);
1311                 break;
1312
1313         default:
1314                 err = 0;
1315         }
1316
1317         if (err)
1318                 goto out;
1319
1320         /* Tuning RX phase */
1321         if ((mmc->ios.timing == MMC_TIMING_UHS_SDR104) ||
1322                         (mmc->ios.timing == MMC_TIMING_UHS_SDR50))
1323                 err = sd_tuning_rx(host, opcode);
1324         else if (mmc->ios.timing == MMC_TIMING_UHS_DDR50)
1325                 err = sd_change_phase(host, DDR50_RX_PHASE(pcr), true);
1326
1327 out:
1328         mutex_unlock(&pcr->pcr_mutex);
1329
1330         return err;
1331 }
1332
1333 static const struct mmc_host_ops realtek_pci_sdmmc_ops = {
1334         .pre_req = sdmmc_pre_req,
1335         .post_req = sdmmc_post_req,
1336         .request = sdmmc_request,
1337         .set_ios = sdmmc_set_ios,
1338         .get_ro = sdmmc_get_ro,
1339         .get_cd = sdmmc_get_cd,
1340         .start_signal_voltage_switch = sdmmc_switch_voltage,
1341         .execute_tuning = sdmmc_execute_tuning,
1342 };
1343
1344 static void init_extra_caps(struct realtek_pci_sdmmc *host)
1345 {
1346         struct mmc_host *mmc = host->mmc;
1347         struct rtsx_pcr *pcr = host->pcr;
1348
1349         dev_dbg(sdmmc_dev(host), "pcr->extra_caps = 0x%x\n", pcr->extra_caps);
1350
1351         if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50)
1352                 mmc->caps |= MMC_CAP_UHS_SDR50;
1353         if (pcr->extra_caps & EXTRA_CAPS_SD_SDR104)
1354                 mmc->caps |= MMC_CAP_UHS_SDR104;
1355         if (pcr->extra_caps & EXTRA_CAPS_SD_DDR50)
1356                 mmc->caps |= MMC_CAP_UHS_DDR50;
1357         if (pcr->extra_caps & EXTRA_CAPS_MMC_HSDDR)
1358                 mmc->caps |= MMC_CAP_1_8V_DDR;
1359         if (pcr->extra_caps & EXTRA_CAPS_MMC_8BIT)
1360                 mmc->caps |= MMC_CAP_8_BIT_DATA;
1361 }
1362
1363 static void realtek_init_host(struct realtek_pci_sdmmc *host)
1364 {
1365         struct mmc_host *mmc = host->mmc;
1366
1367         mmc->f_min = 250000;
1368         mmc->f_max = 208000000;
1369         mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1370         mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED |
1371                 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_BUS_WIDTH_TEST |
1372                 MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | MMC_CAP_ERASE;
1373         mmc->caps2 = MMC_CAP2_NO_PRESCAN_POWERUP | MMC_CAP2_FULL_PWR_CYCLE;
1374         mmc->max_current_330 = 400;
1375         mmc->max_current_180 = 800;
1376         mmc->ops = &realtek_pci_sdmmc_ops;
1377
1378         init_extra_caps(host);
1379
1380         mmc->max_segs = 256;
1381         mmc->max_seg_size = 65536;
1382         mmc->max_blk_size = 512;
1383         mmc->max_blk_count = 65535;
1384         mmc->max_req_size = 524288;
1385 }
1386
1387 static void rtsx_pci_sdmmc_card_event(struct platform_device *pdev)
1388 {
1389         struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1390
1391         host->cookie = -1;
1392         mmc_detect_change(host->mmc, 0);
1393 }
1394
1395 static int rtsx_pci_sdmmc_drv_probe(struct platform_device *pdev)
1396 {
1397         struct mmc_host *mmc;
1398         struct realtek_pci_sdmmc *host;
1399         struct rtsx_pcr *pcr;
1400         struct pcr_handle *handle = pdev->dev.platform_data;
1401
1402         if (!handle)
1403                 return -ENXIO;
1404
1405         pcr = handle->pcr;
1406         if (!pcr)
1407                 return -ENXIO;
1408
1409         dev_dbg(&(pdev->dev), ": Realtek PCI-E SDMMC controller found\n");
1410
1411         mmc = mmc_alloc_host(sizeof(*host), &pdev->dev);
1412         if (!mmc)
1413                 return -ENOMEM;
1414
1415         host = mmc_priv(mmc);
1416         host->pcr = pcr;
1417         host->mmc = mmc;
1418         host->pdev = pdev;
1419         host->cookie = -1;
1420         host->power_state = SDMMC_POWER_OFF;
1421         INIT_WORK(&host->work, sd_request);
1422         platform_set_drvdata(pdev, host);
1423         pcr->slots[RTSX_SD_CARD].p_dev = pdev;
1424         pcr->slots[RTSX_SD_CARD].card_event = rtsx_pci_sdmmc_card_event;
1425
1426         mutex_init(&host->host_mutex);
1427
1428         realtek_init_host(host);
1429
1430         mmc_add_host(mmc);
1431
1432         return 0;
1433 }
1434
1435 static int rtsx_pci_sdmmc_drv_remove(struct platform_device *pdev)
1436 {
1437         struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1438         struct rtsx_pcr *pcr;
1439         struct mmc_host *mmc;
1440
1441         if (!host)
1442                 return 0;
1443
1444         pcr = host->pcr;
1445         pcr->slots[RTSX_SD_CARD].p_dev = NULL;
1446         pcr->slots[RTSX_SD_CARD].card_event = NULL;
1447         mmc = host->mmc;
1448
1449         cancel_work_sync(&host->work);
1450
1451         mutex_lock(&host->host_mutex);
1452         if (host->mrq) {
1453                 dev_dbg(&(pdev->dev),
1454                         "%s: Controller removed during transfer\n",
1455                         mmc_hostname(mmc));
1456
1457                 rtsx_pci_complete_unfinished_transfer(pcr);
1458
1459                 host->mrq->cmd->error = -ENOMEDIUM;
1460                 if (host->mrq->stop)
1461                         host->mrq->stop->error = -ENOMEDIUM;
1462                 mmc_request_done(mmc, host->mrq);
1463         }
1464         mutex_unlock(&host->host_mutex);
1465
1466         mmc_remove_host(mmc);
1467         host->eject = true;
1468
1469         flush_work(&host->work);
1470
1471         mmc_free_host(mmc);
1472
1473         dev_dbg(&(pdev->dev),
1474                 ": Realtek PCI-E SDMMC controller has been removed\n");
1475
1476         return 0;
1477 }
1478
1479 static const struct platform_device_id rtsx_pci_sdmmc_ids[] = {
1480         {
1481                 .name = DRV_NAME_RTSX_PCI_SDMMC,
1482         }, {
1483                 /* sentinel */
1484         }
1485 };
1486 MODULE_DEVICE_TABLE(platform, rtsx_pci_sdmmc_ids);
1487
1488 static struct platform_driver rtsx_pci_sdmmc_driver = {
1489         .probe          = rtsx_pci_sdmmc_drv_probe,
1490         .remove         = rtsx_pci_sdmmc_drv_remove,
1491         .id_table       = rtsx_pci_sdmmc_ids,
1492         .driver         = {
1493                 .name   = DRV_NAME_RTSX_PCI_SDMMC,
1494         },
1495 };
1496 module_platform_driver(rtsx_pci_sdmmc_driver);
1497
1498 MODULE_LICENSE("GPL");
1499 MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
1500 MODULE_DESCRIPTION("Realtek PCI-E SD/MMC Card Host Driver");