drivers/mmc/host/rtsx_pci_sdmmc.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /* Realtek PCI-Express SD/MMC Card Interface driver
   3  *
   4  * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
   5  *
   6  * Author:
   7  *   Wei WANG <wei_wang@realsil.com.cn>
   8  */
   9
  10 #include <linux/module.h>
  11 #include <linux/slab.h>
  12 #include <linux/highmem.h>
  13 #include <linux/delay.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/workqueue.h>
  16 #include <linux/mmc/host.h>
  17 #include <linux/mmc/mmc.h>
  18 #include <linux/mmc/sd.h>
  19 #include <linux/mmc/sdio.h>
  20 #include <linux/mmc/card.h>
  21 #include <linux/rtsx_pci.h>
  22 #include <asm/unaligned.h>
  23
  24 struct realtek_pci_sdmmc {
  25         struct platform_device  *pdev;
  26         struct rtsx_pcr         *pcr;
  27         struct mmc_host         *mmc;
  28         struct mmc_request      *mrq;
  29 #define SDMMC_WORKQ_NAME        "rtsx_pci_sdmmc_workq"
  30
  31         struct work_struct      work;
  32         struct mutex            host_mutex;
  33
  34         u8                      ssc_depth;
  35         unsigned int            clock;
  36         bool                    vpclk;
  37         bool                    double_clk;
  38         bool                    eject;
  39         bool                    initial_mode;
  40         int                     prev_power_state;
  41         int                     sg_count;
  42         s32                     cookie;
  43         int                     cookie_sg_count;
  44         bool                    using_cookie;
  45 };
  46
  47 static inline struct device *sdmmc_dev(struct realtek_pci_sdmmc *host)
  48 {
  49         return &(host->pdev->dev);
  50 }
  51
  52 static inline void sd_clear_error(struct realtek_pci_sdmmc *host)
  53 {
  54         rtsx_pci_write_register(host->pcr, CARD_STOP,
  55                         SD_STOP | SD_CLR_ERR, SD_STOP | SD_CLR_ERR);
  56 }
  57
  58 #ifdef DEBUG
  59 static void dump_reg_range(struct realtek_pci_sdmmc *host, u16 start, u16 end)
  60 {
  61         u16 len = end - start + 1;
  62         int i;
  63         u8 data[8];
  64
  65         for (i = 0; i < len; i += 8) {
  66                 int j;
  67                 int n = min(8, len - i);
  68
  69                 memset(&data, 0, sizeof(data));
  70                 for (j = 0; j < n; j++)
  71                         rtsx_pci_read_register(host->pcr, start + i + j,
  72                                 data + j);
  73                 dev_dbg(sdmmc_dev(host), "0x%04X(%d): %8ph\n",
  74                         start + i, n, data);
  75         }
  76 }
  77
  78 static void sd_print_debug_regs(struct realtek_pci_sdmmc *host)
  79 {
  80         dump_reg_range(host, 0xFDA0, 0xFDB3);
  81         dump_reg_range(host, 0xFD52, 0xFD69);
  82 }
  83 #else
  84 #define sd_print_debug_regs(host)
  85 #endif /* DEBUG */
  86
  87 static inline int sd_get_cd_int(struct realtek_pci_sdmmc *host)
  88 {
  89         return rtsx_pci_readl(host->pcr, RTSX_BIPR) & SD_EXIST;
  90 }
  91
  92 static void sd_cmd_set_sd_cmd(struct rtsx_pcr *pcr, struct mmc_command *cmd)
  93 {
  94         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0, 0xFF,
  95                 SD_CMD_START | cmd->opcode);
  96         rtsx_pci_write_be32(pcr, SD_CMD1, cmd->arg);
  97 }
  98
  99 static void sd_cmd_set_data_len(struct rtsx_pcr *pcr, u16 blocks, u16 blksz)
 100 {
 101         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, blocks);
 102         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, blocks >> 8);
 103         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, blksz);
 104         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, blksz >> 8);
 105 }
 106
 107 static int sd_response_type(struct mmc_command *cmd)
 108 {
 109         switch (mmc_resp_type(cmd)) {
 110         case MMC_RSP_NONE:
 111                 return SD_RSP_TYPE_R0;
 112         case MMC_RSP_R1:
 113                 return SD_RSP_TYPE_R1;
 114         case MMC_RSP_R1_NO_CRC:
 115                 return SD_RSP_TYPE_R1 | SD_NO_CHECK_CRC7;
 116         case MMC_RSP_R1B:
 117                 return SD_RSP_TYPE_R1b;
 118         case MMC_RSP_R2:
 119                 return SD_RSP_TYPE_R2;
 120         case MMC_RSP_R3:
 121                 return SD_RSP_TYPE_R3;
 122         default:
 123                 return -EINVAL;
 124         }
 125 }
 126
 127 static int sd_status_index(int resp_type)
 128 {
 129         if (resp_type == SD_RSP_TYPE_R0)
 130                 return 0;
 131         else if (resp_type == SD_RSP_TYPE_R2)
 132                 return 16;
 133
 134         return 5;
 135 }
 136 /*
 137  * sd_pre_dma_transfer - do dma_map_sg() or using cookie
 138  *
 139  * @pre: if called in pre_req()
 140  * return:
 141  *      0 - do dma_map_sg()
 142  *      1 - using cookie
 143  */
 144 static int sd_pre_dma_transfer(struct realtek_pci_sdmmc *host,
 145                 struct mmc_data *data, bool pre)
 146 {
 147         struct rtsx_pcr *pcr = host->pcr;
 148         int read = data->flags & MMC_DATA_READ;
 149         int count = 0;
 150         int using_cookie = 0;
 151
 152         if (!pre && data->host_cookie && data->host_cookie != host->cookie) {
 153                 dev_err(sdmmc_dev(host),
 154                         "error: data->host_cookie = %d, host->cookie = %d\n",
 155                         data->host_cookie, host->cookie);
 156                 data->host_cookie = 0;
 157         }
 158
 159         if (pre || data->host_cookie != host->cookie) {
 160                 count = rtsx_pci_dma_map_sg(pcr, data->sg, data->sg_len, read);
 161         } else {
 162                 count = host->cookie_sg_count;
 163                 using_cookie = 1;
 164         }
 165
 166         if (pre) {
 167                 host->cookie_sg_count = count;
 168                 if (++host->cookie < 0)
 169                         host->cookie = 1;
 170                 data->host_cookie = host->cookie;
 171         } else {
 172                 host->sg_count = count;
 173         }
 174
 175         return using_cookie;
 176 }
 177
 178 static void sdmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
 179 {
 180         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
 181         struct mmc_data *data = mrq->data;
 182
 183         if (data->host_cookie) {
 184                 dev_err(sdmmc_dev(host),
 185                         "error: reset data->host_cookie = %d\n",
 186                         data->host_cookie);
 187                 data->host_cookie = 0;
 188         }
 189
 190         sd_pre_dma_transfer(host, data, true);
 191         dev_dbg(sdmmc_dev(host), "pre dma sg: %d\n", host->cookie_sg_count);
 192 }
 193
 194 static void sdmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
 195                 int err)
 196 {
 197         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
 198         struct rtsx_pcr *pcr = host->pcr;
 199         struct mmc_data *data = mrq->data;
 200         int read = data->flags & MMC_DATA_READ;
 201
 202         rtsx_pci_dma_unmap_sg(pcr, data->sg, data->sg_len, read);
 203         data->host_cookie = 0;
 204 }
 205
 206 static void sd_send_cmd_get_rsp(struct realtek_pci_sdmmc *host,
 207                 struct mmc_command *cmd)
 208 {
 209         struct rtsx_pcr *pcr = host->pcr;
 210         u8 cmd_idx = (u8)cmd->opcode;
 211         u32 arg = cmd->arg;
 212         int err = 0;
 213         int timeout = 100;
 214         int i;
 215         u8 *ptr;
 216         int rsp_type;
 217         int stat_idx;
 218         bool clock_toggled = false;
 219
 220         dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
 221                         __func__, cmd_idx, arg);
 222
 223         rsp_type = sd_response_type(cmd);
 224         if (rsp_type < 0)
 225                 goto out;
 226
 227         stat_idx = sd_status_index(rsp_type);
 228
 229         if (rsp_type == SD_RSP_TYPE_R1b)
 230                 timeout = cmd->busy_timeout ? cmd->busy_timeout : 3000;
 231
 232         if (cmd->opcode == SD_SWITCH_VOLTAGE) {
 233                 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
 234                                 0xFF, SD_CLK_TOGGLE_EN);
 235                 if (err < 0)
 236                         goto out;
 237
 238                 clock_toggled = true;
 239         }
 240
 241         rtsx_pci_init_cmd(pcr);
 242         sd_cmd_set_sd_cmd(pcr, cmd);
 243         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, rsp_type);
 244         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
 245                         0x01, PINGPONG_BUFFER);
 246         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
 247                         0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START);
 248         rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
 249                      SD_TRANSFER_END | SD_STAT_IDLE,
 250                      SD_TRANSFER_END | SD_STAT_IDLE);
 251
 252         if (rsp_type == SD_RSP_TYPE_R2) {
 253                 /* Read data from ping-pong buffer */
 254                 for (i = PPBUF_BASE2; i < PPBUF_BASE2 + 16; i++)
 255                         rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
 256         } else if (rsp_type != SD_RSP_TYPE_R0) {
 257                 /* Read data from SD_CMDx registers */
 258                 for (i = SD_CMD0; i <= SD_CMD4; i++)
 259                         rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
 260         }
 261
 262         rtsx_pci_add_cmd(pcr, READ_REG_CMD, SD_STAT1, 0, 0);
 263
 264         err = rtsx_pci_send_cmd(pcr, timeout);
 265         if (err < 0) {
 266                 sd_print_debug_regs(host);
 267                 sd_clear_error(host);
 268                 dev_dbg(sdmmc_dev(host),
 269                         "rtsx_pci_send_cmd error (err = %d)\n", err);
 270                 goto out;
 271         }
 272
 273         if (rsp_type == SD_RSP_TYPE_R0) {
 274                 err = 0;
 275                 goto out;
 276         }
 277
 278         /* Eliminate returned value of CHECK_REG_CMD */
 279         ptr = rtsx_pci_get_cmd_data(pcr) + 1;
 280
 281         /* Check (Start,Transmission) bit of Response */
 282         if ((ptr[0] & 0xC0) != 0) {
 283                 err = -EILSEQ;
 284                 dev_dbg(sdmmc_dev(host), "Invalid response bit\n");
 285                 goto out;
 286         }
 287
 288         /* Check CRC7 */
 289         if (!(rsp_type & SD_NO_CHECK_CRC7)) {
 290                 if (ptr[stat_idx] & SD_CRC7_ERR) {
 291                         err = -EILSEQ;
 292                         dev_dbg(sdmmc_dev(host), "CRC7 error\n");
 293                         goto out;
 294                 }
 295         }
 296
 297         if (rsp_type == SD_RSP_TYPE_R2) {
 298                 /*
 299                  * The controller offloads the last byte {CRC-7, end bit 1'b1}
 300                  * of response type R2. Assign dummy CRC, 0, and end bit to the
 301                  * byte(ptr[16], goes into the LSB of resp[3] later).
 302                  */
 303                 ptr[16] = 1;
 304
 305                 for (i = 0; i < 4; i++) {
 306                         cmd->resp[i] = get_unaligned_be32(ptr + 1 + i * 4);
 307                         dev_dbg(sdmmc_dev(host), "cmd->resp[%d] = 0x%08x\n",
 308                                         i, cmd->resp[i]);
 309                 }
 310         } else {
 311                 cmd->resp[0] = get_unaligned_be32(ptr + 1);
 312                 dev_dbg(sdmmc_dev(host), "cmd->resp[0] = 0x%08x\n",
 313                                 cmd->resp[0]);
 314         }
 315
 316 out:
 317         cmd->error = err;
 318
 319         if (err && clock_toggled)
 320                 rtsx_pci_write_register(pcr, SD_BUS_STAT,
 321                                 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
 322 }
 323
 324 static int sd_read_data(struct realtek_pci_sdmmc *host, struct mmc_command *cmd,
 325         u16 byte_cnt, u8 *buf, int buf_len, int timeout)
 326 {
 327         struct rtsx_pcr *pcr = host->pcr;
 328         int err;
 329         u8 trans_mode;
 330
 331         dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
 332                 __func__, cmd->opcode, cmd->arg);
 333
 334         if (!buf)
 335                 buf_len = 0;
 336
 337         if (cmd->opcode == MMC_SEND_TUNING_BLOCK)
 338                 trans_mode = SD_TM_AUTO_TUNING;
 339         else
 340                 trans_mode = SD_TM_NORMAL_READ;
 341
 342         rtsx_pci_init_cmd(pcr);
 343         sd_cmd_set_sd_cmd(pcr, cmd);
 344         sd_cmd_set_data_len(pcr, 1, byte_cnt);
 345         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
 346                         SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
 347                         SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6);
 348         if (trans_mode != SD_TM_AUTO_TUNING)
 349                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
 350                                 CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
 351
 352         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
 353                         0xFF, trans_mode | SD_TRANSFER_START);
 354         rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
 355                         SD_TRANSFER_END, SD_TRANSFER_END);
 356
 357         err = rtsx_pci_send_cmd(pcr, timeout);
 358         if (err < 0) {
 359                 sd_print_debug_regs(host);
 360                 dev_dbg(sdmmc_dev(host),
 361                         "rtsx_pci_send_cmd fail (err = %d)\n", err);
 362                 return err;
 363         }
 364
 365         if (buf && buf_len) {
 366                 err = rtsx_pci_read_ppbuf(pcr, buf, buf_len);
 367                 if (err < 0) {
 368                         dev_dbg(sdmmc_dev(host),
 369                                 "rtsx_pci_read_ppbuf fail (err = %d)\n", err);
 370                         return err;
 371                 }
 372         }
 373
 374         return 0;
 375 }
 376
 377 static int sd_write_data(struct realtek_pci_sdmmc *host,
 378         struct mmc_command *cmd, u16 byte_cnt, u8 *buf, int buf_len,
 379         int timeout)
 380 {
 381         struct rtsx_pcr *pcr = host->pcr;
 382         int err;
 383
 384         dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
 385                 __func__, cmd->opcode, cmd->arg);
 386
 387         if (!buf)
 388                 buf_len = 0;
 389
 390         sd_send_cmd_get_rsp(host, cmd);
 391         if (cmd->error)
 392                 return cmd->error;
 393
 394         if (buf && buf_len) {
 395                 err = rtsx_pci_write_ppbuf(pcr, buf, buf_len);
 396                 if (err < 0) {
 397                         dev_dbg(sdmmc_dev(host),
 398                                 "rtsx_pci_write_ppbuf fail (err = %d)\n", err);
 399                         return err;
 400                 }
 401         }
 402
 403         rtsx_pci_init_cmd(pcr);
 404         sd_cmd_set_data_len(pcr, 1, byte_cnt);
 405         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
 406                 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
 407                 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_0);
 408         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
 409                         SD_TRANSFER_START | SD_TM_AUTO_WRITE_3);
 410         rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
 411                         SD_TRANSFER_END, SD_TRANSFER_END);
 412
 413         err = rtsx_pci_send_cmd(pcr, timeout);
 414         if (err < 0) {
 415                 sd_print_debug_regs(host);
 416                 dev_dbg(sdmmc_dev(host),
 417                         "rtsx_pci_send_cmd fail (err = %d)\n", err);
 418                 return err;
 419         }
 420
 421         return 0;
 422 }
 423
 424 static int sd_read_long_data(struct realtek_pci_sdmmc *host,
 425         struct mmc_request *mrq)
 426 {
 427         struct rtsx_pcr *pcr = host->pcr;
 428         struct mmc_host *mmc = host->mmc;
 429         struct mmc_card *card = mmc->card;
 430         struct mmc_command *cmd = mrq->cmd;
 431         struct mmc_data *data = mrq->data;
 432         int uhs = mmc_card_uhs(card);
 433         u8 cfg2 = 0;
 434         int err;
 435         int resp_type;
 436         size_t data_len = data->blksz * data->blocks;
 437
 438         dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
 439                 __func__, cmd->opcode, cmd->arg);
 440
 441         resp_type = sd_response_type(cmd);
 442         if (resp_type < 0)
 443                 return resp_type;
 444
 445         if (!uhs)
 446                 cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
 447
 448         rtsx_pci_init_cmd(pcr);
 449         sd_cmd_set_sd_cmd(pcr, cmd);
 450         sd_cmd_set_data_len(pcr, data->blocks, data->blksz);
 451         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
 452                         DMA_DONE_INT, DMA_DONE_INT);
 453         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3,
 454                 0xFF, (u8)(data_len >> 24));
 455         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2,
 456                 0xFF, (u8)(data_len >> 16));
 457         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1,
 458                 0xFF, (u8)(data_len >> 8));
 459         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len);
 460         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
 461                 0x03 | DMA_PACK_SIZE_MASK,
 462                 DMA_DIR_FROM_CARD | DMA_EN | DMA_512);
 463         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
 464                         0x01, RING_BUFFER);
 465         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2 | resp_type);
 466         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
 467                         SD_TRANSFER_START | SD_TM_AUTO_READ_2);
 468         rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
 469                         SD_TRANSFER_END, SD_TRANSFER_END);
 470         rtsx_pci_send_cmd_no_wait(pcr);
 471
 472         err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, 1, 10000);
 473         if (err < 0) {
 474                 sd_print_debug_regs(host);
 475                 sd_clear_error(host);
 476                 return err;
 477         }
 478
 479         return 0;
 480 }
 481
 482 static int sd_write_long_data(struct realtek_pci_sdmmc *host,
 483         struct mmc_request *mrq)
 484 {
 485         struct rtsx_pcr *pcr = host->pcr;
 486         struct mmc_host *mmc = host->mmc;
 487         struct mmc_card *card = mmc->card;
 488         struct mmc_command *cmd = mrq->cmd;
 489         struct mmc_data *data = mrq->data;
 490         int uhs = mmc_card_uhs(card);
 491         u8 cfg2;
 492         int err;
 493         size_t data_len = data->blksz * data->blocks;
 494
 495         sd_send_cmd_get_rsp(host, cmd);
 496         if (cmd->error)
 497                 return cmd->error;
 498
 499         dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
 500                 __func__, cmd->opcode, cmd->arg);
 501
 502         cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 |
 503                 SD_NO_WAIT_BUSY_END | SD_NO_CHECK_CRC7 | SD_RSP_LEN_0;
 504
 505         if (!uhs)
 506                 cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
 507
 508         rtsx_pci_init_cmd(pcr);
 509         sd_cmd_set_data_len(pcr, data->blocks, data->blksz);
 510         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
 511                         DMA_DONE_INT, DMA_DONE_INT);
 512         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3,
 513                 0xFF, (u8)(data_len >> 24));
 514         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2,
 515                 0xFF, (u8)(data_len >> 16));
 516         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1,
 517                 0xFF, (u8)(data_len >> 8));
 518         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len);
 519         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
 520                 0x03 | DMA_PACK_SIZE_MASK,
 521                 DMA_DIR_TO_CARD | DMA_EN | DMA_512);
 522         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
 523                         0x01, RING_BUFFER);
 524         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2);
 525         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
 526                         SD_TRANSFER_START | SD_TM_AUTO_WRITE_3);
 527         rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
 528                         SD_TRANSFER_END, SD_TRANSFER_END);
 529         rtsx_pci_send_cmd_no_wait(pcr);
 530         err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, 0, 10000);
 531         if (err < 0) {
 532                 sd_clear_error(host);
 533                 return err;
 534         }
 535
 536         return 0;
 537 }
 538
 539 static inline void sd_enable_initial_mode(struct realtek_pci_sdmmc *host)
 540 {
 541         rtsx_pci_write_register(host->pcr, SD_CFG1,
 542                         SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_128);
 543 }
 544
 545 static inline void sd_disable_initial_mode(struct realtek_pci_sdmmc *host)
 546 {
 547         rtsx_pci_write_register(host->pcr, SD_CFG1,
 548                         SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_0);
 549 }
 550
 551 static int sd_rw_multi(struct realtek_pci_sdmmc *host, struct mmc_request *mrq)
 552 {
 553         struct mmc_data *data = mrq->data;
 554         int err;
 555
 556         if (host->sg_count < 0) {
 557                 data->error = host->sg_count;
 558                 dev_dbg(sdmmc_dev(host), "%s: sg_count = %d is invalid\n",
 559                         __func__, host->sg_count);
 560                 return data->error;
 561         }
 562
 563         if (data->flags & MMC_DATA_READ) {
 564                 if (host->initial_mode)
 565                         sd_disable_initial_mode(host);
 566
 567                 err = sd_read_long_data(host, mrq);
 568
 569                 if (host->initial_mode)
 570                         sd_enable_initial_mode(host);
 571
 572                 return err;
 573         }
 574
 575         return sd_write_long_data(host, mrq);
 576 }
 577
 578 static void sd_normal_rw(struct realtek_pci_sdmmc *host,
 579                 struct mmc_request *mrq)
 580 {
 581         struct mmc_command *cmd = mrq->cmd;
 582         struct mmc_data *data = mrq->data;
 583         u8 *buf;
 584
 585         buf = kzalloc(data->blksz, GFP_NOIO);
 586         if (!buf) {
 587                 cmd->error = -ENOMEM;
 588                 return;
 589         }
 590
 591         if (data->flags & MMC_DATA_READ) {
 592                 if (host->initial_mode)
 593                         sd_disable_initial_mode(host);
 594
 595                 cmd->error = sd_read_data(host, cmd, (u16)data->blksz, buf,
 596                                 data->blksz, 200);
 597
 598                 if (host->initial_mode)
 599                         sd_enable_initial_mode(host);
 600
 601                 sg_copy_from_buffer(data->sg, data->sg_len, buf, data->blksz);
 602         } else {
 603                 sg_copy_to_buffer(data->sg, data->sg_len, buf, data->blksz);
 604
 605                 cmd->error = sd_write_data(host, cmd, (u16)data->blksz, buf,
 606                                 data->blksz, 200);
 607         }
 608
 609         kfree(buf);
 610 }
 611
 612 static int sd_change_phase(struct realtek_pci_sdmmc *host,
 613                 u8 sample_point, bool rx)
 614 {
 615         struct rtsx_pcr *pcr = host->pcr;
 616         u16 SD_VP_CTL = 0;
 617         dev_dbg(sdmmc_dev(host), "%s(%s): sample_point = %d\n",
 618                         __func__, rx ? "RX" : "TX", sample_point);
 619
 620         rtsx_pci_write_register(pcr, CLK_CTL, CHANGE_CLK, CHANGE_CLK);
 621         if (rx) {
 622                 SD_VP_CTL = SD_VPRX_CTL;
 623                 rtsx_pci_write_register(pcr, SD_VPRX_CTL,
 624                         PHASE_SELECT_MASK, sample_point);
 625         } else {
 626                 SD_VP_CTL = SD_VPTX_CTL;
 627                 rtsx_pci_write_register(pcr, SD_VPTX_CTL,
 628                         PHASE_SELECT_MASK, sample_point);
 629         }
 630         rtsx_pci_write_register(pcr, SD_VP_CTL, PHASE_NOT_RESET, 0);
 631         rtsx_pci_write_register(pcr, SD_VP_CTL, PHASE_NOT_RESET,
 632                                 PHASE_NOT_RESET);
 633         rtsx_pci_write_register(pcr, CLK_CTL, CHANGE_CLK, 0);
 634         rtsx_pci_write_register(pcr, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
 635
 636         return 0;
 637 }
 638
 639 static inline u32 test_phase_bit(u32 phase_map, unsigned int bit)
 640 {
 641         bit %= RTSX_PHASE_MAX;
 642         return phase_map & (1 << bit);
 643 }
 644
 645 static int sd_get_phase_len(u32 phase_map, unsigned int start_bit)
 646 {
 647         int i;
 648
 649         for (i = 0; i < RTSX_PHASE_MAX; i++) {
 650                 if (test_phase_bit(phase_map, start_bit + i) == 0)
 651                         return i;
 652         }
 653         return RTSX_PHASE_MAX;
 654 }
 655
 656 static u8 sd_search_final_phase(struct realtek_pci_sdmmc *host, u32 phase_map)
 657 {
 658         int start = 0, len = 0;
 659         int start_final = 0, len_final = 0;
 660         u8 final_phase = 0xFF;
 661
 662         if (phase_map == 0) {
 663                 dev_err(sdmmc_dev(host), "phase error: [map:%x]\n", phase_map);
 664                 return final_phase;
 665         }
 666
 667         while (start < RTSX_PHASE_MAX) {
 668                 len = sd_get_phase_len(phase_map, start);
 669                 if (len_final < len) {
 670                         start_final = start;
 671                         len_final = len;
 672                 }
 673                 start += len ? len : 1;
 674         }
 675
 676         final_phase = (start_final + len_final / 2) % RTSX_PHASE_MAX;
 677         dev_dbg(sdmmc_dev(host), "phase: [map:%x] [maxlen:%d] [final:%d]\n",
 678                 phase_map, len_final, final_phase);
 679
 680         return final_phase;
 681 }
 682
 683 static void sd_wait_data_idle(struct realtek_pci_sdmmc *host)
 684 {
 685         int i;
 686         u8 val = 0;
 687
 688         for (i = 0; i < 100; i++) {
 689                 rtsx_pci_read_register(host->pcr, SD_DATA_STATE, &val);
 690                 if (val & SD_DATA_IDLE)
 691                         return;
 692
 693                 udelay(100);
 694         }
 695 }
 696
 697 static int sd_tuning_rx_cmd(struct realtek_pci_sdmmc *host,
 698                 u8 opcode, u8 sample_point)
 699 {
 700         int err;
 701         struct mmc_command cmd = {};
 702         struct rtsx_pcr *pcr = host->pcr;
 703
 704         sd_change_phase(host, sample_point, true);
 705
 706         rtsx_pci_write_register(pcr, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN,
 707                 SD_RSP_80CLK_TIMEOUT_EN);
 708
 709         cmd.opcode = opcode;
 710         err = sd_read_data(host, &cmd, 0x40, NULL, 0, 100);
 711         if (err < 0) {
 712                 /* Wait till SD DATA IDLE */
 713                 sd_wait_data_idle(host);
 714                 sd_clear_error(host);
 715                 rtsx_pci_write_register(pcr, SD_CFG3,
 716                         SD_RSP_80CLK_TIMEOUT_EN, 0);
 717                 return err;
 718         }
 719
 720         rtsx_pci_write_register(pcr, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0);
 721         return 0;
 722 }
 723
 724 static int sd_tuning_phase(struct realtek_pci_sdmmc *host,
 725                 u8 opcode, u32 *phase_map)
 726 {
 727         int err, i;
 728         u32 raw_phase_map = 0;
 729
 730         for (i = 0; i < RTSX_PHASE_MAX; i++) {
 731                 err = sd_tuning_rx_cmd(host, opcode, (u8)i);
 732                 if (err == 0)
 733                         raw_phase_map |= 1 << i;
 734         }
 735
 736         if (phase_map)
 737                 *phase_map = raw_phase_map;
 738
 739         return 0;
 740 }
 741
 742 static int sd_tuning_rx(struct realtek_pci_sdmmc *host, u8 opcode)
 743 {
 744         int err, i;
 745         u32 raw_phase_map[RX_TUNING_CNT] = {0}, phase_map;
 746         u8 final_phase;
 747
 748         for (i = 0; i < RX_TUNING_CNT; i++) {
 749                 err = sd_tuning_phase(host, opcode, &(raw_phase_map[i]));
 750                 if (err < 0)
 751                         return err;
 752
 753                 if (raw_phase_map[i] == 0)
 754                         break;
 755         }
 756
 757         phase_map = 0xFFFFFFFF;
 758         for (i = 0; i < RX_TUNING_CNT; i++) {
 759                 dev_dbg(sdmmc_dev(host), "RX raw_phase_map[%d] = 0x%08x\n",
 760                                 i, raw_phase_map[i]);
 761                 phase_map &= raw_phase_map[i];
 762         }
 763         dev_dbg(sdmmc_dev(host), "RX phase_map = 0x%08x\n", phase_map);
 764
 765         if (phase_map) {
 766                 final_phase = sd_search_final_phase(host, phase_map);
 767                 if (final_phase == 0xFF)
 768                         return -EINVAL;
 769
 770                 err = sd_change_phase(host, final_phase, true);
 771                 if (err < 0)
 772                         return err;
 773         } else {
 774                 return -EINVAL;
 775         }
 776
 777         return 0;
 778 }
 779
 780 static inline int sdio_extblock_cmd(struct mmc_command *cmd,
 781         struct mmc_data *data)
 782 {
 783         return (cmd->opcode == SD_IO_RW_EXTENDED) && (data->blksz == 512);
 784 }
 785
 786 static inline int sd_rw_cmd(struct mmc_command *cmd)
 787 {
 788         return mmc_op_multi(cmd->opcode) ||
 789                 (cmd->opcode == MMC_READ_SINGLE_BLOCK) ||
 790                 (cmd->opcode == MMC_WRITE_BLOCK);
 791 }
 792
 793 static void sd_request(struct work_struct *work)
 794 {
 795         struct realtek_pci_sdmmc *host = container_of(work,
 796                         struct realtek_pci_sdmmc, work);
 797         struct rtsx_pcr *pcr = host->pcr;
 798
 799         struct mmc_host *mmc = host->mmc;
 800         struct mmc_request *mrq = host->mrq;
 801         struct mmc_command *cmd = mrq->cmd;
 802         struct mmc_data *data = mrq->data;
 803
 804         unsigned int data_size = 0;
 805         int err;
 806
 807         if (host->eject || !sd_get_cd_int(host)) {
 808                 cmd->error = -ENOMEDIUM;
 809                 goto finish;
 810         }
 811
 812         err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
 813         if (err) {
 814                 cmd->error = err;
 815                 goto finish;
 816         }
 817
 818         mutex_lock(&pcr->pcr_mutex);
 819
 820         rtsx_pci_start_run(pcr);
 821
 822         rtsx_pci_switch_clock(pcr, host->clock, host->ssc_depth,
 823                         host->initial_mode, host->double_clk, host->vpclk);
 824         rtsx_pci_write_register(pcr, CARD_SELECT, 0x07, SD_MOD_SEL);
 825         rtsx_pci_write_register(pcr, CARD_SHARE_MODE,
 826                         CARD_SHARE_MASK, CARD_SHARE_48_SD);
 827
 828         mutex_lock(&host->host_mutex);
 829         host->mrq = mrq;
 830         mutex_unlock(&host->host_mutex);
 831
 832         if (mrq->data)
 833                 data_size = data->blocks * data->blksz;
 834
 835         if (!data_size) {
 836                 sd_send_cmd_get_rsp(host, cmd);
 837         } else if (sd_rw_cmd(cmd) || sdio_extblock_cmd(cmd, data)) {
 838                 cmd->error = sd_rw_multi(host, mrq);
 839                 if (!host->using_cookie)
 840                         sdmmc_post_req(host->mmc, host->mrq, 0);
 841
 842                 if (mmc_op_multi(cmd->opcode) && mrq->stop)
 843                         sd_send_cmd_get_rsp(host, mrq->stop);
 844         } else {
 845                 sd_normal_rw(host, mrq);
 846         }
 847
 848         if (mrq->data) {
 849                 if (cmd->error || data->error)
 850                         data->bytes_xfered = 0;
 851                 else
 852                         data->bytes_xfered = data->blocks * data->blksz;
 853         }
 854
 855         mutex_unlock(&pcr->pcr_mutex);
 856
 857 finish:
 858         if (cmd->error) {
 859                 dev_dbg(sdmmc_dev(host), "CMD %d 0x%08x error(%d)\n",
 860                         cmd->opcode, cmd->arg, cmd->error);
 861         }
 862
 863         mutex_lock(&host->host_mutex);
 864         host->mrq = NULL;
 865         mutex_unlock(&host->host_mutex);
 866
 867         mmc_request_done(mmc, mrq);
 868 }
 869
 870 static void sdmmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
 871 {
 872         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
 873         struct mmc_data *data = mrq->data;
 874
 875         mutex_lock(&host->host_mutex);
 876         host->mrq = mrq;
 877         mutex_unlock(&host->host_mutex);
 878
 879         if (sd_rw_cmd(mrq->cmd) || sdio_extblock_cmd(mrq->cmd, data))
 880                 host->using_cookie = sd_pre_dma_transfer(host, data, false);
 881
 882         schedule_work(&host->work);
 883 }
 884
 885 static int sd_set_bus_width(struct realtek_pci_sdmmc *host,
 886                 unsigned char bus_width)
 887 {
 888         int err = 0;
 889         u8 width[] = {
 890                 [MMC_BUS_WIDTH_1] = SD_BUS_WIDTH_1BIT,
 891                 [MMC_BUS_WIDTH_4] = SD_BUS_WIDTH_4BIT,
 892                 [MMC_BUS_WIDTH_8] = SD_BUS_WIDTH_8BIT,
 893         };
 894
 895         if (bus_width <= MMC_BUS_WIDTH_8)
 896                 err = rtsx_pci_write_register(host->pcr, SD_CFG1,
 897                                 0x03, width[bus_width]);
 898
 899         return err;
 900 }
 901
 902 static int sd_power_on(struct realtek_pci_sdmmc *host, unsigned char power_mode)
 903 {
 904         struct rtsx_pcr *pcr = host->pcr;
 905         int err;
 906
 907         if (host->prev_power_state == MMC_POWER_ON)
 908                 return 0;
 909
 910         if (host->prev_power_state == MMC_POWER_UP) {
 911                 rtsx_pci_write_register(pcr, SD_BUS_STAT, SD_CLK_TOGGLE_EN, 0);
 912                 goto finish;
 913         }
 914
 915         msleep(100);
 916
 917         rtsx_pci_init_cmd(pcr);
 918         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SELECT, 0x07, SD_MOD_SEL);
 919         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SHARE_MODE,
 920                         CARD_SHARE_MASK, CARD_SHARE_48_SD);
 921         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN,
 922                         SD_CLK_EN, SD_CLK_EN);
 923         err = rtsx_pci_send_cmd(pcr, 100);
 924         if (err < 0)
 925                 return err;
 926
 927         err = rtsx_pci_card_pull_ctl_enable(pcr, RTSX_SD_CARD);
 928         if (err < 0)
 929                 return err;
 930
 931         err = rtsx_pci_card_power_on(pcr, RTSX_SD_CARD);
 932         if (err < 0)
 933                 return err;
 934
 935         mdelay(1);
 936
 937         err = rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN);
 938         if (err < 0)
 939                 return err;
 940
 941         /* send at least 74 clocks */
 942         rtsx_pci_write_register(pcr, SD_BUS_STAT, SD_CLK_TOGGLE_EN, SD_CLK_TOGGLE_EN);
 943
 944 finish:
 945         host->prev_power_state = power_mode;
 946         return 0;
 947 }
 948
 949 static int sd_power_off(struct realtek_pci_sdmmc *host)
 950 {
 951         struct rtsx_pcr *pcr = host->pcr;
 952         int err;
 953
 954         host->prev_power_state = MMC_POWER_OFF;
 955
 956         rtsx_pci_init_cmd(pcr);
 957
 958         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, 0);
 959         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0);
 960
 961         err = rtsx_pci_send_cmd(pcr, 100);
 962         if (err < 0)
 963                 return err;
 964
 965         err = rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);
 966         if (err < 0)
 967                 return err;
 968
 969         return rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD);
 970 }
 971
 972 static int sd_set_power_mode(struct realtek_pci_sdmmc *host,
 973                 unsigned char power_mode)
 974 {
 975         int err;
 976
 977         if (power_mode == MMC_POWER_OFF)
 978                 err = sd_power_off(host);
 979         else
 980                 err = sd_power_on(host, power_mode);
 981
 982         return err;
 983 }
 984
 985 static int sd_set_timing(struct realtek_pci_sdmmc *host, unsigned char timing)
 986 {
 987         struct rtsx_pcr *pcr = host->pcr;
 988         int err = 0;
 989
 990         rtsx_pci_init_cmd(pcr);
 991
 992         switch (timing) {
 993         case MMC_TIMING_UHS_SDR104:
 994         case MMC_TIMING_UHS_SDR50:
 995                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
 996                                 0x0C | SD_ASYNC_FIFO_NOT_RST,
 997                                 SD_30_MODE | SD_ASYNC_FIFO_NOT_RST);
 998                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
 999                                 CLK_LOW_FREQ, CLK_LOW_FREQ);
1000                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1001                                 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
1002                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1003                 break;
1004
1005         case MMC_TIMING_MMC_DDR52:
1006         case MMC_TIMING_UHS_DDR50:
1007                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
1008                                 0x0C | SD_ASYNC_FIFO_NOT_RST,
1009                                 SD_DDR_MODE | SD_ASYNC_FIFO_NOT_RST);
1010                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1011                                 CLK_LOW_FREQ, CLK_LOW_FREQ);
1012                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1013                                 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
1014                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1015                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
1016                                 DDR_VAR_TX_CMD_DAT, DDR_VAR_TX_CMD_DAT);
1017                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
1018                                 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD,
1019                                 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD);
1020                 break;
1021
1022         case MMC_TIMING_MMC_HS:
1023         case MMC_TIMING_SD_HS:
1024                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
1025                                 0x0C, SD_20_MODE);
1026                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1027                                 CLK_LOW_FREQ, CLK_LOW_FREQ);
1028                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1029                                 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
1030                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1031                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
1032                                 SD20_TX_SEL_MASK, SD20_TX_14_AHEAD);
1033                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
1034                                 SD20_RX_SEL_MASK, SD20_RX_14_DELAY);
1035                 break;
1036
1037         default:
1038                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
1039                                 SD_CFG1, 0x0C, SD_20_MODE);
1040                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1041                                 CLK_LOW_FREQ, CLK_LOW_FREQ);
1042                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1043                                 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
1044                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1045                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
1046                                 SD_PUSH_POINT_CTL, 0xFF, 0);
1047                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
1048                                 SD20_RX_SEL_MASK, SD20_RX_POS_EDGE);
1049                 break;
1050         }
1051
1052         err = rtsx_pci_send_cmd(pcr, 100);
1053
1054         return err;
1055 }
1056
1057 static void sdmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1058 {
1059         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1060         struct rtsx_pcr *pcr = host->pcr;
1061
1062         if (host->eject)
1063                 return;
1064
1065         if (rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD))
1066                 return;
1067
1068         mutex_lock(&pcr->pcr_mutex);
1069
1070         rtsx_pci_start_run(pcr);
1071
1072         sd_set_bus_width(host, ios->bus_width);
1073         sd_set_power_mode(host, ios->power_mode);
1074         sd_set_timing(host, ios->timing);
1075
1076         host->vpclk = false;
1077         host->double_clk = true;
1078
1079         switch (ios->timing) {
1080         case MMC_TIMING_UHS_SDR104:
1081         case MMC_TIMING_UHS_SDR50:
1082                 host->ssc_depth = RTSX_SSC_DEPTH_2M;
1083                 host->vpclk = true;
1084                 host->double_clk = false;
1085                 break;
1086         case MMC_TIMING_MMC_DDR52:
1087         case MMC_TIMING_UHS_DDR50:
1088         case MMC_TIMING_UHS_SDR25:
1089                 host->ssc_depth = RTSX_SSC_DEPTH_1M;
1090                 break;
1091         default:
1092                 host->ssc_depth = RTSX_SSC_DEPTH_500K;
1093                 break;
1094         }
1095
1096         host->initial_mode = (ios->clock <= 1000000) ? true : false;
1097
1098         host->clock = ios->clock;
1099         rtsx_pci_switch_clock(pcr, ios->clock, host->ssc_depth,
1100                         host->initial_mode, host->double_clk, host->vpclk);
1101
1102         mutex_unlock(&pcr->pcr_mutex);
1103 }
1104
1105 static int sdmmc_get_ro(struct mmc_host *mmc)
1106 {
1107         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1108         struct rtsx_pcr *pcr = host->pcr;
1109         int ro = 0;
1110         u32 val;
1111
1112         if (host->eject)
1113                 return -ENOMEDIUM;
1114
1115         mutex_lock(&pcr->pcr_mutex);
1116
1117         rtsx_pci_start_run(pcr);
1118
1119         /* Check SD mechanical write-protect switch */
1120         val = rtsx_pci_readl(pcr, RTSX_BIPR);
1121         dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val);
1122         if (val & SD_WRITE_PROTECT)
1123                 ro = 1;
1124
1125         mutex_unlock(&pcr->pcr_mutex);
1126
1127         return ro;
1128 }
1129
1130 static int sdmmc_get_cd(struct mmc_host *mmc)
1131 {
1132         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1133         struct rtsx_pcr *pcr = host->pcr;
1134         int cd = 0;
1135         u32 val;
1136
1137         if (host->eject)
1138                 return cd;
1139
1140         mutex_lock(&pcr->pcr_mutex);
1141
1142         rtsx_pci_start_run(pcr);
1143
1144         /* Check SD card detect */
1145         val = rtsx_pci_card_exist(pcr);
1146         dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val);
1147         if (val & SD_EXIST)
1148                 cd = 1;
1149
1150         mutex_unlock(&pcr->pcr_mutex);
1151
1152         return cd;
1153 }
1154
1155 static int sd_wait_voltage_stable_1(struct realtek_pci_sdmmc *host)
1156 {
1157         struct rtsx_pcr *pcr = host->pcr;
1158         int err;
1159         u8 stat;
1160
1161         /* Reference to Signal Voltage Switch Sequence in SD spec.
1162          * Wait for a period of time so that the card can drive SD_CMD and
1163          * SD_DAT[3:0] to low after sending back CMD11 response.
1164          */
1165         mdelay(1);
1166
1167         /* SD_CMD, SD_DAT[3:0] should be driven to low by card;
1168          * If either one of SD_CMD,SD_DAT[3:0] is not low,
1169          * abort the voltage switch sequence;
1170          */
1171         err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1172         if (err < 0)
1173                 return err;
1174
1175         if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1176                                 SD_DAT1_STATUS | SD_DAT0_STATUS))
1177                 return -EINVAL;
1178
1179         /* Stop toggle SD clock */
1180         err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1181                         0xFF, SD_CLK_FORCE_STOP);
1182         if (err < 0)
1183                 return err;
1184
1185         return 0;
1186 }
1187
1188 static int sd_wait_voltage_stable_2(struct realtek_pci_sdmmc *host)
1189 {
1190         struct rtsx_pcr *pcr = host->pcr;
1191         int err;
1192         u8 stat, mask, val;
1193
1194         /* Wait 1.8V output of voltage regulator in card stable */
1195         msleep(50);
1196
1197         /* Toggle SD clock again */
1198         err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN);
1199         if (err < 0)
1200                 return err;
1201
1202         /* Wait for a period of time so that the card can drive
1203          * SD_DAT[3:0] to high at 1.8V
1204          */
1205         msleep(20);
1206
1207         /* SD_CMD, SD_DAT[3:0] should be pulled high by host */
1208         err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1209         if (err < 0)
1210                 return err;
1211
1212         mask = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1213                 SD_DAT1_STATUS | SD_DAT0_STATUS;
1214         val = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1215                 SD_DAT1_STATUS | SD_DAT0_STATUS;
1216         if ((stat & mask) != val) {
1217                 dev_dbg(sdmmc_dev(host),
1218                         "%s: SD_BUS_STAT = 0x%x\n", __func__, stat);
1219                 rtsx_pci_write_register(pcr, SD_BUS_STAT,
1220                                 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
1221                 rtsx_pci_write_register(pcr, CARD_CLK_EN, 0xFF, 0);
1222                 return -EINVAL;
1223         }
1224
1225         return 0;
1226 }
1227
1228 static int sdmmc_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1229 {
1230         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1231         struct rtsx_pcr *pcr = host->pcr;
1232         int err = 0;
1233         u8 voltage;
1234
1235         dev_dbg(sdmmc_dev(host), "%s: signal_voltage = %d\n",
1236                         __func__, ios->signal_voltage);
1237
1238         if (host->eject)
1239                 return -ENOMEDIUM;
1240
1241         err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
1242         if (err)
1243                 return err;
1244
1245         mutex_lock(&pcr->pcr_mutex);
1246
1247         rtsx_pci_start_run(pcr);
1248
1249         if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1250                 voltage = OUTPUT_3V3;
1251         else
1252                 voltage = OUTPUT_1V8;
1253
1254         if (voltage == OUTPUT_1V8) {
1255                 err = sd_wait_voltage_stable_1(host);
1256                 if (err < 0)
1257                         goto out;
1258         }
1259
1260         err = rtsx_pci_switch_output_voltage(pcr, voltage);
1261         if (err < 0)
1262                 goto out;
1263
1264         if (voltage == OUTPUT_1V8) {
1265                 err = sd_wait_voltage_stable_2(host);
1266                 if (err < 0)
1267                         goto out;
1268         }
1269
1270 out:
1271         /* Stop toggle SD clock in idle */
1272         err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1273                         SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
1274
1275         mutex_unlock(&pcr->pcr_mutex);
1276
1277         return err;
1278 }
1279
1280 static int sdmmc_execute_tuning(struct mmc_host *mmc, u32 opcode)
1281 {
1282         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1283         struct rtsx_pcr *pcr = host->pcr;
1284         int err = 0;
1285
1286         if (host->eject)
1287                 return -ENOMEDIUM;
1288
1289         err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
1290         if (err)
1291                 return err;
1292
1293         mutex_lock(&pcr->pcr_mutex);
1294
1295         rtsx_pci_start_run(pcr);
1296
1297         /* Set initial TX phase */
1298         switch (mmc->ios.timing) {
1299         case MMC_TIMING_UHS_SDR104:
1300                 err = sd_change_phase(host, SDR104_TX_PHASE(pcr), false);
1301                 break;
1302
1303         case MMC_TIMING_UHS_SDR50:
1304                 err = sd_change_phase(host, SDR50_TX_PHASE(pcr), false);
1305                 break;
1306
1307         case MMC_TIMING_UHS_DDR50:
1308                 err = sd_change_phase(host, DDR50_TX_PHASE(pcr), false);
1309                 break;
1310
1311         default:
1312                 err = 0;
1313         }
1314
1315         if (err)
1316                 goto out;
1317
1318         /* Tuning RX phase */
1319         if ((mmc->ios.timing == MMC_TIMING_UHS_SDR104) ||
1320                         (mmc->ios.timing == MMC_TIMING_UHS_SDR50))
1321                 err = sd_tuning_rx(host, opcode);
1322         else if (mmc->ios.timing == MMC_TIMING_UHS_DDR50)
1323                 err = sd_change_phase(host, DDR50_RX_PHASE(pcr), true);
1324
1325 out:
1326         mutex_unlock(&pcr->pcr_mutex);
1327
1328         return err;
1329 }
1330
1331 static const struct mmc_host_ops realtek_pci_sdmmc_ops = {
1332         .pre_req = sdmmc_pre_req,
1333         .post_req = sdmmc_post_req,
1334         .request = sdmmc_request,
1335         .set_ios = sdmmc_set_ios,
1336         .get_ro = sdmmc_get_ro,
1337         .get_cd = sdmmc_get_cd,
1338         .start_signal_voltage_switch = sdmmc_switch_voltage,
1339         .execute_tuning = sdmmc_execute_tuning,
1340 };
1341
1342 static void init_extra_caps(struct realtek_pci_sdmmc *host)
1343 {
1344         struct mmc_host *mmc = host->mmc;
1345         struct rtsx_pcr *pcr = host->pcr;
1346
1347         dev_dbg(sdmmc_dev(host), "pcr->extra_caps = 0x%x\n", pcr->extra_caps);
1348
1349         if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50)
1350                 mmc->caps |= MMC_CAP_UHS_SDR50;
1351         if (pcr->extra_caps & EXTRA_CAPS_SD_SDR104)
1352                 mmc->caps |= MMC_CAP_UHS_SDR104;
1353         if (pcr->extra_caps & EXTRA_CAPS_SD_DDR50)
1354                 mmc->caps |= MMC_CAP_UHS_DDR50;
1355         if (pcr->extra_caps & EXTRA_CAPS_MMC_HSDDR)
1356                 mmc->caps |= MMC_CAP_1_8V_DDR;
1357         if (pcr->extra_caps & EXTRA_CAPS_MMC_8BIT)
1358                 mmc->caps |= MMC_CAP_8_BIT_DATA;
1359         if (pcr->extra_caps & EXTRA_CAPS_NO_MMC)
1360                 mmc->caps2 |= MMC_CAP2_NO_MMC;
1361 }
1362
1363 static void realtek_init_host(struct realtek_pci_sdmmc *host)
1364 {
1365         struct mmc_host *mmc = host->mmc;
1366
1367         mmc->f_min = 250000;
1368         mmc->f_max = 208000000;
1369         mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1370         mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED |
1371                 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_BUS_WIDTH_TEST |
1372                 MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
1373         mmc->caps2 = MMC_CAP2_NO_PRESCAN_POWERUP | MMC_CAP2_FULL_PWR_CYCLE;
1374         mmc->max_current_330 = 400;
1375         mmc->max_current_180 = 800;
1376         mmc->ops = &realtek_pci_sdmmc_ops;
1377
1378         init_extra_caps(host);
1379
1380         mmc->max_segs = 256;
1381         mmc->max_seg_size = 65536;
1382         mmc->max_blk_size = 512;
1383         mmc->max_blk_count = 65535;
1384         mmc->max_req_size = 524288;
1385 }
1386
1387 static void rtsx_pci_sdmmc_card_event(struct platform_device *pdev)
1388 {
1389         struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1390
1391         host->cookie = -1;
1392         mmc_detect_change(host->mmc, 0);
1393 }
1394
1395 static int rtsx_pci_sdmmc_drv_probe(struct platform_device *pdev)
1396 {
1397         struct mmc_host *mmc;
1398         struct realtek_pci_sdmmc *host;
1399         struct rtsx_pcr *pcr;
1400         struct pcr_handle *handle = pdev->dev.platform_data;
1401
1402         if (!handle)
1403                 return -ENXIO;
1404
1405         pcr = handle->pcr;
1406         if (!pcr)
1407                 return -ENXIO;
1408
1409         dev_dbg(&(pdev->dev), ": Realtek PCI-E SDMMC controller found\n");
1410
1411         mmc = mmc_alloc_host(sizeof(*host), &pdev->dev);
1412         if (!mmc)
1413                 return -ENOMEM;
1414
1415         host = mmc_priv(mmc);
1416         host->pcr = pcr;
1417         mmc->ios.power_delay_ms = 5;
1418         host->mmc = mmc;
1419         host->pdev = pdev;
1420         host->cookie = -1;
1421         host->prev_power_state = MMC_POWER_OFF;
1422         INIT_WORK(&host->work, sd_request);
1423         platform_set_drvdata(pdev, host);
1424         pcr->slots[RTSX_SD_CARD].p_dev = pdev;
1425         pcr->slots[RTSX_SD_CARD].card_event = rtsx_pci_sdmmc_card_event;
1426
1427         mutex_init(&host->host_mutex);
1428
1429         realtek_init_host(host);
1430
1431         mmc_add_host(mmc);
1432
1433         return 0;
1434 }
1435
1436 static int rtsx_pci_sdmmc_drv_remove(struct platform_device *pdev)
1437 {
1438         struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1439         struct rtsx_pcr *pcr;
1440         struct mmc_host *mmc;
1441
1442         if (!host)
1443                 return 0;
1444
1445         pcr = host->pcr;
1446         pcr->slots[RTSX_SD_CARD].p_dev = NULL;
1447         pcr->slots[RTSX_SD_CARD].card_event = NULL;
1448         mmc = host->mmc;
1449
1450         cancel_work_sync(&host->work);
1451
1452         mutex_lock(&host->host_mutex);
1453         if (host->mrq) {
1454                 dev_dbg(&(pdev->dev),
1455                         "%s: Controller removed during transfer\n",
1456                         mmc_hostname(mmc));
1457
1458                 rtsx_pci_complete_unfinished_transfer(pcr);
1459
1460                 host->mrq->cmd->error = -ENOMEDIUM;
1461                 if (host->mrq->stop)
1462                         host->mrq->stop->error = -ENOMEDIUM;
1463                 mmc_request_done(mmc, host->mrq);
1464         }
1465         mutex_unlock(&host->host_mutex);
1466
1467         mmc_remove_host(mmc);
1468         host->eject = true;
1469
1470         flush_work(&host->work);
1471
1472         mmc_free_host(mmc);
1473
1474         dev_dbg(&(pdev->dev),
1475                 ": Realtek PCI-E SDMMC controller has been removed\n");
1476
1477         return 0;
1478 }
1479
1480 static const struct platform_device_id rtsx_pci_sdmmc_ids[] = {
1481         {
1482                 .name = DRV_NAME_RTSX_PCI_SDMMC,
1483         }, {
1484                 /* sentinel */
1485         }
1486 };
1487 MODULE_DEVICE_TABLE(platform, rtsx_pci_sdmmc_ids);
1488
1489 static struct platform_driver rtsx_pci_sdmmc_driver = {
1490         .probe          = rtsx_pci_sdmmc_drv_probe,
1491         .remove         = rtsx_pci_sdmmc_drv_remove,
1492         .id_table       = rtsx_pci_sdmmc_ids,
1493         .driver         = {
1494                 .name   = DRV_NAME_RTSX_PCI_SDMMC,
1495                 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1496         },
1497 };
1498 module_platform_driver(rtsx_pci_sdmmc_driver);
1499
1500 MODULE_LICENSE("GPL");
1501 MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
1502 MODULE_DESCRIPTION("Realtek PCI-E SD/MMC Card Host Driver");