1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Realtek PCI-Express SD/MMC Card Interface driver
4 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
7 * Wei WANG <wei_wang@realsil.com.cn>
10 #include <linux/module.h>
11 #include <linux/slab.h>
12 #include <linux/highmem.h>
13 #include <linux/delay.h>
14 #include <linux/platform_device.h>
15 #include <linux/workqueue.h>
16 #include <linux/mmc/host.h>
17 #include <linux/mmc/mmc.h>
18 #include <linux/mmc/sd.h>
19 #include <linux/mmc/sdio.h>
20 #include <linux/mmc/card.h>
21 #include <linux/rtsx_pci.h>
22 #include <asm/unaligned.h>
24 struct realtek_pci_sdmmc {
25 struct platform_device *pdev;
28 struct mmc_request *mrq;
29 #define SDMMC_WORKQ_NAME "rtsx_pci_sdmmc_workq"
31 struct work_struct work;
32 struct mutex host_mutex;
47 static inline struct device *sdmmc_dev(struct realtek_pci_sdmmc *host)
49 return &(host->pdev->dev);
52 static inline void sd_clear_error(struct realtek_pci_sdmmc *host)
54 rtsx_pci_write_register(host->pcr, CARD_STOP,
55 SD_STOP | SD_CLR_ERR, SD_STOP | SD_CLR_ERR);
59 static void dump_reg_range(struct realtek_pci_sdmmc *host, u16 start, u16 end)
61 u16 len = end - start + 1;
65 for (i = 0; i < len; i += 8) {
67 int n = min(8, len - i);
69 memset(&data, 0, sizeof(data));
70 for (j = 0; j < n; j++)
71 rtsx_pci_read_register(host->pcr, start + i + j,
73 dev_dbg(sdmmc_dev(host), "0x%04X(%d): %8ph\n",
78 static void sd_print_debug_regs(struct realtek_pci_sdmmc *host)
80 dump_reg_range(host, 0xFDA0, 0xFDB3);
81 dump_reg_range(host, 0xFD52, 0xFD69);
84 #define sd_print_debug_regs(host)
87 static inline int sd_get_cd_int(struct realtek_pci_sdmmc *host)
89 return rtsx_pci_readl(host->pcr, RTSX_BIPR) & SD_EXIST;
92 static void sd_cmd_set_sd_cmd(struct rtsx_pcr *pcr, struct mmc_command *cmd)
94 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0, 0xFF,
95 SD_CMD_START | cmd->opcode);
96 rtsx_pci_write_be32(pcr, SD_CMD1, cmd->arg);
99 static void sd_cmd_set_data_len(struct rtsx_pcr *pcr, u16 blocks, u16 blksz)
101 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, blocks);
102 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, blocks >> 8);
103 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, blksz);
104 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, blksz >> 8);
107 static int sd_response_type(struct mmc_command *cmd)
109 switch (mmc_resp_type(cmd)) {
111 return SD_RSP_TYPE_R0;
113 return SD_RSP_TYPE_R1;
114 case MMC_RSP_R1_NO_CRC:
115 return SD_RSP_TYPE_R1 | SD_NO_CHECK_CRC7;
117 return SD_RSP_TYPE_R1b;
119 return SD_RSP_TYPE_R2;
121 return SD_RSP_TYPE_R3;
127 static int sd_status_index(int resp_type)
129 if (resp_type == SD_RSP_TYPE_R0)
131 else if (resp_type == SD_RSP_TYPE_R2)
137 * sd_pre_dma_transfer - do dma_map_sg() or using cookie
139 * @pre: if called in pre_req()
141 * 0 - do dma_map_sg()
144 static int sd_pre_dma_transfer(struct realtek_pci_sdmmc *host,
145 struct mmc_data *data, bool pre)
147 struct rtsx_pcr *pcr = host->pcr;
148 int read = data->flags & MMC_DATA_READ;
150 int using_cookie = 0;
152 if (!pre && data->host_cookie && data->host_cookie != host->cookie) {
153 dev_err(sdmmc_dev(host),
154 "error: data->host_cookie = %d, host->cookie = %d\n",
155 data->host_cookie, host->cookie);
156 data->host_cookie = 0;
159 if (pre || data->host_cookie != host->cookie) {
160 count = rtsx_pci_dma_map_sg(pcr, data->sg, data->sg_len, read);
162 count = host->cookie_sg_count;
167 host->cookie_sg_count = count;
168 if (++host->cookie < 0)
170 data->host_cookie = host->cookie;
172 host->sg_count = count;
178 static void sdmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
180 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
181 struct mmc_data *data = mrq->data;
183 if (data->host_cookie) {
184 dev_err(sdmmc_dev(host),
185 "error: reset data->host_cookie = %d\n",
187 data->host_cookie = 0;
190 sd_pre_dma_transfer(host, data, true);
191 dev_dbg(sdmmc_dev(host), "pre dma sg: %d\n", host->cookie_sg_count);
194 static void sdmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
197 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
198 struct rtsx_pcr *pcr = host->pcr;
199 struct mmc_data *data = mrq->data;
200 int read = data->flags & MMC_DATA_READ;
202 rtsx_pci_dma_unmap_sg(pcr, data->sg, data->sg_len, read);
203 data->host_cookie = 0;
206 static void sd_send_cmd_get_rsp(struct realtek_pci_sdmmc *host,
207 struct mmc_command *cmd)
209 struct rtsx_pcr *pcr = host->pcr;
210 u8 cmd_idx = (u8)cmd->opcode;
218 bool clock_toggled = false;
220 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
221 __func__, cmd_idx, arg);
223 rsp_type = sd_response_type(cmd);
227 stat_idx = sd_status_index(rsp_type);
229 if (rsp_type == SD_RSP_TYPE_R1b)
230 timeout = cmd->busy_timeout ? cmd->busy_timeout : 3000;
232 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
233 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
234 0xFF, SD_CLK_TOGGLE_EN);
238 clock_toggled = true;
241 rtsx_pci_init_cmd(pcr);
242 sd_cmd_set_sd_cmd(pcr, cmd);
243 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, rsp_type);
244 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
245 0x01, PINGPONG_BUFFER);
246 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
247 0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START);
248 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
249 SD_TRANSFER_END | SD_STAT_IDLE,
250 SD_TRANSFER_END | SD_STAT_IDLE);
252 if (rsp_type == SD_RSP_TYPE_R2) {
253 /* Read data from ping-pong buffer */
254 for (i = PPBUF_BASE2; i < PPBUF_BASE2 + 16; i++)
255 rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
256 } else if (rsp_type != SD_RSP_TYPE_R0) {
257 /* Read data from SD_CMDx registers */
258 for (i = SD_CMD0; i <= SD_CMD4; i++)
259 rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
262 rtsx_pci_add_cmd(pcr, READ_REG_CMD, SD_STAT1, 0, 0);
264 err = rtsx_pci_send_cmd(pcr, timeout);
266 sd_print_debug_regs(host);
267 sd_clear_error(host);
268 dev_dbg(sdmmc_dev(host),
269 "rtsx_pci_send_cmd error (err = %d)\n", err);
273 if (rsp_type == SD_RSP_TYPE_R0) {
278 /* Eliminate returned value of CHECK_REG_CMD */
279 ptr = rtsx_pci_get_cmd_data(pcr) + 1;
281 /* Check (Start,Transmission) bit of Response */
282 if ((ptr[0] & 0xC0) != 0) {
284 dev_dbg(sdmmc_dev(host), "Invalid response bit\n");
289 if (!(rsp_type & SD_NO_CHECK_CRC7)) {
290 if (ptr[stat_idx] & SD_CRC7_ERR) {
292 dev_dbg(sdmmc_dev(host), "CRC7 error\n");
297 if (rsp_type == SD_RSP_TYPE_R2) {
299 * The controller offloads the last byte {CRC-7, end bit 1'b1}
300 * of response type R2. Assign dummy CRC, 0, and end bit to the
301 * byte(ptr[16], goes into the LSB of resp[3] later).
305 for (i = 0; i < 4; i++) {
306 cmd->resp[i] = get_unaligned_be32(ptr + 1 + i * 4);
307 dev_dbg(sdmmc_dev(host), "cmd->resp[%d] = 0x%08x\n",
311 cmd->resp[0] = get_unaligned_be32(ptr + 1);
312 dev_dbg(sdmmc_dev(host), "cmd->resp[0] = 0x%08x\n",
319 if (err && clock_toggled)
320 rtsx_pci_write_register(pcr, SD_BUS_STAT,
321 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
324 static int sd_read_data(struct realtek_pci_sdmmc *host, struct mmc_command *cmd,
325 u16 byte_cnt, u8 *buf, int buf_len, int timeout)
327 struct rtsx_pcr *pcr = host->pcr;
331 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
332 __func__, cmd->opcode, cmd->arg);
337 if (cmd->opcode == MMC_SEND_TUNING_BLOCK)
338 trans_mode = SD_TM_AUTO_TUNING;
340 trans_mode = SD_TM_NORMAL_READ;
342 rtsx_pci_init_cmd(pcr);
343 sd_cmd_set_sd_cmd(pcr, cmd);
344 sd_cmd_set_data_len(pcr, 1, byte_cnt);
345 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
346 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
347 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6);
348 if (trans_mode != SD_TM_AUTO_TUNING)
349 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
350 CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
352 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
353 0xFF, trans_mode | SD_TRANSFER_START);
354 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
355 SD_TRANSFER_END, SD_TRANSFER_END);
357 err = rtsx_pci_send_cmd(pcr, timeout);
359 sd_print_debug_regs(host);
360 dev_dbg(sdmmc_dev(host),
361 "rtsx_pci_send_cmd fail (err = %d)\n", err);
365 if (buf && buf_len) {
366 err = rtsx_pci_read_ppbuf(pcr, buf, buf_len);
368 dev_dbg(sdmmc_dev(host),
369 "rtsx_pci_read_ppbuf fail (err = %d)\n", err);
377 static int sd_write_data(struct realtek_pci_sdmmc *host,
378 struct mmc_command *cmd, u16 byte_cnt, u8 *buf, int buf_len,
381 struct rtsx_pcr *pcr = host->pcr;
384 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
385 __func__, cmd->opcode, cmd->arg);
390 sd_send_cmd_get_rsp(host, cmd);
394 if (buf && buf_len) {
395 err = rtsx_pci_write_ppbuf(pcr, buf, buf_len);
397 dev_dbg(sdmmc_dev(host),
398 "rtsx_pci_write_ppbuf fail (err = %d)\n", err);
403 rtsx_pci_init_cmd(pcr);
404 sd_cmd_set_data_len(pcr, 1, byte_cnt);
405 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
406 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
407 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_0);
408 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
409 SD_TRANSFER_START | SD_TM_AUTO_WRITE_3);
410 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
411 SD_TRANSFER_END, SD_TRANSFER_END);
413 err = rtsx_pci_send_cmd(pcr, timeout);
415 sd_print_debug_regs(host);
416 dev_dbg(sdmmc_dev(host),
417 "rtsx_pci_send_cmd fail (err = %d)\n", err);
424 static int sd_read_long_data(struct realtek_pci_sdmmc *host,
425 struct mmc_request *mrq)
427 struct rtsx_pcr *pcr = host->pcr;
428 struct mmc_host *mmc = host->mmc;
429 struct mmc_card *card = mmc->card;
430 struct mmc_command *cmd = mrq->cmd;
431 struct mmc_data *data = mrq->data;
432 int uhs = mmc_card_uhs(card);
436 size_t data_len = data->blksz * data->blocks;
438 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
439 __func__, cmd->opcode, cmd->arg);
441 resp_type = sd_response_type(cmd);
446 cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
448 rtsx_pci_init_cmd(pcr);
449 sd_cmd_set_sd_cmd(pcr, cmd);
450 sd_cmd_set_data_len(pcr, data->blocks, data->blksz);
451 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
452 DMA_DONE_INT, DMA_DONE_INT);
453 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3,
454 0xFF, (u8)(data_len >> 24));
455 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2,
456 0xFF, (u8)(data_len >> 16));
457 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1,
458 0xFF, (u8)(data_len >> 8));
459 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len);
460 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
461 0x03 | DMA_PACK_SIZE_MASK,
462 DMA_DIR_FROM_CARD | DMA_EN | DMA_512);
463 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
465 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2 | resp_type);
466 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
467 SD_TRANSFER_START | SD_TM_AUTO_READ_2);
468 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
469 SD_TRANSFER_END, SD_TRANSFER_END);
470 rtsx_pci_send_cmd_no_wait(pcr);
472 err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, 1, 10000);
474 sd_print_debug_regs(host);
475 sd_clear_error(host);
482 static int sd_write_long_data(struct realtek_pci_sdmmc *host,
483 struct mmc_request *mrq)
485 struct rtsx_pcr *pcr = host->pcr;
486 struct mmc_host *mmc = host->mmc;
487 struct mmc_card *card = mmc->card;
488 struct mmc_command *cmd = mrq->cmd;
489 struct mmc_data *data = mrq->data;
490 int uhs = mmc_card_uhs(card);
493 size_t data_len = data->blksz * data->blocks;
495 sd_send_cmd_get_rsp(host, cmd);
499 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
500 __func__, cmd->opcode, cmd->arg);
502 cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 |
503 SD_NO_WAIT_BUSY_END | SD_NO_CHECK_CRC7 | SD_RSP_LEN_0;
506 cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
508 rtsx_pci_init_cmd(pcr);
509 sd_cmd_set_data_len(pcr, data->blocks, data->blksz);
510 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
511 DMA_DONE_INT, DMA_DONE_INT);
512 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3,
513 0xFF, (u8)(data_len >> 24));
514 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2,
515 0xFF, (u8)(data_len >> 16));
516 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1,
517 0xFF, (u8)(data_len >> 8));
518 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len);
519 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
520 0x03 | DMA_PACK_SIZE_MASK,
521 DMA_DIR_TO_CARD | DMA_EN | DMA_512);
522 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
524 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2);
525 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
526 SD_TRANSFER_START | SD_TM_AUTO_WRITE_3);
527 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
528 SD_TRANSFER_END, SD_TRANSFER_END);
529 rtsx_pci_send_cmd_no_wait(pcr);
530 err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, 0, 10000);
532 sd_clear_error(host);
539 static inline void sd_enable_initial_mode(struct realtek_pci_sdmmc *host)
541 rtsx_pci_write_register(host->pcr, SD_CFG1,
542 SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_128);
545 static inline void sd_disable_initial_mode(struct realtek_pci_sdmmc *host)
547 rtsx_pci_write_register(host->pcr, SD_CFG1,
548 SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_0);
551 static int sd_rw_multi(struct realtek_pci_sdmmc *host, struct mmc_request *mrq)
553 struct mmc_data *data = mrq->data;
556 if (host->sg_count < 0) {
557 data->error = host->sg_count;
558 dev_dbg(sdmmc_dev(host), "%s: sg_count = %d is invalid\n",
559 __func__, host->sg_count);
563 if (data->flags & MMC_DATA_READ) {
564 if (host->initial_mode)
565 sd_disable_initial_mode(host);
567 err = sd_read_long_data(host, mrq);
569 if (host->initial_mode)
570 sd_enable_initial_mode(host);
575 return sd_write_long_data(host, mrq);
578 static void sd_normal_rw(struct realtek_pci_sdmmc *host,
579 struct mmc_request *mrq)
581 struct mmc_command *cmd = mrq->cmd;
582 struct mmc_data *data = mrq->data;
585 buf = kzalloc(data->blksz, GFP_NOIO);
587 cmd->error = -ENOMEM;
591 if (data->flags & MMC_DATA_READ) {
592 if (host->initial_mode)
593 sd_disable_initial_mode(host);
595 cmd->error = sd_read_data(host, cmd, (u16)data->blksz, buf,
598 if (host->initial_mode)
599 sd_enable_initial_mode(host);
601 sg_copy_from_buffer(data->sg, data->sg_len, buf, data->blksz);
603 sg_copy_to_buffer(data->sg, data->sg_len, buf, data->blksz);
605 cmd->error = sd_write_data(host, cmd, (u16)data->blksz, buf,
612 static int sd_change_phase(struct realtek_pci_sdmmc *host,
613 u8 sample_point, bool rx)
615 struct rtsx_pcr *pcr = host->pcr;
617 dev_dbg(sdmmc_dev(host), "%s(%s): sample_point = %d\n",
618 __func__, rx ? "RX" : "TX", sample_point);
620 rtsx_pci_write_register(pcr, CLK_CTL, CHANGE_CLK, CHANGE_CLK);
622 SD_VP_CTL = SD_VPRX_CTL;
623 rtsx_pci_write_register(pcr, SD_VPRX_CTL,
624 PHASE_SELECT_MASK, sample_point);
626 SD_VP_CTL = SD_VPTX_CTL;
627 rtsx_pci_write_register(pcr, SD_VPTX_CTL,
628 PHASE_SELECT_MASK, sample_point);
630 rtsx_pci_write_register(pcr, SD_VP_CTL, PHASE_NOT_RESET, 0);
631 rtsx_pci_write_register(pcr, SD_VP_CTL, PHASE_NOT_RESET,
633 rtsx_pci_write_register(pcr, CLK_CTL, CHANGE_CLK, 0);
634 rtsx_pci_write_register(pcr, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
639 static inline u32 test_phase_bit(u32 phase_map, unsigned int bit)
641 bit %= RTSX_PHASE_MAX;
642 return phase_map & (1 << bit);
645 static int sd_get_phase_len(u32 phase_map, unsigned int start_bit)
649 for (i = 0; i < RTSX_PHASE_MAX; i++) {
650 if (test_phase_bit(phase_map, start_bit + i) == 0)
653 return RTSX_PHASE_MAX;
656 static u8 sd_search_final_phase(struct realtek_pci_sdmmc *host, u32 phase_map)
658 int start = 0, len = 0;
659 int start_final = 0, len_final = 0;
660 u8 final_phase = 0xFF;
662 if (phase_map == 0) {
663 dev_err(sdmmc_dev(host), "phase error: [map:%x]\n", phase_map);
667 while (start < RTSX_PHASE_MAX) {
668 len = sd_get_phase_len(phase_map, start);
669 if (len_final < len) {
673 start += len ? len : 1;
676 final_phase = (start_final + len_final / 2) % RTSX_PHASE_MAX;
677 dev_dbg(sdmmc_dev(host), "phase: [map:%x] [maxlen:%d] [final:%d]\n",
678 phase_map, len_final, final_phase);
683 static void sd_wait_data_idle(struct realtek_pci_sdmmc *host)
688 for (i = 0; i < 100; i++) {
689 rtsx_pci_read_register(host->pcr, SD_DATA_STATE, &val);
690 if (val & SD_DATA_IDLE)
697 static int sd_tuning_rx_cmd(struct realtek_pci_sdmmc *host,
698 u8 opcode, u8 sample_point)
701 struct mmc_command cmd = {};
702 struct rtsx_pcr *pcr = host->pcr;
704 sd_change_phase(host, sample_point, true);
706 rtsx_pci_write_register(pcr, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN,
707 SD_RSP_80CLK_TIMEOUT_EN);
710 err = sd_read_data(host, &cmd, 0x40, NULL, 0, 100);
712 /* Wait till SD DATA IDLE */
713 sd_wait_data_idle(host);
714 sd_clear_error(host);
715 rtsx_pci_write_register(pcr, SD_CFG3,
716 SD_RSP_80CLK_TIMEOUT_EN, 0);
720 rtsx_pci_write_register(pcr, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0);
724 static int sd_tuning_phase(struct realtek_pci_sdmmc *host,
725 u8 opcode, u32 *phase_map)
728 u32 raw_phase_map = 0;
730 for (i = 0; i < RTSX_PHASE_MAX; i++) {
731 err = sd_tuning_rx_cmd(host, opcode, (u8)i);
733 raw_phase_map |= 1 << i;
737 *phase_map = raw_phase_map;
742 static int sd_tuning_rx(struct realtek_pci_sdmmc *host, u8 opcode)
745 u32 raw_phase_map[RX_TUNING_CNT] = {0}, phase_map;
748 for (i = 0; i < RX_TUNING_CNT; i++) {
749 err = sd_tuning_phase(host, opcode, &(raw_phase_map[i]));
753 if (raw_phase_map[i] == 0)
757 phase_map = 0xFFFFFFFF;
758 for (i = 0; i < RX_TUNING_CNT; i++) {
759 dev_dbg(sdmmc_dev(host), "RX raw_phase_map[%d] = 0x%08x\n",
760 i, raw_phase_map[i]);
761 phase_map &= raw_phase_map[i];
763 dev_dbg(sdmmc_dev(host), "RX phase_map = 0x%08x\n", phase_map);
766 final_phase = sd_search_final_phase(host, phase_map);
767 if (final_phase == 0xFF)
770 err = sd_change_phase(host, final_phase, true);
780 static inline int sdio_extblock_cmd(struct mmc_command *cmd,
781 struct mmc_data *data)
783 return (cmd->opcode == SD_IO_RW_EXTENDED) && (data->blksz == 512);
786 static inline int sd_rw_cmd(struct mmc_command *cmd)
788 return mmc_op_multi(cmd->opcode) ||
789 (cmd->opcode == MMC_READ_SINGLE_BLOCK) ||
790 (cmd->opcode == MMC_WRITE_BLOCK);
793 static void sd_request(struct work_struct *work)
795 struct realtek_pci_sdmmc *host = container_of(work,
796 struct realtek_pci_sdmmc, work);
797 struct rtsx_pcr *pcr = host->pcr;
799 struct mmc_host *mmc = host->mmc;
800 struct mmc_request *mrq = host->mrq;
801 struct mmc_command *cmd = mrq->cmd;
802 struct mmc_data *data = mrq->data;
804 unsigned int data_size = 0;
807 if (host->eject || !sd_get_cd_int(host)) {
808 cmd->error = -ENOMEDIUM;
812 err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
818 mutex_lock(&pcr->pcr_mutex);
820 rtsx_pci_start_run(pcr);
822 rtsx_pci_switch_clock(pcr, host->clock, host->ssc_depth,
823 host->initial_mode, host->double_clk, host->vpclk);
824 rtsx_pci_write_register(pcr, CARD_SELECT, 0x07, SD_MOD_SEL);
825 rtsx_pci_write_register(pcr, CARD_SHARE_MODE,
826 CARD_SHARE_MASK, CARD_SHARE_48_SD);
828 mutex_lock(&host->host_mutex);
830 mutex_unlock(&host->host_mutex);
833 data_size = data->blocks * data->blksz;
836 sd_send_cmd_get_rsp(host, cmd);
837 } else if (sd_rw_cmd(cmd) || sdio_extblock_cmd(cmd, data)) {
838 cmd->error = sd_rw_multi(host, mrq);
839 if (!host->using_cookie)
840 sdmmc_post_req(host->mmc, host->mrq, 0);
842 if (mmc_op_multi(cmd->opcode) && mrq->stop)
843 sd_send_cmd_get_rsp(host, mrq->stop);
845 sd_normal_rw(host, mrq);
849 if (cmd->error || data->error)
850 data->bytes_xfered = 0;
852 data->bytes_xfered = data->blocks * data->blksz;
855 mutex_unlock(&pcr->pcr_mutex);
859 dev_dbg(sdmmc_dev(host), "CMD %d 0x%08x error(%d)\n",
860 cmd->opcode, cmd->arg, cmd->error);
863 mutex_lock(&host->host_mutex);
865 mutex_unlock(&host->host_mutex);
867 mmc_request_done(mmc, mrq);
870 static void sdmmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
872 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
873 struct mmc_data *data = mrq->data;
875 mutex_lock(&host->host_mutex);
877 mutex_unlock(&host->host_mutex);
879 if (sd_rw_cmd(mrq->cmd) || sdio_extblock_cmd(mrq->cmd, data))
880 host->using_cookie = sd_pre_dma_transfer(host, data, false);
882 schedule_work(&host->work);
885 static int sd_set_bus_width(struct realtek_pci_sdmmc *host,
886 unsigned char bus_width)
890 [MMC_BUS_WIDTH_1] = SD_BUS_WIDTH_1BIT,
891 [MMC_BUS_WIDTH_4] = SD_BUS_WIDTH_4BIT,
892 [MMC_BUS_WIDTH_8] = SD_BUS_WIDTH_8BIT,
895 if (bus_width <= MMC_BUS_WIDTH_8)
896 err = rtsx_pci_write_register(host->pcr, SD_CFG1,
897 0x03, width[bus_width]);
902 static int sd_power_on(struct realtek_pci_sdmmc *host, unsigned char power_mode)
904 struct rtsx_pcr *pcr = host->pcr;
907 if (host->prev_power_state == MMC_POWER_ON)
910 if (host->prev_power_state == MMC_POWER_UP) {
911 rtsx_pci_write_register(pcr, SD_BUS_STAT, SD_CLK_TOGGLE_EN, 0);
917 rtsx_pci_init_cmd(pcr);
918 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SELECT, 0x07, SD_MOD_SEL);
919 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SHARE_MODE,
920 CARD_SHARE_MASK, CARD_SHARE_48_SD);
921 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN,
922 SD_CLK_EN, SD_CLK_EN);
923 err = rtsx_pci_send_cmd(pcr, 100);
927 err = rtsx_pci_card_pull_ctl_enable(pcr, RTSX_SD_CARD);
931 err = rtsx_pci_card_power_on(pcr, RTSX_SD_CARD);
937 err = rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN);
941 /* send at least 74 clocks */
942 rtsx_pci_write_register(pcr, SD_BUS_STAT, SD_CLK_TOGGLE_EN, SD_CLK_TOGGLE_EN);
945 host->prev_power_state = power_mode;
949 static int sd_power_off(struct realtek_pci_sdmmc *host)
951 struct rtsx_pcr *pcr = host->pcr;
954 host->prev_power_state = MMC_POWER_OFF;
956 rtsx_pci_init_cmd(pcr);
958 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, 0);
959 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0);
961 err = rtsx_pci_send_cmd(pcr, 100);
965 err = rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);
969 return rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD);
972 static int sd_set_power_mode(struct realtek_pci_sdmmc *host,
973 unsigned char power_mode)
977 if (power_mode == MMC_POWER_OFF)
978 err = sd_power_off(host);
980 err = sd_power_on(host, power_mode);
985 static int sd_set_timing(struct realtek_pci_sdmmc *host, unsigned char timing)
987 struct rtsx_pcr *pcr = host->pcr;
990 rtsx_pci_init_cmd(pcr);
993 case MMC_TIMING_UHS_SDR104:
994 case MMC_TIMING_UHS_SDR50:
995 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
996 0x0C | SD_ASYNC_FIFO_NOT_RST,
997 SD_30_MODE | SD_ASYNC_FIFO_NOT_RST);
998 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
999 CLK_LOW_FREQ, CLK_LOW_FREQ);
1000 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1001 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
1002 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1005 case MMC_TIMING_MMC_DDR52:
1006 case MMC_TIMING_UHS_DDR50:
1007 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
1008 0x0C | SD_ASYNC_FIFO_NOT_RST,
1009 SD_DDR_MODE | SD_ASYNC_FIFO_NOT_RST);
1010 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1011 CLK_LOW_FREQ, CLK_LOW_FREQ);
1012 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1013 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
1014 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1015 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
1016 DDR_VAR_TX_CMD_DAT, DDR_VAR_TX_CMD_DAT);
1017 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
1018 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD,
1019 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD);
1022 case MMC_TIMING_MMC_HS:
1023 case MMC_TIMING_SD_HS:
1024 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
1026 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1027 CLK_LOW_FREQ, CLK_LOW_FREQ);
1028 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1029 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
1030 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1031 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
1032 SD20_TX_SEL_MASK, SD20_TX_14_AHEAD);
1033 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
1034 SD20_RX_SEL_MASK, SD20_RX_14_DELAY);
1038 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
1039 SD_CFG1, 0x0C, SD_20_MODE);
1040 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1041 CLK_LOW_FREQ, CLK_LOW_FREQ);
1042 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1043 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
1044 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1045 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
1046 SD_PUSH_POINT_CTL, 0xFF, 0);
1047 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
1048 SD20_RX_SEL_MASK, SD20_RX_POS_EDGE);
1052 err = rtsx_pci_send_cmd(pcr, 100);
1057 static void sdmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1059 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1060 struct rtsx_pcr *pcr = host->pcr;
1065 if (rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD))
1068 mutex_lock(&pcr->pcr_mutex);
1070 rtsx_pci_start_run(pcr);
1072 sd_set_bus_width(host, ios->bus_width);
1073 sd_set_power_mode(host, ios->power_mode);
1074 sd_set_timing(host, ios->timing);
1076 host->vpclk = false;
1077 host->double_clk = true;
1079 switch (ios->timing) {
1080 case MMC_TIMING_UHS_SDR104:
1081 case MMC_TIMING_UHS_SDR50:
1082 host->ssc_depth = RTSX_SSC_DEPTH_2M;
1084 host->double_clk = false;
1086 case MMC_TIMING_MMC_DDR52:
1087 case MMC_TIMING_UHS_DDR50:
1088 case MMC_TIMING_UHS_SDR25:
1089 host->ssc_depth = RTSX_SSC_DEPTH_1M;
1092 host->ssc_depth = RTSX_SSC_DEPTH_500K;
1096 host->initial_mode = (ios->clock <= 1000000) ? true : false;
1098 host->clock = ios->clock;
1099 rtsx_pci_switch_clock(pcr, ios->clock, host->ssc_depth,
1100 host->initial_mode, host->double_clk, host->vpclk);
1102 mutex_unlock(&pcr->pcr_mutex);
1105 static int sdmmc_get_ro(struct mmc_host *mmc)
1107 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1108 struct rtsx_pcr *pcr = host->pcr;
1115 mutex_lock(&pcr->pcr_mutex);
1117 rtsx_pci_start_run(pcr);
1119 /* Check SD mechanical write-protect switch */
1120 val = rtsx_pci_readl(pcr, RTSX_BIPR);
1121 dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val);
1122 if (val & SD_WRITE_PROTECT)
1125 mutex_unlock(&pcr->pcr_mutex);
1130 static int sdmmc_get_cd(struct mmc_host *mmc)
1132 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1133 struct rtsx_pcr *pcr = host->pcr;
1140 mutex_lock(&pcr->pcr_mutex);
1142 rtsx_pci_start_run(pcr);
1144 /* Check SD card detect */
1145 val = rtsx_pci_card_exist(pcr);
1146 dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val);
1150 mutex_unlock(&pcr->pcr_mutex);
1155 static int sd_wait_voltage_stable_1(struct realtek_pci_sdmmc *host)
1157 struct rtsx_pcr *pcr = host->pcr;
1161 /* Reference to Signal Voltage Switch Sequence in SD spec.
1162 * Wait for a period of time so that the card can drive SD_CMD and
1163 * SD_DAT[3:0] to low after sending back CMD11 response.
1167 /* SD_CMD, SD_DAT[3:0] should be driven to low by card;
1168 * If either one of SD_CMD,SD_DAT[3:0] is not low,
1169 * abort the voltage switch sequence;
1171 err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1175 if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1176 SD_DAT1_STATUS | SD_DAT0_STATUS))
1179 /* Stop toggle SD clock */
1180 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1181 0xFF, SD_CLK_FORCE_STOP);
1188 static int sd_wait_voltage_stable_2(struct realtek_pci_sdmmc *host)
1190 struct rtsx_pcr *pcr = host->pcr;
1194 /* Wait 1.8V output of voltage regulator in card stable */
1197 /* Toggle SD clock again */
1198 err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN);
1202 /* Wait for a period of time so that the card can drive
1203 * SD_DAT[3:0] to high at 1.8V
1207 /* SD_CMD, SD_DAT[3:0] should be pulled high by host */
1208 err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1212 mask = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1213 SD_DAT1_STATUS | SD_DAT0_STATUS;
1214 val = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1215 SD_DAT1_STATUS | SD_DAT0_STATUS;
1216 if ((stat & mask) != val) {
1217 dev_dbg(sdmmc_dev(host),
1218 "%s: SD_BUS_STAT = 0x%x\n", __func__, stat);
1219 rtsx_pci_write_register(pcr, SD_BUS_STAT,
1220 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
1221 rtsx_pci_write_register(pcr, CARD_CLK_EN, 0xFF, 0);
1228 static int sdmmc_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1230 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1231 struct rtsx_pcr *pcr = host->pcr;
1235 dev_dbg(sdmmc_dev(host), "%s: signal_voltage = %d\n",
1236 __func__, ios->signal_voltage);
1241 err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
1245 mutex_lock(&pcr->pcr_mutex);
1247 rtsx_pci_start_run(pcr);
1249 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1250 voltage = OUTPUT_3V3;
1252 voltage = OUTPUT_1V8;
1254 if (voltage == OUTPUT_1V8) {
1255 err = sd_wait_voltage_stable_1(host);
1260 err = rtsx_pci_switch_output_voltage(pcr, voltage);
1264 if (voltage == OUTPUT_1V8) {
1265 err = sd_wait_voltage_stable_2(host);
1271 /* Stop toggle SD clock in idle */
1272 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1273 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
1275 mutex_unlock(&pcr->pcr_mutex);
1280 static int sdmmc_execute_tuning(struct mmc_host *mmc, u32 opcode)
1282 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1283 struct rtsx_pcr *pcr = host->pcr;
1289 err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
1293 mutex_lock(&pcr->pcr_mutex);
1295 rtsx_pci_start_run(pcr);
1297 /* Set initial TX phase */
1298 switch (mmc->ios.timing) {
1299 case MMC_TIMING_UHS_SDR104:
1300 err = sd_change_phase(host, SDR104_TX_PHASE(pcr), false);
1303 case MMC_TIMING_UHS_SDR50:
1304 err = sd_change_phase(host, SDR50_TX_PHASE(pcr), false);
1307 case MMC_TIMING_UHS_DDR50:
1308 err = sd_change_phase(host, DDR50_TX_PHASE(pcr), false);
1318 /* Tuning RX phase */
1319 if ((mmc->ios.timing == MMC_TIMING_UHS_SDR104) ||
1320 (mmc->ios.timing == MMC_TIMING_UHS_SDR50))
1321 err = sd_tuning_rx(host, opcode);
1322 else if (mmc->ios.timing == MMC_TIMING_UHS_DDR50)
1323 err = sd_change_phase(host, DDR50_RX_PHASE(pcr), true);
1326 mutex_unlock(&pcr->pcr_mutex);
1331 static const struct mmc_host_ops realtek_pci_sdmmc_ops = {
1332 .pre_req = sdmmc_pre_req,
1333 .post_req = sdmmc_post_req,
1334 .request = sdmmc_request,
1335 .set_ios = sdmmc_set_ios,
1336 .get_ro = sdmmc_get_ro,
1337 .get_cd = sdmmc_get_cd,
1338 .start_signal_voltage_switch = sdmmc_switch_voltage,
1339 .execute_tuning = sdmmc_execute_tuning,
1342 static void init_extra_caps(struct realtek_pci_sdmmc *host)
1344 struct mmc_host *mmc = host->mmc;
1345 struct rtsx_pcr *pcr = host->pcr;
1347 dev_dbg(sdmmc_dev(host), "pcr->extra_caps = 0x%x\n", pcr->extra_caps);
1349 if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50)
1350 mmc->caps |= MMC_CAP_UHS_SDR50;
1351 if (pcr->extra_caps & EXTRA_CAPS_SD_SDR104)
1352 mmc->caps |= MMC_CAP_UHS_SDR104;
1353 if (pcr->extra_caps & EXTRA_CAPS_SD_DDR50)
1354 mmc->caps |= MMC_CAP_UHS_DDR50;
1355 if (pcr->extra_caps & EXTRA_CAPS_MMC_HSDDR)
1356 mmc->caps |= MMC_CAP_1_8V_DDR;
1357 if (pcr->extra_caps & EXTRA_CAPS_MMC_8BIT)
1358 mmc->caps |= MMC_CAP_8_BIT_DATA;
1359 if (pcr->extra_caps & EXTRA_CAPS_NO_MMC)
1360 mmc->caps2 |= MMC_CAP2_NO_MMC;
1363 static void realtek_init_host(struct realtek_pci_sdmmc *host)
1365 struct mmc_host *mmc = host->mmc;
1367 mmc->f_min = 250000;
1368 mmc->f_max = 208000000;
1369 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1370 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED |
1371 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_BUS_WIDTH_TEST |
1372 MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
1373 mmc->caps2 = MMC_CAP2_NO_PRESCAN_POWERUP | MMC_CAP2_FULL_PWR_CYCLE;
1374 mmc->max_current_330 = 400;
1375 mmc->max_current_180 = 800;
1376 mmc->ops = &realtek_pci_sdmmc_ops;
1378 init_extra_caps(host);
1380 mmc->max_segs = 256;
1381 mmc->max_seg_size = 65536;
1382 mmc->max_blk_size = 512;
1383 mmc->max_blk_count = 65535;
1384 mmc->max_req_size = 524288;
1387 static void rtsx_pci_sdmmc_card_event(struct platform_device *pdev)
1389 struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1392 mmc_detect_change(host->mmc, 0);
1395 static int rtsx_pci_sdmmc_drv_probe(struct platform_device *pdev)
1397 struct mmc_host *mmc;
1398 struct realtek_pci_sdmmc *host;
1399 struct rtsx_pcr *pcr;
1400 struct pcr_handle *handle = pdev->dev.platform_data;
1409 dev_dbg(&(pdev->dev), ": Realtek PCI-E SDMMC controller found\n");
1411 mmc = mmc_alloc_host(sizeof(*host), &pdev->dev);
1415 host = mmc_priv(mmc);
1417 mmc->ios.power_delay_ms = 5;
1421 host->prev_power_state = MMC_POWER_OFF;
1422 INIT_WORK(&host->work, sd_request);
1423 platform_set_drvdata(pdev, host);
1424 pcr->slots[RTSX_SD_CARD].p_dev = pdev;
1425 pcr->slots[RTSX_SD_CARD].card_event = rtsx_pci_sdmmc_card_event;
1427 mutex_init(&host->host_mutex);
1429 realtek_init_host(host);
1436 static int rtsx_pci_sdmmc_drv_remove(struct platform_device *pdev)
1438 struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1439 struct rtsx_pcr *pcr;
1440 struct mmc_host *mmc;
1446 pcr->slots[RTSX_SD_CARD].p_dev = NULL;
1447 pcr->slots[RTSX_SD_CARD].card_event = NULL;
1450 cancel_work_sync(&host->work);
1452 mutex_lock(&host->host_mutex);
1454 dev_dbg(&(pdev->dev),
1455 "%s: Controller removed during transfer\n",
1458 rtsx_pci_complete_unfinished_transfer(pcr);
1460 host->mrq->cmd->error = -ENOMEDIUM;
1461 if (host->mrq->stop)
1462 host->mrq->stop->error = -ENOMEDIUM;
1463 mmc_request_done(mmc, host->mrq);
1465 mutex_unlock(&host->host_mutex);
1467 mmc_remove_host(mmc);
1470 flush_work(&host->work);
1474 dev_dbg(&(pdev->dev),
1475 ": Realtek PCI-E SDMMC controller has been removed\n");
1480 static const struct platform_device_id rtsx_pci_sdmmc_ids[] = {
1482 .name = DRV_NAME_RTSX_PCI_SDMMC,
1487 MODULE_DEVICE_TABLE(platform, rtsx_pci_sdmmc_ids);
1489 static struct platform_driver rtsx_pci_sdmmc_driver = {
1490 .probe = rtsx_pci_sdmmc_drv_probe,
1491 .remove = rtsx_pci_sdmmc_drv_remove,
1492 .id_table = rtsx_pci_sdmmc_ids,
1494 .name = DRV_NAME_RTSX_PCI_SDMMC,
1495 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1498 module_platform_driver(rtsx_pci_sdmmc_driver);
1500 MODULE_LICENSE("GPL");
1501 MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
1502 MODULE_DESCRIPTION("Realtek PCI-E SD/MMC Card Host Driver");