1 /* Realtek PCI-Express SD/MMC Card Interface driver
3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 * Wei WANG <wei_wang@realsil.com.cn>
22 #include <linux/module.h>
23 #include <linux/slab.h>
24 #include <linux/highmem.h>
25 #include <linux/delay.h>
26 #include <linux/platform_device.h>
27 #include <linux/workqueue.h>
28 #include <linux/mmc/host.h>
29 #include <linux/mmc/mmc.h>
30 #include <linux/mmc/sd.h>
31 #include <linux/mmc/sdio.h>
32 #include <linux/mmc/card.h>
33 #include <linux/mfd/rtsx_pci.h>
34 #include <asm/unaligned.h>
36 struct realtek_pci_sdmmc {
37 struct platform_device *pdev;
40 struct mmc_request *mrq;
41 #define SDMMC_WORKQ_NAME "rtsx_pci_sdmmc_workq"
43 struct work_struct work;
44 struct mutex host_mutex;
59 static inline struct device *sdmmc_dev(struct realtek_pci_sdmmc *host)
61 return &(host->pdev->dev);
64 static inline void sd_clear_error(struct realtek_pci_sdmmc *host)
66 rtsx_pci_write_register(host->pcr, CARD_STOP,
67 SD_STOP | SD_CLR_ERR, SD_STOP | SD_CLR_ERR);
71 static void dump_reg_range(struct realtek_pci_sdmmc *host, u16 start, u16 end)
73 u16 len = end - start + 1;
77 for (i = 0; i < len; i += 8) {
79 int n = min(8, len - i);
81 memset(&data, 0, sizeof(data));
82 for (j = 0; j < n; j++)
83 rtsx_pci_read_register(host->pcr, start + i + j,
85 dev_dbg(sdmmc_dev(host), "0x%04X(%d): %8ph\n",
90 static void sd_print_debug_regs(struct realtek_pci_sdmmc *host)
92 dump_reg_range(host, 0xFDA0, 0xFDB3);
93 dump_reg_range(host, 0xFD52, 0xFD69);
96 #define sd_print_debug_regs(host)
99 static inline int sd_get_cd_int(struct realtek_pci_sdmmc *host)
101 return rtsx_pci_readl(host->pcr, RTSX_BIPR) & SD_EXIST;
104 static void sd_cmd_set_sd_cmd(struct rtsx_pcr *pcr, struct mmc_command *cmd)
106 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0, 0xFF,
107 SD_CMD_START | cmd->opcode);
108 rtsx_pci_write_be32(pcr, SD_CMD1, cmd->arg);
111 static void sd_cmd_set_data_len(struct rtsx_pcr *pcr, u16 blocks, u16 blksz)
113 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, blocks);
114 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, blocks >> 8);
115 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, blksz);
116 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, blksz >> 8);
119 static int sd_response_type(struct mmc_command *cmd)
121 switch (mmc_resp_type(cmd)) {
123 return SD_RSP_TYPE_R0;
125 return SD_RSP_TYPE_R1;
126 case MMC_RSP_R1_NO_CRC:
127 return SD_RSP_TYPE_R1 | SD_NO_CHECK_CRC7;
129 return SD_RSP_TYPE_R1b;
131 return SD_RSP_TYPE_R2;
133 return SD_RSP_TYPE_R3;
139 static int sd_status_index(int resp_type)
141 if (resp_type == SD_RSP_TYPE_R0)
143 else if (resp_type == SD_RSP_TYPE_R2)
149 * sd_pre_dma_transfer - do dma_map_sg() or using cookie
151 * @pre: if called in pre_req()
153 * 0 - do dma_map_sg()
156 static int sd_pre_dma_transfer(struct realtek_pci_sdmmc *host,
157 struct mmc_data *data, bool pre)
159 struct rtsx_pcr *pcr = host->pcr;
160 int read = data->flags & MMC_DATA_READ;
162 int using_cookie = 0;
164 if (!pre && data->host_cookie && data->host_cookie != host->cookie) {
165 dev_err(sdmmc_dev(host),
166 "error: data->host_cookie = %d, host->cookie = %d\n",
167 data->host_cookie, host->cookie);
168 data->host_cookie = 0;
171 if (pre || data->host_cookie != host->cookie) {
172 count = rtsx_pci_dma_map_sg(pcr, data->sg, data->sg_len, read);
174 count = host->cookie_sg_count;
179 host->cookie_sg_count = count;
180 if (++host->cookie < 0)
182 data->host_cookie = host->cookie;
184 host->sg_count = count;
190 static void sdmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
193 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
194 struct mmc_data *data = mrq->data;
196 if (data->host_cookie) {
197 dev_err(sdmmc_dev(host),
198 "error: reset data->host_cookie = %d\n",
200 data->host_cookie = 0;
203 sd_pre_dma_transfer(host, data, true);
204 dev_dbg(sdmmc_dev(host), "pre dma sg: %d\n", host->cookie_sg_count);
207 static void sdmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
210 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
211 struct rtsx_pcr *pcr = host->pcr;
212 struct mmc_data *data = mrq->data;
213 int read = data->flags & MMC_DATA_READ;
215 rtsx_pci_dma_unmap_sg(pcr, data->sg, data->sg_len, read);
216 data->host_cookie = 0;
219 static void sd_send_cmd_get_rsp(struct realtek_pci_sdmmc *host,
220 struct mmc_command *cmd)
222 struct rtsx_pcr *pcr = host->pcr;
223 u8 cmd_idx = (u8)cmd->opcode;
231 bool clock_toggled = false;
233 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
234 __func__, cmd_idx, arg);
236 rsp_type = sd_response_type(cmd);
240 stat_idx = sd_status_index(rsp_type);
242 if (rsp_type == SD_RSP_TYPE_R1b)
243 timeout = cmd->busy_timeout ? cmd->busy_timeout : 3000;
245 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
246 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
247 0xFF, SD_CLK_TOGGLE_EN);
251 clock_toggled = true;
254 rtsx_pci_init_cmd(pcr);
255 sd_cmd_set_sd_cmd(pcr, cmd);
256 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, rsp_type);
257 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
258 0x01, PINGPONG_BUFFER);
259 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
260 0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START);
261 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
262 SD_TRANSFER_END | SD_STAT_IDLE,
263 SD_TRANSFER_END | SD_STAT_IDLE);
265 if (rsp_type == SD_RSP_TYPE_R2) {
266 /* Read data from ping-pong buffer */
267 for (i = PPBUF_BASE2; i < PPBUF_BASE2 + 16; i++)
268 rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
269 } else if (rsp_type != SD_RSP_TYPE_R0) {
270 /* Read data from SD_CMDx registers */
271 for (i = SD_CMD0; i <= SD_CMD4; i++)
272 rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
275 rtsx_pci_add_cmd(pcr, READ_REG_CMD, SD_STAT1, 0, 0);
277 err = rtsx_pci_send_cmd(pcr, timeout);
279 sd_print_debug_regs(host);
280 sd_clear_error(host);
281 dev_dbg(sdmmc_dev(host),
282 "rtsx_pci_send_cmd error (err = %d)\n", err);
286 if (rsp_type == SD_RSP_TYPE_R0) {
291 /* Eliminate returned value of CHECK_REG_CMD */
292 ptr = rtsx_pci_get_cmd_data(pcr) + 1;
294 /* Check (Start,Transmission) bit of Response */
295 if ((ptr[0] & 0xC0) != 0) {
297 dev_dbg(sdmmc_dev(host), "Invalid response bit\n");
302 if (!(rsp_type & SD_NO_CHECK_CRC7)) {
303 if (ptr[stat_idx] & SD_CRC7_ERR) {
305 dev_dbg(sdmmc_dev(host), "CRC7 error\n");
310 if (rsp_type == SD_RSP_TYPE_R2) {
312 * The controller offloads the last byte {CRC-7, end bit 1'b1}
313 * of response type R2. Assign dummy CRC, 0, and end bit to the
314 * byte(ptr[16], goes into the LSB of resp[3] later).
318 for (i = 0; i < 4; i++) {
319 cmd->resp[i] = get_unaligned_be32(ptr + 1 + i * 4);
320 dev_dbg(sdmmc_dev(host), "cmd->resp[%d] = 0x%08x\n",
324 cmd->resp[0] = get_unaligned_be32(ptr + 1);
325 dev_dbg(sdmmc_dev(host), "cmd->resp[0] = 0x%08x\n",
332 if (err && clock_toggled)
333 rtsx_pci_write_register(pcr, SD_BUS_STAT,
334 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
337 static int sd_read_data(struct realtek_pci_sdmmc *host, struct mmc_command *cmd,
338 u16 byte_cnt, u8 *buf, int buf_len, int timeout)
340 struct rtsx_pcr *pcr = host->pcr;
344 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
345 __func__, cmd->opcode, cmd->arg);
350 if (cmd->opcode == MMC_SEND_TUNING_BLOCK)
351 trans_mode = SD_TM_AUTO_TUNING;
353 trans_mode = SD_TM_NORMAL_READ;
355 rtsx_pci_init_cmd(pcr);
356 sd_cmd_set_sd_cmd(pcr, cmd);
357 sd_cmd_set_data_len(pcr, 1, byte_cnt);
358 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
359 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
360 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6);
361 if (trans_mode != SD_TM_AUTO_TUNING)
362 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
363 CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
365 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
366 0xFF, trans_mode | SD_TRANSFER_START);
367 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
368 SD_TRANSFER_END, SD_TRANSFER_END);
370 err = rtsx_pci_send_cmd(pcr, timeout);
372 sd_print_debug_regs(host);
373 dev_dbg(sdmmc_dev(host),
374 "rtsx_pci_send_cmd fail (err = %d)\n", err);
378 if (buf && buf_len) {
379 err = rtsx_pci_read_ppbuf(pcr, buf, buf_len);
381 dev_dbg(sdmmc_dev(host),
382 "rtsx_pci_read_ppbuf fail (err = %d)\n", err);
390 static int sd_write_data(struct realtek_pci_sdmmc *host,
391 struct mmc_command *cmd, u16 byte_cnt, u8 *buf, int buf_len,
394 struct rtsx_pcr *pcr = host->pcr;
397 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
398 __func__, cmd->opcode, cmd->arg);
403 sd_send_cmd_get_rsp(host, cmd);
407 if (buf && buf_len) {
408 err = rtsx_pci_write_ppbuf(pcr, buf, buf_len);
410 dev_dbg(sdmmc_dev(host),
411 "rtsx_pci_write_ppbuf fail (err = %d)\n", err);
416 rtsx_pci_init_cmd(pcr);
417 sd_cmd_set_data_len(pcr, 1, byte_cnt);
418 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
419 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
420 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_0);
421 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
422 SD_TRANSFER_START | SD_TM_AUTO_WRITE_3);
423 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
424 SD_TRANSFER_END, SD_TRANSFER_END);
426 err = rtsx_pci_send_cmd(pcr, timeout);
428 sd_print_debug_regs(host);
429 dev_dbg(sdmmc_dev(host),
430 "rtsx_pci_send_cmd fail (err = %d)\n", err);
437 static int sd_read_long_data(struct realtek_pci_sdmmc *host,
438 struct mmc_request *mrq)
440 struct rtsx_pcr *pcr = host->pcr;
441 struct mmc_host *mmc = host->mmc;
442 struct mmc_card *card = mmc->card;
443 struct mmc_command *cmd = mrq->cmd;
444 struct mmc_data *data = mrq->data;
445 int uhs = mmc_card_uhs(card);
449 size_t data_len = data->blksz * data->blocks;
451 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
452 __func__, cmd->opcode, cmd->arg);
454 resp_type = sd_response_type(cmd);
459 cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
461 rtsx_pci_init_cmd(pcr);
462 sd_cmd_set_sd_cmd(pcr, cmd);
463 sd_cmd_set_data_len(pcr, data->blocks, data->blksz);
464 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
465 DMA_DONE_INT, DMA_DONE_INT);
466 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3,
467 0xFF, (u8)(data_len >> 24));
468 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2,
469 0xFF, (u8)(data_len >> 16));
470 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1,
471 0xFF, (u8)(data_len >> 8));
472 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len);
473 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
474 0x03 | DMA_PACK_SIZE_MASK,
475 DMA_DIR_FROM_CARD | DMA_EN | DMA_512);
476 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
478 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2 | resp_type);
479 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
480 SD_TRANSFER_START | SD_TM_AUTO_READ_2);
481 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
482 SD_TRANSFER_END, SD_TRANSFER_END);
483 rtsx_pci_send_cmd_no_wait(pcr);
485 err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, 1, 10000);
487 sd_print_debug_regs(host);
488 sd_clear_error(host);
495 static int sd_write_long_data(struct realtek_pci_sdmmc *host,
496 struct mmc_request *mrq)
498 struct rtsx_pcr *pcr = host->pcr;
499 struct mmc_host *mmc = host->mmc;
500 struct mmc_card *card = mmc->card;
501 struct mmc_command *cmd = mrq->cmd;
502 struct mmc_data *data = mrq->data;
503 int uhs = mmc_card_uhs(card);
506 size_t data_len = data->blksz * data->blocks;
508 sd_send_cmd_get_rsp(host, cmd);
512 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
513 __func__, cmd->opcode, cmd->arg);
515 cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 |
516 SD_NO_WAIT_BUSY_END | SD_NO_CHECK_CRC7 | SD_RSP_LEN_0;
519 cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
521 rtsx_pci_init_cmd(pcr);
522 sd_cmd_set_data_len(pcr, data->blocks, data->blksz);
523 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
524 DMA_DONE_INT, DMA_DONE_INT);
525 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3,
526 0xFF, (u8)(data_len >> 24));
527 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2,
528 0xFF, (u8)(data_len >> 16));
529 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1,
530 0xFF, (u8)(data_len >> 8));
531 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len);
532 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
533 0x03 | DMA_PACK_SIZE_MASK,
534 DMA_DIR_TO_CARD | DMA_EN | DMA_512);
535 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
537 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2);
538 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
539 SD_TRANSFER_START | SD_TM_AUTO_WRITE_3);
540 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
541 SD_TRANSFER_END, SD_TRANSFER_END);
542 rtsx_pci_send_cmd_no_wait(pcr);
543 err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, 0, 10000);
545 sd_clear_error(host);
552 static inline void sd_enable_initial_mode(struct realtek_pci_sdmmc *host)
554 rtsx_pci_write_register(host->pcr, SD_CFG1,
555 SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_128);
558 static inline void sd_disable_initial_mode(struct realtek_pci_sdmmc *host)
560 rtsx_pci_write_register(host->pcr, SD_CFG1,
561 SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_0);
564 static int sd_rw_multi(struct realtek_pci_sdmmc *host, struct mmc_request *mrq)
566 struct mmc_data *data = mrq->data;
569 if (host->sg_count < 0) {
570 data->error = host->sg_count;
571 dev_dbg(sdmmc_dev(host), "%s: sg_count = %d is invalid\n",
572 __func__, host->sg_count);
576 if (data->flags & MMC_DATA_READ) {
577 if (host->initial_mode)
578 sd_disable_initial_mode(host);
580 err = sd_read_long_data(host, mrq);
582 if (host->initial_mode)
583 sd_enable_initial_mode(host);
588 return sd_write_long_data(host, mrq);
591 static void sd_normal_rw(struct realtek_pci_sdmmc *host,
592 struct mmc_request *mrq)
594 struct mmc_command *cmd = mrq->cmd;
595 struct mmc_data *data = mrq->data;
598 buf = kzalloc(data->blksz, GFP_NOIO);
600 cmd->error = -ENOMEM;
604 if (data->flags & MMC_DATA_READ) {
605 if (host->initial_mode)
606 sd_disable_initial_mode(host);
608 cmd->error = sd_read_data(host, cmd, (u16)data->blksz, buf,
611 if (host->initial_mode)
612 sd_enable_initial_mode(host);
614 sg_copy_from_buffer(data->sg, data->sg_len, buf, data->blksz);
616 sg_copy_to_buffer(data->sg, data->sg_len, buf, data->blksz);
618 cmd->error = sd_write_data(host, cmd, (u16)data->blksz, buf,
625 static int sd_change_phase(struct realtek_pci_sdmmc *host,
626 u8 sample_point, bool rx)
628 struct rtsx_pcr *pcr = host->pcr;
631 dev_dbg(sdmmc_dev(host), "%s(%s): sample_point = %d\n",
632 __func__, rx ? "RX" : "TX", sample_point);
634 rtsx_pci_init_cmd(pcr);
636 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, CHANGE_CLK);
638 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
639 SD_VPRX_CTL, 0x1F, sample_point);
641 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
642 SD_VPTX_CTL, 0x1F, sample_point);
643 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0);
644 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
645 PHASE_NOT_RESET, PHASE_NOT_RESET);
646 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, 0);
647 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
649 err = rtsx_pci_send_cmd(pcr, 100);
656 static inline u32 test_phase_bit(u32 phase_map, unsigned int bit)
658 bit %= RTSX_PHASE_MAX;
659 return phase_map & (1 << bit);
662 static int sd_get_phase_len(u32 phase_map, unsigned int start_bit)
666 for (i = 0; i < RTSX_PHASE_MAX; i++) {
667 if (test_phase_bit(phase_map, start_bit + i) == 0)
670 return RTSX_PHASE_MAX;
673 static u8 sd_search_final_phase(struct realtek_pci_sdmmc *host, u32 phase_map)
675 int start = 0, len = 0;
676 int start_final = 0, len_final = 0;
677 u8 final_phase = 0xFF;
679 if (phase_map == 0) {
680 dev_err(sdmmc_dev(host), "phase error: [map:%x]\n", phase_map);
684 while (start < RTSX_PHASE_MAX) {
685 len = sd_get_phase_len(phase_map, start);
686 if (len_final < len) {
690 start += len ? len : 1;
693 final_phase = (start_final + len_final / 2) % RTSX_PHASE_MAX;
694 dev_dbg(sdmmc_dev(host), "phase: [map:%x] [maxlen:%d] [final:%d]\n",
695 phase_map, len_final, final_phase);
700 static void sd_wait_data_idle(struct realtek_pci_sdmmc *host)
705 for (i = 0; i < 100; i++) {
706 err = rtsx_pci_read_register(host->pcr, SD_DATA_STATE, &val);
707 if (val & SD_DATA_IDLE)
714 static int sd_tuning_rx_cmd(struct realtek_pci_sdmmc *host,
715 u8 opcode, u8 sample_point)
718 struct mmc_command cmd = {0};
720 err = sd_change_phase(host, sample_point, true);
725 err = sd_read_data(host, &cmd, 0x40, NULL, 0, 100);
727 /* Wait till SD DATA IDLE */
728 sd_wait_data_idle(host);
729 sd_clear_error(host);
736 static int sd_tuning_phase(struct realtek_pci_sdmmc *host,
737 u8 opcode, u32 *phase_map)
740 u32 raw_phase_map = 0;
742 for (i = 0; i < RTSX_PHASE_MAX; i++) {
743 err = sd_tuning_rx_cmd(host, opcode, (u8)i);
745 raw_phase_map |= 1 << i;
749 *phase_map = raw_phase_map;
754 static int sd_tuning_rx(struct realtek_pci_sdmmc *host, u8 opcode)
757 u32 raw_phase_map[RX_TUNING_CNT] = {0}, phase_map;
760 for (i = 0; i < RX_TUNING_CNT; i++) {
761 err = sd_tuning_phase(host, opcode, &(raw_phase_map[i]));
765 if (raw_phase_map[i] == 0)
769 phase_map = 0xFFFFFFFF;
770 for (i = 0; i < RX_TUNING_CNT; i++) {
771 dev_dbg(sdmmc_dev(host), "RX raw_phase_map[%d] = 0x%08x\n",
772 i, raw_phase_map[i]);
773 phase_map &= raw_phase_map[i];
775 dev_dbg(sdmmc_dev(host), "RX phase_map = 0x%08x\n", phase_map);
778 final_phase = sd_search_final_phase(host, phase_map);
779 if (final_phase == 0xFF)
782 err = sd_change_phase(host, final_phase, true);
792 static inline int sdio_extblock_cmd(struct mmc_command *cmd,
793 struct mmc_data *data)
795 return (cmd->opcode == SD_IO_RW_EXTENDED) && (data->blksz == 512);
798 static inline int sd_rw_cmd(struct mmc_command *cmd)
800 return mmc_op_multi(cmd->opcode) ||
801 (cmd->opcode == MMC_READ_SINGLE_BLOCK) ||
802 (cmd->opcode == MMC_WRITE_BLOCK);
805 static void sd_request(struct work_struct *work)
807 struct realtek_pci_sdmmc *host = container_of(work,
808 struct realtek_pci_sdmmc, work);
809 struct rtsx_pcr *pcr = host->pcr;
811 struct mmc_host *mmc = host->mmc;
812 struct mmc_request *mrq = host->mrq;
813 struct mmc_command *cmd = mrq->cmd;
814 struct mmc_data *data = mrq->data;
816 unsigned int data_size = 0;
819 if (host->eject || !sd_get_cd_int(host)) {
820 cmd->error = -ENOMEDIUM;
824 err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
830 mutex_lock(&pcr->pcr_mutex);
832 rtsx_pci_start_run(pcr);
834 rtsx_pci_switch_clock(pcr, host->clock, host->ssc_depth,
835 host->initial_mode, host->double_clk, host->vpclk);
836 rtsx_pci_write_register(pcr, CARD_SELECT, 0x07, SD_MOD_SEL);
837 rtsx_pci_write_register(pcr, CARD_SHARE_MODE,
838 CARD_SHARE_MASK, CARD_SHARE_48_SD);
840 mutex_lock(&host->host_mutex);
842 mutex_unlock(&host->host_mutex);
845 data_size = data->blocks * data->blksz;
848 sd_send_cmd_get_rsp(host, cmd);
849 } else if (sd_rw_cmd(cmd) || sdio_extblock_cmd(cmd, data)) {
850 cmd->error = sd_rw_multi(host, mrq);
851 if (!host->using_cookie)
852 sdmmc_post_req(host->mmc, host->mrq, 0);
854 if (mmc_op_multi(cmd->opcode) && mrq->stop)
855 sd_send_cmd_get_rsp(host, mrq->stop);
857 sd_normal_rw(host, mrq);
861 if (cmd->error || data->error)
862 data->bytes_xfered = 0;
864 data->bytes_xfered = data->blocks * data->blksz;
867 mutex_unlock(&pcr->pcr_mutex);
871 dev_dbg(sdmmc_dev(host), "CMD %d 0x%08x error(%d)\n",
872 cmd->opcode, cmd->arg, cmd->error);
875 mutex_lock(&host->host_mutex);
877 mutex_unlock(&host->host_mutex);
879 mmc_request_done(mmc, mrq);
882 static void sdmmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
884 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
885 struct mmc_data *data = mrq->data;
887 mutex_lock(&host->host_mutex);
889 mutex_unlock(&host->host_mutex);
891 if (sd_rw_cmd(mrq->cmd) || sdio_extblock_cmd(mrq->cmd, data))
892 host->using_cookie = sd_pre_dma_transfer(host, data, false);
894 schedule_work(&host->work);
897 static int sd_set_bus_width(struct realtek_pci_sdmmc *host,
898 unsigned char bus_width)
902 [MMC_BUS_WIDTH_1] = SD_BUS_WIDTH_1BIT,
903 [MMC_BUS_WIDTH_4] = SD_BUS_WIDTH_4BIT,
904 [MMC_BUS_WIDTH_8] = SD_BUS_WIDTH_8BIT,
907 if (bus_width <= MMC_BUS_WIDTH_8)
908 err = rtsx_pci_write_register(host->pcr, SD_CFG1,
909 0x03, width[bus_width]);
914 static int sd_power_on(struct realtek_pci_sdmmc *host, unsigned char power_mode)
916 struct rtsx_pcr *pcr = host->pcr;
919 if (host->prev_power_state == MMC_POWER_ON)
922 if (host->prev_power_state == MMC_POWER_UP) {
923 rtsx_pci_write_register(pcr, SD_BUS_STAT, SD_CLK_TOGGLE_EN, 0);
929 rtsx_pci_init_cmd(pcr);
930 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SELECT, 0x07, SD_MOD_SEL);
931 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SHARE_MODE,
932 CARD_SHARE_MASK, CARD_SHARE_48_SD);
933 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN,
934 SD_CLK_EN, SD_CLK_EN);
935 err = rtsx_pci_send_cmd(pcr, 100);
939 err = rtsx_pci_card_pull_ctl_enable(pcr, RTSX_SD_CARD);
943 err = rtsx_pci_card_power_on(pcr, RTSX_SD_CARD);
949 err = rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN);
953 /* send at least 74 clocks */
954 rtsx_pci_write_register(pcr, SD_BUS_STAT, SD_CLK_TOGGLE_EN, SD_CLK_TOGGLE_EN);
957 host->prev_power_state = power_mode;
961 static int sd_power_off(struct realtek_pci_sdmmc *host)
963 struct rtsx_pcr *pcr = host->pcr;
966 host->prev_power_state = MMC_POWER_OFF;
968 rtsx_pci_init_cmd(pcr);
970 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, 0);
971 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0);
973 err = rtsx_pci_send_cmd(pcr, 100);
977 err = rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);
981 return rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD);
984 static int sd_set_power_mode(struct realtek_pci_sdmmc *host,
985 unsigned char power_mode)
989 if (power_mode == MMC_POWER_OFF)
990 err = sd_power_off(host);
992 err = sd_power_on(host, power_mode);
997 static int sd_set_timing(struct realtek_pci_sdmmc *host, unsigned char timing)
999 struct rtsx_pcr *pcr = host->pcr;
1002 rtsx_pci_init_cmd(pcr);
1005 case MMC_TIMING_UHS_SDR104:
1006 case MMC_TIMING_UHS_SDR50:
1007 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
1008 0x0C | SD_ASYNC_FIFO_NOT_RST,
1009 SD_30_MODE | SD_ASYNC_FIFO_NOT_RST);
1010 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1011 CLK_LOW_FREQ, CLK_LOW_FREQ);
1012 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1013 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
1014 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1017 case MMC_TIMING_MMC_DDR52:
1018 case MMC_TIMING_UHS_DDR50:
1019 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
1020 0x0C | SD_ASYNC_FIFO_NOT_RST,
1021 SD_DDR_MODE | SD_ASYNC_FIFO_NOT_RST);
1022 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1023 CLK_LOW_FREQ, CLK_LOW_FREQ);
1024 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1025 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
1026 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1027 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
1028 DDR_VAR_TX_CMD_DAT, DDR_VAR_TX_CMD_DAT);
1029 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
1030 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD,
1031 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD);
1034 case MMC_TIMING_MMC_HS:
1035 case MMC_TIMING_SD_HS:
1036 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
1038 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1039 CLK_LOW_FREQ, CLK_LOW_FREQ);
1040 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1041 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
1042 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1043 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
1044 SD20_TX_SEL_MASK, SD20_TX_14_AHEAD);
1045 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
1046 SD20_RX_SEL_MASK, SD20_RX_14_DELAY);
1050 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
1051 SD_CFG1, 0x0C, SD_20_MODE);
1052 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1053 CLK_LOW_FREQ, CLK_LOW_FREQ);
1054 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1055 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
1056 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1057 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
1058 SD_PUSH_POINT_CTL, 0xFF, 0);
1059 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
1060 SD20_RX_SEL_MASK, SD20_RX_POS_EDGE);
1064 err = rtsx_pci_send_cmd(pcr, 100);
1069 static void sdmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1071 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1072 struct rtsx_pcr *pcr = host->pcr;
1077 if (rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD))
1080 mutex_lock(&pcr->pcr_mutex);
1082 rtsx_pci_start_run(pcr);
1084 sd_set_bus_width(host, ios->bus_width);
1085 sd_set_power_mode(host, ios->power_mode);
1086 sd_set_timing(host, ios->timing);
1088 host->vpclk = false;
1089 host->double_clk = true;
1091 switch (ios->timing) {
1092 case MMC_TIMING_UHS_SDR104:
1093 case MMC_TIMING_UHS_SDR50:
1094 host->ssc_depth = RTSX_SSC_DEPTH_2M;
1096 host->double_clk = false;
1098 case MMC_TIMING_MMC_DDR52:
1099 case MMC_TIMING_UHS_DDR50:
1100 case MMC_TIMING_UHS_SDR25:
1101 host->ssc_depth = RTSX_SSC_DEPTH_1M;
1104 host->ssc_depth = RTSX_SSC_DEPTH_500K;
1108 host->initial_mode = (ios->clock <= 1000000) ? true : false;
1110 host->clock = ios->clock;
1111 rtsx_pci_switch_clock(pcr, ios->clock, host->ssc_depth,
1112 host->initial_mode, host->double_clk, host->vpclk);
1114 mutex_unlock(&pcr->pcr_mutex);
1117 static int sdmmc_get_ro(struct mmc_host *mmc)
1119 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1120 struct rtsx_pcr *pcr = host->pcr;
1127 mutex_lock(&pcr->pcr_mutex);
1129 rtsx_pci_start_run(pcr);
1131 /* Check SD mechanical write-protect switch */
1132 val = rtsx_pci_readl(pcr, RTSX_BIPR);
1133 dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val);
1134 if (val & SD_WRITE_PROTECT)
1137 mutex_unlock(&pcr->pcr_mutex);
1142 static int sdmmc_get_cd(struct mmc_host *mmc)
1144 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1145 struct rtsx_pcr *pcr = host->pcr;
1152 mutex_lock(&pcr->pcr_mutex);
1154 rtsx_pci_start_run(pcr);
1156 /* Check SD card detect */
1157 val = rtsx_pci_card_exist(pcr);
1158 dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val);
1162 mutex_unlock(&pcr->pcr_mutex);
1167 static int sd_wait_voltage_stable_1(struct realtek_pci_sdmmc *host)
1169 struct rtsx_pcr *pcr = host->pcr;
1173 /* Reference to Signal Voltage Switch Sequence in SD spec.
1174 * Wait for a period of time so that the card can drive SD_CMD and
1175 * SD_DAT[3:0] to low after sending back CMD11 response.
1179 /* SD_CMD, SD_DAT[3:0] should be driven to low by card;
1180 * If either one of SD_CMD,SD_DAT[3:0] is not low,
1181 * abort the voltage switch sequence;
1183 err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1187 if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1188 SD_DAT1_STATUS | SD_DAT0_STATUS))
1191 /* Stop toggle SD clock */
1192 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1193 0xFF, SD_CLK_FORCE_STOP);
1200 static int sd_wait_voltage_stable_2(struct realtek_pci_sdmmc *host)
1202 struct rtsx_pcr *pcr = host->pcr;
1206 /* Wait 1.8V output of voltage regulator in card stable */
1209 /* Toggle SD clock again */
1210 err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN);
1214 /* Wait for a period of time so that the card can drive
1215 * SD_DAT[3:0] to high at 1.8V
1219 /* SD_CMD, SD_DAT[3:0] should be pulled high by host */
1220 err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1224 mask = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1225 SD_DAT1_STATUS | SD_DAT0_STATUS;
1226 val = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1227 SD_DAT1_STATUS | SD_DAT0_STATUS;
1228 if ((stat & mask) != val) {
1229 dev_dbg(sdmmc_dev(host),
1230 "%s: SD_BUS_STAT = 0x%x\n", __func__, stat);
1231 rtsx_pci_write_register(pcr, SD_BUS_STAT,
1232 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
1233 rtsx_pci_write_register(pcr, CARD_CLK_EN, 0xFF, 0);
1240 static int sdmmc_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1242 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1243 struct rtsx_pcr *pcr = host->pcr;
1247 dev_dbg(sdmmc_dev(host), "%s: signal_voltage = %d\n",
1248 __func__, ios->signal_voltage);
1253 err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
1257 mutex_lock(&pcr->pcr_mutex);
1259 rtsx_pci_start_run(pcr);
1261 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1262 voltage = OUTPUT_3V3;
1264 voltage = OUTPUT_1V8;
1266 if (voltage == OUTPUT_1V8) {
1267 err = sd_wait_voltage_stable_1(host);
1272 err = rtsx_pci_switch_output_voltage(pcr, voltage);
1276 if (voltage == OUTPUT_1V8) {
1277 err = sd_wait_voltage_stable_2(host);
1283 /* Stop toggle SD clock in idle */
1284 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1285 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
1287 mutex_unlock(&pcr->pcr_mutex);
1292 static int sdmmc_execute_tuning(struct mmc_host *mmc, u32 opcode)
1294 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1295 struct rtsx_pcr *pcr = host->pcr;
1301 err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
1305 mutex_lock(&pcr->pcr_mutex);
1307 rtsx_pci_start_run(pcr);
1309 /* Set initial TX phase */
1310 switch (mmc->ios.timing) {
1311 case MMC_TIMING_UHS_SDR104:
1312 err = sd_change_phase(host, SDR104_TX_PHASE(pcr), false);
1315 case MMC_TIMING_UHS_SDR50:
1316 err = sd_change_phase(host, SDR50_TX_PHASE(pcr), false);
1319 case MMC_TIMING_UHS_DDR50:
1320 err = sd_change_phase(host, DDR50_TX_PHASE(pcr), false);
1330 /* Tuning RX phase */
1331 if ((mmc->ios.timing == MMC_TIMING_UHS_SDR104) ||
1332 (mmc->ios.timing == MMC_TIMING_UHS_SDR50))
1333 err = sd_tuning_rx(host, opcode);
1334 else if (mmc->ios.timing == MMC_TIMING_UHS_DDR50)
1335 err = sd_change_phase(host, DDR50_RX_PHASE(pcr), true);
1338 mutex_unlock(&pcr->pcr_mutex);
1343 static const struct mmc_host_ops realtek_pci_sdmmc_ops = {
1344 .pre_req = sdmmc_pre_req,
1345 .post_req = sdmmc_post_req,
1346 .request = sdmmc_request,
1347 .set_ios = sdmmc_set_ios,
1348 .get_ro = sdmmc_get_ro,
1349 .get_cd = sdmmc_get_cd,
1350 .start_signal_voltage_switch = sdmmc_switch_voltage,
1351 .execute_tuning = sdmmc_execute_tuning,
1354 static void init_extra_caps(struct realtek_pci_sdmmc *host)
1356 struct mmc_host *mmc = host->mmc;
1357 struct rtsx_pcr *pcr = host->pcr;
1359 dev_dbg(sdmmc_dev(host), "pcr->extra_caps = 0x%x\n", pcr->extra_caps);
1361 if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50)
1362 mmc->caps |= MMC_CAP_UHS_SDR50;
1363 if (pcr->extra_caps & EXTRA_CAPS_SD_SDR104)
1364 mmc->caps |= MMC_CAP_UHS_SDR104;
1365 if (pcr->extra_caps & EXTRA_CAPS_SD_DDR50)
1366 mmc->caps |= MMC_CAP_UHS_DDR50;
1367 if (pcr->extra_caps & EXTRA_CAPS_MMC_HSDDR)
1368 mmc->caps |= MMC_CAP_1_8V_DDR;
1369 if (pcr->extra_caps & EXTRA_CAPS_MMC_8BIT)
1370 mmc->caps |= MMC_CAP_8_BIT_DATA;
1373 static void realtek_init_host(struct realtek_pci_sdmmc *host)
1375 struct mmc_host *mmc = host->mmc;
1377 mmc->f_min = 250000;
1378 mmc->f_max = 208000000;
1379 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1380 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED |
1381 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_BUS_WIDTH_TEST |
1382 MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | MMC_CAP_ERASE;
1383 mmc->caps2 = MMC_CAP2_NO_PRESCAN_POWERUP | MMC_CAP2_FULL_PWR_CYCLE;
1384 mmc->max_current_330 = 400;
1385 mmc->max_current_180 = 800;
1386 mmc->ops = &realtek_pci_sdmmc_ops;
1388 init_extra_caps(host);
1390 mmc->max_segs = 256;
1391 mmc->max_seg_size = 65536;
1392 mmc->max_blk_size = 512;
1393 mmc->max_blk_count = 65535;
1394 mmc->max_req_size = 524288;
1397 static void rtsx_pci_sdmmc_card_event(struct platform_device *pdev)
1399 struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1402 mmc_detect_change(host->mmc, 0);
1405 static int rtsx_pci_sdmmc_drv_probe(struct platform_device *pdev)
1407 struct mmc_host *mmc;
1408 struct realtek_pci_sdmmc *host;
1409 struct rtsx_pcr *pcr;
1410 struct pcr_handle *handle = pdev->dev.platform_data;
1419 dev_dbg(&(pdev->dev), ": Realtek PCI-E SDMMC controller found\n");
1421 mmc = mmc_alloc_host(sizeof(*host), &pdev->dev);
1425 host = mmc_priv(mmc);
1430 host->prev_power_state = MMC_POWER_OFF;
1431 INIT_WORK(&host->work, sd_request);
1432 platform_set_drvdata(pdev, host);
1433 pcr->slots[RTSX_SD_CARD].p_dev = pdev;
1434 pcr->slots[RTSX_SD_CARD].card_event = rtsx_pci_sdmmc_card_event;
1436 mutex_init(&host->host_mutex);
1438 realtek_init_host(host);
1445 static int rtsx_pci_sdmmc_drv_remove(struct platform_device *pdev)
1447 struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1448 struct rtsx_pcr *pcr;
1449 struct mmc_host *mmc;
1455 pcr->slots[RTSX_SD_CARD].p_dev = NULL;
1456 pcr->slots[RTSX_SD_CARD].card_event = NULL;
1459 cancel_work_sync(&host->work);
1461 mutex_lock(&host->host_mutex);
1463 dev_dbg(&(pdev->dev),
1464 "%s: Controller removed during transfer\n",
1467 rtsx_pci_complete_unfinished_transfer(pcr);
1469 host->mrq->cmd->error = -ENOMEDIUM;
1470 if (host->mrq->stop)
1471 host->mrq->stop->error = -ENOMEDIUM;
1472 mmc_request_done(mmc, host->mrq);
1474 mutex_unlock(&host->host_mutex);
1476 mmc_remove_host(mmc);
1479 flush_work(&host->work);
1483 dev_dbg(&(pdev->dev),
1484 ": Realtek PCI-E SDMMC controller has been removed\n");
1489 static const struct platform_device_id rtsx_pci_sdmmc_ids[] = {
1491 .name = DRV_NAME_RTSX_PCI_SDMMC,
1496 MODULE_DEVICE_TABLE(platform, rtsx_pci_sdmmc_ids);
1498 static struct platform_driver rtsx_pci_sdmmc_driver = {
1499 .probe = rtsx_pci_sdmmc_drv_probe,
1500 .remove = rtsx_pci_sdmmc_drv_remove,
1501 .id_table = rtsx_pci_sdmmc_ids,
1503 .name = DRV_NAME_RTSX_PCI_SDMMC,
1506 module_platform_driver(rtsx_pci_sdmmc_driver);
1508 MODULE_LICENSE("GPL");
1509 MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
1510 MODULE_DESCRIPTION("Realtek PCI-E SD/MMC Card Host Driver");