drivers/mmc/host/rtsx_pci_sdmmc.c

   1 /* Realtek PCI-Express SD/MMC Card Interface driver
   2  *
   3  * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2, or (at your option) any
   8  * later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program; if not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * Author:
  19  *   Wei WANG <wei_wang@realsil.com.cn>
  20  */
  21
  22 #include <linux/module.h>
  23 #include <linux/slab.h>
  24 #include <linux/highmem.h>
  25 #include <linux/delay.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/workqueue.h>
  28 #include <linux/mmc/host.h>
  29 #include <linux/mmc/mmc.h>
  30 #include <linux/mmc/sd.h>
  31 #include <linux/mmc/sdio.h>
  32 #include <linux/mmc/card.h>
  33 #include <linux/mfd/rtsx_pci.h>
  34 #include <asm/unaligned.h>
  35
  36 struct realtek_pci_sdmmc {
  37         struct platform_device  *pdev;
  38         struct rtsx_pcr         *pcr;
  39         struct mmc_host         *mmc;
  40         struct mmc_request      *mrq;
  41 #define SDMMC_WORKQ_NAME        "rtsx_pci_sdmmc_workq"
  42
  43         struct work_struct      work;
  44         struct mutex            host_mutex;
  45
  46         u8                      ssc_depth;
  47         unsigned int            clock;
  48         bool                    vpclk;
  49         bool                    double_clk;
  50         bool                    eject;
  51         bool                    initial_mode;
  52         int                     prev_power_state;
  53         int                     sg_count;
  54         s32                     cookie;
  55         int                     cookie_sg_count;
  56         bool                    using_cookie;
  57 };
  58
  59 static inline struct device *sdmmc_dev(struct realtek_pci_sdmmc *host)
  60 {
  61         return &(host->pdev->dev);
  62 }
  63
  64 static inline void sd_clear_error(struct realtek_pci_sdmmc *host)
  65 {
  66         rtsx_pci_write_register(host->pcr, CARD_STOP,
  67                         SD_STOP | SD_CLR_ERR, SD_STOP | SD_CLR_ERR);
  68 }
  69
  70 #ifdef DEBUG
  71 static void dump_reg_range(struct realtek_pci_sdmmc *host, u16 start, u16 end)
  72 {
  73         u16 len = end - start + 1;
  74         int i;
  75         u8 data[8];
  76
  77         for (i = 0; i < len; i += 8) {
  78                 int j;
  79                 int n = min(8, len - i);
  80
  81                 memset(&data, 0, sizeof(data));
  82                 for (j = 0; j < n; j++)
  83                         rtsx_pci_read_register(host->pcr, start + i + j,
  84                                 data + j);
  85                 dev_dbg(sdmmc_dev(host), "0x%04X(%d): %8ph\n",
  86                         start + i, n, data);
  87         }
  88 }
  89
  90 static void sd_print_debug_regs(struct realtek_pci_sdmmc *host)
  91 {
  92         dump_reg_range(host, 0xFDA0, 0xFDB3);
  93         dump_reg_range(host, 0xFD52, 0xFD69);
  94 }
  95 #else
  96 #define sd_print_debug_regs(host)
  97 #endif /* DEBUG */
  98
  99 static inline int sd_get_cd_int(struct realtek_pci_sdmmc *host)
 100 {
 101         return rtsx_pci_readl(host->pcr, RTSX_BIPR) & SD_EXIST;
 102 }
 103
 104 static void sd_cmd_set_sd_cmd(struct rtsx_pcr *pcr, struct mmc_command *cmd)
 105 {
 106         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0, 0xFF,
 107                 SD_CMD_START | cmd->opcode);
 108         rtsx_pci_write_be32(pcr, SD_CMD1, cmd->arg);
 109 }
 110
 111 static void sd_cmd_set_data_len(struct rtsx_pcr *pcr, u16 blocks, u16 blksz)
 112 {
 113         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, blocks);
 114         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, blocks >> 8);
 115         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, blksz);
 116         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, blksz >> 8);
 117 }
 118
 119 static int sd_response_type(struct mmc_command *cmd)
 120 {
 121         switch (mmc_resp_type(cmd)) {
 122         case MMC_RSP_NONE:
 123                 return SD_RSP_TYPE_R0;
 124         case MMC_RSP_R1:
 125                 return SD_RSP_TYPE_R1;
 126         case MMC_RSP_R1_NO_CRC:
 127                 return SD_RSP_TYPE_R1 | SD_NO_CHECK_CRC7;
 128         case MMC_RSP_R1B:
 129                 return SD_RSP_TYPE_R1b;
 130         case MMC_RSP_R2:
 131                 return SD_RSP_TYPE_R2;
 132         case MMC_RSP_R3:
 133                 return SD_RSP_TYPE_R3;
 134         default:
 135                 return -EINVAL;
 136         }
 137 }
 138
 139 static int sd_status_index(int resp_type)
 140 {
 141         if (resp_type == SD_RSP_TYPE_R0)
 142                 return 0;
 143         else if (resp_type == SD_RSP_TYPE_R2)
 144                 return 16;
 145
 146         return 5;
 147 }
 148 /*
 149  * sd_pre_dma_transfer - do dma_map_sg() or using cookie
 150  *
 151  * @pre: if called in pre_req()
 152  * return:
 153  *      0 - do dma_map_sg()
 154  *      1 - using cookie
 155  */
 156 static int sd_pre_dma_transfer(struct realtek_pci_sdmmc *host,
 157                 struct mmc_data *data, bool pre)
 158 {
 159         struct rtsx_pcr *pcr = host->pcr;
 160         int read = data->flags & MMC_DATA_READ;
 161         int count = 0;
 162         int using_cookie = 0;
 163
 164         if (!pre && data->host_cookie && data->host_cookie != host->cookie) {
 165                 dev_err(sdmmc_dev(host),
 166                         "error: data->host_cookie = %d, host->cookie = %d\n",
 167                         data->host_cookie, host->cookie);
 168                 data->host_cookie = 0;
 169         }
 170
 171         if (pre || data->host_cookie != host->cookie) {
 172                 count = rtsx_pci_dma_map_sg(pcr, data->sg, data->sg_len, read);
 173         } else {
 174                 count = host->cookie_sg_count;
 175                 using_cookie = 1;
 176         }
 177
 178         if (pre) {
 179                 host->cookie_sg_count = count;
 180                 if (++host->cookie < 0)
 181                         host->cookie = 1;
 182                 data->host_cookie = host->cookie;
 183         } else {
 184                 host->sg_count = count;
 185         }
 186
 187         return using_cookie;
 188 }
 189
 190 static void sdmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
 191 {
 192         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
 193         struct mmc_data *data = mrq->data;
 194
 195         if (data->host_cookie) {
 196                 dev_err(sdmmc_dev(host),
 197                         "error: reset data->host_cookie = %d\n",
 198                         data->host_cookie);
 199                 data->host_cookie = 0;
 200         }
 201
 202         sd_pre_dma_transfer(host, data, true);
 203         dev_dbg(sdmmc_dev(host), "pre dma sg: %d\n", host->cookie_sg_count);
 204 }
 205
 206 static void sdmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
 207                 int err)
 208 {
 209         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
 210         struct rtsx_pcr *pcr = host->pcr;
 211         struct mmc_data *data = mrq->data;
 212         int read = data->flags & MMC_DATA_READ;
 213
 214         rtsx_pci_dma_unmap_sg(pcr, data->sg, data->sg_len, read);
 215         data->host_cookie = 0;
 216 }
 217
 218 static void sd_send_cmd_get_rsp(struct realtek_pci_sdmmc *host,
 219                 struct mmc_command *cmd)
 220 {
 221         struct rtsx_pcr *pcr = host->pcr;
 222         u8 cmd_idx = (u8)cmd->opcode;
 223         u32 arg = cmd->arg;
 224         int err = 0;
 225         int timeout = 100;
 226         int i;
 227         u8 *ptr;
 228         int rsp_type;
 229         int stat_idx;
 230         bool clock_toggled = false;
 231
 232         dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
 233                         __func__, cmd_idx, arg);
 234
 235         rsp_type = sd_response_type(cmd);
 236         if (rsp_type < 0)
 237                 goto out;
 238
 239         stat_idx = sd_status_index(rsp_type);
 240
 241         if (rsp_type == SD_RSP_TYPE_R1b)
 242                 timeout = cmd->busy_timeout ? cmd->busy_timeout : 3000;
 243
 244         if (cmd->opcode == SD_SWITCH_VOLTAGE) {
 245                 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
 246                                 0xFF, SD_CLK_TOGGLE_EN);
 247                 if (err < 0)
 248                         goto out;
 249
 250                 clock_toggled = true;
 251         }
 252
 253         rtsx_pci_init_cmd(pcr);
 254         sd_cmd_set_sd_cmd(pcr, cmd);
 255         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, rsp_type);
 256         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
 257                         0x01, PINGPONG_BUFFER);
 258         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
 259                         0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START);
 260         rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
 261                      SD_TRANSFER_END | SD_STAT_IDLE,
 262                      SD_TRANSFER_END | SD_STAT_IDLE);
 263
 264         if (rsp_type == SD_RSP_TYPE_R2) {
 265                 /* Read data from ping-pong buffer */
 266                 for (i = PPBUF_BASE2; i < PPBUF_BASE2 + 16; i++)
 267                         rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
 268         } else if (rsp_type != SD_RSP_TYPE_R0) {
 269                 /* Read data from SD_CMDx registers */
 270                 for (i = SD_CMD0; i <= SD_CMD4; i++)
 271                         rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
 272         }
 273
 274         rtsx_pci_add_cmd(pcr, READ_REG_CMD, SD_STAT1, 0, 0);
 275
 276         err = rtsx_pci_send_cmd(pcr, timeout);
 277         if (err < 0) {
 278                 sd_print_debug_regs(host);
 279                 sd_clear_error(host);
 280                 dev_dbg(sdmmc_dev(host),
 281                         "rtsx_pci_send_cmd error (err = %d)\n", err);
 282                 goto out;
 283         }
 284
 285         if (rsp_type == SD_RSP_TYPE_R0) {
 286                 err = 0;
 287                 goto out;
 288         }
 289
 290         /* Eliminate returned value of CHECK_REG_CMD */
 291         ptr = rtsx_pci_get_cmd_data(pcr) + 1;
 292
 293         /* Check (Start,Transmission) bit of Response */
 294         if ((ptr[0] & 0xC0) != 0) {
 295                 err = -EILSEQ;
 296                 dev_dbg(sdmmc_dev(host), "Invalid response bit\n");
 297                 goto out;
 298         }
 299
 300         /* Check CRC7 */
 301         if (!(rsp_type & SD_NO_CHECK_CRC7)) {
 302                 if (ptr[stat_idx] & SD_CRC7_ERR) {
 303                         err = -EILSEQ;
 304                         dev_dbg(sdmmc_dev(host), "CRC7 error\n");
 305                         goto out;
 306                 }
 307         }
 308
 309         if (rsp_type == SD_RSP_TYPE_R2) {
 310                 /*
 311                  * The controller offloads the last byte {CRC-7, end bit 1'b1}
 312                  * of response type R2. Assign dummy CRC, 0, and end bit to the
 313                  * byte(ptr[16], goes into the LSB of resp[3] later).
 314                  */
 315                 ptr[16] = 1;
 316
 317                 for (i = 0; i < 4; i++) {
 318                         cmd->resp[i] = get_unaligned_be32(ptr + 1 + i * 4);
 319                         dev_dbg(sdmmc_dev(host), "cmd->resp[%d] = 0x%08x\n",
 320                                         i, cmd->resp[i]);
 321                 }
 322         } else {
 323                 cmd->resp[0] = get_unaligned_be32(ptr + 1);
 324                 dev_dbg(sdmmc_dev(host), "cmd->resp[0] = 0x%08x\n",
 325                                 cmd->resp[0]);
 326         }
 327
 328 out:
 329         cmd->error = err;
 330
 331         if (err && clock_toggled)
 332                 rtsx_pci_write_register(pcr, SD_BUS_STAT,
 333                                 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
 334 }
 335
 336 static int sd_read_data(struct realtek_pci_sdmmc *host, struct mmc_command *cmd,
 337         u16 byte_cnt, u8 *buf, int buf_len, int timeout)
 338 {
 339         struct rtsx_pcr *pcr = host->pcr;
 340         int err;
 341         u8 trans_mode;
 342
 343         dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
 344                 __func__, cmd->opcode, cmd->arg);
 345
 346         if (!buf)
 347                 buf_len = 0;
 348
 349         if (cmd->opcode == MMC_SEND_TUNING_BLOCK)
 350                 trans_mode = SD_TM_AUTO_TUNING;
 351         else
 352                 trans_mode = SD_TM_NORMAL_READ;
 353
 354         rtsx_pci_init_cmd(pcr);
 355         sd_cmd_set_sd_cmd(pcr, cmd);
 356         sd_cmd_set_data_len(pcr, 1, byte_cnt);
 357         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
 358                         SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
 359                         SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6);
 360         if (trans_mode != SD_TM_AUTO_TUNING)
 361                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
 362                                 CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
 363
 364         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
 365                         0xFF, trans_mode | SD_TRANSFER_START);
 366         rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
 367                         SD_TRANSFER_END, SD_TRANSFER_END);
 368
 369         err = rtsx_pci_send_cmd(pcr, timeout);
 370         if (err < 0) {
 371                 sd_print_debug_regs(host);
 372                 dev_dbg(sdmmc_dev(host),
 373                         "rtsx_pci_send_cmd fail (err = %d)\n", err);
 374                 return err;
 375         }
 376
 377         if (buf && buf_len) {
 378                 err = rtsx_pci_read_ppbuf(pcr, buf, buf_len);
 379                 if (err < 0) {
 380                         dev_dbg(sdmmc_dev(host),
 381                                 "rtsx_pci_read_ppbuf fail (err = %d)\n", err);
 382                         return err;
 383                 }
 384         }
 385
 386         return 0;
 387 }
 388
 389 static int sd_write_data(struct realtek_pci_sdmmc *host,
 390         struct mmc_command *cmd, u16 byte_cnt, u8 *buf, int buf_len,
 391         int timeout)
 392 {
 393         struct rtsx_pcr *pcr = host->pcr;
 394         int err;
 395
 396         dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
 397                 __func__, cmd->opcode, cmd->arg);
 398
 399         if (!buf)
 400                 buf_len = 0;
 401
 402         sd_send_cmd_get_rsp(host, cmd);
 403         if (cmd->error)
 404                 return cmd->error;
 405
 406         if (buf && buf_len) {
 407                 err = rtsx_pci_write_ppbuf(pcr, buf, buf_len);
 408                 if (err < 0) {
 409                         dev_dbg(sdmmc_dev(host),
 410                                 "rtsx_pci_write_ppbuf fail (err = %d)\n", err);
 411                         return err;
 412                 }
 413         }
 414
 415         rtsx_pci_init_cmd(pcr);
 416         sd_cmd_set_data_len(pcr, 1, byte_cnt);
 417         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
 418                 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
 419                 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_0);
 420         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
 421                         SD_TRANSFER_START | SD_TM_AUTO_WRITE_3);
 422         rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
 423                         SD_TRANSFER_END, SD_TRANSFER_END);
 424
 425         err = rtsx_pci_send_cmd(pcr, timeout);
 426         if (err < 0) {
 427                 sd_print_debug_regs(host);
 428                 dev_dbg(sdmmc_dev(host),
 429                         "rtsx_pci_send_cmd fail (err = %d)\n", err);
 430                 return err;
 431         }
 432
 433         return 0;
 434 }
 435
 436 static int sd_read_long_data(struct realtek_pci_sdmmc *host,
 437         struct mmc_request *mrq)
 438 {
 439         struct rtsx_pcr *pcr = host->pcr;
 440         struct mmc_host *mmc = host->mmc;
 441         struct mmc_card *card = mmc->card;
 442         struct mmc_command *cmd = mrq->cmd;
 443         struct mmc_data *data = mrq->data;
 444         int uhs = mmc_card_uhs(card);
 445         u8 cfg2 = 0;
 446         int err;
 447         int resp_type;
 448         size_t data_len = data->blksz * data->blocks;
 449
 450         dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
 451                 __func__, cmd->opcode, cmd->arg);
 452
 453         resp_type = sd_response_type(cmd);
 454         if (resp_type < 0)
 455                 return resp_type;
 456
 457         if (!uhs)
 458                 cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
 459
 460         rtsx_pci_init_cmd(pcr);
 461         sd_cmd_set_sd_cmd(pcr, cmd);
 462         sd_cmd_set_data_len(pcr, data->blocks, data->blksz);
 463         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
 464                         DMA_DONE_INT, DMA_DONE_INT);
 465         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3,
 466                 0xFF, (u8)(data_len >> 24));
 467         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2,
 468                 0xFF, (u8)(data_len >> 16));
 469         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1,
 470                 0xFF, (u8)(data_len >> 8));
 471         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len);
 472         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
 473                 0x03 | DMA_PACK_SIZE_MASK,
 474                 DMA_DIR_FROM_CARD | DMA_EN | DMA_512);
 475         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
 476                         0x01, RING_BUFFER);
 477         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2 | resp_type);
 478         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
 479                         SD_TRANSFER_START | SD_TM_AUTO_READ_2);
 480         rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
 481                         SD_TRANSFER_END, SD_TRANSFER_END);
 482         rtsx_pci_send_cmd_no_wait(pcr);
 483
 484         err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, 1, 10000);
 485         if (err < 0) {
 486                 sd_print_debug_regs(host);
 487                 sd_clear_error(host);
 488                 return err;
 489         }
 490
 491         return 0;
 492 }
 493
 494 static int sd_write_long_data(struct realtek_pci_sdmmc *host,
 495         struct mmc_request *mrq)
 496 {
 497         struct rtsx_pcr *pcr = host->pcr;
 498         struct mmc_host *mmc = host->mmc;
 499         struct mmc_card *card = mmc->card;
 500         struct mmc_command *cmd = mrq->cmd;
 501         struct mmc_data *data = mrq->data;
 502         int uhs = mmc_card_uhs(card);
 503         u8 cfg2;
 504         int err;
 505         size_t data_len = data->blksz * data->blocks;
 506
 507         sd_send_cmd_get_rsp(host, cmd);
 508         if (cmd->error)
 509                 return cmd->error;
 510
 511         dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
 512                 __func__, cmd->opcode, cmd->arg);
 513
 514         cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 |
 515                 SD_NO_WAIT_BUSY_END | SD_NO_CHECK_CRC7 | SD_RSP_LEN_0;
 516
 517         if (!uhs)
 518                 cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
 519
 520         rtsx_pci_init_cmd(pcr);
 521         sd_cmd_set_data_len(pcr, data->blocks, data->blksz);
 522         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
 523                         DMA_DONE_INT, DMA_DONE_INT);
 524         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3,
 525                 0xFF, (u8)(data_len >> 24));
 526         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2,
 527                 0xFF, (u8)(data_len >> 16));
 528         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1,
 529                 0xFF, (u8)(data_len >> 8));
 530         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len);
 531         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
 532                 0x03 | DMA_PACK_SIZE_MASK,
 533                 DMA_DIR_TO_CARD | DMA_EN | DMA_512);
 534         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
 535                         0x01, RING_BUFFER);
 536         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2);
 537         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
 538                         SD_TRANSFER_START | SD_TM_AUTO_WRITE_3);
 539         rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
 540                         SD_TRANSFER_END, SD_TRANSFER_END);
 541         rtsx_pci_send_cmd_no_wait(pcr);
 542         err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, 0, 10000);
 543         if (err < 0) {
 544                 sd_clear_error(host);
 545                 return err;
 546         }
 547
 548         return 0;
 549 }
 550
 551 static inline void sd_enable_initial_mode(struct realtek_pci_sdmmc *host)
 552 {
 553         rtsx_pci_write_register(host->pcr, SD_CFG1,
 554                         SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_128);
 555 }
 556
 557 static inline void sd_disable_initial_mode(struct realtek_pci_sdmmc *host)
 558 {
 559         rtsx_pci_write_register(host->pcr, SD_CFG1,
 560                         SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_0);
 561 }
 562
 563 static int sd_rw_multi(struct realtek_pci_sdmmc *host, struct mmc_request *mrq)
 564 {
 565         struct mmc_data *data = mrq->data;
 566         int err;
 567
 568         if (host->sg_count < 0) {
 569                 data->error = host->sg_count;
 570                 dev_dbg(sdmmc_dev(host), "%s: sg_count = %d is invalid\n",
 571                         __func__, host->sg_count);
 572                 return data->error;
 573         }
 574
 575         if (data->flags & MMC_DATA_READ) {
 576                 if (host->initial_mode)
 577                         sd_disable_initial_mode(host);
 578
 579                 err = sd_read_long_data(host, mrq);
 580
 581                 if (host->initial_mode)
 582                         sd_enable_initial_mode(host);
 583
 584                 return err;
 585         }
 586
 587         return sd_write_long_data(host, mrq);
 588 }
 589
 590 static void sd_normal_rw(struct realtek_pci_sdmmc *host,
 591                 struct mmc_request *mrq)
 592 {
 593         struct mmc_command *cmd = mrq->cmd;
 594         struct mmc_data *data = mrq->data;
 595         u8 *buf;
 596
 597         buf = kzalloc(data->blksz, GFP_NOIO);
 598         if (!buf) {
 599                 cmd->error = -ENOMEM;
 600                 return;
 601         }
 602
 603         if (data->flags & MMC_DATA_READ) {
 604                 if (host->initial_mode)
 605                         sd_disable_initial_mode(host);
 606
 607                 cmd->error = sd_read_data(host, cmd, (u16)data->blksz, buf,
 608                                 data->blksz, 200);
 609
 610                 if (host->initial_mode)
 611                         sd_enable_initial_mode(host);
 612
 613                 sg_copy_from_buffer(data->sg, data->sg_len, buf, data->blksz);
 614         } else {
 615                 sg_copy_to_buffer(data->sg, data->sg_len, buf, data->blksz);
 616
 617                 cmd->error = sd_write_data(host, cmd, (u16)data->blksz, buf,
 618                                 data->blksz, 200);
 619         }
 620
 621         kfree(buf);
 622 }
 623
 624 static int sd_change_phase(struct realtek_pci_sdmmc *host,
 625                 u8 sample_point, bool rx)
 626 {
 627         struct rtsx_pcr *pcr = host->pcr;
 628         int err;
 629
 630         dev_dbg(sdmmc_dev(host), "%s(%s): sample_point = %d\n",
 631                         __func__, rx ? "RX" : "TX", sample_point);
 632
 633         rtsx_pci_init_cmd(pcr);
 634
 635         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, CHANGE_CLK);
 636         if (rx)
 637                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
 638                                 SD_VPRX_CTL, 0x1F, sample_point);
 639         else
 640                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
 641                                 SD_VPTX_CTL, 0x1F, sample_point);
 642         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0);
 643         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
 644                         PHASE_NOT_RESET, PHASE_NOT_RESET);
 645         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, 0);
 646         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
 647
 648         err = rtsx_pci_send_cmd(pcr, 100);
 649         if (err < 0)
 650                 return err;
 651
 652         return 0;
 653 }
 654
 655 static inline u32 test_phase_bit(u32 phase_map, unsigned int bit)
 656 {
 657         bit %= RTSX_PHASE_MAX;
 658         return phase_map & (1 << bit);
 659 }
 660
 661 static int sd_get_phase_len(u32 phase_map, unsigned int start_bit)
 662 {
 663         int i;
 664
 665         for (i = 0; i < RTSX_PHASE_MAX; i++) {
 666                 if (test_phase_bit(phase_map, start_bit + i) == 0)
 667                         return i;
 668         }
 669         return RTSX_PHASE_MAX;
 670 }
 671
 672 static u8 sd_search_final_phase(struct realtek_pci_sdmmc *host, u32 phase_map)
 673 {
 674         int start = 0, len = 0;
 675         int start_final = 0, len_final = 0;
 676         u8 final_phase = 0xFF;
 677
 678         if (phase_map == 0) {
 679                 dev_err(sdmmc_dev(host), "phase error: [map:%x]\n", phase_map);
 680                 return final_phase;
 681         }
 682
 683         while (start < RTSX_PHASE_MAX) {
 684                 len = sd_get_phase_len(phase_map, start);
 685                 if (len_final < len) {
 686                         start_final = start;
 687                         len_final = len;
 688                 }
 689                 start += len ? len : 1;
 690         }
 691
 692         final_phase = (start_final + len_final / 2) % RTSX_PHASE_MAX;
 693         dev_dbg(sdmmc_dev(host), "phase: [map:%x] [maxlen:%d] [final:%d]\n",
 694                 phase_map, len_final, final_phase);
 695
 696         return final_phase;
 697 }
 698
 699 static void sd_wait_data_idle(struct realtek_pci_sdmmc *host)
 700 {
 701         int err, i;
 702         u8 val = 0;
 703
 704         for (i = 0; i < 100; i++) {
 705                 err = rtsx_pci_read_register(host->pcr, SD_DATA_STATE, &val);
 706                 if (val & SD_DATA_IDLE)
 707                         return;
 708
 709                 udelay(100);
 710         }
 711 }
 712
 713 static int sd_tuning_rx_cmd(struct realtek_pci_sdmmc *host,
 714                 u8 opcode, u8 sample_point)
 715 {
 716         int err;
 717         struct mmc_command cmd = {};
 718
 719         err = sd_change_phase(host, sample_point, true);
 720         if (err < 0)
 721                 return err;
 722
 723         cmd.opcode = opcode;
 724         err = sd_read_data(host, &cmd, 0x40, NULL, 0, 100);
 725         if (err < 0) {
 726                 /* Wait till SD DATA IDLE */
 727                 sd_wait_data_idle(host);
 728                 sd_clear_error(host);
 729                 return err;
 730         }
 731
 732         return 0;
 733 }
 734
 735 static int sd_tuning_phase(struct realtek_pci_sdmmc *host,
 736                 u8 opcode, u32 *phase_map)
 737 {
 738         int err, i;
 739         u32 raw_phase_map = 0;
 740
 741         for (i = 0; i < RTSX_PHASE_MAX; i++) {
 742                 err = sd_tuning_rx_cmd(host, opcode, (u8)i);
 743                 if (err == 0)
 744                         raw_phase_map |= 1 << i;
 745         }
 746
 747         if (phase_map)
 748                 *phase_map = raw_phase_map;
 749
 750         return 0;
 751 }
 752
 753 static int sd_tuning_rx(struct realtek_pci_sdmmc *host, u8 opcode)
 754 {
 755         int err, i;
 756         u32 raw_phase_map[RX_TUNING_CNT] = {0}, phase_map;
 757         u8 final_phase;
 758
 759         for (i = 0; i < RX_TUNING_CNT; i++) {
 760                 err = sd_tuning_phase(host, opcode, &(raw_phase_map[i]));
 761                 if (err < 0)
 762                         return err;
 763
 764                 if (raw_phase_map[i] == 0)
 765                         break;
 766         }
 767
 768         phase_map = 0xFFFFFFFF;
 769         for (i = 0; i < RX_TUNING_CNT; i++) {
 770                 dev_dbg(sdmmc_dev(host), "RX raw_phase_map[%d] = 0x%08x\n",
 771                                 i, raw_phase_map[i]);
 772                 phase_map &= raw_phase_map[i];
 773         }
 774         dev_dbg(sdmmc_dev(host), "RX phase_map = 0x%08x\n", phase_map);
 775
 776         if (phase_map) {
 777                 final_phase = sd_search_final_phase(host, phase_map);
 778                 if (final_phase == 0xFF)
 779                         return -EINVAL;
 780
 781                 err = sd_change_phase(host, final_phase, true);
 782                 if (err < 0)
 783                         return err;
 784         } else {
 785                 return -EINVAL;
 786         }
 787
 788         return 0;
 789 }
 790
 791 static inline int sdio_extblock_cmd(struct mmc_command *cmd,
 792         struct mmc_data *data)
 793 {
 794         return (cmd->opcode == SD_IO_RW_EXTENDED) && (data->blksz == 512);
 795 }
 796
 797 static inline int sd_rw_cmd(struct mmc_command *cmd)
 798 {
 799         return mmc_op_multi(cmd->opcode) ||
 800                 (cmd->opcode == MMC_READ_SINGLE_BLOCK) ||
 801                 (cmd->opcode == MMC_WRITE_BLOCK);
 802 }
 803
 804 static void sd_request(struct work_struct *work)
 805 {
 806         struct realtek_pci_sdmmc *host = container_of(work,
 807                         struct realtek_pci_sdmmc, work);
 808         struct rtsx_pcr *pcr = host->pcr;
 809
 810         struct mmc_host *mmc = host->mmc;
 811         struct mmc_request *mrq = host->mrq;
 812         struct mmc_command *cmd = mrq->cmd;
 813         struct mmc_data *data = mrq->data;
 814
 815         unsigned int data_size = 0;
 816         int err;
 817
 818         if (host->eject || !sd_get_cd_int(host)) {
 819                 cmd->error = -ENOMEDIUM;
 820                 goto finish;
 821         }
 822
 823         err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
 824         if (err) {
 825                 cmd->error = err;
 826                 goto finish;
 827         }
 828
 829         mutex_lock(&pcr->pcr_mutex);
 830
 831         rtsx_pci_start_run(pcr);
 832
 833         rtsx_pci_switch_clock(pcr, host->clock, host->ssc_depth,
 834                         host->initial_mode, host->double_clk, host->vpclk);
 835         rtsx_pci_write_register(pcr, CARD_SELECT, 0x07, SD_MOD_SEL);
 836         rtsx_pci_write_register(pcr, CARD_SHARE_MODE,
 837                         CARD_SHARE_MASK, CARD_SHARE_48_SD);
 838
 839         mutex_lock(&host->host_mutex);
 840         host->mrq = mrq;
 841         mutex_unlock(&host->host_mutex);
 842
 843         if (mrq->data)
 844                 data_size = data->blocks * data->blksz;
 845
 846         if (!data_size) {
 847                 sd_send_cmd_get_rsp(host, cmd);
 848         } else if (sd_rw_cmd(cmd) || sdio_extblock_cmd(cmd, data)) {
 849                 cmd->error = sd_rw_multi(host, mrq);
 850                 if (!host->using_cookie)
 851                         sdmmc_post_req(host->mmc, host->mrq, 0);
 852
 853                 if (mmc_op_multi(cmd->opcode) && mrq->stop)
 854                         sd_send_cmd_get_rsp(host, mrq->stop);
 855         } else {
 856                 sd_normal_rw(host, mrq);
 857         }
 858
 859         if (mrq->data) {
 860                 if (cmd->error || data->error)
 861                         data->bytes_xfered = 0;
 862                 else
 863                         data->bytes_xfered = data->blocks * data->blksz;
 864         }
 865
 866         mutex_unlock(&pcr->pcr_mutex);
 867
 868 finish:
 869         if (cmd->error) {
 870                 dev_dbg(sdmmc_dev(host), "CMD %d 0x%08x error(%d)\n",
 871                         cmd->opcode, cmd->arg, cmd->error);
 872         }
 873
 874         mutex_lock(&host->host_mutex);
 875         host->mrq = NULL;
 876         mutex_unlock(&host->host_mutex);
 877
 878         mmc_request_done(mmc, mrq);
 879 }
 880
 881 static void sdmmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
 882 {
 883         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
 884         struct mmc_data *data = mrq->data;
 885
 886         mutex_lock(&host->host_mutex);
 887         host->mrq = mrq;
 888         mutex_unlock(&host->host_mutex);
 889
 890         if (sd_rw_cmd(mrq->cmd) || sdio_extblock_cmd(mrq->cmd, data))
 891                 host->using_cookie = sd_pre_dma_transfer(host, data, false);
 892
 893         schedule_work(&host->work);
 894 }
 895
 896 static int sd_set_bus_width(struct realtek_pci_sdmmc *host,
 897                 unsigned char bus_width)
 898 {
 899         int err = 0;
 900         u8 width[] = {
 901                 [MMC_BUS_WIDTH_1] = SD_BUS_WIDTH_1BIT,
 902                 [MMC_BUS_WIDTH_4] = SD_BUS_WIDTH_4BIT,
 903                 [MMC_BUS_WIDTH_8] = SD_BUS_WIDTH_8BIT,
 904         };
 905
 906         if (bus_width <= MMC_BUS_WIDTH_8)
 907                 err = rtsx_pci_write_register(host->pcr, SD_CFG1,
 908                                 0x03, width[bus_width]);
 909
 910         return err;
 911 }
 912
 913 static int sd_power_on(struct realtek_pci_sdmmc *host, unsigned char power_mode)
 914 {
 915         struct rtsx_pcr *pcr = host->pcr;
 916         int err;
 917
 918         if (host->prev_power_state == MMC_POWER_ON)
 919                 return 0;
 920
 921         if (host->prev_power_state == MMC_POWER_UP) {
 922                 rtsx_pci_write_register(pcr, SD_BUS_STAT, SD_CLK_TOGGLE_EN, 0);
 923                 goto finish;
 924         }
 925
 926         msleep(100);
 927
 928         rtsx_pci_init_cmd(pcr);
 929         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SELECT, 0x07, SD_MOD_SEL);
 930         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SHARE_MODE,
 931                         CARD_SHARE_MASK, CARD_SHARE_48_SD);
 932         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN,
 933                         SD_CLK_EN, SD_CLK_EN);
 934         err = rtsx_pci_send_cmd(pcr, 100);
 935         if (err < 0)
 936                 return err;
 937
 938         err = rtsx_pci_card_pull_ctl_enable(pcr, RTSX_SD_CARD);
 939         if (err < 0)
 940                 return err;
 941
 942         err = rtsx_pci_card_power_on(pcr, RTSX_SD_CARD);
 943         if (err < 0)
 944                 return err;
 945
 946         mdelay(1);
 947
 948         err = rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN);
 949         if (err < 0)
 950                 return err;
 951
 952         /* send at least 74 clocks */
 953         rtsx_pci_write_register(pcr, SD_BUS_STAT, SD_CLK_TOGGLE_EN, SD_CLK_TOGGLE_EN);
 954
 955 finish:
 956         host->prev_power_state = power_mode;
 957         return 0;
 958 }
 959
 960 static int sd_power_off(struct realtek_pci_sdmmc *host)
 961 {
 962         struct rtsx_pcr *pcr = host->pcr;
 963         int err;
 964
 965         host->prev_power_state = MMC_POWER_OFF;
 966
 967         rtsx_pci_init_cmd(pcr);
 968
 969         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, 0);
 970         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0);
 971
 972         err = rtsx_pci_send_cmd(pcr, 100);
 973         if (err < 0)
 974                 return err;
 975
 976         err = rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);
 977         if (err < 0)
 978                 return err;
 979
 980         return rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD);
 981 }
 982
 983 static int sd_set_power_mode(struct realtek_pci_sdmmc *host,
 984                 unsigned char power_mode)
 985 {
 986         int err;
 987
 988         if (power_mode == MMC_POWER_OFF)
 989                 err = sd_power_off(host);
 990         else
 991                 err = sd_power_on(host, power_mode);
 992
 993         return err;
 994 }
 995
 996 static int sd_set_timing(struct realtek_pci_sdmmc *host, unsigned char timing)
 997 {
 998         struct rtsx_pcr *pcr = host->pcr;
 999         int err = 0;
1000
1001         rtsx_pci_init_cmd(pcr);
1002
1003         switch (timing) {
1004         case MMC_TIMING_UHS_SDR104:
1005         case MMC_TIMING_UHS_SDR50:
1006                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
1007                                 0x0C | SD_ASYNC_FIFO_NOT_RST,
1008                                 SD_30_MODE | SD_ASYNC_FIFO_NOT_RST);
1009                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1010                                 CLK_LOW_FREQ, CLK_LOW_FREQ);
1011                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1012                                 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
1013                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1014                 break;
1015
1016         case MMC_TIMING_MMC_DDR52:
1017         case MMC_TIMING_UHS_DDR50:
1018                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
1019                                 0x0C | SD_ASYNC_FIFO_NOT_RST,
1020                                 SD_DDR_MODE | SD_ASYNC_FIFO_NOT_RST);
1021                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1022                                 CLK_LOW_FREQ, CLK_LOW_FREQ);
1023                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1024                                 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
1025                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1026                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
1027                                 DDR_VAR_TX_CMD_DAT, DDR_VAR_TX_CMD_DAT);
1028                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
1029                                 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD,
1030                                 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD);
1031                 break;
1032
1033         case MMC_TIMING_MMC_HS:
1034         case MMC_TIMING_SD_HS:
1035                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
1036                                 0x0C, SD_20_MODE);
1037                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1038                                 CLK_LOW_FREQ, CLK_LOW_FREQ);
1039                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1040                                 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
1041                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1042                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
1043                                 SD20_TX_SEL_MASK, SD20_TX_14_AHEAD);
1044                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
1045                                 SD20_RX_SEL_MASK, SD20_RX_14_DELAY);
1046                 break;
1047
1048         default:
1049                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
1050                                 SD_CFG1, 0x0C, SD_20_MODE);
1051                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1052                                 CLK_LOW_FREQ, CLK_LOW_FREQ);
1053                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1054                                 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
1055                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1056                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
1057                                 SD_PUSH_POINT_CTL, 0xFF, 0);
1058                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
1059                                 SD20_RX_SEL_MASK, SD20_RX_POS_EDGE);
1060                 break;
1061         }
1062
1063         err = rtsx_pci_send_cmd(pcr, 100);
1064
1065         return err;
1066 }
1067
1068 static void sdmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1069 {
1070         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1071         struct rtsx_pcr *pcr = host->pcr;
1072
1073         if (host->eject)
1074                 return;
1075
1076         if (rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD))
1077                 return;
1078
1079         mutex_lock(&pcr->pcr_mutex);
1080
1081         rtsx_pci_start_run(pcr);
1082
1083         sd_set_bus_width(host, ios->bus_width);
1084         sd_set_power_mode(host, ios->power_mode);
1085         sd_set_timing(host, ios->timing);
1086
1087         host->vpclk = false;
1088         host->double_clk = true;
1089
1090         switch (ios->timing) {
1091         case MMC_TIMING_UHS_SDR104:
1092         case MMC_TIMING_UHS_SDR50:
1093                 host->ssc_depth = RTSX_SSC_DEPTH_2M;
1094                 host->vpclk = true;
1095                 host->double_clk = false;
1096                 break;
1097         case MMC_TIMING_MMC_DDR52:
1098         case MMC_TIMING_UHS_DDR50:
1099         case MMC_TIMING_UHS_SDR25:
1100                 host->ssc_depth = RTSX_SSC_DEPTH_1M;
1101                 break;
1102         default:
1103                 host->ssc_depth = RTSX_SSC_DEPTH_500K;
1104                 break;
1105         }
1106
1107         host->initial_mode = (ios->clock <= 1000000) ? true : false;
1108
1109         host->clock = ios->clock;
1110         rtsx_pci_switch_clock(pcr, ios->clock, host->ssc_depth,
1111                         host->initial_mode, host->double_clk, host->vpclk);
1112
1113         mutex_unlock(&pcr->pcr_mutex);
1114 }
1115
1116 static int sdmmc_get_ro(struct mmc_host *mmc)
1117 {
1118         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1119         struct rtsx_pcr *pcr = host->pcr;
1120         int ro = 0;
1121         u32 val;
1122
1123         if (host->eject)
1124                 return -ENOMEDIUM;
1125
1126         mutex_lock(&pcr->pcr_mutex);
1127
1128         rtsx_pci_start_run(pcr);
1129
1130         /* Check SD mechanical write-protect switch */
1131         val = rtsx_pci_readl(pcr, RTSX_BIPR);
1132         dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val);
1133         if (val & SD_WRITE_PROTECT)
1134                 ro = 1;
1135
1136         mutex_unlock(&pcr->pcr_mutex);
1137
1138         return ro;
1139 }
1140
1141 static int sdmmc_get_cd(struct mmc_host *mmc)
1142 {
1143         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1144         struct rtsx_pcr *pcr = host->pcr;
1145         int cd = 0;
1146         u32 val;
1147
1148         if (host->eject)
1149                 return cd;
1150
1151         mutex_lock(&pcr->pcr_mutex);
1152
1153         rtsx_pci_start_run(pcr);
1154
1155         /* Check SD card detect */
1156         val = rtsx_pci_card_exist(pcr);
1157         dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val);
1158         if (val & SD_EXIST)
1159                 cd = 1;
1160
1161         mutex_unlock(&pcr->pcr_mutex);
1162
1163         return cd;
1164 }
1165
1166 static int sd_wait_voltage_stable_1(struct realtek_pci_sdmmc *host)
1167 {
1168         struct rtsx_pcr *pcr = host->pcr;
1169         int err;
1170         u8 stat;
1171
1172         /* Reference to Signal Voltage Switch Sequence in SD spec.
1173          * Wait for a period of time so that the card can drive SD_CMD and
1174          * SD_DAT[3:0] to low after sending back CMD11 response.
1175          */
1176         mdelay(1);
1177
1178         /* SD_CMD, SD_DAT[3:0] should be driven to low by card;
1179          * If either one of SD_CMD,SD_DAT[3:0] is not low,
1180          * abort the voltage switch sequence;
1181          */
1182         err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1183         if (err < 0)
1184                 return err;
1185
1186         if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1187                                 SD_DAT1_STATUS | SD_DAT0_STATUS))
1188                 return -EINVAL;
1189
1190         /* Stop toggle SD clock */
1191         err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1192                         0xFF, SD_CLK_FORCE_STOP);
1193         if (err < 0)
1194                 return err;
1195
1196         return 0;
1197 }
1198
1199 static int sd_wait_voltage_stable_2(struct realtek_pci_sdmmc *host)
1200 {
1201         struct rtsx_pcr *pcr = host->pcr;
1202         int err;
1203         u8 stat, mask, val;
1204
1205         /* Wait 1.8V output of voltage regulator in card stable */
1206         msleep(50);
1207
1208         /* Toggle SD clock again */
1209         err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN);
1210         if (err < 0)
1211                 return err;
1212
1213         /* Wait for a period of time so that the card can drive
1214          * SD_DAT[3:0] to high at 1.8V
1215          */
1216         msleep(20);
1217
1218         /* SD_CMD, SD_DAT[3:0] should be pulled high by host */
1219         err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1220         if (err < 0)
1221                 return err;
1222
1223         mask = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1224                 SD_DAT1_STATUS | SD_DAT0_STATUS;
1225         val = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1226                 SD_DAT1_STATUS | SD_DAT0_STATUS;
1227         if ((stat & mask) != val) {
1228                 dev_dbg(sdmmc_dev(host),
1229                         "%s: SD_BUS_STAT = 0x%x\n", __func__, stat);
1230                 rtsx_pci_write_register(pcr, SD_BUS_STAT,
1231                                 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
1232                 rtsx_pci_write_register(pcr, CARD_CLK_EN, 0xFF, 0);
1233                 return -EINVAL;
1234         }
1235
1236         return 0;
1237 }
1238
1239 static int sdmmc_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1240 {
1241         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1242         struct rtsx_pcr *pcr = host->pcr;
1243         int err = 0;
1244         u8 voltage;
1245
1246         dev_dbg(sdmmc_dev(host), "%s: signal_voltage = %d\n",
1247                         __func__, ios->signal_voltage);
1248
1249         if (host->eject)
1250                 return -ENOMEDIUM;
1251
1252         err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
1253         if (err)
1254                 return err;
1255
1256         mutex_lock(&pcr->pcr_mutex);
1257
1258         rtsx_pci_start_run(pcr);
1259
1260         if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1261                 voltage = OUTPUT_3V3;
1262         else
1263                 voltage = OUTPUT_1V8;
1264
1265         if (voltage == OUTPUT_1V8) {
1266                 err = sd_wait_voltage_stable_1(host);
1267                 if (err < 0)
1268                         goto out;
1269         }
1270
1271         err = rtsx_pci_switch_output_voltage(pcr, voltage);
1272         if (err < 0)
1273                 goto out;
1274
1275         if (voltage == OUTPUT_1V8) {
1276                 err = sd_wait_voltage_stable_2(host);
1277                 if (err < 0)
1278                         goto out;
1279         }
1280
1281 out:
1282         /* Stop toggle SD clock in idle */
1283         err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1284                         SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
1285
1286         mutex_unlock(&pcr->pcr_mutex);
1287
1288         return err;
1289 }
1290
1291 static int sdmmc_execute_tuning(struct mmc_host *mmc, u32 opcode)
1292 {
1293         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1294         struct rtsx_pcr *pcr = host->pcr;
1295         int err = 0;
1296
1297         if (host->eject)
1298                 return -ENOMEDIUM;
1299
1300         err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
1301         if (err)
1302                 return err;
1303
1304         mutex_lock(&pcr->pcr_mutex);
1305
1306         rtsx_pci_start_run(pcr);
1307
1308         /* Set initial TX phase */
1309         switch (mmc->ios.timing) {
1310         case MMC_TIMING_UHS_SDR104:
1311                 err = sd_change_phase(host, SDR104_TX_PHASE(pcr), false);
1312                 break;
1313
1314         case MMC_TIMING_UHS_SDR50:
1315                 err = sd_change_phase(host, SDR50_TX_PHASE(pcr), false);
1316                 break;
1317
1318         case MMC_TIMING_UHS_DDR50:
1319                 err = sd_change_phase(host, DDR50_TX_PHASE(pcr), false);
1320                 break;
1321
1322         default:
1323                 err = 0;
1324         }
1325
1326         if (err)
1327                 goto out;
1328
1329         /* Tuning RX phase */
1330         if ((mmc->ios.timing == MMC_TIMING_UHS_SDR104) ||
1331                         (mmc->ios.timing == MMC_TIMING_UHS_SDR50))
1332                 err = sd_tuning_rx(host, opcode);
1333         else if (mmc->ios.timing == MMC_TIMING_UHS_DDR50)
1334                 err = sd_change_phase(host, DDR50_RX_PHASE(pcr), true);
1335
1336 out:
1337         mutex_unlock(&pcr->pcr_mutex);
1338
1339         return err;
1340 }
1341
1342 static const struct mmc_host_ops realtek_pci_sdmmc_ops = {
1343         .pre_req = sdmmc_pre_req,
1344         .post_req = sdmmc_post_req,
1345         .request = sdmmc_request,
1346         .set_ios = sdmmc_set_ios,
1347         .get_ro = sdmmc_get_ro,
1348         .get_cd = sdmmc_get_cd,
1349         .start_signal_voltage_switch = sdmmc_switch_voltage,
1350         .execute_tuning = sdmmc_execute_tuning,
1351 };
1352
1353 static void init_extra_caps(struct realtek_pci_sdmmc *host)
1354 {
1355         struct mmc_host *mmc = host->mmc;
1356         struct rtsx_pcr *pcr = host->pcr;
1357
1358         dev_dbg(sdmmc_dev(host), "pcr->extra_caps = 0x%x\n", pcr->extra_caps);
1359
1360         if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50)
1361                 mmc->caps |= MMC_CAP_UHS_SDR50;
1362         if (pcr->extra_caps & EXTRA_CAPS_SD_SDR104)
1363                 mmc->caps |= MMC_CAP_UHS_SDR104;
1364         if (pcr->extra_caps & EXTRA_CAPS_SD_DDR50)
1365                 mmc->caps |= MMC_CAP_UHS_DDR50;
1366         if (pcr->extra_caps & EXTRA_CAPS_MMC_HSDDR)
1367                 mmc->caps |= MMC_CAP_1_8V_DDR;
1368         if (pcr->extra_caps & EXTRA_CAPS_MMC_8BIT)
1369                 mmc->caps |= MMC_CAP_8_BIT_DATA;
1370 }
1371
1372 static void realtek_init_host(struct realtek_pci_sdmmc *host)
1373 {
1374         struct mmc_host *mmc = host->mmc;
1375
1376         mmc->f_min = 250000;
1377         mmc->f_max = 208000000;
1378         mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1379         mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED |
1380                 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_BUS_WIDTH_TEST |
1381                 MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | MMC_CAP_ERASE;
1382         mmc->caps2 = MMC_CAP2_NO_PRESCAN_POWERUP | MMC_CAP2_FULL_PWR_CYCLE;
1383         mmc->max_current_330 = 400;
1384         mmc->max_current_180 = 800;
1385         mmc->ops = &realtek_pci_sdmmc_ops;
1386
1387         init_extra_caps(host);
1388
1389         mmc->max_segs = 256;
1390         mmc->max_seg_size = 65536;
1391         mmc->max_blk_size = 512;
1392         mmc->max_blk_count = 65535;
1393         mmc->max_req_size = 524288;
1394 }
1395
1396 static void rtsx_pci_sdmmc_card_event(struct platform_device *pdev)
1397 {
1398         struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1399
1400         host->cookie = -1;
1401         mmc_detect_change(host->mmc, 0);
1402 }
1403
1404 static int rtsx_pci_sdmmc_drv_probe(struct platform_device *pdev)
1405 {
1406         struct mmc_host *mmc;
1407         struct realtek_pci_sdmmc *host;
1408         struct rtsx_pcr *pcr;
1409         struct pcr_handle *handle = pdev->dev.platform_data;
1410
1411         if (!handle)
1412                 return -ENXIO;
1413
1414         pcr = handle->pcr;
1415         if (!pcr)
1416                 return -ENXIO;
1417
1418         dev_dbg(&(pdev->dev), ": Realtek PCI-E SDMMC controller found\n");
1419
1420         mmc = mmc_alloc_host(sizeof(*host), &pdev->dev);
1421         if (!mmc)
1422                 return -ENOMEM;
1423
1424         host = mmc_priv(mmc);
1425         host->pcr = pcr;
1426         host->mmc = mmc;
1427         host->pdev = pdev;
1428         host->cookie = -1;
1429         host->prev_power_state = MMC_POWER_OFF;
1430         INIT_WORK(&host->work, sd_request);
1431         platform_set_drvdata(pdev, host);
1432         pcr->slots[RTSX_SD_CARD].p_dev = pdev;
1433         pcr->slots[RTSX_SD_CARD].card_event = rtsx_pci_sdmmc_card_event;
1434
1435         mutex_init(&host->host_mutex);
1436
1437         realtek_init_host(host);
1438
1439         mmc_add_host(mmc);
1440
1441         return 0;
1442 }
1443
1444 static int rtsx_pci_sdmmc_drv_remove(struct platform_device *pdev)
1445 {
1446         struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1447         struct rtsx_pcr *pcr;
1448         struct mmc_host *mmc;
1449
1450         if (!host)
1451                 return 0;
1452
1453         pcr = host->pcr;
1454         pcr->slots[RTSX_SD_CARD].p_dev = NULL;
1455         pcr->slots[RTSX_SD_CARD].card_event = NULL;
1456         mmc = host->mmc;
1457
1458         cancel_work_sync(&host->work);
1459
1460         mutex_lock(&host->host_mutex);
1461         if (host->mrq) {
1462                 dev_dbg(&(pdev->dev),
1463                         "%s: Controller removed during transfer\n",
1464                         mmc_hostname(mmc));
1465
1466                 rtsx_pci_complete_unfinished_transfer(pcr);
1467
1468                 host->mrq->cmd->error = -ENOMEDIUM;
1469                 if (host->mrq->stop)
1470                         host->mrq->stop->error = -ENOMEDIUM;
1471                 mmc_request_done(mmc, host->mrq);
1472         }
1473         mutex_unlock(&host->host_mutex);
1474
1475         mmc_remove_host(mmc);
1476         host->eject = true;
1477
1478         flush_work(&host->work);
1479
1480         mmc_free_host(mmc);
1481
1482         dev_dbg(&(pdev->dev),
1483                 ": Realtek PCI-E SDMMC controller has been removed\n");
1484
1485         return 0;
1486 }
1487
1488 static const struct platform_device_id rtsx_pci_sdmmc_ids[] = {
1489         {
1490                 .name = DRV_NAME_RTSX_PCI_SDMMC,
1491         }, {
1492                 /* sentinel */
1493         }
1494 };
1495 MODULE_DEVICE_TABLE(platform, rtsx_pci_sdmmc_ids);
1496
1497 static struct platform_driver rtsx_pci_sdmmc_driver = {
1498         .probe          = rtsx_pci_sdmmc_drv_probe,
1499         .remove         = rtsx_pci_sdmmc_drv_remove,
1500         .id_table       = rtsx_pci_sdmmc_ids,
1501         .driver         = {
1502                 .name   = DRV_NAME_RTSX_PCI_SDMMC,
1503         },
1504 };
1505 module_platform_driver(rtsx_pci_sdmmc_driver);
1506
1507 MODULE_LICENSE("GPL");
1508 MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
1509 MODULE_DESCRIPTION("Realtek PCI-E SD/MMC Card Host Driver");