2 * DMA support for Internal DMAC with SDHI SD/SDIO controller
4 * Copyright (C) 2016-17 Renesas Electronics Corporation
5 * Copyright (C) 2016-17 Horms Solutions, Simon Horman
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/device.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/io-64-nonatomic-hi-lo.h>
15 #include <linux/mfd/tmio.h>
16 #include <linux/mmc/host.h>
17 #include <linux/mod_devicetable.h>
18 #include <linux/module.h>
19 #include <linux/pagemap.h>
20 #include <linux/scatterlist.h>
21 #include <linux/sys_soc.h>
23 #include "renesas_sdhi.h"
26 #define DM_CM_DTRAN_MODE 0x820
27 #define DM_CM_DTRAN_CTRL 0x828
28 #define DM_CM_RST 0x830
29 #define DM_CM_INFO1 0x840
30 #define DM_CM_INFO1_MASK 0x848
31 #define DM_CM_INFO2 0x850
32 #define DM_CM_INFO2_MASK 0x858
33 #define DM_DTRAN_ADDR 0x880
35 /* DM_CM_DTRAN_MODE */
36 #define DTRAN_MODE_CH_NUM_CH0 0 /* "downstream" = for write commands */
37 #define DTRAN_MODE_CH_NUM_CH1 BIT(16) /* "uptream" = for read commands */
38 #define DTRAN_MODE_BUS_WID_TH (BIT(5) | BIT(4))
39 #define DTRAN_MODE_ADDR_MODE BIT(0) /* 1 = Increment address */
41 /* DM_CM_DTRAN_CTRL */
42 #define DTRAN_CTRL_DM_START BIT(0)
45 #define RST_DTRANRST1 BIT(9)
46 #define RST_DTRANRST0 BIT(8)
47 #define RST_RESERVED_BITS GENMASK_ULL(31, 0)
49 /* DM_CM_INFO1 and DM_CM_INFO1_MASK */
51 #define INFO1_DTRANEND1 BIT(17)
52 #define INFO1_DTRANEND0 BIT(16)
54 /* DM_CM_INFO2 and DM_CM_INFO2_MASK */
55 #define INFO2_DTRANERR1 BIT(17)
56 #define INFO2_DTRANERR0 BIT(16)
59 * Specification of this driver:
60 * - host->chan_{rx,tx} will be used as a flag of enabling/disabling the dma
61 * - Since this SDHI DMAC register set has 16 but 32-bit width, we
62 * need a custom accessor.
65 /* Definitions for sampling clocks */
66 static struct renesas_sdhi_scc rcar_gen3_scc_taps[] = {
73 static const struct renesas_sdhi_of_data of_rcar_gen3_compatible = {
74 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_WRPROTECT_DISABLE |
75 TMIO_MMC_CLK_ACTUAL | TMIO_MMC_HAVE_CBSY |
77 .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
81 .taps = rcar_gen3_scc_taps,
82 .taps_num = ARRAY_SIZE(rcar_gen3_scc_taps),
83 /* Gen3 SDHI DMAC can handle 0xffffffff blk count, but seg = 1 */
84 .max_blk_count = 0xffffffff,
88 static const struct of_device_id renesas_sdhi_internal_dmac_of_match[] = {
89 { .compatible = "renesas,sdhi-r8a7795", .data = &of_rcar_gen3_compatible, },
90 { .compatible = "renesas,sdhi-r8a7796", .data = &of_rcar_gen3_compatible, },
93 MODULE_DEVICE_TABLE(of, renesas_sdhi_internal_dmac_of_match);
96 renesas_sdhi_internal_dmac_dm_write(struct tmio_mmc_host *host,
99 writeq(val, host->ctl + addr);
103 renesas_sdhi_internal_dmac_enable_dma(struct tmio_mmc_host *host, bool enable)
105 if (!host->chan_tx || !host->chan_rx)
109 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_INFO1,
112 if (host->dma->enable)
113 host->dma->enable(host, enable);
117 renesas_sdhi_internal_dmac_abort_dma(struct tmio_mmc_host *host) {
118 u64 val = RST_DTRANRST1 | RST_DTRANRST0;
120 renesas_sdhi_internal_dmac_enable_dma(host, false);
122 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_RST,
123 RST_RESERVED_BITS & ~val);
124 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_RST,
125 RST_RESERVED_BITS | val);
127 renesas_sdhi_internal_dmac_enable_dma(host, true);
131 renesas_sdhi_internal_dmac_dataend_dma(struct tmio_mmc_host *host) {
132 tasklet_schedule(&host->dma_complete);
136 renesas_sdhi_internal_dmac_start_dma(struct tmio_mmc_host *host,
137 struct mmc_data *data)
139 struct scatterlist *sg = host->sg_ptr;
140 u32 dtran_mode = DTRAN_MODE_BUS_WID_TH | DTRAN_MODE_ADDR_MODE;
141 enum dma_data_direction dir;
145 /* This DMAC cannot handle if sg_len is not 1 */
146 WARN_ON(host->sg_len > 1);
148 /* This DMAC cannot handle if buffer is not 8-bytes alignment */
149 if (!IS_ALIGNED(sg->offset, 8))
152 if (data->flags & MMC_DATA_READ) {
153 dtran_mode |= DTRAN_MODE_CH_NUM_CH1;
154 dir = DMA_FROM_DEVICE;
155 irq_mask = TMIO_STAT_RXRDY;
157 dtran_mode |= DTRAN_MODE_CH_NUM_CH0;
159 irq_mask = TMIO_STAT_TXRQ;
162 ret = dma_map_sg(&host->pdev->dev, sg, host->sg_len, dir);
166 renesas_sdhi_internal_dmac_enable_dma(host, true);
168 /* disable PIO irqs to avoid "PIO IRQ in DMA mode!" */
169 tmio_mmc_disable_mmc_irqs(host, irq_mask);
171 /* set dma parameters */
172 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_DTRAN_MODE,
174 renesas_sdhi_internal_dmac_dm_write(host, DM_DTRAN_ADDR,
180 host->force_pio = true;
181 renesas_sdhi_internal_dmac_enable_dma(host, false);
184 static void renesas_sdhi_internal_dmac_issue_tasklet_fn(unsigned long arg)
186 struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg;
188 tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND);
191 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_DTRAN_CTRL,
192 DTRAN_CTRL_DM_START);
195 static void renesas_sdhi_internal_dmac_complete_tasklet_fn(unsigned long arg)
197 struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg;
198 enum dma_data_direction dir;
200 spin_lock_irq(&host->lock);
205 if (host->data->flags & MMC_DATA_READ)
206 dir = DMA_FROM_DEVICE;
210 renesas_sdhi_internal_dmac_enable_dma(host, false);
211 dma_unmap_sg(&host->pdev->dev, host->sg_ptr, host->sg_len, dir);
213 tmio_mmc_do_data_irq(host);
215 spin_unlock_irq(&host->lock);
219 renesas_sdhi_internal_dmac_request_dma(struct tmio_mmc_host *host,
220 struct tmio_mmc_data *pdata)
222 /* Each value is set to non-zero to assume "enabling" each DMA */
223 host->chan_rx = host->chan_tx = (void *)0xdeadbeaf;
225 tasklet_init(&host->dma_complete,
226 renesas_sdhi_internal_dmac_complete_tasklet_fn,
227 (unsigned long)host);
228 tasklet_init(&host->dma_issue,
229 renesas_sdhi_internal_dmac_issue_tasklet_fn,
230 (unsigned long)host);
234 renesas_sdhi_internal_dmac_release_dma(struct tmio_mmc_host *host)
236 /* Each value is set to zero to assume "disabling" each DMA */
237 host->chan_rx = host->chan_tx = NULL;
240 static const struct tmio_mmc_dma_ops renesas_sdhi_internal_dmac_dma_ops = {
241 .start = renesas_sdhi_internal_dmac_start_dma,
242 .enable = renesas_sdhi_internal_dmac_enable_dma,
243 .request = renesas_sdhi_internal_dmac_request_dma,
244 .release = renesas_sdhi_internal_dmac_release_dma,
245 .abort = renesas_sdhi_internal_dmac_abort_dma,
246 .dataend = renesas_sdhi_internal_dmac_dataend_dma,
250 * Whitelist of specific R-Car Gen3 SoC ES versions to use this DMAC
251 * implementation as others may use a different implementation.
253 static const struct soc_device_attribute gen3_soc_whitelist[] = {
254 { .soc_id = "r8a7795", .revision = "ES1.*" },
255 { .soc_id = "r8a7795", .revision = "ES2.0" },
256 { .soc_id = "r8a7796", .revision = "ES1.0" },
260 static int renesas_sdhi_internal_dmac_probe(struct platform_device *pdev)
262 if (!soc_device_match(gen3_soc_whitelist))
265 return renesas_sdhi_probe(pdev, &renesas_sdhi_internal_dmac_dma_ops);
268 static const struct dev_pm_ops renesas_sdhi_internal_dmac_dev_pm_ops = {
269 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
270 pm_runtime_force_resume)
271 SET_RUNTIME_PM_OPS(tmio_mmc_host_runtime_suspend,
272 tmio_mmc_host_runtime_resume,
276 static struct platform_driver renesas_internal_dmac_sdhi_driver = {
278 .name = "renesas_sdhi_internal_dmac",
279 .pm = &renesas_sdhi_internal_dmac_dev_pm_ops,
280 .of_match_table = renesas_sdhi_internal_dmac_of_match,
282 .probe = renesas_sdhi_internal_dmac_probe,
283 .remove = renesas_sdhi_remove,
286 module_platform_driver(renesas_internal_dmac_sdhi_driver);
288 MODULE_DESCRIPTION("Renesas SDHI driver for internal DMAC");
289 MODULE_AUTHOR("Yoshihiro Shimoda");
290 MODULE_LICENSE("GPL v2");