drivers/mmc/host/renesas_sdhi_core.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Renesas SDHI
   4  *
   5  * Copyright (C) 2015-19 Renesas Electronics Corporation
   6  * Copyright (C) 2016-19 Sang Engineering, Wolfram Sang
   7  * Copyright (C) 2016-17 Horms Solutions, Simon Horman
   8  * Copyright (C) 2009 Magnus Damm
   9  *
  10  * Based on "Compaq ASIC3 support":
  11  *
  12  * Copyright 2001 Compaq Computer Corporation.
  13  * Copyright 2004-2005 Phil Blundell
  14  * Copyright 2007-2008 OpenedHand Ltd.
  15  *
  16  * Authors: Phil Blundell <pb@handhelds.org>,
  17  *          Samuel Ortiz <sameo@openedhand.com>
  18  *
  19  */
  20
  21 #include <linux/kernel.h>
  22 #include <linux/clk.h>
  23 #include <linux/slab.h>
  24 #include <linux/module.h>
  25 #include <linux/of_device.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/pm_domain.h>
  28 #include <linux/mmc/host.h>
  29 #include <linux/mmc/mmc.h>
  30 #include <linux/mmc/slot-gpio.h>
  31 #include <linux/mfd/tmio.h>
  32 #include <linux/sh_dma.h>
  33 #include <linux/delay.h>
  34 #include <linux/pinctrl/consumer.h>
  35 #include <linux/pinctrl/pinctrl-state.h>
  36 #include <linux/regulator/consumer.h>
  37 #include <linux/sys_soc.h>
  38
  39 #include "renesas_sdhi.h"
  40 #include "tmio_mmc.h"
  41
  42 #define HOST_MODE               0xe4
  43
  44 #define SDHI_VER_GEN2_SDR50     0x490c
  45 #define SDHI_VER_RZ_A1          0x820b
  46 /* very old datasheets said 0x490c for SDR104, too. They are wrong! */
  47 #define SDHI_VER_GEN2_SDR104    0xcb0d
  48 #define SDHI_VER_GEN3_SD        0xcc10
  49 #define SDHI_VER_GEN3_SDMMC     0xcd10
  50
  51 #define SDHI_GEN3_MMC0_ADDR     0xee140000
  52
  53 static void renesas_sdhi_sdbuf_width(struct tmio_mmc_host *host, int width)
  54 {
  55         u32 val;
  56
  57         /*
  58          * see also
  59          *      renesas_sdhi_of_data :: dma_buswidth
  60          */
  61         switch (sd_ctrl_read16(host, CTL_VERSION)) {
  62         case SDHI_VER_GEN2_SDR50:
  63                 val = (width == 32) ? 0x0001 : 0x0000;
  64                 break;
  65         case SDHI_VER_GEN2_SDR104:
  66                 val = (width == 32) ? 0x0000 : 0x0001;
  67                 break;
  68         case SDHI_VER_GEN3_SD:
  69         case SDHI_VER_GEN3_SDMMC:
  70                 if (width == 64)
  71                         val = 0x0000;
  72                 else if (width == 32)
  73                         val = 0x0101;
  74                 else
  75                         val = 0x0001;
  76                 break;
  77         default:
  78                 /* nothing to do */
  79                 return;
  80         }
  81
  82         sd_ctrl_write16(host, HOST_MODE, val);
  83 }
  84
  85 static int renesas_sdhi_clk_enable(struct tmio_mmc_host *host)
  86 {
  87         struct mmc_host *mmc = host->mmc;
  88         struct renesas_sdhi *priv = host_to_priv(host);
  89         int ret;
  90
  91         ret = clk_prepare_enable(priv->clk_cd);
  92         if (ret < 0)
  93                 return ret;
  94
  95         /*
  96          * The clock driver may not know what maximum frequency
  97          * actually works, so it should be set with the max-frequency
  98          * property which will already have been read to f_max.  If it
  99          * was missing, assume the current frequency is the maximum.
 100          */
 101         if (!mmc->f_max)
 102                 mmc->f_max = clk_get_rate(priv->clk);
 103
 104         /*
 105          * Minimum frequency is the minimum input clock frequency
 106          * divided by our maximum divider.
 107          */
 108         mmc->f_min = max(clk_round_rate(priv->clk, 1) / 512, 1L);
 109
 110         /* enable 16bit data access on SDBUF as default */
 111         renesas_sdhi_sdbuf_width(host, 16);
 112
 113         return 0;
 114 }
 115
 116 static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host,
 117                                             unsigned int new_clock)
 118 {
 119         struct renesas_sdhi *priv = host_to_priv(host);
 120         unsigned int freq, diff, best_freq = 0, diff_min = ~0;
 121         int i;
 122
 123         /*
 124          * We simply return the current rate if a) we are not on a R-Car Gen2+
 125          * SoC (may work for others, but untested) or b) if the SCC needs its
 126          * clock during tuning, so we don't change the external clock setup.
 127          */
 128         if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2) || mmc_doing_tune(host->mmc))
 129                 return clk_get_rate(priv->clk);
 130
 131         /*
 132          * We want the bus clock to be as close as possible to, but no
 133          * greater than, new_clock.  As we can divide by 1 << i for
 134          * any i in [0, 9] we want the input clock to be as close as
 135          * possible, but no greater than, new_clock << i.
 136          */
 137         for (i = min(9, ilog2(UINT_MAX / new_clock)); i >= 0; i--) {
 138                 freq = clk_round_rate(priv->clk, new_clock << i);
 139                 if (freq > (new_clock << i)) {
 140                         /* Too fast; look for a slightly slower option */
 141                         freq = clk_round_rate(priv->clk,
 142                                               (new_clock << i) / 4 * 3);
 143                         if (freq > (new_clock << i))
 144                                 continue;
 145                 }
 146
 147                 diff = new_clock - (freq >> i);
 148                 if (diff <= diff_min) {
 149                         best_freq = freq;
 150                         diff_min = diff;
 151                 }
 152         }
 153
 154         clk_set_rate(priv->clk, best_freq);
 155
 156         return clk_get_rate(priv->clk);
 157 }
 158
 159 static void renesas_sdhi_set_clock(struct tmio_mmc_host *host,
 160                                    unsigned int new_clock)
 161 {
 162         u32 clk = 0, clock;
 163
 164         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
 165                 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 166
 167         if (new_clock == 0) {
 168                 host->mmc->actual_clock = 0;
 169                 goto out;
 170         }
 171
 172         host->mmc->actual_clock = renesas_sdhi_clk_update(host, new_clock);
 173         clock = host->mmc->actual_clock / 512;
 174
 175         for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1)
 176                 clock <<= 1;
 177
 178         /* 1/1 clock is option */
 179         if ((host->pdata->flags & TMIO_MMC_CLK_ACTUAL) && ((clk >> 22) & 0x1)) {
 180                 if (!(host->mmc->ios.timing == MMC_TIMING_MMC_HS400))
 181                         clk |= 0xff;
 182                 else
 183                         clk &= ~0xff;
 184         }
 185
 186         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK);
 187         if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
 188                 usleep_range(10000, 11000);
 189
 190         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
 191                 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 192
 193 out:
 194         /* HW engineers overrode docs: no sleep needed on R-Car2+ */
 195         if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
 196                 usleep_range(10000, 11000);
 197 }
 198
 199 static void renesas_sdhi_clk_disable(struct tmio_mmc_host *host)
 200 {
 201         struct renesas_sdhi *priv = host_to_priv(host);
 202
 203         clk_disable_unprepare(priv->clk_cd);
 204 }
 205
 206 static int renesas_sdhi_card_busy(struct mmc_host *mmc)
 207 {
 208         struct tmio_mmc_host *host = mmc_priv(mmc);
 209
 210         return !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) &
 211                  TMIO_STAT_DAT0);
 212 }
 213
 214 static int renesas_sdhi_start_signal_voltage_switch(struct mmc_host *mmc,
 215                                                     struct mmc_ios *ios)
 216 {
 217         struct tmio_mmc_host *host = mmc_priv(mmc);
 218         struct renesas_sdhi *priv = host_to_priv(host);
 219         struct pinctrl_state *pin_state;
 220         int ret;
 221
 222         switch (ios->signal_voltage) {
 223         case MMC_SIGNAL_VOLTAGE_330:
 224                 pin_state = priv->pins_default;
 225                 break;
 226         case MMC_SIGNAL_VOLTAGE_180:
 227                 pin_state = priv->pins_uhs;
 228                 break;
 229         default:
 230                 return -EINVAL;
 231         }
 232
 233         /*
 234          * If anything is missing, assume signal voltage is fixed at
 235          * 3.3V and succeed/fail accordingly.
 236          */
 237         if (IS_ERR(priv->pinctrl) || IS_ERR(pin_state))
 238                 return ios->signal_voltage ==
 239                         MMC_SIGNAL_VOLTAGE_330 ? 0 : -EINVAL;
 240
 241         ret = mmc_regulator_set_vqmmc(host->mmc, ios);
 242         if (ret < 0)
 243                 return ret;
 244
 245         return pinctrl_select_state(priv->pinctrl, pin_state);
 246 }
 247
 248 /* SCC registers */
 249 #define SH_MOBILE_SDHI_SCC_DTCNTL       0x000
 250 #define SH_MOBILE_SDHI_SCC_TAPSET       0x002
 251 #define SH_MOBILE_SDHI_SCC_DT2FF        0x004
 252 #define SH_MOBILE_SDHI_SCC_CKSEL        0x006
 253 #define SH_MOBILE_SDHI_SCC_RVSCNTL      0x008
 254 #define SH_MOBILE_SDHI_SCC_RVSREQ       0x00A
 255 #define SH_MOBILE_SDHI_SCC_SMPCMP       0x00C
 256 #define SH_MOBILE_SDHI_SCC_TMPPORT2     0x00E
 257 #define SH_MOBILE_SDHI_SCC_TMPPORT3     0x014
 258 #define SH_MOBILE_SDHI_SCC_TMPPORT4     0x016
 259 #define SH_MOBILE_SDHI_SCC_TMPPORT5     0x018
 260 #define SH_MOBILE_SDHI_SCC_TMPPORT6     0x01A
 261 #define SH_MOBILE_SDHI_SCC_TMPPORT7     0x01C
 262
 263 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN         BIT(0)
 264 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT  16
 265 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK   0xff
 266
 267 #define SH_MOBILE_SDHI_SCC_CKSEL_DTSEL          BIT(0)
 268
 269 #define SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN        BIT(0)
 270
 271 #define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN    BIT(0)
 272 #define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP      BIT(1)
 273 #define SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR        BIT(2)
 274
 275 #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN   BIT(8)
 276 #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP     BIT(24)
 277 #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR       (BIT(8) | BIT(24))
 278
 279 #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL   BIT(4)
 280 #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN     BIT(31)
 281
 282 /* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT4 register */
 283 #define SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START       BIT(0)
 284
 285 /* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT5 register */
 286 #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R        BIT(8)
 287 #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W        (0 << 8)
 288 #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK        0x3F
 289
 290 /* Definitions for values the SH_MOBILE_SDHI_SCC register */
 291 #define SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE      0xa5000000
 292 #define SH_MOBILE_SDHI_SCC_TMPPORT_CALIB_CODE_MASK      0x1f
 293 #define SH_MOBILE_SDHI_SCC_TMPPORT_MANUAL_MODE          BIT(7)
 294
 295 static const u8 r8a7796_es13_calib_table[2][SDHI_CALIB_TABLE_MAX] = {
 296         { 3,  3,  3,  3,  3,  3,  3,  4,  4,  5,  6,  7,  8,  9, 10, 15,
 297          16, 16, 16, 16, 16, 16, 17, 18, 18, 19, 20, 21, 22, 23, 24, 25 },
 298         { 5,  5,  5,  5,  5,  5,  5,  5,  5,  5,  5,  5,  6,  7,  8, 11,
 299          12, 17, 18, 18, 18, 18, 18, 18, 18, 19, 20, 21, 22, 23, 25, 25 }
 300 };
 301
 302 static const u8 r8a77965_calib_table[2][SDHI_CALIB_TABLE_MAX] = {
 303         { 1,  2,  6,  6,  7,  8,  9, 10, 11, 12, 13, 14, 15, 15, 15, 16,
 304          17, 18, 19, 20, 21, 22, 23, 24, 25, 25, 26, 27, 28, 29, 30, 31 },
 305         { 2,  3,  4,  4,  5,  6,  7,  9, 10, 11, 12, 13, 14, 15, 16, 17,
 306          17, 17, 20, 21, 22, 23, 24, 25, 27, 28, 29, 30, 31, 31, 31, 31 }
 307 };
 308
 309 static const u8 r8a77990_calib_table[2][SDHI_CALIB_TABLE_MAX] = {
 310         { 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,
 311           0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0 },
 312         { 0,  0,  0,  1,  2,  3,  3,  4,  4,  4,  5,  5,  6,  8,  9, 10,
 313          11, 12, 13, 15, 16, 17, 17, 18, 18, 19, 20, 22, 24, 25, 26, 26 }
 314 };
 315
 316 static inline u32 sd_scc_read32(struct tmio_mmc_host *host,
 317                                 struct renesas_sdhi *priv, int addr)
 318 {
 319         return readl(priv->scc_ctl + (addr << host->bus_shift));
 320 }
 321
 322 static inline void sd_scc_write32(struct tmio_mmc_host *host,
 323                                   struct renesas_sdhi *priv,
 324                                   int addr, u32 val)
 325 {
 326         writel(val, priv->scc_ctl + (addr << host->bus_shift));
 327 }
 328
 329 static unsigned int renesas_sdhi_init_tuning(struct tmio_mmc_host *host)
 330 {
 331         struct renesas_sdhi *priv;
 332
 333         priv = host_to_priv(host);
 334
 335         /* Initialize SCC */
 336         sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, 0x0);
 337
 338         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
 339                         sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 340
 341         /* set sampling clock selection range */
 342         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
 343                        SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN |
 344                        0x8 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT);
 345
 346         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
 347                        SH_MOBILE_SDHI_SCC_CKSEL_DTSEL |
 348                        sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL));
 349
 350         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
 351                        ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
 352                        sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
 353
 354         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos);
 355
 356         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
 357                         sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 358
 359         /* Read TAPNUM */
 360         return (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL) >>
 361                 SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) &
 362                 SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK;
 363 }
 364
 365 static void renesas_sdhi_hs400_complete(struct mmc_host *mmc)
 366 {
 367         struct tmio_mmc_host *host = mmc_priv(mmc);
 368         struct renesas_sdhi *priv = host_to_priv(host);
 369         u32 bad_taps = priv->quirks ? priv->quirks->hs400_bad_taps : 0;
 370         bool use_4tap = priv->quirks && priv->quirks->hs400_4taps;
 371
 372         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
 373                 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 374
 375         /* Set HS400 mode */
 376         sd_ctrl_write16(host, CTL_SDIF_MODE, 0x0001 |
 377                         sd_ctrl_read16(host, CTL_SDIF_MODE));
 378
 379         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF,
 380                        priv->scc_tappos_hs400);
 381
 382         /* Gen3 can't do automatic tap correction with HS400, so disable it */
 383         if (sd_ctrl_read16(host, CTL_VERSION) == SDHI_VER_GEN3_SDMMC)
 384                 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
 385                                ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
 386                                sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
 387
 388         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2,
 389                        (SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN |
 390                         SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) |
 391                         sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2));
 392
 393         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
 394                        SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN |
 395                        sd_scc_read32(host, priv,
 396                                      SH_MOBILE_SDHI_SCC_DTCNTL));
 397
 398         /* Avoid bad TAP */
 399         if (bad_taps & BIT(priv->tap_set)) {
 400                 u32 new_tap = (priv->tap_set + 1) % priv->tap_num;
 401
 402                 if (bad_taps & BIT(new_tap))
 403                         new_tap = (priv->tap_set - 1) % priv->tap_num;
 404
 405                 if (bad_taps & BIT(new_tap)) {
 406                         new_tap = priv->tap_set;
 407                         dev_dbg(&host->pdev->dev, "Can't handle three bad tap in a row\n");
 408                 }
 409
 410                 priv->tap_set = new_tap;
 411         }
 412
 413         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET,
 414                        priv->tap_set / (use_4tap ? 2 : 1));
 415
 416         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
 417                        SH_MOBILE_SDHI_SCC_CKSEL_DTSEL |
 418                        sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL));
 419
 420         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
 421                         sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 422
 423         if (priv->adjust_hs400_calib_table)
 424                 priv->needs_adjust_hs400 = true;
 425 }
 426
 427 static void renesas_sdhi_reset_scc(struct tmio_mmc_host *host,
 428                                    struct renesas_sdhi *priv)
 429 {
 430         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
 431                         sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 432
 433         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
 434                        ~SH_MOBILE_SDHI_SCC_CKSEL_DTSEL &
 435                        sd_scc_read32(host, priv,
 436                                      SH_MOBILE_SDHI_SCC_CKSEL));
 437 }
 438
 439 static void renesas_sdhi_disable_scc(struct mmc_host *mmc)
 440 {
 441         struct tmio_mmc_host *host = mmc_priv(mmc);
 442         struct renesas_sdhi *priv = host_to_priv(host);
 443
 444         renesas_sdhi_reset_scc(host, priv);
 445
 446         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
 447                        ~SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN &
 448                        sd_scc_read32(host, priv,
 449                                      SH_MOBILE_SDHI_SCC_DTCNTL));
 450
 451         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
 452                         sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 453 }
 454
 455 static u32 sd_scc_tmpport_read32(struct tmio_mmc_host *host,
 456                                  struct renesas_sdhi *priv, u32 addr)
 457 {
 458         /* read mode */
 459         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT5,
 460                        SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R |
 461                        (SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr));
 462
 463         /* access start and stop */
 464         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4,
 465                        SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START);
 466         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 0);
 467
 468         return sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT7);
 469 }
 470
 471 static void sd_scc_tmpport_write32(struct tmio_mmc_host *host,
 472                                    struct renesas_sdhi *priv, u32 addr, u32 val)
 473 {
 474         /* write mode */
 475         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT5,
 476                        SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W |
 477                        (SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr));
 478
 479         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT6, val);
 480
 481         /* access start and stop */
 482         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4,
 483                        SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START);
 484         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 0);
 485 }
 486
 487 static void renesas_sdhi_adjust_hs400_mode_enable(struct tmio_mmc_host *host)
 488 {
 489         struct renesas_sdhi *priv = host_to_priv(host);
 490         u32 calib_code;
 491
 492         /* disable write protect */
 493         sd_scc_tmpport_write32(host, priv, 0x00,
 494                                SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE);
 495         /* read calibration code and adjust */
 496         calib_code = sd_scc_tmpport_read32(host, priv, 0x26);
 497         calib_code &= SH_MOBILE_SDHI_SCC_TMPPORT_CALIB_CODE_MASK;
 498
 499         sd_scc_tmpport_write32(host, priv, 0x22,
 500                                SH_MOBILE_SDHI_SCC_TMPPORT_MANUAL_MODE |
 501                                priv->adjust_hs400_calib_table[calib_code]);
 502
 503         /* set offset value to TMPPORT3, hardcoded to OFFSET0 (= 0x3) for now */
 504         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT3, 0x3);
 505
 506         /* adjustment done, clear flag */
 507         priv->needs_adjust_hs400 = false;
 508 }
 509
 510 static void renesas_sdhi_adjust_hs400_mode_disable(struct tmio_mmc_host *host)
 511 {
 512         struct renesas_sdhi *priv = host_to_priv(host);
 513
 514         /* disable write protect */
 515         sd_scc_tmpport_write32(host, priv, 0x00,
 516                                SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE);
 517         /* disable manual calibration */
 518         sd_scc_tmpport_write32(host, priv, 0x22, 0);
 519         /* clear offset value of TMPPORT3 */
 520         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT3, 0);
 521 }
 522
 523 static void renesas_sdhi_reset_hs400_mode(struct tmio_mmc_host *host,
 524                                           struct renesas_sdhi *priv)
 525 {
 526         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
 527                         sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 528
 529         /* Reset HS400 mode */
 530         sd_ctrl_write16(host, CTL_SDIF_MODE, ~0x0001 &
 531                         sd_ctrl_read16(host, CTL_SDIF_MODE));
 532
 533         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos);
 534
 535         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2,
 536                        ~(SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN |
 537                          SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) &
 538                         sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2));
 539
 540         if (priv->quirks && (priv->quirks->hs400_calib_table || priv->quirks->hs400_bad_taps))
 541                 renesas_sdhi_adjust_hs400_mode_disable(host);
 542
 543         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
 544                         sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 545 }
 546
 547 static int renesas_sdhi_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
 548 {
 549         struct tmio_mmc_host *host = mmc_priv(mmc);
 550
 551         renesas_sdhi_reset_hs400_mode(host, host_to_priv(host));
 552         return 0;
 553 }
 554
 555 static void renesas_sdhi_reset(struct tmio_mmc_host *host)
 556 {
 557         struct renesas_sdhi *priv = host_to_priv(host);
 558
 559         if (priv->scc_ctl) {
 560                 renesas_sdhi_reset_scc(host, priv);
 561                 renesas_sdhi_reset_hs400_mode(host, priv);
 562                 priv->needs_adjust_hs400 = false;
 563
 564                 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
 565                                 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 566
 567                 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
 568                                ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
 569                                sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
 570         }
 571
 572         if (host->pdata->flags & TMIO_MMC_MIN_RCAR2)
 573                 sd_ctrl_write32_as_16_and_16(host, CTL_IRQ_MASK,
 574                                              TMIO_MASK_ALL_RCAR2);
 575 }
 576
 577 #define SH_MOBILE_SDHI_MIN_TAP_ROW 3
 578
 579 static int renesas_sdhi_select_tuning(struct tmio_mmc_host *host)
 580 {
 581         struct renesas_sdhi *priv = host_to_priv(host);
 582         unsigned int tap_start = 0, tap_end = 0, tap_cnt = 0, rs, re, i;
 583         unsigned int taps_size = priv->tap_num * 2, min_tap_row;
 584         unsigned long *bitmap;
 585
 586         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
 587
 588         /*
 589          * When tuning CMD19 is issued twice for each tap, merge the
 590          * result requiring the tap to be good in both runs before
 591          * considering it for tuning selection.
 592          */
 593         for (i = 0; i < taps_size; i++) {
 594                 int offset = priv->tap_num * (i < priv->tap_num ? 1 : -1);
 595
 596                 if (!test_bit(i, priv->taps))
 597                         clear_bit(i + offset, priv->taps);
 598
 599                 if (!test_bit(i, priv->smpcmp))
 600                         clear_bit(i + offset, priv->smpcmp);
 601         }
 602
 603         /*
 604          * If all TAP are OK, the sampling clock position is selected by
 605          * identifying the change point of data.
 606          */
 607         if (bitmap_full(priv->taps, taps_size)) {
 608                 bitmap = priv->smpcmp;
 609                 min_tap_row = 1;
 610         } else {
 611                 bitmap = priv->taps;
 612                 min_tap_row = SH_MOBILE_SDHI_MIN_TAP_ROW;
 613         }
 614
 615         /*
 616          * Find the longest consecutive run of successful probes. If that
 617          * is at least SH_MOBILE_SDHI_MIN_TAP_ROW probes long then use the
 618          * center index as the tap, otherwise bail out.
 619          */
 620         bitmap_for_each_set_region(bitmap, rs, re, 0, taps_size) {
 621                 if (re - rs > tap_cnt) {
 622                         tap_end = re;
 623                         tap_start = rs;
 624                         tap_cnt = tap_end - tap_start;
 625                 }
 626         }
 627
 628         if (tap_cnt >= min_tap_row)
 629                 priv->tap_set = (tap_start + tap_end) / 2 % priv->tap_num;
 630         else
 631                 return -EIO;
 632
 633         /* Set SCC */
 634         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, priv->tap_set);
 635
 636         /* Enable auto re-tuning */
 637         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
 638                        SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN |
 639                        sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
 640
 641         return 0;
 642 }
 643
 644 static int renesas_sdhi_execute_tuning(struct mmc_host *mmc, u32 opcode)
 645 {
 646         struct tmio_mmc_host *host = mmc_priv(mmc);
 647         struct renesas_sdhi *priv = host_to_priv(host);
 648         int i, ret;
 649
 650         priv->tap_num = renesas_sdhi_init_tuning(host);
 651         if (!priv->tap_num)
 652                 return 0; /* Tuning is not supported */
 653
 654         if (priv->tap_num * 2 >= sizeof(priv->taps) * BITS_PER_BYTE) {
 655                 dev_err(&host->pdev->dev,
 656                         "Too many taps, please update 'taps' in tmio_mmc_host!\n");
 657                 return -EINVAL;
 658         }
 659
 660         bitmap_zero(priv->taps, priv->tap_num * 2);
 661         bitmap_zero(priv->smpcmp, priv->tap_num * 2);
 662
 663         /* Issue CMD19 twice for each tap */
 664         for (i = 0; i < 2 * priv->tap_num; i++) {
 665                 int cmd_error = 0;
 666
 667                 /* Set sampling clock position */
 668                 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, i % priv->tap_num);
 669
 670                 if (mmc_send_tuning(mmc, opcode, &cmd_error) == 0)
 671                         set_bit(i, priv->taps);
 672
 673                 if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) == 0)
 674                         set_bit(i, priv->smpcmp);
 675
 676                 if (cmd_error)
 677                         mmc_abort_tuning(mmc, opcode);
 678         }
 679
 680         ret = renesas_sdhi_select_tuning(host);
 681         if (ret < 0)
 682                 renesas_sdhi_reset(host);
 683         return ret;
 684 }
 685
 686 static bool renesas_sdhi_manual_correction(struct tmio_mmc_host *host, bool use_4tap)
 687 {
 688         struct renesas_sdhi *priv = host_to_priv(host);
 689         unsigned int new_tap = priv->tap_set, error_tap = priv->tap_set;
 690         u32 val;
 691
 692         val = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ);
 693         if (!val)
 694                 return false;
 695
 696         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
 697
 698         /* Change TAP position according to correction status */
 699         if (sd_ctrl_read16(host, CTL_VERSION) == SDHI_VER_GEN3_SDMMC &&
 700             host->mmc->ios.timing == MMC_TIMING_MMC_HS400) {
 701                 u32 bad_taps = priv->quirks ? priv->quirks->hs400_bad_taps : 0;
 702                 /*
 703                  * With HS400, the DAT signal is based on DS, not CLK.
 704                  * Therefore, use only CMD status.
 705                  */
 706                 u32 smpcmp = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) &
 707                                            SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR;
 708                 if (!smpcmp) {
 709                         return false;   /* no error in CMD signal */
 710                 } else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP) {
 711                         new_tap++;
 712                         error_tap--;
 713                 } else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN) {
 714                         new_tap--;
 715                         error_tap++;
 716                 } else {
 717                         return true;    /* need retune */
 718                 }
 719
 720                 /*
 721                  * When new_tap is a bad tap, we cannot change. Then, we compare
 722                  * with the HS200 tuning result. When smpcmp[error_tap] is OK,
 723                  * we can at least retune.
 724                  */
 725                 if (bad_taps & BIT(new_tap % priv->tap_num))
 726                         return test_bit(error_tap % priv->tap_num, priv->smpcmp);
 727         } else {
 728                 if (val & SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR)
 729                         return true;    /* need retune */
 730                 else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP)
 731                         new_tap++;
 732                 else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN)
 733                         new_tap--;
 734                 else
 735                         return false;
 736         }
 737
 738         priv->tap_set = (new_tap % priv->tap_num);
 739         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET,
 740                        priv->tap_set / (use_4tap ? 2 : 1));
 741
 742         return false;
 743 }
 744
 745 static bool renesas_sdhi_auto_correction(struct tmio_mmc_host *host)
 746 {
 747         struct renesas_sdhi *priv = host_to_priv(host);
 748
 749         /* Check SCC error */
 750         if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ) &
 751             SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) {
 752                 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
 753                 return true;
 754         }
 755
 756         return false;
 757 }
 758
 759 static bool renesas_sdhi_check_scc_error(struct tmio_mmc_host *host)
 760 {
 761         struct renesas_sdhi *priv = host_to_priv(host);
 762         bool use_4tap = priv->quirks && priv->quirks->hs400_4taps;
 763
 764         /*
 765          * Skip checking SCC errors when running on 4 taps in HS400 mode as
 766          * any retuning would still result in the same 4 taps being used.
 767          */
 768         if (!(host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) &&
 769             !(host->mmc->ios.timing == MMC_TIMING_MMC_HS200) &&
 770             !(host->mmc->ios.timing == MMC_TIMING_MMC_HS400 && !use_4tap))
 771                 return false;
 772
 773         if (mmc_doing_tune(host->mmc))
 774                 return false;
 775
 776         if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL) &
 777             SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN)
 778                 return renesas_sdhi_auto_correction(host);
 779
 780         return renesas_sdhi_manual_correction(host, use_4tap);
 781 }
 782
 783 static int renesas_sdhi_wait_idle(struct tmio_mmc_host *host, u32 bit)
 784 {
 785         int timeout = 1000;
 786         /* CBSY is set when busy, SCLKDIVEN is cleared when busy */
 787         u32 wait_state = (bit == TMIO_STAT_CMD_BUSY ? TMIO_STAT_CMD_BUSY : 0);
 788
 789         while (--timeout && (sd_ctrl_read16_and_16_as_32(host, CTL_STATUS)
 790                               & bit) == wait_state)
 791                 udelay(1);
 792
 793         if (!timeout) {
 794                 dev_warn(&host->pdev->dev, "timeout waiting for SD bus idle\n");
 795                 return -EBUSY;
 796         }
 797
 798         return 0;
 799 }
 800
 801 static int renesas_sdhi_write16_hook(struct tmio_mmc_host *host, int addr)
 802 {
 803         u32 bit = TMIO_STAT_SCLKDIVEN;
 804
 805         switch (addr) {
 806         case CTL_SD_CMD:
 807         case CTL_STOP_INTERNAL_ACTION:
 808         case CTL_XFER_BLK_COUNT:
 809         case CTL_SD_XFER_LEN:
 810         case CTL_SD_MEM_CARD_OPT:
 811         case CTL_TRANSACTION_CTL:
 812         case CTL_DMA_ENABLE:
 813         case HOST_MODE:
 814                 if (host->pdata->flags & TMIO_MMC_HAVE_CBSY)
 815                         bit = TMIO_STAT_CMD_BUSY;
 816                 fallthrough;
 817         case CTL_SD_CARD_CLK_CTL:
 818                 return renesas_sdhi_wait_idle(host, bit);
 819         }
 820
 821         return 0;
 822 }
 823
 824 static int renesas_sdhi_multi_io_quirk(struct mmc_card *card,
 825                                        unsigned int direction, int blk_size)
 826 {
 827         /*
 828          * In Renesas controllers, when performing a
 829          * multiple block read of one or two blocks,
 830          * depending on the timing with which the
 831          * response register is read, the response
 832          * value may not be read properly.
 833          * Use single block read for this HW bug
 834          */
 835         if ((direction == MMC_DATA_READ) &&
 836             blk_size == 2)
 837                 return 1;
 838
 839         return blk_size;
 840 }
 841
 842 static void renesas_sdhi_fixup_request(struct tmio_mmc_host *host, struct mmc_request *mrq)
 843 {
 844         struct renesas_sdhi *priv = host_to_priv(host);
 845
 846         if (priv->needs_adjust_hs400 && mrq->cmd->opcode == MMC_SEND_STATUS)
 847                 renesas_sdhi_adjust_hs400_mode_enable(host);
 848 }
 849 static void renesas_sdhi_enable_dma(struct tmio_mmc_host *host, bool enable)
 850 {
 851         /* Iff regs are 8 byte apart, sdbuf is 64 bit. Otherwise always 32. */
 852         int width = (host->bus_shift == 2) ? 64 : 32;
 853
 854         sd_ctrl_write16(host, CTL_DMA_ENABLE, enable ? DMA_ENABLE_DMASDRW : 0);
 855         renesas_sdhi_sdbuf_width(host, enable ? width : 16);
 856 }
 857
 858 static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400 = {
 859         .hs400_disabled = true,
 860         .hs400_4taps = true,
 861 };
 862
 863 static const struct renesas_sdhi_quirks sdhi_quirks_4tap = {
 864         .hs400_4taps = true,
 865         .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
 866 };
 867
 868 static const struct renesas_sdhi_quirks sdhi_quirks_nohs400 = {
 869         .hs400_disabled = true,
 870 };
 871
 872 static const struct renesas_sdhi_quirks sdhi_quirks_bad_taps1357 = {
 873         .hs400_bad_taps = BIT(1) | BIT(3) | BIT(5) | BIT(7),
 874 };
 875
 876 static const struct renesas_sdhi_quirks sdhi_quirks_bad_taps2367 = {
 877         .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
 878 };
 879
 880 static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es13 = {
 881         .hs400_4taps = true,
 882         .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
 883         .hs400_calib_table = r8a7796_es13_calib_table,
 884 };
 885
 886 static const struct renesas_sdhi_quirks sdhi_quirks_r8a77965 = {
 887         .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
 888         .hs400_calib_table = r8a77965_calib_table,
 889 };
 890
 891 static const struct renesas_sdhi_quirks sdhi_quirks_r8a77990 = {
 892         .hs400_calib_table = r8a77990_calib_table,
 893 };
 894
 895 /*
 896  * Note for r8a7796 / r8a774a1: we can't distinguish ES1.1 and 1.2 as of now.
 897  * So, we want to treat them equally and only have a match for ES1.2 to enforce
 898  * this if there ever will be a way to distinguish ES1.2.
 899  */
 900 static const struct soc_device_attribute sdhi_quirks_match[]  = {
 901         { .soc_id = "r8a774a1", .revision = "ES1.[012]", .data = &sdhi_quirks_4tap_nohs400 },
 902         { .soc_id = "r8a7795", .revision = "ES1.*", .data = &sdhi_quirks_4tap_nohs400 },
 903         { .soc_id = "r8a7795", .revision = "ES2.0", .data = &sdhi_quirks_4tap },
 904         { .soc_id = "r8a7795", .revision = "ES3.*", .data = &sdhi_quirks_bad_taps2367 },
 905         { .soc_id = "r8a7796", .revision = "ES1.[012]", .data = &sdhi_quirks_4tap_nohs400 },
 906         { .soc_id = "r8a7796", .revision = "ES1.*", .data = &sdhi_quirks_r8a7796_es13 },
 907         { .soc_id = "r8a77961", .data = &sdhi_quirks_bad_taps1357 },
 908         { .soc_id = "r8a77965", .data = &sdhi_quirks_r8a77965 },
 909         { .soc_id = "r8a77980", .data = &sdhi_quirks_nohs400 },
 910         { .soc_id = "r8a77990", .data = &sdhi_quirks_r8a77990 },
 911         { /* Sentinel. */ },
 912 };
 913
 914 int renesas_sdhi_probe(struct platform_device *pdev,
 915                        const struct tmio_mmc_dma_ops *dma_ops)
 916 {
 917         struct tmio_mmc_data *mmd = pdev->dev.platform_data;
 918         const struct renesas_sdhi_quirks *quirks = NULL;
 919         const struct renesas_sdhi_of_data *of_data;
 920         const struct soc_device_attribute *attr;
 921         struct tmio_mmc_data *mmc_data;
 922         struct tmio_mmc_dma *dma_priv;
 923         struct tmio_mmc_host *host;
 924         struct renesas_sdhi *priv;
 925         int num_irqs, irq, ret, i;
 926         struct resource *res;
 927         u16 ver;
 928
 929         of_data = of_device_get_match_data(&pdev->dev);
 930
 931         attr = soc_device_match(sdhi_quirks_match);
 932         if (attr)
 933                 quirks = attr->data;
 934
 935         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 936         if (!res)
 937                 return -EINVAL;
 938
 939         priv = devm_kzalloc(&pdev->dev, sizeof(struct renesas_sdhi),
 940                             GFP_KERNEL);
 941         if (!priv)
 942                 return -ENOMEM;
 943
 944         priv->quirks = quirks;
 945         mmc_data = &priv->mmc_data;
 946         dma_priv = &priv->dma_priv;
 947
 948         priv->clk = devm_clk_get(&pdev->dev, NULL);
 949         if (IS_ERR(priv->clk)) {
 950                 ret = PTR_ERR(priv->clk);
 951                 dev_err(&pdev->dev, "cannot get clock: %d\n", ret);
 952                 return ret;
 953         }
 954
 955         /*
 956          * Some controllers provide a 2nd clock just to run the internal card
 957          * detection logic. Unfortunately, the existing driver architecture does
 958          * not support a separation of clocks for runtime PM usage. When
 959          * native hotplug is used, the tmio driver assumes that the core
 960          * must continue to run for card detect to stay active, so we cannot
 961          * disable it.
 962          * Additionally, it is prohibited to supply a clock to the core but not
 963          * to the card detect circuit. That leaves us with if separate clocks
 964          * are presented, we must treat them both as virtually 1 clock.
 965          */
 966         priv->clk_cd = devm_clk_get(&pdev->dev, "cd");
 967         if (IS_ERR(priv->clk_cd))
 968                 priv->clk_cd = NULL;
 969
 970         priv->pinctrl = devm_pinctrl_get(&pdev->dev);
 971         if (!IS_ERR(priv->pinctrl)) {
 972                 priv->pins_default = pinctrl_lookup_state(priv->pinctrl,
 973                                                 PINCTRL_STATE_DEFAULT);
 974                 priv->pins_uhs = pinctrl_lookup_state(priv->pinctrl,
 975                                                 "state_uhs");
 976         }
 977
 978         host = tmio_mmc_host_alloc(pdev, mmc_data);
 979         if (IS_ERR(host))
 980                 return PTR_ERR(host);
 981
 982         if (of_data) {
 983                 mmc_data->flags |= of_data->tmio_flags;
 984                 mmc_data->ocr_mask = of_data->tmio_ocr_mask;
 985                 mmc_data->capabilities |= of_data->capabilities;
 986                 mmc_data->capabilities2 |= of_data->capabilities2;
 987                 mmc_data->dma_rx_offset = of_data->dma_rx_offset;
 988                 mmc_data->max_blk_count = of_data->max_blk_count;
 989                 mmc_data->max_segs = of_data->max_segs;
 990                 dma_priv->dma_buswidth = of_data->dma_buswidth;
 991                 host->bus_shift = of_data->bus_shift;
 992         }
 993
 994         host->write16_hook      = renesas_sdhi_write16_hook;
 995         host->clk_enable        = renesas_sdhi_clk_enable;
 996         host->clk_disable       = renesas_sdhi_clk_disable;
 997         host->set_clock         = renesas_sdhi_set_clock;
 998         host->multi_io_quirk    = renesas_sdhi_multi_io_quirk;
 999         host->dma_ops           = dma_ops;
1000
1001         if (quirks && quirks->hs400_disabled)
1002                 host->mmc->caps2 &= ~(MMC_CAP2_HS400 | MMC_CAP2_HS400_ES);
1003
1004         /* For some SoC, we disable internal WP. GPIO may override this */
1005         if (mmc_can_gpio_ro(host->mmc))
1006                 mmc_data->capabilities2 &= ~MMC_CAP2_NO_WRITE_PROTECT;
1007
1008         /* SDR speeds are only available on Gen2+ */
1009         if (mmc_data->flags & TMIO_MMC_MIN_RCAR2) {
1010                 /* card_busy caused issues on r8a73a4 (pre-Gen2) CD-less SDHI */
1011                 host->ops.card_busy = renesas_sdhi_card_busy;
1012                 host->ops.start_signal_voltage_switch =
1013                         renesas_sdhi_start_signal_voltage_switch;
1014                 host->sdcard_irq_setbit_mask = TMIO_STAT_ALWAYS_SET_27;
1015                 host->sdcard_irq_mask_all = TMIO_MASK_ALL_RCAR2;
1016                 host->reset = renesas_sdhi_reset;
1017         } else {
1018                 host->sdcard_irq_mask_all = TMIO_MASK_ALL;
1019         }
1020
1021         /* Orginally registers were 16 bit apart, could be 32 or 64 nowadays */
1022         if (!host->bus_shift && resource_size(res) > 0x100) /* old way to determine the shift */
1023                 host->bus_shift = 1;
1024
1025         if (mmd)
1026                 *mmc_data = *mmd;
1027
1028         dma_priv->filter = shdma_chan_filter;
1029         dma_priv->enable = renesas_sdhi_enable_dma;
1030
1031         mmc_data->alignment_shift = 1; /* 2-byte alignment */
1032         mmc_data->capabilities |= MMC_CAP_MMC_HIGHSPEED;
1033
1034         /*
1035          * All SDHI blocks support 2-byte and larger block sizes in 4-bit
1036          * bus width mode.
1037          */
1038         mmc_data->flags |= TMIO_MMC_BLKSZ_2BYTES;
1039
1040         /*
1041          * All SDHI blocks support SDIO IRQ signalling.
1042          */
1043         mmc_data->flags |= TMIO_MMC_SDIO_IRQ;
1044
1045         /* All SDHI have CMD12 control bit */
1046         mmc_data->flags |= TMIO_MMC_HAVE_CMD12_CTRL;
1047
1048         /* All SDHI have SDIO status bits which must be 1 */
1049         mmc_data->flags |= TMIO_MMC_SDIO_STATUS_SETBITS;
1050
1051         dev_pm_domain_start(&pdev->dev);
1052
1053         ret = renesas_sdhi_clk_enable(host);
1054         if (ret)
1055                 goto efree;
1056
1057         ver = sd_ctrl_read16(host, CTL_VERSION);
1058         /* GEN2_SDR104 is first known SDHI to use 32bit block count */
1059         if (ver < SDHI_VER_GEN2_SDR104 && mmc_data->max_blk_count > U16_MAX)
1060                 mmc_data->max_blk_count = U16_MAX;
1061
1062         /* One Gen2 SDHI incarnation does NOT have a CBSY bit */
1063         if (ver == SDHI_VER_GEN2_SDR50)
1064                 mmc_data->flags &= ~TMIO_MMC_HAVE_CBSY;
1065
1066         if (ver == SDHI_VER_GEN3_SDMMC && quirks && quirks->hs400_calib_table) {
1067                 host->fixup_request = renesas_sdhi_fixup_request;
1068                 priv->adjust_hs400_calib_table = *(
1069                         res->start == SDHI_GEN3_MMC0_ADDR ?
1070                         quirks->hs400_calib_table :
1071                         quirks->hs400_calib_table + 1);
1072         }
1073
1074         /* Enable tuning iff we have an SCC and a supported mode */
1075         if (of_data && of_data->scc_offset &&
1076             (host->mmc->caps & MMC_CAP_UHS_SDR104 ||
1077              host->mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR |
1078                                  MMC_CAP2_HS400_1_8V))) {
1079                 const struct renesas_sdhi_scc *taps = of_data->taps;
1080                 bool use_4tap = priv->quirks && priv->quirks->hs400_4taps;
1081                 bool hit = false;
1082
1083                 for (i = 0; i < of_data->taps_num; i++) {
1084                         if (taps[i].clk_rate == 0 ||
1085                             taps[i].clk_rate == host->mmc->f_max) {
1086                                 priv->scc_tappos = taps->tap;
1087                                 priv->scc_tappos_hs400 = use_4tap ?
1088                                                          taps->tap_hs400_4tap :
1089                                                          taps->tap;
1090                                 hit = true;
1091                                 break;
1092                         }
1093                 }
1094
1095                 if (!hit)
1096                         dev_warn(&host->pdev->dev, "Unknown clock rate for tuning\n");
1097
1098                 priv->scc_ctl = host->ctl + of_data->scc_offset;
1099                 host->check_retune = renesas_sdhi_check_scc_error;
1100                 host->ops.execute_tuning = renesas_sdhi_execute_tuning;
1101                 host->ops.prepare_hs400_tuning = renesas_sdhi_prepare_hs400_tuning;
1102                 host->ops.hs400_downgrade = renesas_sdhi_disable_scc;
1103                 host->ops.hs400_complete = renesas_sdhi_hs400_complete;
1104         }
1105
1106         sd_ctrl_write32_as_16_and_16(host, CTL_IRQ_MASK, host->sdcard_irq_mask_all);
1107
1108         num_irqs = platform_irq_count(pdev);
1109         if (num_irqs < 0) {
1110                 ret = num_irqs;
1111                 goto eirq;
1112         }
1113
1114         /* There must be at least one IRQ source */
1115         if (!num_irqs) {
1116                 ret = -ENXIO;
1117                 goto eirq;
1118         }
1119
1120         for (i = 0; i < num_irqs; i++) {
1121                 irq = platform_get_irq(pdev, i);
1122                 if (irq < 0) {
1123                         ret = irq;
1124                         goto eirq;
1125                 }
1126
1127                 ret = devm_request_irq(&pdev->dev, irq, tmio_mmc_irq, 0,
1128                                        dev_name(&pdev->dev), host);
1129                 if (ret)
1130                         goto eirq;
1131         }
1132
1133         ret = tmio_mmc_host_probe(host);
1134         if (ret < 0)
1135                 goto edisclk;
1136
1137         dev_info(&pdev->dev, "%s base at %pa, max clock rate %u MHz\n",
1138                  mmc_hostname(host->mmc), &res->start, host->mmc->f_max / 1000000);
1139
1140         return ret;
1141
1142 eirq:
1143         tmio_mmc_host_remove(host);
1144 edisclk:
1145         renesas_sdhi_clk_disable(host);
1146 efree:
1147         tmio_mmc_host_free(host);
1148
1149         return ret;
1150 }
1151 EXPORT_SYMBOL_GPL(renesas_sdhi_probe);
1152
1153 int renesas_sdhi_remove(struct platform_device *pdev)
1154 {
1155         struct tmio_mmc_host *host = platform_get_drvdata(pdev);
1156
1157         tmio_mmc_host_remove(host);
1158         renesas_sdhi_clk_disable(host);
1159         tmio_mmc_host_free(host);
1160
1161         return 0;
1162 }
1163 EXPORT_SYMBOL_GPL(renesas_sdhi_remove);
1164
1165 MODULE_LICENSE("GPL v2");