1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-19 Renesas Electronics Corporation
6 * Copyright (C) 2016-19 Sang Engineering, Wolfram Sang
7 * Copyright (C) 2016-17 Horms Solutions, Simon Horman
8 * Copyright (C) 2009 Magnus Damm
10 * Based on "Compaq ASIC3 support":
12 * Copyright 2001 Compaq Computer Corporation.
13 * Copyright 2004-2005 Phil Blundell
14 * Copyright 2007-2008 OpenedHand Ltd.
16 * Authors: Phil Blundell <pb@handhelds.org>,
17 * Samuel Ortiz <sameo@openedhand.com>
21 #include <linux/kernel.h>
22 #include <linux/clk.h>
23 #include <linux/slab.h>
24 #include <linux/module.h>
25 #include <linux/of_device.h>
26 #include <linux/platform_device.h>
27 #include <linux/pm_domain.h>
28 #include <linux/mmc/host.h>
29 #include <linux/mmc/mmc.h>
30 #include <linux/mmc/slot-gpio.h>
31 #include <linux/mfd/tmio.h>
32 #include <linux/sh_dma.h>
33 #include <linux/delay.h>
34 #include <linux/pinctrl/consumer.h>
35 #include <linux/pinctrl/pinctrl-state.h>
36 #include <linux/regulator/consumer.h>
37 #include <linux/sys_soc.h>
39 #include "renesas_sdhi.h"
42 #define HOST_MODE 0xe4
44 #define SDHI_VER_GEN2_SDR50 0x490c
45 #define SDHI_VER_RZ_A1 0x820b
46 /* very old datasheets said 0x490c for SDR104, too. They are wrong! */
47 #define SDHI_VER_GEN2_SDR104 0xcb0d
48 #define SDHI_VER_GEN3_SD 0xcc10
49 #define SDHI_VER_GEN3_SDMMC 0xcd10
51 #define SDHI_GEN3_MMC0_ADDR 0xee140000
53 static void renesas_sdhi_sdbuf_width(struct tmio_mmc_host *host, int width)
59 * renesas_sdhi_of_data :: dma_buswidth
61 switch (sd_ctrl_read16(host, CTL_VERSION)) {
62 case SDHI_VER_GEN2_SDR50:
63 val = (width == 32) ? 0x0001 : 0x0000;
65 case SDHI_VER_GEN2_SDR104:
66 val = (width == 32) ? 0x0000 : 0x0001;
68 case SDHI_VER_GEN3_SD:
69 case SDHI_VER_GEN3_SDMMC:
82 sd_ctrl_write16(host, HOST_MODE, val);
85 static int renesas_sdhi_clk_enable(struct tmio_mmc_host *host)
87 struct mmc_host *mmc = host->mmc;
88 struct renesas_sdhi *priv = host_to_priv(host);
91 ret = clk_prepare_enable(priv->clk_cd);
96 * The clock driver may not know what maximum frequency
97 * actually works, so it should be set with the max-frequency
98 * property which will already have been read to f_max. If it
99 * was missing, assume the current frequency is the maximum.
102 mmc->f_max = clk_get_rate(priv->clk);
105 * Minimum frequency is the minimum input clock frequency
106 * divided by our maximum divider.
108 mmc->f_min = max(clk_round_rate(priv->clk, 1) / 512, 1L);
110 /* enable 16bit data access on SDBUF as default */
111 renesas_sdhi_sdbuf_width(host, 16);
116 static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host,
117 unsigned int new_clock)
119 struct renesas_sdhi *priv = host_to_priv(host);
120 unsigned int freq, diff, best_freq = 0, diff_min = ~0;
124 * We simply return the current rate if a) we are not on a R-Car Gen2+
125 * SoC (may work for others, but untested) or b) if the SCC needs its
126 * clock during tuning, so we don't change the external clock setup.
128 if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2) || mmc_doing_tune(host->mmc))
129 return clk_get_rate(priv->clk);
132 * We want the bus clock to be as close as possible to, but no
133 * greater than, new_clock. As we can divide by 1 << i for
134 * any i in [0, 9] we want the input clock to be as close as
135 * possible, but no greater than, new_clock << i.
137 for (i = min(9, ilog2(UINT_MAX / new_clock)); i >= 0; i--) {
138 freq = clk_round_rate(priv->clk, new_clock << i);
139 if (freq > (new_clock << i)) {
140 /* Too fast; look for a slightly slower option */
141 freq = clk_round_rate(priv->clk,
142 (new_clock << i) / 4 * 3);
143 if (freq > (new_clock << i))
147 diff = new_clock - (freq >> i);
148 if (diff <= diff_min) {
154 clk_set_rate(priv->clk, best_freq);
156 return clk_get_rate(priv->clk);
159 static void renesas_sdhi_set_clock(struct tmio_mmc_host *host,
160 unsigned int new_clock)
164 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
165 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
167 if (new_clock == 0) {
168 host->mmc->actual_clock = 0;
172 host->mmc->actual_clock = renesas_sdhi_clk_update(host, new_clock);
173 clock = host->mmc->actual_clock / 512;
175 for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1)
178 /* 1/1 clock is option */
179 if ((host->pdata->flags & TMIO_MMC_CLK_ACTUAL) && ((clk >> 22) & 0x1)) {
180 if (!(host->mmc->ios.timing == MMC_TIMING_MMC_HS400))
186 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK);
187 if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
188 usleep_range(10000, 11000);
190 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
191 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
194 /* HW engineers overrode docs: no sleep needed on R-Car2+ */
195 if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
196 usleep_range(10000, 11000);
199 static void renesas_sdhi_clk_disable(struct tmio_mmc_host *host)
201 struct renesas_sdhi *priv = host_to_priv(host);
203 clk_disable_unprepare(priv->clk_cd);
206 static int renesas_sdhi_card_busy(struct mmc_host *mmc)
208 struct tmio_mmc_host *host = mmc_priv(mmc);
210 return !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) &
214 static int renesas_sdhi_start_signal_voltage_switch(struct mmc_host *mmc,
217 struct tmio_mmc_host *host = mmc_priv(mmc);
218 struct renesas_sdhi *priv = host_to_priv(host);
219 struct pinctrl_state *pin_state;
222 switch (ios->signal_voltage) {
223 case MMC_SIGNAL_VOLTAGE_330:
224 pin_state = priv->pins_default;
226 case MMC_SIGNAL_VOLTAGE_180:
227 pin_state = priv->pins_uhs;
234 * If anything is missing, assume signal voltage is fixed at
235 * 3.3V and succeed/fail accordingly.
237 if (IS_ERR(priv->pinctrl) || IS_ERR(pin_state))
238 return ios->signal_voltage ==
239 MMC_SIGNAL_VOLTAGE_330 ? 0 : -EINVAL;
241 ret = mmc_regulator_set_vqmmc(host->mmc, ios);
245 return pinctrl_select_state(priv->pinctrl, pin_state);
249 #define SH_MOBILE_SDHI_SCC_DTCNTL 0x000
250 #define SH_MOBILE_SDHI_SCC_TAPSET 0x002
251 #define SH_MOBILE_SDHI_SCC_DT2FF 0x004
252 #define SH_MOBILE_SDHI_SCC_CKSEL 0x006
253 #define SH_MOBILE_SDHI_SCC_RVSCNTL 0x008
254 #define SH_MOBILE_SDHI_SCC_RVSREQ 0x00A
255 #define SH_MOBILE_SDHI_SCC_SMPCMP 0x00C
256 #define SH_MOBILE_SDHI_SCC_TMPPORT2 0x00E
257 #define SH_MOBILE_SDHI_SCC_TMPPORT3 0x014
258 #define SH_MOBILE_SDHI_SCC_TMPPORT4 0x016
259 #define SH_MOBILE_SDHI_SCC_TMPPORT5 0x018
260 #define SH_MOBILE_SDHI_SCC_TMPPORT6 0x01A
261 #define SH_MOBILE_SDHI_SCC_TMPPORT7 0x01C
263 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN BIT(0)
264 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16
265 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff
267 #define SH_MOBILE_SDHI_SCC_CKSEL_DTSEL BIT(0)
269 #define SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN BIT(0)
271 #define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN BIT(0)
272 #define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP BIT(1)
273 #define SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR BIT(2)
275 #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN BIT(8)
276 #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP BIT(24)
277 #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR (BIT(8) | BIT(24))
279 #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4)
280 #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN BIT(31)
282 /* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT4 register */
283 #define SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START BIT(0)
285 /* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT5 register */
286 #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R BIT(8)
287 #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W (0 << 8)
288 #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK 0x3F
290 /* Definitions for values the SH_MOBILE_SDHI_SCC register */
291 #define SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE 0xa5000000
292 #define SH_MOBILE_SDHI_SCC_TMPPORT_CALIB_CODE_MASK 0x1f
293 #define SH_MOBILE_SDHI_SCC_TMPPORT_MANUAL_MODE BIT(7)
295 static const u8 r8a7796_es13_calib_table[2][SDHI_CALIB_TABLE_MAX] = {
296 { 3, 3, 3, 3, 3, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 15,
297 16, 16, 16, 16, 16, 16, 17, 18, 18, 19, 20, 21, 22, 23, 24, 25 },
298 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 6, 7, 8, 11,
299 12, 17, 18, 18, 18, 18, 18, 18, 18, 19, 20, 21, 22, 23, 25, 25 }
302 static const u8 r8a77965_calib_table[2][SDHI_CALIB_TABLE_MAX] = {
303 { 1, 2, 6, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 16,
304 17, 18, 19, 20, 21, 22, 23, 24, 25, 25, 26, 27, 28, 29, 30, 31 },
305 { 2, 3, 4, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14, 15, 16, 17,
306 17, 17, 20, 21, 22, 23, 24, 25, 27, 28, 29, 30, 31, 31, 31, 31 }
309 static const u8 r8a77990_calib_table[2][SDHI_CALIB_TABLE_MAX] = {
310 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
311 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
312 { 0, 0, 0, 1, 2, 3, 3, 4, 4, 4, 5, 5, 6, 8, 9, 10,
313 11, 12, 13, 15, 16, 17, 17, 18, 18, 19, 20, 22, 24, 25, 26, 26 }
316 static inline u32 sd_scc_read32(struct tmio_mmc_host *host,
317 struct renesas_sdhi *priv, int addr)
319 return readl(priv->scc_ctl + (addr << host->bus_shift));
322 static inline void sd_scc_write32(struct tmio_mmc_host *host,
323 struct renesas_sdhi *priv,
326 writel(val, priv->scc_ctl + (addr << host->bus_shift));
329 static unsigned int renesas_sdhi_init_tuning(struct tmio_mmc_host *host)
331 struct renesas_sdhi *priv;
333 priv = host_to_priv(host);
336 sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, 0x0);
338 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
339 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
341 /* set sampling clock selection range */
342 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
343 SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN |
344 0x8 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT);
346 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
347 SH_MOBILE_SDHI_SCC_CKSEL_DTSEL |
348 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL));
350 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
351 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
352 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
354 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos);
356 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
357 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
360 return (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL) >>
361 SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) &
362 SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK;
365 static void renesas_sdhi_hs400_complete(struct mmc_host *mmc)
367 struct tmio_mmc_host *host = mmc_priv(mmc);
368 struct renesas_sdhi *priv = host_to_priv(host);
369 u32 bad_taps = priv->quirks ? priv->quirks->hs400_bad_taps : 0;
370 bool use_4tap = priv->quirks && priv->quirks->hs400_4taps;
372 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
373 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
376 sd_ctrl_write16(host, CTL_SDIF_MODE, 0x0001 |
377 sd_ctrl_read16(host, CTL_SDIF_MODE));
379 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF,
380 priv->scc_tappos_hs400);
382 /* Gen3 can't do automatic tap correction with HS400, so disable it */
383 if (sd_ctrl_read16(host, CTL_VERSION) == SDHI_VER_GEN3_SDMMC)
384 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
385 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
386 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
388 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2,
389 (SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN |
390 SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) |
391 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2));
393 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
394 SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN |
395 sd_scc_read32(host, priv,
396 SH_MOBILE_SDHI_SCC_DTCNTL));
399 if (bad_taps & BIT(priv->tap_set)) {
400 u32 new_tap = (priv->tap_set + 1) % priv->tap_num;
402 if (bad_taps & BIT(new_tap))
403 new_tap = (priv->tap_set - 1) % priv->tap_num;
405 if (bad_taps & BIT(new_tap)) {
406 new_tap = priv->tap_set;
407 dev_dbg(&host->pdev->dev, "Can't handle three bad tap in a row\n");
410 priv->tap_set = new_tap;
413 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET,
414 priv->tap_set / (use_4tap ? 2 : 1));
416 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
417 SH_MOBILE_SDHI_SCC_CKSEL_DTSEL |
418 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL));
420 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
421 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
423 if (priv->adjust_hs400_calib_table)
424 priv->needs_adjust_hs400 = true;
427 static void renesas_sdhi_reset_scc(struct tmio_mmc_host *host,
428 struct renesas_sdhi *priv)
430 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
431 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
433 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
434 ~SH_MOBILE_SDHI_SCC_CKSEL_DTSEL &
435 sd_scc_read32(host, priv,
436 SH_MOBILE_SDHI_SCC_CKSEL));
439 static void renesas_sdhi_disable_scc(struct mmc_host *mmc)
441 struct tmio_mmc_host *host = mmc_priv(mmc);
442 struct renesas_sdhi *priv = host_to_priv(host);
444 renesas_sdhi_reset_scc(host, priv);
446 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
447 ~SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN &
448 sd_scc_read32(host, priv,
449 SH_MOBILE_SDHI_SCC_DTCNTL));
451 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
452 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
455 static u32 sd_scc_tmpport_read32(struct tmio_mmc_host *host,
456 struct renesas_sdhi *priv, u32 addr)
459 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT5,
460 SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R |
461 (SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr));
463 /* access start and stop */
464 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4,
465 SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START);
466 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 0);
468 return sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT7);
471 static void sd_scc_tmpport_write32(struct tmio_mmc_host *host,
472 struct renesas_sdhi *priv, u32 addr, u32 val)
475 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT5,
476 SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W |
477 (SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr));
479 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT6, val);
481 /* access start and stop */
482 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4,
483 SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START);
484 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 0);
487 static void renesas_sdhi_adjust_hs400_mode_enable(struct tmio_mmc_host *host)
489 struct renesas_sdhi *priv = host_to_priv(host);
492 /* disable write protect */
493 sd_scc_tmpport_write32(host, priv, 0x00,
494 SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE);
495 /* read calibration code and adjust */
496 calib_code = sd_scc_tmpport_read32(host, priv, 0x26);
497 calib_code &= SH_MOBILE_SDHI_SCC_TMPPORT_CALIB_CODE_MASK;
499 sd_scc_tmpport_write32(host, priv, 0x22,
500 SH_MOBILE_SDHI_SCC_TMPPORT_MANUAL_MODE |
501 priv->adjust_hs400_calib_table[calib_code]);
503 /* set offset value to TMPPORT3, hardcoded to OFFSET0 (= 0x3) for now */
504 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT3, 0x3);
506 /* adjustment done, clear flag */
507 priv->needs_adjust_hs400 = false;
510 static void renesas_sdhi_adjust_hs400_mode_disable(struct tmio_mmc_host *host)
512 struct renesas_sdhi *priv = host_to_priv(host);
514 /* disable write protect */
515 sd_scc_tmpport_write32(host, priv, 0x00,
516 SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE);
517 /* disable manual calibration */
518 sd_scc_tmpport_write32(host, priv, 0x22, 0);
519 /* clear offset value of TMPPORT3 */
520 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT3, 0);
523 static void renesas_sdhi_reset_hs400_mode(struct tmio_mmc_host *host,
524 struct renesas_sdhi *priv)
526 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
527 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
529 /* Reset HS400 mode */
530 sd_ctrl_write16(host, CTL_SDIF_MODE, ~0x0001 &
531 sd_ctrl_read16(host, CTL_SDIF_MODE));
533 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos);
535 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2,
536 ~(SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN |
537 SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) &
538 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2));
540 if (priv->adjust_hs400_calib_table)
541 renesas_sdhi_adjust_hs400_mode_disable(host);
543 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
544 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
547 static int renesas_sdhi_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
549 struct tmio_mmc_host *host = mmc_priv(mmc);
551 renesas_sdhi_reset_hs400_mode(host, host_to_priv(host));
555 static void renesas_sdhi_reset(struct tmio_mmc_host *host)
557 struct renesas_sdhi *priv = host_to_priv(host);
559 renesas_sdhi_reset_scc(host, priv);
560 renesas_sdhi_reset_hs400_mode(host, priv);
561 priv->needs_adjust_hs400 = false;
563 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
564 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
566 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
567 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
568 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
570 if (host->pdata->flags & TMIO_MMC_MIN_RCAR2)
571 sd_ctrl_write32_as_16_and_16(host, CTL_IRQ_MASK,
572 TMIO_MASK_INIT_RCAR2);
575 #define SH_MOBILE_SDHI_MIN_TAP_ROW 3
577 static int renesas_sdhi_select_tuning(struct tmio_mmc_host *host)
579 struct renesas_sdhi *priv = host_to_priv(host);
580 unsigned int tap_start = 0, tap_end = 0, tap_cnt = 0, rs, re, i;
581 unsigned int taps_size = priv->tap_num * 2, min_tap_row;
582 unsigned long *bitmap;
584 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
587 * When tuning CMD19 is issued twice for each tap, merge the
588 * result requiring the tap to be good in both runs before
589 * considering it for tuning selection.
591 for (i = 0; i < taps_size; i++) {
592 int offset = priv->tap_num * (i < priv->tap_num ? 1 : -1);
594 if (!test_bit(i, priv->taps))
595 clear_bit(i + offset, priv->taps);
597 if (!test_bit(i, priv->smpcmp))
598 clear_bit(i + offset, priv->smpcmp);
602 * If all TAP are OK, the sampling clock position is selected by
603 * identifying the change point of data.
605 if (bitmap_full(priv->taps, taps_size)) {
606 bitmap = priv->smpcmp;
610 min_tap_row = SH_MOBILE_SDHI_MIN_TAP_ROW;
614 * Find the longest consecutive run of successful probes. If that
615 * is at least SH_MOBILE_SDHI_MIN_TAP_ROW probes long then use the
616 * center index as the tap, otherwise bail out.
618 bitmap_for_each_set_region(bitmap, rs, re, 0, taps_size) {
619 if (re - rs > tap_cnt) {
622 tap_cnt = tap_end - tap_start;
626 if (tap_cnt >= min_tap_row)
627 priv->tap_set = (tap_start + tap_end) / 2 % priv->tap_num;
632 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, priv->tap_set);
634 /* Enable auto re-tuning */
635 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
636 SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN |
637 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
642 static int renesas_sdhi_execute_tuning(struct mmc_host *mmc, u32 opcode)
644 struct tmio_mmc_host *host = mmc_priv(mmc);
645 struct renesas_sdhi *priv = host_to_priv(host);
648 priv->tap_num = renesas_sdhi_init_tuning(host);
650 return 0; /* Tuning is not supported */
652 if (priv->tap_num * 2 >= sizeof(priv->taps) * BITS_PER_BYTE) {
653 dev_err(&host->pdev->dev,
654 "Too many taps, please update 'taps' in tmio_mmc_host!\n");
658 bitmap_zero(priv->taps, priv->tap_num * 2);
659 bitmap_zero(priv->smpcmp, priv->tap_num * 2);
661 /* Issue CMD19 twice for each tap */
662 for (i = 0; i < 2 * priv->tap_num; i++) {
665 /* Set sampling clock position */
666 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, i % priv->tap_num);
668 if (mmc_send_tuning(mmc, opcode, &cmd_error) == 0)
669 set_bit(i, priv->taps);
671 if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) == 0)
672 set_bit(i, priv->smpcmp);
675 mmc_abort_tuning(mmc, opcode);
678 ret = renesas_sdhi_select_tuning(host);
680 renesas_sdhi_reset(host);
684 static bool renesas_sdhi_manual_correction(struct tmio_mmc_host *host, bool use_4tap)
686 struct renesas_sdhi *priv = host_to_priv(host);
687 unsigned int new_tap = priv->tap_set, error_tap = priv->tap_set;
690 val = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ);
694 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
696 /* Change TAP position according to correction status */
697 if (sd_ctrl_read16(host, CTL_VERSION) == SDHI_VER_GEN3_SDMMC &&
698 host->mmc->ios.timing == MMC_TIMING_MMC_HS400) {
699 u32 bad_taps = priv->quirks ? priv->quirks->hs400_bad_taps : 0;
701 * With HS400, the DAT signal is based on DS, not CLK.
702 * Therefore, use only CMD status.
704 u32 smpcmp = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) &
705 SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR;
707 return false; /* no error in CMD signal */
708 } else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP) {
711 } else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN) {
715 return true; /* need retune */
719 * When new_tap is a bad tap, we cannot change. Then, we compare
720 * with the HS200 tuning result. When smpcmp[error_tap] is OK,
721 * we can at least retune.
723 if (bad_taps & BIT(new_tap % priv->tap_num))
724 return test_bit(error_tap % priv->tap_num, priv->smpcmp);
726 if (val & SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR)
727 return true; /* need retune */
728 else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP)
730 else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN)
736 priv->tap_set = (new_tap % priv->tap_num);
737 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET,
738 priv->tap_set / (use_4tap ? 2 : 1));
743 static bool renesas_sdhi_auto_correction(struct tmio_mmc_host *host)
745 struct renesas_sdhi *priv = host_to_priv(host);
747 /* Check SCC error */
748 if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ) &
749 SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) {
750 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
757 static bool renesas_sdhi_check_scc_error(struct tmio_mmc_host *host)
759 struct renesas_sdhi *priv = host_to_priv(host);
760 bool use_4tap = priv->quirks && priv->quirks->hs400_4taps;
763 * Skip checking SCC errors when running on 4 taps in HS400 mode as
764 * any retuning would still result in the same 4 taps being used.
766 if (!(host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) &&
767 !(host->mmc->ios.timing == MMC_TIMING_MMC_HS200) &&
768 !(host->mmc->ios.timing == MMC_TIMING_MMC_HS400 && !use_4tap))
771 if (mmc_doing_tune(host->mmc))
774 if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL) &
775 SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN)
776 return renesas_sdhi_auto_correction(host);
778 return renesas_sdhi_manual_correction(host, use_4tap);
781 static int renesas_sdhi_wait_idle(struct tmio_mmc_host *host, u32 bit)
784 /* CBSY is set when busy, SCLKDIVEN is cleared when busy */
785 u32 wait_state = (bit == TMIO_STAT_CMD_BUSY ? TMIO_STAT_CMD_BUSY : 0);
787 while (--timeout && (sd_ctrl_read16_and_16_as_32(host, CTL_STATUS)
788 & bit) == wait_state)
792 dev_warn(&host->pdev->dev, "timeout waiting for SD bus idle\n");
799 static int renesas_sdhi_write16_hook(struct tmio_mmc_host *host, int addr)
801 u32 bit = TMIO_STAT_SCLKDIVEN;
805 case CTL_STOP_INTERNAL_ACTION:
806 case CTL_XFER_BLK_COUNT:
807 case CTL_SD_XFER_LEN:
808 case CTL_SD_MEM_CARD_OPT:
809 case CTL_TRANSACTION_CTL:
812 if (host->pdata->flags & TMIO_MMC_HAVE_CBSY)
813 bit = TMIO_STAT_CMD_BUSY;
815 case CTL_SD_CARD_CLK_CTL:
816 return renesas_sdhi_wait_idle(host, bit);
822 static int renesas_sdhi_multi_io_quirk(struct mmc_card *card,
823 unsigned int direction, int blk_size)
826 * In Renesas controllers, when performing a
827 * multiple block read of one or two blocks,
828 * depending on the timing with which the
829 * response register is read, the response
830 * value may not be read properly.
831 * Use single block read for this HW bug
833 if ((direction == MMC_DATA_READ) &&
840 static void renesas_sdhi_fixup_request(struct tmio_mmc_host *host, struct mmc_request *mrq)
842 struct renesas_sdhi *priv = host_to_priv(host);
844 if (priv->needs_adjust_hs400 && mrq->cmd->opcode == MMC_SEND_STATUS)
845 renesas_sdhi_adjust_hs400_mode_enable(host);
847 static void renesas_sdhi_enable_dma(struct tmio_mmc_host *host, bool enable)
849 /* Iff regs are 8 byte apart, sdbuf is 64 bit. Otherwise always 32. */
850 int width = (host->bus_shift == 2) ? 64 : 32;
852 sd_ctrl_write16(host, CTL_DMA_ENABLE, enable ? DMA_ENABLE_DMASDRW : 0);
853 renesas_sdhi_sdbuf_width(host, enable ? width : 16);
856 static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400 = {
857 .hs400_disabled = true,
861 static const struct renesas_sdhi_quirks sdhi_quirks_4tap = {
863 .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
866 static const struct renesas_sdhi_quirks sdhi_quirks_nohs400 = {
867 .hs400_disabled = true,
870 static const struct renesas_sdhi_quirks sdhi_quirks_bad_taps1357 = {
871 .hs400_bad_taps = BIT(1) | BIT(3) | BIT(5) | BIT(7),
874 static const struct renesas_sdhi_quirks sdhi_quirks_bad_taps2367 = {
875 .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
878 static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es13 = {
880 .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
881 .hs400_calib_table = r8a7796_es13_calib_table,
884 static const struct renesas_sdhi_quirks sdhi_quirks_r8a77965 = {
885 .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
886 .hs400_calib_table = r8a77965_calib_table,
889 static const struct renesas_sdhi_quirks sdhi_quirks_r8a77990 = {
890 .hs400_calib_table = r8a77990_calib_table,
894 * Note for r8a7796 / r8a774a1: we can't distinguish ES1.1 and 1.2 as of now.
895 * So, we want to treat them equally and only have a match for ES1.2 to enforce
896 * this if there ever will be a way to distinguish ES1.2.
898 static const struct soc_device_attribute sdhi_quirks_match[] = {
899 { .soc_id = "r8a774a1", .revision = "ES1.[012]", .data = &sdhi_quirks_4tap_nohs400 },
900 { .soc_id = "r8a7795", .revision = "ES1.*", .data = &sdhi_quirks_4tap_nohs400 },
901 { .soc_id = "r8a7795", .revision = "ES2.0", .data = &sdhi_quirks_4tap },
902 { .soc_id = "r8a7795", .revision = "ES3.*", .data = &sdhi_quirks_bad_taps2367 },
903 { .soc_id = "r8a7796", .revision = "ES1.[012]", .data = &sdhi_quirks_4tap_nohs400 },
904 { .soc_id = "r8a7796", .revision = "ES1.*", .data = &sdhi_quirks_r8a7796_es13 },
905 { .soc_id = "r8a77961", .data = &sdhi_quirks_bad_taps1357 },
906 { .soc_id = "r8a77965", .data = &sdhi_quirks_r8a77965 },
907 { .soc_id = "r8a77980", .data = &sdhi_quirks_nohs400 },
908 { .soc_id = "r8a77990", .data = &sdhi_quirks_r8a77990 },
912 int renesas_sdhi_probe(struct platform_device *pdev,
913 const struct tmio_mmc_dma_ops *dma_ops)
915 struct tmio_mmc_data *mmd = pdev->dev.platform_data;
916 const struct renesas_sdhi_quirks *quirks = NULL;
917 const struct renesas_sdhi_of_data *of_data;
918 const struct soc_device_attribute *attr;
919 struct tmio_mmc_data *mmc_data;
920 struct tmio_mmc_dma *dma_priv;
921 struct tmio_mmc_host *host;
922 struct renesas_sdhi *priv;
923 int num_irqs, irq, ret, i;
924 struct resource *res;
927 of_data = of_device_get_match_data(&pdev->dev);
929 attr = soc_device_match(sdhi_quirks_match);
933 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
937 priv = devm_kzalloc(&pdev->dev, sizeof(struct renesas_sdhi),
942 priv->quirks = quirks;
943 mmc_data = &priv->mmc_data;
944 dma_priv = &priv->dma_priv;
946 priv->clk = devm_clk_get(&pdev->dev, NULL);
947 if (IS_ERR(priv->clk)) {
948 ret = PTR_ERR(priv->clk);
949 dev_err(&pdev->dev, "cannot get clock: %d\n", ret);
954 * Some controllers provide a 2nd clock just to run the internal card
955 * detection logic. Unfortunately, the existing driver architecture does
956 * not support a separation of clocks for runtime PM usage. When
957 * native hotplug is used, the tmio driver assumes that the core
958 * must continue to run for card detect to stay active, so we cannot
960 * Additionally, it is prohibited to supply a clock to the core but not
961 * to the card detect circuit. That leaves us with if separate clocks
962 * are presented, we must treat them both as virtually 1 clock.
964 priv->clk_cd = devm_clk_get(&pdev->dev, "cd");
965 if (IS_ERR(priv->clk_cd))
968 priv->pinctrl = devm_pinctrl_get(&pdev->dev);
969 if (!IS_ERR(priv->pinctrl)) {
970 priv->pins_default = pinctrl_lookup_state(priv->pinctrl,
971 PINCTRL_STATE_DEFAULT);
972 priv->pins_uhs = pinctrl_lookup_state(priv->pinctrl,
976 host = tmio_mmc_host_alloc(pdev, mmc_data);
978 return PTR_ERR(host);
981 mmc_data->flags |= of_data->tmio_flags;
982 mmc_data->ocr_mask = of_data->tmio_ocr_mask;
983 mmc_data->capabilities |= of_data->capabilities;
984 mmc_data->capabilities2 |= of_data->capabilities2;
985 mmc_data->dma_rx_offset = of_data->dma_rx_offset;
986 mmc_data->max_blk_count = of_data->max_blk_count;
987 mmc_data->max_segs = of_data->max_segs;
988 dma_priv->dma_buswidth = of_data->dma_buswidth;
989 host->bus_shift = of_data->bus_shift;
992 host->write16_hook = renesas_sdhi_write16_hook;
993 host->clk_enable = renesas_sdhi_clk_enable;
994 host->clk_disable = renesas_sdhi_clk_disable;
995 host->set_clock = renesas_sdhi_set_clock;
996 host->multi_io_quirk = renesas_sdhi_multi_io_quirk;
997 host->dma_ops = dma_ops;
999 if (quirks && quirks->hs400_disabled)
1000 host->mmc->caps2 &= ~(MMC_CAP2_HS400 | MMC_CAP2_HS400_ES);
1002 /* For some SoC, we disable internal WP. GPIO may override this */
1003 if (mmc_can_gpio_ro(host->mmc))
1004 mmc_data->capabilities2 &= ~MMC_CAP2_NO_WRITE_PROTECT;
1006 /* SDR speeds are only available on Gen2+ */
1007 if (mmc_data->flags & TMIO_MMC_MIN_RCAR2) {
1008 /* card_busy caused issues on r8a73a4 (pre-Gen2) CD-less SDHI */
1009 host->ops.card_busy = renesas_sdhi_card_busy;
1010 host->ops.start_signal_voltage_switch =
1011 renesas_sdhi_start_signal_voltage_switch;
1012 host->sdcard_irq_setbit_mask = TMIO_STAT_ALWAYS_SET_27;
1014 if (of_data && of_data->scc_offset) {
1015 priv->scc_ctl = host->ctl + of_data->scc_offset;
1016 host->reset = renesas_sdhi_reset;
1020 /* Orginally registers were 16 bit apart, could be 32 or 64 nowadays */
1021 if (!host->bus_shift && resource_size(res) > 0x100) /* old way to determine the shift */
1022 host->bus_shift = 1;
1027 dma_priv->filter = shdma_chan_filter;
1028 dma_priv->enable = renesas_sdhi_enable_dma;
1030 mmc_data->alignment_shift = 1; /* 2-byte alignment */
1031 mmc_data->capabilities |= MMC_CAP_MMC_HIGHSPEED;
1034 * All SDHI blocks support 2-byte and larger block sizes in 4-bit
1037 mmc_data->flags |= TMIO_MMC_BLKSZ_2BYTES;
1040 * All SDHI blocks support SDIO IRQ signalling.
1042 mmc_data->flags |= TMIO_MMC_SDIO_IRQ;
1044 /* All SDHI have CMD12 control bit */
1045 mmc_data->flags |= TMIO_MMC_HAVE_CMD12_CTRL;
1047 /* All SDHI have SDIO status bits which must be 1 */
1048 mmc_data->flags |= TMIO_MMC_SDIO_STATUS_SETBITS;
1050 dev_pm_domain_start(&pdev->dev);
1052 ret = renesas_sdhi_clk_enable(host);
1056 ver = sd_ctrl_read16(host, CTL_VERSION);
1057 /* GEN2_SDR104 is first known SDHI to use 32bit block count */
1058 if (ver < SDHI_VER_GEN2_SDR104 && mmc_data->max_blk_count > U16_MAX)
1059 mmc_data->max_blk_count = U16_MAX;
1061 /* One Gen2 SDHI incarnation does NOT have a CBSY bit */
1062 if (ver == SDHI_VER_GEN2_SDR50)
1063 mmc_data->flags &= ~TMIO_MMC_HAVE_CBSY;
1065 if (ver == SDHI_VER_GEN3_SDMMC && quirks && quirks->hs400_calib_table) {
1066 host->fixup_request = renesas_sdhi_fixup_request;
1067 priv->adjust_hs400_calib_table = *(
1068 res->start == SDHI_GEN3_MMC0_ADDR ?
1069 quirks->hs400_calib_table :
1070 quirks->hs400_calib_table + 1);
1073 ret = tmio_mmc_host_probe(host);
1077 /* Enable tuning iff we have an SCC and a supported mode */
1078 if (of_data && of_data->scc_offset &&
1079 (host->mmc->caps & MMC_CAP_UHS_SDR104 ||
1080 host->mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR |
1081 MMC_CAP2_HS400_1_8V))) {
1082 const struct renesas_sdhi_scc *taps = of_data->taps;
1083 bool use_4tap = priv->quirks && priv->quirks->hs400_4taps;
1086 for (i = 0; i < of_data->taps_num; i++) {
1087 if (taps[i].clk_rate == 0 ||
1088 taps[i].clk_rate == host->mmc->f_max) {
1089 priv->scc_tappos = taps->tap;
1090 priv->scc_tappos_hs400 = use_4tap ?
1091 taps->tap_hs400_4tap :
1099 dev_warn(&host->pdev->dev, "Unknown clock rate for tuning\n");
1101 host->check_retune = renesas_sdhi_check_scc_error;
1102 host->ops.execute_tuning = renesas_sdhi_execute_tuning;
1103 host->ops.prepare_hs400_tuning = renesas_sdhi_prepare_hs400_tuning;
1104 host->ops.hs400_downgrade = renesas_sdhi_disable_scc;
1105 host->ops.hs400_complete = renesas_sdhi_hs400_complete;
1108 num_irqs = platform_irq_count(pdev);
1114 /* There must be at least one IRQ source */
1120 for (i = 0; i < num_irqs; i++) {
1121 irq = platform_get_irq(pdev, i);
1127 ret = devm_request_irq(&pdev->dev, irq, tmio_mmc_irq, 0,
1128 dev_name(&pdev->dev), host);
1133 dev_info(&pdev->dev, "%s base at %pa, max clock rate %u MHz\n",
1134 mmc_hostname(host->mmc), &res->start, host->mmc->f_max / 1000000);
1139 tmio_mmc_host_remove(host);
1141 renesas_sdhi_clk_disable(host);
1143 tmio_mmc_host_free(host);
1147 EXPORT_SYMBOL_GPL(renesas_sdhi_probe);
1149 int renesas_sdhi_remove(struct platform_device *pdev)
1151 struct tmio_mmc_host *host = platform_get_drvdata(pdev);
1153 tmio_mmc_host_remove(host);
1154 renesas_sdhi_clk_disable(host);
1155 tmio_mmc_host_free(host);
1159 EXPORT_SYMBOL_GPL(renesas_sdhi_remove);
1161 MODULE_LICENSE("GPL v2");