drivers/mmc/host/renesas_sdhi_core.c

   1 /*
   2  * Renesas SDHI
   3  *
   4  * Copyright (C) 2015-17 Renesas Electronics Corporation
   5  * Copyright (C) 2016-17 Sang Engineering, Wolfram Sang
   6  * Copyright (C) 2016-17 Horms Solutions, Simon Horman
   7  * Copyright (C) 2009 Magnus Damm
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * Based on "Compaq ASIC3 support":
  14  *
  15  * Copyright 2001 Compaq Computer Corporation.
  16  * Copyright 2004-2005 Phil Blundell
  17  * Copyright 2007-2008 OpenedHand Ltd.
  18  *
  19  * Authors: Phil Blundell <pb@handhelds.org>,
  20  *          Samuel Ortiz <sameo@openedhand.com>
  21  *
  22  */
  23
  24 #include <linux/kernel.h>
  25 #include <linux/clk.h>
  26 #include <linux/slab.h>
  27 #include <linux/module.h>
  28 #include <linux/of_device.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/mmc/host.h>
  31 #include <linux/mmc/slot-gpio.h>
  32 #include <linux/mfd/tmio.h>
  33 #include <linux/sh_dma.h>
  34 #include <linux/delay.h>
  35 #include <linux/pinctrl/consumer.h>
  36 #include <linux/pinctrl/pinctrl-state.h>
  37 #include <linux/regulator/consumer.h>
  38
  39 #include "renesas_sdhi.h"
  40 #include "tmio_mmc.h"
  41
  42 #define HOST_MODE               0xe4
  43
  44 #define SDHI_VER_GEN2_SDR50     0x490c
  45 #define SDHI_VER_RZ_A1          0x820b
  46 /* very old datasheets said 0x490c for SDR104, too. They are wrong! */
  47 #define SDHI_VER_GEN2_SDR104    0xcb0d
  48 #define SDHI_VER_GEN3_SD        0xcc10
  49 #define SDHI_VER_GEN3_SDMMC     0xcd10
  50
  51 static void renesas_sdhi_sdbuf_width(struct tmio_mmc_host *host, int width)
  52 {
  53         u32 val;
  54
  55         /*
  56          * see also
  57          *      renesas_sdhi_of_data :: dma_buswidth
  58          */
  59         switch (sd_ctrl_read16(host, CTL_VERSION)) {
  60         case SDHI_VER_GEN2_SDR50:
  61                 val = (width == 32) ? 0x0001 : 0x0000;
  62                 break;
  63         case SDHI_VER_GEN2_SDR104:
  64                 val = (width == 32) ? 0x0000 : 0x0001;
  65                 break;
  66         case SDHI_VER_GEN3_SD:
  67         case SDHI_VER_GEN3_SDMMC:
  68                 if (width == 64)
  69                         val = 0x0000;
  70                 else if (width == 32)
  71                         val = 0x0101;
  72                 else
  73                         val = 0x0001;
  74                 break;
  75         default:
  76                 /* nothing to do */
  77                 return;
  78         }
  79
  80         sd_ctrl_write16(host, HOST_MODE, val);
  81 }
  82
  83 static int renesas_sdhi_clk_enable(struct tmio_mmc_host *host)
  84 {
  85         struct mmc_host *mmc = host->mmc;
  86         struct renesas_sdhi *priv = host_to_priv(host);
  87         int ret = clk_prepare_enable(priv->clk);
  88
  89         if (ret < 0)
  90                 return ret;
  91
  92         ret = clk_prepare_enable(priv->clk_cd);
  93         if (ret < 0) {
  94                 clk_disable_unprepare(priv->clk);
  95                 return ret;
  96         }
  97
  98         /*
  99          * The clock driver may not know what maximum frequency
 100          * actually works, so it should be set with the max-frequency
 101          * property which will already have been read to f_max.  If it
 102          * was missing, assume the current frequency is the maximum.
 103          */
 104         if (!mmc->f_max)
 105                 mmc->f_max = clk_get_rate(priv->clk);
 106
 107         /*
 108          * Minimum frequency is the minimum input clock frequency
 109          * divided by our maximum divider.
 110          */
 111         mmc->f_min = max(clk_round_rate(priv->clk, 1) / 512, 1L);
 112
 113         /* enable 16bit data access on SDBUF as default */
 114         renesas_sdhi_sdbuf_width(host, 16);
 115
 116         return 0;
 117 }
 118
 119 static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host,
 120                                             unsigned int new_clock)
 121 {
 122         struct renesas_sdhi *priv = host_to_priv(host);
 123         unsigned int freq, diff, best_freq = 0, diff_min = ~0;
 124         int i, ret;
 125
 126         /* tested only on R-Car Gen2+ currently; may work for others */
 127         if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
 128                 return clk_get_rate(priv->clk);
 129
 130         /*
 131          * We want the bus clock to be as close as possible to, but no
 132          * greater than, new_clock.  As we can divide by 1 << i for
 133          * any i in [0, 9] we want the input clock to be as close as
 134          * possible, but no greater than, new_clock << i.
 135          */
 136         for (i = min(9, ilog2(UINT_MAX / new_clock)); i >= 0; i--) {
 137                 freq = clk_round_rate(priv->clk, new_clock << i);
 138                 if (freq > (new_clock << i)) {
 139                         /* Too fast; look for a slightly slower option */
 140                         freq = clk_round_rate(priv->clk,
 141                                               (new_clock << i) / 4 * 3);
 142                         if (freq > (new_clock << i))
 143                                 continue;
 144                 }
 145
 146                 diff = new_clock - (freq >> i);
 147                 if (diff <= diff_min) {
 148                         best_freq = freq;
 149                         diff_min = diff;
 150                 }
 151         }
 152
 153         ret = clk_set_rate(priv->clk, best_freq);
 154
 155         return ret == 0 ? best_freq : clk_get_rate(priv->clk);
 156 }
 157
 158 static void renesas_sdhi_clk_start(struct tmio_mmc_host *host)
 159 {
 160         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
 161                 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 162
 163         /* HW engineers overrode docs: no sleep needed on R-Car2+ */
 164         if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
 165                 usleep_range(10000, 11000);
 166 }
 167
 168 static void renesas_sdhi_clk_stop(struct tmio_mmc_host *host)
 169 {
 170         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
 171                 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 172
 173         /* HW engineers overrode docs: no sleep needed on R-Car2+ */
 174         if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
 175                 usleep_range(10000, 11000);
 176 }
 177
 178 static void renesas_sdhi_set_clock(struct tmio_mmc_host *host,
 179                                    unsigned int new_clock)
 180 {
 181         u32 clk = 0, clock;
 182
 183         if (new_clock == 0) {
 184                 renesas_sdhi_clk_stop(host);
 185                 return;
 186         }
 187         /*
 188          * Both HS400 and HS200/SD104 set 200MHz, but some devices need to
 189          * set 400MHz to distinguish the CPG settings in HS400.
 190          */
 191         if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400 &&
 192             host->pdata->flags & TMIO_MMC_HAVE_4TAP_HS400 &&
 193             new_clock == 200000000)
 194                 new_clock = 400000000;
 195
 196         clock = renesas_sdhi_clk_update(host, new_clock) / 512;
 197
 198         for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1)
 199                 clock <<= 1;
 200
 201         /* 1/1 clock is option */
 202         if ((host->pdata->flags & TMIO_MMC_CLK_ACTUAL) && ((clk >> 22) & 0x1)) {
 203                 if (!(host->mmc->ios.timing == MMC_TIMING_MMC_HS400))
 204                         clk |= 0xff;
 205                 else
 206                         clk &= ~0xff;
 207         }
 208
 209         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
 210                         sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 211         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK);
 212         if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
 213                 usleep_range(10000, 11000);
 214
 215         renesas_sdhi_clk_start(host);
 216 }
 217
 218 static void renesas_sdhi_clk_disable(struct tmio_mmc_host *host)
 219 {
 220         struct renesas_sdhi *priv = host_to_priv(host);
 221
 222         clk_disable_unprepare(priv->clk);
 223         clk_disable_unprepare(priv->clk_cd);
 224 }
 225
 226 static int renesas_sdhi_card_busy(struct mmc_host *mmc)
 227 {
 228         struct tmio_mmc_host *host = mmc_priv(mmc);
 229
 230         return !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) &
 231                  TMIO_STAT_DAT0);
 232 }
 233
 234 static int renesas_sdhi_start_signal_voltage_switch(struct mmc_host *mmc,
 235                                                     struct mmc_ios *ios)
 236 {
 237         struct tmio_mmc_host *host = mmc_priv(mmc);
 238         struct renesas_sdhi *priv = host_to_priv(host);
 239         struct pinctrl_state *pin_state;
 240         int ret;
 241
 242         switch (ios->signal_voltage) {
 243         case MMC_SIGNAL_VOLTAGE_330:
 244                 pin_state = priv->pins_default;
 245                 break;
 246         case MMC_SIGNAL_VOLTAGE_180:
 247                 pin_state = priv->pins_uhs;
 248                 break;
 249         default:
 250                 return -EINVAL;
 251         }
 252
 253         /*
 254          * If anything is missing, assume signal voltage is fixed at
 255          * 3.3V and succeed/fail accordingly.
 256          */
 257         if (IS_ERR(priv->pinctrl) || IS_ERR(pin_state))
 258                 return ios->signal_voltage ==
 259                         MMC_SIGNAL_VOLTAGE_330 ? 0 : -EINVAL;
 260
 261         ret = mmc_regulator_set_vqmmc(host->mmc, ios);
 262         if (ret)
 263                 return ret;
 264
 265         return pinctrl_select_state(priv->pinctrl, pin_state);
 266 }
 267
 268 /* SCC registers */
 269 #define SH_MOBILE_SDHI_SCC_DTCNTL       0x000
 270 #define SH_MOBILE_SDHI_SCC_TAPSET       0x002
 271 #define SH_MOBILE_SDHI_SCC_DT2FF        0x004
 272 #define SH_MOBILE_SDHI_SCC_CKSEL        0x006
 273 #define SH_MOBILE_SDHI_SCC_RVSCNTL      0x008
 274 #define SH_MOBILE_SDHI_SCC_RVSREQ       0x00A
 275 #define SH_MOBILE_SDHI_SCC_TMPPORT2     0x00E
 276
 277 /* Definitions for values the SH_MOBILE_SDHI_SCC_DTCNTL register */
 278 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN         BIT(0)
 279 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT  16
 280 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK   0xff
 281
 282 /* Definitions for values the SH_MOBILE_SDHI_SCC_CKSEL register */
 283 #define SH_MOBILE_SDHI_SCC_CKSEL_DTSEL          BIT(0)
 284 /* Definitions for values the SH_MOBILE_SDHI_SCC_RVSCNTL register */
 285 #define SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN        BIT(0)
 286 /* Definitions for values the SH_MOBILE_SDHI_SCC_RVSREQ register */
 287 #define SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR        BIT(2)
 288 /* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT2 register */
 289 #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL   BIT(4)
 290 #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN     BIT(31)
 291
 292 static inline u32 sd_scc_read32(struct tmio_mmc_host *host,
 293                                 struct renesas_sdhi *priv, int addr)
 294 {
 295         return readl(priv->scc_ctl + (addr << host->bus_shift));
 296 }
 297
 298 static inline void sd_scc_write32(struct tmio_mmc_host *host,
 299                                   struct renesas_sdhi *priv,
 300                                   int addr, u32 val)
 301 {
 302         writel(val, priv->scc_ctl + (addr << host->bus_shift));
 303 }
 304
 305 static unsigned int renesas_sdhi_init_tuning(struct tmio_mmc_host *host)
 306 {
 307         struct renesas_sdhi *priv;
 308
 309         priv = host_to_priv(host);
 310
 311         /* Initialize SCC */
 312         sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, 0x0);
 313
 314         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
 315                         sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 316
 317         /* set sampling clock selection range */
 318         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
 319                        SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN |
 320                        0x8 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT);
 321
 322         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
 323                        SH_MOBILE_SDHI_SCC_CKSEL_DTSEL |
 324                        sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL));
 325
 326         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
 327                        ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
 328                        sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
 329
 330         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos);
 331
 332         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
 333                         sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 334
 335         /* Read TAPNUM */
 336         return (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL) >>
 337                 SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) &
 338                 SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK;
 339 }
 340
 341 static void renesas_sdhi_prepare_tuning(struct tmio_mmc_host *host,
 342                                         unsigned long tap)
 343 {
 344         struct renesas_sdhi *priv = host_to_priv(host);
 345
 346         /* Set sampling clock position */
 347         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, tap);
 348 }
 349
 350 static void renesas_sdhi_hs400_complete(struct tmio_mmc_host *host)
 351 {
 352         struct renesas_sdhi *priv = host_to_priv(host);
 353
 354         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
 355                 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 356
 357         /* Set HS400 mode */
 358         sd_ctrl_write16(host, CTL_SDIF_MODE, 0x0001 |
 359                         sd_ctrl_read16(host, CTL_SDIF_MODE));
 360         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2,
 361                        (SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN |
 362                         SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) |
 363                         sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2));
 364
 365         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
 366                        SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN |
 367                        sd_scc_read32(host, priv,
 368                                      SH_MOBILE_SDHI_SCC_DTCNTL));
 369
 370
 371         if (host->pdata->flags & TMIO_MMC_HAVE_4TAP_HS400)
 372                 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET,
 373                                host->tap_set / 2);
 374
 375         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
 376                        SH_MOBILE_SDHI_SCC_CKSEL_DTSEL |
 377                        sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL));
 378
 379         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
 380                         sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 381 }
 382
 383 static void renesas_sdhi_reset_scc(struct tmio_mmc_host *host,
 384                                    struct renesas_sdhi *priv)
 385 {
 386         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
 387                         sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 388
 389         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
 390                        ~SH_MOBILE_SDHI_SCC_CKSEL_DTSEL &
 391                        sd_scc_read32(host, priv,
 392                                      SH_MOBILE_SDHI_SCC_CKSEL));
 393 }
 394
 395 static void renesas_sdhi_disable_scc(struct tmio_mmc_host *host)
 396 {
 397         struct renesas_sdhi *priv = host_to_priv(host);
 398
 399         renesas_sdhi_reset_scc(host, priv);
 400
 401         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
 402                        ~SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN &
 403                        sd_scc_read32(host, priv,
 404                                      SH_MOBILE_SDHI_SCC_DTCNTL));
 405
 406         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
 407                         sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 408 }
 409
 410 static void renesas_sdhi_reset_hs400_mode(struct tmio_mmc_host *host,
 411                                           struct renesas_sdhi *priv)
 412 {
 413         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
 414                         sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 415
 416         /* Reset HS400 mode */
 417         sd_ctrl_write16(host, CTL_SDIF_MODE, ~0x0001 &
 418                         sd_ctrl_read16(host, CTL_SDIF_MODE));
 419         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2,
 420                        ~(SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN |
 421                          SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) &
 422                         sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2));
 423
 424         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
 425                         sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 426 }
 427
 428 static void renesas_sdhi_prepare_hs400_tuning(struct tmio_mmc_host *host)
 429 {
 430         renesas_sdhi_reset_hs400_mode(host, host_to_priv(host));
 431 }
 432
 433 #define SH_MOBILE_SDHI_MAX_TAP 3
 434
 435 static int renesas_sdhi_select_tuning(struct tmio_mmc_host *host)
 436 {
 437         struct renesas_sdhi *priv = host_to_priv(host);
 438         unsigned long tap_cnt;  /* counter of tuning success */
 439         unsigned long tap_start;/* start position of tuning success */
 440         unsigned long tap_end;  /* end position of tuning success */
 441         unsigned long ntap;     /* temporary counter of tuning success */
 442         unsigned long i;
 443
 444         /* Clear SCC_RVSREQ */
 445         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
 446
 447         /*
 448          * When tuning CMD19 is issued twice for each tap, merge the
 449          * result requiring the tap to be good in both runs before
 450          * considering it for tuning selection.
 451          */
 452         for (i = 0; i < host->tap_num * 2; i++) {
 453                 int offset = host->tap_num * (i < host->tap_num ? 1 : -1);
 454
 455                 if (!test_bit(i, host->taps))
 456                         clear_bit(i + offset, host->taps);
 457         }
 458
 459         /*
 460          * Find the longest consecutive run of successful probes.  If that
 461          * is more than SH_MOBILE_SDHI_MAX_TAP probes long then use the
 462          * center index as the tap.
 463          */
 464         tap_cnt = 0;
 465         ntap = 0;
 466         tap_start = 0;
 467         tap_end = 0;
 468         for (i = 0; i < host->tap_num * 2; i++) {
 469                 if (test_bit(i, host->taps)) {
 470                         ntap++;
 471                 } else {
 472                         if (ntap > tap_cnt) {
 473                                 tap_start = i - ntap;
 474                                 tap_end = i - 1;
 475                                 tap_cnt = ntap;
 476                         }
 477                         ntap = 0;
 478                 }
 479         }
 480
 481         if (ntap > tap_cnt) {
 482                 tap_start = i - ntap;
 483                 tap_end = i - 1;
 484                 tap_cnt = ntap;
 485         }
 486
 487         if (tap_cnt >= SH_MOBILE_SDHI_MAX_TAP)
 488                 host->tap_set = (tap_start + tap_end) / 2 % host->tap_num;
 489         else
 490                 return -EIO;
 491
 492         /* Set SCC */
 493         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, host->tap_set);
 494
 495         /* Enable auto re-tuning */
 496         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
 497                        SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN |
 498                        sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
 499
 500         return 0;
 501 }
 502
 503 static bool renesas_sdhi_check_scc_error(struct tmio_mmc_host *host)
 504 {
 505         struct renesas_sdhi *priv = host_to_priv(host);
 506
 507         /* Check SCC error */
 508         if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL) &
 509             SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &&
 510             sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ) &
 511             SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) {
 512                 /* Clear SCC error */
 513                 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
 514                 return true;
 515         }
 516
 517         return false;
 518 }
 519
 520 static void renesas_sdhi_hw_reset(struct tmio_mmc_host *host)
 521 {
 522         struct renesas_sdhi *priv;
 523
 524         priv = host_to_priv(host);
 525
 526         renesas_sdhi_reset_scc(host, priv);
 527         renesas_sdhi_reset_hs400_mode(host, priv);
 528
 529         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
 530                         sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 531
 532         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
 533                        ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
 534                        sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
 535
 536         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
 537                        ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
 538                        sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
 539 }
 540
 541 static int renesas_sdhi_wait_idle(struct tmio_mmc_host *host, u32 bit)
 542 {
 543         int timeout = 1000;
 544         /* CBSY is set when busy, SCLKDIVEN is cleared when busy */
 545         u32 wait_state = (bit == TMIO_STAT_CMD_BUSY ? TMIO_STAT_CMD_BUSY : 0);
 546
 547         while (--timeout && (sd_ctrl_read16_and_16_as_32(host, CTL_STATUS)
 548                               & bit) == wait_state)
 549                 udelay(1);
 550
 551         if (!timeout) {
 552                 dev_warn(&host->pdev->dev, "timeout waiting for SD bus idle\n");
 553                 return -EBUSY;
 554         }
 555
 556         return 0;
 557 }
 558
 559 static int renesas_sdhi_write16_hook(struct tmio_mmc_host *host, int addr)
 560 {
 561         u32 bit = TMIO_STAT_SCLKDIVEN;
 562
 563         switch (addr) {
 564         case CTL_SD_CMD:
 565         case CTL_STOP_INTERNAL_ACTION:
 566         case CTL_XFER_BLK_COUNT:
 567         case CTL_SD_XFER_LEN:
 568         case CTL_SD_MEM_CARD_OPT:
 569         case CTL_TRANSACTION_CTL:
 570         case CTL_DMA_ENABLE:
 571         case HOST_MODE:
 572                 if (host->pdata->flags & TMIO_MMC_HAVE_CBSY)
 573                         bit = TMIO_STAT_CMD_BUSY;
 574                 /* fallthrough */
 575         case CTL_SD_CARD_CLK_CTL:
 576                 return renesas_sdhi_wait_idle(host, bit);
 577         }
 578
 579         return 0;
 580 }
 581
 582 static int renesas_sdhi_multi_io_quirk(struct mmc_card *card,
 583                                        unsigned int direction, int blk_size)
 584 {
 585         /*
 586          * In Renesas controllers, when performing a
 587          * multiple block read of one or two blocks,
 588          * depending on the timing with which the
 589          * response register is read, the response
 590          * value may not be read properly.
 591          * Use single block read for this HW bug
 592          */
 593         if ((direction == MMC_DATA_READ) &&
 594             blk_size == 2)
 595                 return 1;
 596
 597         return blk_size;
 598 }
 599
 600 static void renesas_sdhi_enable_dma(struct tmio_mmc_host *host, bool enable)
 601 {
 602         /* Iff regs are 8 byte apart, sdbuf is 64 bit. Otherwise always 32. */
 603         int width = (host->bus_shift == 2) ? 64 : 32;
 604
 605         sd_ctrl_write16(host, CTL_DMA_ENABLE, enable ? DMA_ENABLE_DMASDRW : 0);
 606         renesas_sdhi_sdbuf_width(host, enable ? width : 16);
 607 }
 608
 609 int renesas_sdhi_probe(struct platform_device *pdev,
 610                        const struct tmio_mmc_dma_ops *dma_ops)
 611 {
 612         struct tmio_mmc_data *mmd = pdev->dev.platform_data;
 613         const struct renesas_sdhi_of_data *of_data;
 614         struct tmio_mmc_data *mmc_data;
 615         struct tmio_mmc_dma *dma_priv;
 616         struct tmio_mmc_host *host;
 617         struct renesas_sdhi *priv;
 618         struct resource *res;
 619         int irq, ret, i;
 620         u16 ver;
 621
 622         of_data = of_device_get_match_data(&pdev->dev);
 623
 624         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 625         if (!res)
 626                 return -EINVAL;
 627
 628         priv = devm_kzalloc(&pdev->dev, sizeof(struct renesas_sdhi),
 629                             GFP_KERNEL);
 630         if (!priv)
 631                 return -ENOMEM;
 632
 633         mmc_data = &priv->mmc_data;
 634         dma_priv = &priv->dma_priv;
 635
 636         priv->clk = devm_clk_get(&pdev->dev, NULL);
 637         if (IS_ERR(priv->clk)) {
 638                 ret = PTR_ERR(priv->clk);
 639                 dev_err(&pdev->dev, "cannot get clock: %d\n", ret);
 640                 return ret;
 641         }
 642
 643         /*
 644          * Some controllers provide a 2nd clock just to run the internal card
 645          * detection logic. Unfortunately, the existing driver architecture does
 646          * not support a separation of clocks for runtime PM usage. When
 647          * native hotplug is used, the tmio driver assumes that the core
 648          * must continue to run for card detect to stay active, so we cannot
 649          * disable it.
 650          * Additionally, it is prohibited to supply a clock to the core but not
 651          * to the card detect circuit. That leaves us with if separate clocks
 652          * are presented, we must treat them both as virtually 1 clock.
 653          */
 654         priv->clk_cd = devm_clk_get(&pdev->dev, "cd");
 655         if (IS_ERR(priv->clk_cd))
 656                 priv->clk_cd = NULL;
 657
 658         priv->pinctrl = devm_pinctrl_get(&pdev->dev);
 659         if (!IS_ERR(priv->pinctrl)) {
 660                 priv->pins_default = pinctrl_lookup_state(priv->pinctrl,
 661                                                 PINCTRL_STATE_DEFAULT);
 662                 priv->pins_uhs = pinctrl_lookup_state(priv->pinctrl,
 663                                                 "state_uhs");
 664         }
 665
 666         host = tmio_mmc_host_alloc(pdev, mmc_data);
 667         if (IS_ERR(host))
 668                 return PTR_ERR(host);
 669
 670         if (of_data) {
 671                 mmc_data->flags |= of_data->tmio_flags;
 672                 mmc_data->ocr_mask = of_data->tmio_ocr_mask;
 673                 mmc_data->capabilities |= of_data->capabilities;
 674                 mmc_data->capabilities2 |= of_data->capabilities2;
 675                 mmc_data->dma_rx_offset = of_data->dma_rx_offset;
 676                 mmc_data->max_blk_count = of_data->max_blk_count;
 677                 mmc_data->max_segs = of_data->max_segs;
 678                 dma_priv->dma_buswidth = of_data->dma_buswidth;
 679                 host->bus_shift = of_data->bus_shift;
 680         }
 681
 682         host->write16_hook      = renesas_sdhi_write16_hook;
 683         host->clk_enable        = renesas_sdhi_clk_enable;
 684         host->clk_disable       = renesas_sdhi_clk_disable;
 685         host->set_clock         = renesas_sdhi_set_clock;
 686         host->multi_io_quirk    = renesas_sdhi_multi_io_quirk;
 687         host->dma_ops           = dma_ops;
 688
 689         /* For some SoC, we disable internal WP. GPIO may override this */
 690         if (mmc_can_gpio_ro(host->mmc))
 691                 mmc_data->capabilities2 &= ~MMC_CAP2_NO_WRITE_PROTECT;
 692
 693         /* SDR speeds are only available on Gen2+ */
 694         if (mmc_data->flags & TMIO_MMC_MIN_RCAR2) {
 695                 /* card_busy caused issues on r8a73a4 (pre-Gen2) CD-less SDHI */
 696                 host->ops.card_busy = renesas_sdhi_card_busy;
 697                 host->ops.start_signal_voltage_switch =
 698                         renesas_sdhi_start_signal_voltage_switch;
 699
 700                 /* SDR and HS200/400 registers requires HW reset */
 701                 if (of_data && of_data->scc_offset) {
 702                         priv->scc_ctl = host->ctl + of_data->scc_offset;
 703                         host->mmc->caps |= MMC_CAP_HW_RESET;
 704                         host->hw_reset = renesas_sdhi_hw_reset;
 705                 }
 706         }
 707
 708         /* Orginally registers were 16 bit apart, could be 32 or 64 nowadays */
 709         if (!host->bus_shift && resource_size(res) > 0x100) /* old way to determine the shift */
 710                 host->bus_shift = 1;
 711
 712         if (mmd)
 713                 *mmc_data = *mmd;
 714
 715         dma_priv->filter = shdma_chan_filter;
 716         dma_priv->enable = renesas_sdhi_enable_dma;
 717
 718         mmc_data->alignment_shift = 1; /* 2-byte alignment */
 719         mmc_data->capabilities |= MMC_CAP_MMC_HIGHSPEED;
 720
 721         /*
 722          * All SDHI blocks support 2-byte and larger block sizes in 4-bit
 723          * bus width mode.
 724          */
 725         mmc_data->flags |= TMIO_MMC_BLKSZ_2BYTES;
 726
 727         /*
 728          * All SDHI blocks support SDIO IRQ signalling.
 729          */
 730         mmc_data->flags |= TMIO_MMC_SDIO_IRQ;
 731
 732         /* All SDHI have CMD12 control bit */
 733         mmc_data->flags |= TMIO_MMC_HAVE_CMD12_CTRL;
 734
 735         /* All SDHI have SDIO status bits which must be 1 */
 736         mmc_data->flags |= TMIO_MMC_SDIO_STATUS_SETBITS;
 737
 738         ret = renesas_sdhi_clk_enable(host);
 739         if (ret)
 740                 goto efree;
 741
 742         ver = sd_ctrl_read16(host, CTL_VERSION);
 743         /* GEN2_SDR104 is first known SDHI to use 32bit block count */
 744         if (ver < SDHI_VER_GEN2_SDR104 && mmc_data->max_blk_count > U16_MAX)
 745                 mmc_data->max_blk_count = U16_MAX;
 746
 747         ret = tmio_mmc_host_probe(host);
 748         if (ret < 0)
 749                 goto edisclk;
 750
 751         /* One Gen2 SDHI incarnation does NOT have a CBSY bit */
 752         if (ver == SDHI_VER_GEN2_SDR50)
 753                 mmc_data->flags &= ~TMIO_MMC_HAVE_CBSY;
 754
 755         /* Enable tuning iff we have an SCC and a supported mode */
 756         if (of_data && of_data->scc_offset &&
 757             (host->mmc->caps & MMC_CAP_UHS_SDR104 ||
 758              host->mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR |
 759                                  MMC_CAP2_HS400_1_8V))) {
 760                 const struct renesas_sdhi_scc *taps = of_data->taps;
 761                 bool hit = false;
 762
 763                 for (i = 0; i < of_data->taps_num; i++) {
 764                         if (taps[i].clk_rate == 0 ||
 765                             taps[i].clk_rate == host->mmc->f_max) {
 766                                 priv->scc_tappos = taps->tap;
 767                                 hit = true;
 768                                 break;
 769                         }
 770                 }
 771
 772                 if (!hit)
 773                         dev_warn(&host->pdev->dev, "Unknown clock rate for SDR104\n");
 774
 775                 host->init_tuning = renesas_sdhi_init_tuning;
 776                 host->prepare_tuning = renesas_sdhi_prepare_tuning;
 777                 host->select_tuning = renesas_sdhi_select_tuning;
 778                 host->check_scc_error = renesas_sdhi_check_scc_error;
 779                 host->prepare_hs400_tuning =
 780                         renesas_sdhi_prepare_hs400_tuning;
 781                 host->hs400_downgrade = renesas_sdhi_disable_scc;
 782                 host->hs400_complete = renesas_sdhi_hs400_complete;
 783         }
 784
 785         i = 0;
 786         while (1) {
 787                 irq = platform_get_irq(pdev, i);
 788                 if (irq < 0)
 789                         break;
 790                 i++;
 791                 ret = devm_request_irq(&pdev->dev, irq, tmio_mmc_irq, 0,
 792                                        dev_name(&pdev->dev), host);
 793                 if (ret)
 794                         goto eirq;
 795         }
 796
 797         /* There must be at least one IRQ source */
 798         if (!i) {
 799                 ret = irq;
 800                 goto eirq;
 801         }
 802
 803         dev_info(&pdev->dev, "%s base at 0x%08lx max clock rate %u MHz\n",
 804                  mmc_hostname(host->mmc), (unsigned long)
 805                  (platform_get_resource(pdev, IORESOURCE_MEM, 0)->start),
 806                  host->mmc->f_max / 1000000);
 807
 808         return ret;
 809
 810 eirq:
 811         tmio_mmc_host_remove(host);
 812 edisclk:
 813         renesas_sdhi_clk_disable(host);
 814 efree:
 815         tmio_mmc_host_free(host);
 816
 817         return ret;
 818 }
 819 EXPORT_SYMBOL_GPL(renesas_sdhi_probe);
 820
 821 int renesas_sdhi_remove(struct platform_device *pdev)
 822 {
 823         struct tmio_mmc_host *host = platform_get_drvdata(pdev);
 824
 825         tmio_mmc_host_remove(host);
 826         renesas_sdhi_clk_disable(host);
 827         tmio_mmc_host_free(host);
 828
 829         return 0;
 830 }
 831 EXPORT_SYMBOL_GPL(renesas_sdhi_remove);
 832
 833 MODULE_LICENSE("GPL v2");