2 * drivers/mmc/host/omap_hsmmc.c
4 * Driver for OMAP2430/3430 MMC controller.
6 * Copyright (C) 2007 Texas Instruments.
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/kernel.h>
21 #include <linux/debugfs.h>
22 #include <linux/dmaengine.h>
23 #include <linux/seq_file.h>
24 #include <linux/sizes.h>
25 #include <linux/interrupt.h>
26 #include <linux/delay.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/platform_device.h>
29 #include <linux/timer.h>
30 #include <linux/clk.h>
32 #include <linux/of_irq.h>
33 #include <linux/of_device.h>
34 #include <linux/mmc/host.h>
35 #include <linux/mmc/core.h>
36 #include <linux/mmc/mmc.h>
37 #include <linux/mmc/slot-gpio.h>
39 #include <linux/irq.h>
40 #include <linux/regulator/consumer.h>
41 #include <linux/pinctrl/consumer.h>
42 #include <linux/pm_runtime.h>
43 #include <linux/pm_wakeirq.h>
44 #include <linux/platform_data/hsmmc-omap.h>
46 /* OMAP HSMMC Host Controller Registers */
47 #define OMAP_HSMMC_SYSSTATUS 0x0014
48 #define OMAP_HSMMC_CON 0x002C
49 #define OMAP_HSMMC_SDMASA 0x0100
50 #define OMAP_HSMMC_BLK 0x0104
51 #define OMAP_HSMMC_ARG 0x0108
52 #define OMAP_HSMMC_CMD 0x010C
53 #define OMAP_HSMMC_RSP10 0x0110
54 #define OMAP_HSMMC_RSP32 0x0114
55 #define OMAP_HSMMC_RSP54 0x0118
56 #define OMAP_HSMMC_RSP76 0x011C
57 #define OMAP_HSMMC_DATA 0x0120
58 #define OMAP_HSMMC_PSTATE 0x0124
59 #define OMAP_HSMMC_HCTL 0x0128
60 #define OMAP_HSMMC_SYSCTL 0x012C
61 #define OMAP_HSMMC_STAT 0x0130
62 #define OMAP_HSMMC_IE 0x0134
63 #define OMAP_HSMMC_ISE 0x0138
64 #define OMAP_HSMMC_AC12 0x013C
65 #define OMAP_HSMMC_CAPA 0x0140
67 #define VS18 (1 << 26)
68 #define VS30 (1 << 25)
70 #define SDVS18 (0x5 << 9)
71 #define SDVS30 (0x6 << 9)
72 #define SDVS33 (0x7 << 9)
73 #define SDVS_MASK 0x00000E00
74 #define SDVSCLR 0xFFFFF1FF
75 #define SDVSDET 0x00000400
82 #define CLKD_MAX 0x3FF /* max clock divisor: 1023 */
83 #define CLKD_MASK 0x0000FFC0
85 #define DTO_MASK 0x000F0000
87 #define INIT_STREAM (1 << 1)
88 #define ACEN_ACMD23 (2 << 2)
89 #define DP_SELECT (1 << 21)
94 #define FOUR_BIT (1 << 1)
98 #define CLKEXTFREE (1 << 16)
99 #define CTPL (1 << 11)
102 #define STAT_CLEAR 0xFFFFFFFF
103 #define INIT_STREAM_CMD 0x00000000
104 #define DUAL_VOLT_OCR_BIT 7
105 #define SRC (1 << 25)
106 #define SRD (1 << 26)
107 #define SOFTRESET (1 << 1)
110 #define DLEV_DAT(x) (1 << (20 + (x)))
112 /* Interrupt masks for IE and ISE register */
113 #define CC_EN (1 << 0)
114 #define TC_EN (1 << 1)
115 #define BWR_EN (1 << 4)
116 #define BRR_EN (1 << 5)
117 #define CIRQ_EN (1 << 8)
118 #define ERR_EN (1 << 15)
119 #define CTO_EN (1 << 16)
120 #define CCRC_EN (1 << 17)
121 #define CEB_EN (1 << 18)
122 #define CIE_EN (1 << 19)
123 #define DTO_EN (1 << 20)
124 #define DCRC_EN (1 << 21)
125 #define DEB_EN (1 << 22)
126 #define ACE_EN (1 << 24)
127 #define CERR_EN (1 << 28)
128 #define BADA_EN (1 << 29)
130 #define INT_EN_MASK (BADA_EN | CERR_EN | ACE_EN | DEB_EN | DCRC_EN |\
131 DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \
132 BRR_EN | BWR_EN | TC_EN | CC_EN)
135 #define ACIE (1 << 4)
136 #define ACEB (1 << 3)
137 #define ACCE (1 << 2)
138 #define ACTO (1 << 1)
139 #define ACNE (1 << 0)
141 #define MMC_AUTOSUSPEND_DELAY 100
142 #define MMC_TIMEOUT_MS 20 /* 20 mSec */
143 #define MMC_TIMEOUT_US 20000 /* 20000 micro Sec */
144 #define OMAP_MMC_MIN_CLOCK 400000
145 #define OMAP_MMC_MAX_CLOCK 52000000
146 #define DRIVER_NAME "omap_hsmmc"
149 * One controller can have multiple slots, like on some omap boards using
150 * omap.c controller driver. Luckily this is not currently done on any known
151 * omap_hsmmc.c device.
153 #define mmc_pdata(host) host->pdata
156 * MMC Host controller read/write API's
158 #define OMAP_HSMMC_READ(base, reg) \
159 __raw_readl((base) + OMAP_HSMMC_##reg)
161 #define OMAP_HSMMC_WRITE(base, reg, val) \
162 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
164 struct omap_hsmmc_next {
165 unsigned int dma_len;
169 struct omap_hsmmc_host {
171 struct mmc_host *mmc;
172 struct mmc_request *mrq;
173 struct mmc_command *cmd;
174 struct mmc_data *data;
177 struct regulator *pbias;
181 resource_size_t mapbase;
182 spinlock_t irq_lock; /* Prevent races with irq handler */
183 unsigned int dma_len;
184 unsigned int dma_sg_idx;
185 unsigned char bus_mode;
186 unsigned char power_mode;
195 struct dma_chan *tx_chan;
196 struct dma_chan *rx_chan;
201 unsigned long clk_rate;
203 #define AUTO_CMD23 (1 << 0) /* Auto CMD23 support */
204 #define HSMMC_SDIO_IRQ_ENABLED (1 << 1) /* SDIO irq enabled */
205 struct omap_hsmmc_next next_data;
206 struct omap_hsmmc_platform_data *pdata;
209 struct omap_mmc_of_data {
214 static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host);
216 static int omap_hsmmc_enable_supply(struct mmc_host *mmc)
219 struct omap_hsmmc_host *host = mmc_priv(mmc);
220 struct mmc_ios *ios = &mmc->ios;
222 if (!IS_ERR(mmc->supply.vmmc)) {
223 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
228 /* Enable interface voltage rail, if needed */
229 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
230 ret = regulator_enable(mmc->supply.vqmmc);
232 dev_err(mmc_dev(mmc), "vmmc_aux reg enable failed\n");
235 host->vqmmc_enabled = 1;
241 if (!IS_ERR(mmc->supply.vmmc))
242 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
247 static int omap_hsmmc_disable_supply(struct mmc_host *mmc)
251 struct omap_hsmmc_host *host = mmc_priv(mmc);
253 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
254 ret = regulator_disable(mmc->supply.vqmmc);
256 dev_err(mmc_dev(mmc), "vmmc_aux reg disable failed\n");
259 host->vqmmc_enabled = 0;
262 if (!IS_ERR(mmc->supply.vmmc)) {
263 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
271 if (!IS_ERR(mmc->supply.vqmmc)) {
272 status = regulator_enable(mmc->supply.vqmmc);
274 dev_err(mmc_dev(mmc), "vmmc_aux re-enable failed\n");
280 static int omap_hsmmc_set_pbias(struct omap_hsmmc_host *host, bool power_on)
284 if (IS_ERR(host->pbias))
288 if (host->pbias_enabled == 0) {
289 ret = regulator_enable(host->pbias);
291 dev_err(host->dev, "pbias reg enable fail\n");
294 host->pbias_enabled = 1;
297 if (host->pbias_enabled == 1) {
298 ret = regulator_disable(host->pbias);
300 dev_err(host->dev, "pbias reg disable fail\n");
303 host->pbias_enabled = 0;
310 static int omap_hsmmc_set_power(struct omap_hsmmc_host *host, int power_on)
312 struct mmc_host *mmc = host->mmc;
316 * If we don't see a Vcc regulator, assume it's a fixed
317 * voltage always-on regulator.
319 if (IS_ERR(mmc->supply.vmmc))
322 ret = omap_hsmmc_set_pbias(host, false);
327 * Assume Vcc regulator is used only to power the card ... OMAP
328 * VDDS is used to power the pins, optionally with a transceiver to
329 * support cards using voltages other than VDDS (1.8V nominal). When a
330 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
332 * In some cases this regulator won't support enable/disable;
333 * e.g. it's a fixed rail for a WLAN chip.
335 * In other cases vcc_aux switches interface power. Example, for
336 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
337 * chips/cards need an interface voltage rail too.
340 ret = omap_hsmmc_enable_supply(mmc);
344 ret = omap_hsmmc_set_pbias(host, true);
346 goto err_set_voltage;
348 ret = omap_hsmmc_disable_supply(mmc);
356 omap_hsmmc_disable_supply(mmc);
361 static int omap_hsmmc_disable_boot_regulator(struct regulator *reg)
368 if (regulator_is_enabled(reg)) {
369 ret = regulator_enable(reg);
373 ret = regulator_disable(reg);
381 static int omap_hsmmc_disable_boot_regulators(struct omap_hsmmc_host *host)
383 struct mmc_host *mmc = host->mmc;
387 * disable regulators enabled during boot and get the usecount
388 * right so that regulators can be enabled/disabled by checking
389 * the return value of regulator_is_enabled
391 ret = omap_hsmmc_disable_boot_regulator(mmc->supply.vmmc);
393 dev_err(host->dev, "fail to disable boot enabled vmmc reg\n");
397 ret = omap_hsmmc_disable_boot_regulator(mmc->supply.vqmmc);
400 "fail to disable boot enabled vmmc_aux reg\n");
404 ret = omap_hsmmc_disable_boot_regulator(host->pbias);
407 "failed to disable boot enabled pbias reg\n");
414 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
417 struct mmc_host *mmc = host->mmc;
420 ret = mmc_regulator_get_supply(mmc);
424 /* Allow an aux regulator */
425 if (IS_ERR(mmc->supply.vqmmc)) {
426 mmc->supply.vqmmc = devm_regulator_get_optional(host->dev,
428 if (IS_ERR(mmc->supply.vqmmc)) {
429 ret = PTR_ERR(mmc->supply.vqmmc);
430 if ((ret != -ENODEV) && host->dev->of_node)
432 dev_dbg(host->dev, "unable to get vmmc_aux regulator %ld\n",
433 PTR_ERR(mmc->supply.vqmmc));
437 host->pbias = devm_regulator_get_optional(host->dev, "pbias");
438 if (IS_ERR(host->pbias)) {
439 ret = PTR_ERR(host->pbias);
440 if ((ret != -ENODEV) && host->dev->of_node) {
442 "SD card detect fail? enable CONFIG_REGULATOR_PBIAS\n");
445 dev_dbg(host->dev, "unable to get pbias regulator %ld\n",
446 PTR_ERR(host->pbias));
449 /* For eMMC do not power off when not in sleep state */
450 if (mmc_pdata(host)->no_regulator_off_init)
453 ret = omap_hsmmc_disable_boot_regulators(host);
461 * Start clock to the card
463 static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
465 OMAP_HSMMC_WRITE(host->base, SYSCTL,
466 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
470 * Stop clock to the card
472 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
474 OMAP_HSMMC_WRITE(host->base, SYSCTL,
475 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
476 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
477 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n");
480 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
481 struct mmc_command *cmd)
483 u32 irq_mask = INT_EN_MASK;
487 irq_mask &= ~(BRR_EN | BWR_EN);
489 /* Disable timeout for erases */
490 if (cmd->opcode == MMC_ERASE)
493 spin_lock_irqsave(&host->irq_lock, flags);
494 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
495 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
497 /* latch pending CIRQ, but don't signal MMC core */
498 if (host->flags & HSMMC_SDIO_IRQ_ENABLED)
500 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
501 spin_unlock_irqrestore(&host->irq_lock, flags);
504 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
509 spin_lock_irqsave(&host->irq_lock, flags);
510 /* no transfer running but need to keep cirq if enabled */
511 if (host->flags & HSMMC_SDIO_IRQ_ENABLED)
513 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
514 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
515 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
516 spin_unlock_irqrestore(&host->irq_lock, flags);
519 /* Calculate divisor for the given clock frequency */
520 static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
525 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
533 static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
535 struct mmc_ios *ios = &host->mmc->ios;
536 unsigned long regval;
537 unsigned long timeout;
538 unsigned long clkdiv;
540 dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
542 omap_hsmmc_stop_clock(host);
544 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
545 regval = regval & ~(CLKD_MASK | DTO_MASK);
546 clkdiv = calc_divisor(host, ios);
547 regval = regval | (clkdiv << 6) | (DTO << 16);
548 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
549 OMAP_HSMMC_WRITE(host->base, SYSCTL,
550 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
552 /* Wait till the ICS bit is set */
553 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
554 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
555 && time_before(jiffies, timeout))
559 * Enable High-Speed Support
561 * - Controller should support High-Speed-Enable Bit
562 * - Controller should not be using DDR Mode
563 * - Controller should advertise that it supports High Speed
564 * in capabilities register
565 * - MMC/SD clock coming out of controller > 25MHz
567 if ((mmc_pdata(host)->features & HSMMC_HAS_HSPE_SUPPORT) &&
568 (ios->timing != MMC_TIMING_MMC_DDR52) &&
569 (ios->timing != MMC_TIMING_UHS_DDR50) &&
570 ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) {
571 regval = OMAP_HSMMC_READ(host->base, HCTL);
572 if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000)
577 OMAP_HSMMC_WRITE(host->base, HCTL, regval);
580 omap_hsmmc_start_clock(host);
583 static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
585 struct mmc_ios *ios = &host->mmc->ios;
588 con = OMAP_HSMMC_READ(host->base, CON);
589 if (ios->timing == MMC_TIMING_MMC_DDR52 ||
590 ios->timing == MMC_TIMING_UHS_DDR50)
591 con |= DDR; /* configure in DDR mode */
594 switch (ios->bus_width) {
595 case MMC_BUS_WIDTH_8:
596 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
598 case MMC_BUS_WIDTH_4:
599 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
600 OMAP_HSMMC_WRITE(host->base, HCTL,
601 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
603 case MMC_BUS_WIDTH_1:
604 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
605 OMAP_HSMMC_WRITE(host->base, HCTL,
606 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
611 static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
613 struct mmc_ios *ios = &host->mmc->ios;
616 con = OMAP_HSMMC_READ(host->base, CON);
617 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
618 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
620 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
626 * Restore the MMC host context, if it was lost as result of a
627 * power state change.
629 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
631 struct mmc_ios *ios = &host->mmc->ios;
633 unsigned long timeout;
635 if (host->con == OMAP_HSMMC_READ(host->base, CON) &&
636 host->hctl == OMAP_HSMMC_READ(host->base, HCTL) &&
637 host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) &&
638 host->capa == OMAP_HSMMC_READ(host->base, CAPA))
641 host->context_loss++;
643 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
644 if (host->power_mode != MMC_POWER_OFF &&
645 (1 << ios->vdd) <= MMC_VDD_23_24)
655 if (host->mmc->caps & MMC_CAP_SDIO_IRQ)
658 OMAP_HSMMC_WRITE(host->base, HCTL,
659 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
661 OMAP_HSMMC_WRITE(host->base, CAPA,
662 OMAP_HSMMC_READ(host->base, CAPA) | capa);
664 OMAP_HSMMC_WRITE(host->base, HCTL,
665 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
667 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
668 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
669 && time_before(jiffies, timeout))
672 OMAP_HSMMC_WRITE(host->base, ISE, 0);
673 OMAP_HSMMC_WRITE(host->base, IE, 0);
674 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
676 /* Do not initialize card-specific things if the power is off */
677 if (host->power_mode == MMC_POWER_OFF)
680 omap_hsmmc_set_bus_width(host);
682 omap_hsmmc_set_clock(host);
684 omap_hsmmc_set_bus_mode(host);
687 dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n",
693 * Save the MMC host context (store the number of power state changes so far).
695 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
697 host->con = OMAP_HSMMC_READ(host->base, CON);
698 host->hctl = OMAP_HSMMC_READ(host->base, HCTL);
699 host->sysctl = OMAP_HSMMC_READ(host->base, SYSCTL);
700 host->capa = OMAP_HSMMC_READ(host->base, CAPA);
705 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
710 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
717 * Send init stream sequence to card
718 * before sending IDLE command
720 static void send_init_stream(struct omap_hsmmc_host *host)
723 unsigned long timeout;
725 disable_irq(host->irq);
727 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
728 OMAP_HSMMC_WRITE(host->base, CON,
729 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
730 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
732 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
733 while ((reg != CC_EN) && time_before(jiffies, timeout))
734 reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN;
736 OMAP_HSMMC_WRITE(host->base, CON,
737 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
739 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
740 OMAP_HSMMC_READ(host->base, STAT);
742 enable_irq(host->irq);
746 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
749 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
750 struct omap_hsmmc_host *host = mmc_priv(mmc);
752 return sprintf(buf, "%s\n", mmc_pdata(host)->name);
755 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
758 * Configure the response type and send the cmd.
761 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
762 struct mmc_data *data)
764 int cmdreg = 0, resptype = 0, cmdtype = 0;
766 dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
767 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
770 omap_hsmmc_enable_irq(host, cmd);
772 host->response_busy = 0;
773 if (cmd->flags & MMC_RSP_PRESENT) {
774 if (cmd->flags & MMC_RSP_136)
776 else if (cmd->flags & MMC_RSP_BUSY) {
778 host->response_busy = 1;
784 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
785 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
786 * a val of 0x3, rest 0x0.
788 if (cmd == host->mrq->stop)
791 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
793 if ((host->flags & AUTO_CMD23) && mmc_op_multi(cmd->opcode) &&
795 cmdreg |= ACEN_ACMD23;
796 OMAP_HSMMC_WRITE(host->base, SDMASA, host->mrq->sbc->arg);
799 cmdreg |= DP_SELECT | MSBS | BCE;
800 if (data->flags & MMC_DATA_READ)
809 host->req_in_progress = 1;
811 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
812 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
815 static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host,
816 struct mmc_data *data)
818 return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
821 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
826 spin_lock_irqsave(&host->irq_lock, flags);
827 host->req_in_progress = 0;
828 dma_ch = host->dma_ch;
829 spin_unlock_irqrestore(&host->irq_lock, flags);
831 omap_hsmmc_disable_irq(host);
832 /* Do not complete the request if DMA is still in progress */
833 if (mrq->data && host->use_dma && dma_ch != -1)
836 mmc_request_done(host->mmc, mrq);
840 * Notify the transfer complete to MMC core
843 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
846 struct mmc_request *mrq = host->mrq;
848 /* TC before CC from CMD6 - don't know why, but it happens */
849 if (host->cmd && host->cmd->opcode == 6 &&
850 host->response_busy) {
851 host->response_busy = 0;
855 omap_hsmmc_request_done(host, mrq);
862 data->bytes_xfered += data->blocks * (data->blksz);
864 data->bytes_xfered = 0;
866 if (data->stop && (data->error || !host->mrq->sbc))
867 omap_hsmmc_start_command(host, data->stop, NULL);
869 omap_hsmmc_request_done(host, data->mrq);
873 * Notify the core about command completion
876 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
878 if (host->mrq->sbc && (host->cmd == host->mrq->sbc) &&
879 !host->mrq->sbc->error && !(host->flags & AUTO_CMD23)) {
881 omap_hsmmc_start_dma_transfer(host);
882 omap_hsmmc_start_command(host, host->mrq->cmd,
889 if (cmd->flags & MMC_RSP_PRESENT) {
890 if (cmd->flags & MMC_RSP_136) {
891 /* response type 2 */
892 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
893 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
894 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
895 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
897 /* response types 1, 1b, 3, 4, 5, 6 */
898 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
901 if ((host->data == NULL && !host->response_busy) || cmd->error)
902 omap_hsmmc_request_done(host, host->mrq);
906 * DMA clean up for command errors
908 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
913 host->data->error = errno;
915 spin_lock_irqsave(&host->irq_lock, flags);
916 dma_ch = host->dma_ch;
918 spin_unlock_irqrestore(&host->irq_lock, flags);
920 if (host->use_dma && dma_ch != -1) {
921 struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data);
923 dmaengine_terminate_all(chan);
924 dma_unmap_sg(chan->device->dev,
925 host->data->sg, host->data->sg_len,
926 mmc_get_dma_dir(host->data));
928 host->data->host_cookie = 0;
934 * Readable error output
936 #ifdef CONFIG_MMC_DEBUG
937 static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
939 /* --- means reserved bit without definition at documentation */
940 static const char *omap_hsmmc_status_bits[] = {
941 "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
942 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
943 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
944 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
950 len = sprintf(buf, "MMC IRQ 0x%x :", status);
953 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
954 if (status & (1 << i)) {
955 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
959 dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
962 static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
966 #endif /* CONFIG_MMC_DEBUG */
969 * MMC controller internal state machines reset
971 * Used to reset command or data internal state machines, using respectively
972 * SRC or SRD bit of SYSCTL register
973 * Can be called from interrupt context
975 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
979 unsigned long limit = MMC_TIMEOUT_US;
981 OMAP_HSMMC_WRITE(host->base, SYSCTL,
982 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
985 * OMAP4 ES2 and greater has an updated reset logic.
986 * Monitor a 0->1 transition first
988 if (mmc_pdata(host)->features & HSMMC_HAS_UPDATED_RESET) {
989 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
995 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
999 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
1000 dev_err(mmc_dev(host->mmc),
1001 "Timeout waiting on controller reset in %s\n",
1005 static void hsmmc_command_incomplete(struct omap_hsmmc_host *host,
1006 int err, int end_cmd)
1009 omap_hsmmc_reset_controller_fsm(host, SRC);
1011 host->cmd->error = err;
1015 omap_hsmmc_reset_controller_fsm(host, SRD);
1016 omap_hsmmc_dma_cleanup(host, err);
1017 } else if (host->mrq && host->mrq->cmd)
1018 host->mrq->cmd->error = err;
1021 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
1023 struct mmc_data *data;
1024 int end_cmd = 0, end_trans = 0;
1028 dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1030 if (status & ERR_EN) {
1031 omap_hsmmc_dbg_report_irq(host, status);
1033 if (status & (CTO_EN | CCRC_EN | CEB_EN))
1035 if (host->data || host->response_busy) {
1036 end_trans = !end_cmd;
1037 host->response_busy = 0;
1039 if (status & (CTO_EN | DTO_EN))
1040 hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd);
1041 else if (status & (CCRC_EN | DCRC_EN | DEB_EN | CEB_EN |
1043 hsmmc_command_incomplete(host, -EILSEQ, end_cmd);
1045 if (status & ACE_EN) {
1047 ac12 = OMAP_HSMMC_READ(host->base, AC12);
1048 if (!(ac12 & ACNE) && host->mrq->sbc) {
1052 else if (ac12 & (ACCE | ACEB | ACIE))
1054 host->mrq->sbc->error = error;
1055 hsmmc_command_incomplete(host, error, end_cmd);
1057 dev_dbg(mmc_dev(host->mmc), "AC12 err: 0x%x\n", ac12);
1061 OMAP_HSMMC_WRITE(host->base, STAT, status);
1062 if (end_cmd || ((status & CC_EN) && host->cmd))
1063 omap_hsmmc_cmd_done(host, host->cmd);
1064 if ((end_trans || (status & TC_EN)) && host->mrq)
1065 omap_hsmmc_xfer_done(host, data);
1069 * MMC controller IRQ handler
1071 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1073 struct omap_hsmmc_host *host = dev_id;
1076 status = OMAP_HSMMC_READ(host->base, STAT);
1077 while (status & (INT_EN_MASK | CIRQ_EN)) {
1078 if (host->req_in_progress)
1079 omap_hsmmc_do_irq(host, status);
1081 if (status & CIRQ_EN)
1082 mmc_signal_sdio_irq(host->mmc);
1084 /* Flush posted write */
1085 status = OMAP_HSMMC_READ(host->base, STAT);
1091 static void set_sd_bus_power(struct omap_hsmmc_host *host)
1095 OMAP_HSMMC_WRITE(host->base, HCTL,
1096 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1097 for (i = 0; i < loops_per_jiffy; i++) {
1098 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1105 * Switch MMC interface voltage ... only relevant for MMC1.
1107 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1108 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1109 * Some chips, like eMMC ones, use internal transceivers.
1111 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1116 /* Disable the clocks */
1117 clk_disable_unprepare(host->dbclk);
1119 /* Turn the power off */
1120 ret = omap_hsmmc_set_power(host, 0);
1122 /* Turn the power ON with given VDD 1.8 or 3.0v */
1124 ret = omap_hsmmc_set_power(host, 1);
1125 clk_prepare_enable(host->dbclk);
1130 OMAP_HSMMC_WRITE(host->base, HCTL,
1131 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1132 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1135 * If a MMC dual voltage card is detected, the set_ios fn calls
1136 * this fn with VDD bit set for 1.8V. Upon card removal from the
1137 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1139 * Cope with a bit of slop in the range ... per data sheets:
1140 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1141 * but recommended values are 1.71V to 1.89V
1142 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1143 * but recommended values are 2.7V to 3.3V
1145 * Board setup code shouldn't permit anything very out-of-range.
1146 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1147 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1149 if ((1 << vdd) <= MMC_VDD_23_24)
1154 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1155 set_sd_bus_power(host);
1159 dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1163 static void omap_hsmmc_dma_callback(void *param)
1165 struct omap_hsmmc_host *host = param;
1166 struct dma_chan *chan;
1167 struct mmc_data *data;
1168 int req_in_progress;
1170 spin_lock_irq(&host->irq_lock);
1171 if (host->dma_ch < 0) {
1172 spin_unlock_irq(&host->irq_lock);
1176 data = host->mrq->data;
1177 chan = omap_hsmmc_get_dma_chan(host, data);
1178 if (!data->host_cookie)
1179 dma_unmap_sg(chan->device->dev,
1180 data->sg, data->sg_len,
1181 mmc_get_dma_dir(data));
1183 req_in_progress = host->req_in_progress;
1185 spin_unlock_irq(&host->irq_lock);
1187 /* If DMA has finished after TC, complete the request */
1188 if (!req_in_progress) {
1189 struct mmc_request *mrq = host->mrq;
1192 mmc_request_done(host->mmc, mrq);
1196 static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1197 struct mmc_data *data,
1198 struct omap_hsmmc_next *next,
1199 struct dma_chan *chan)
1203 if (!next && data->host_cookie &&
1204 data->host_cookie != host->next_data.cookie) {
1205 dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d"
1206 " host->next_data.cookie %d\n",
1207 __func__, data->host_cookie, host->next_data.cookie);
1208 data->host_cookie = 0;
1211 /* Check if next job is already prepared */
1212 if (next || data->host_cookie != host->next_data.cookie) {
1213 dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len,
1214 mmc_get_dma_dir(data));
1217 dma_len = host->next_data.dma_len;
1218 host->next_data.dma_len = 0;
1226 next->dma_len = dma_len;
1227 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1229 host->dma_len = dma_len;
1235 * Routine to configure and start DMA for the MMC card
1237 static int omap_hsmmc_setup_dma_transfer(struct omap_hsmmc_host *host,
1238 struct mmc_request *req)
1240 struct dma_async_tx_descriptor *tx;
1242 struct mmc_data *data = req->data;
1243 struct dma_chan *chan;
1244 struct dma_slave_config cfg = {
1245 .src_addr = host->mapbase + OMAP_HSMMC_DATA,
1246 .dst_addr = host->mapbase + OMAP_HSMMC_DATA,
1247 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
1248 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
1249 .src_maxburst = data->blksz / 4,
1250 .dst_maxburst = data->blksz / 4,
1253 /* Sanity check: all the SG entries must be aligned by block size. */
1254 for (i = 0; i < data->sg_len; i++) {
1255 struct scatterlist *sgl;
1258 if (sgl->length % data->blksz)
1261 if ((data->blksz % 4) != 0)
1262 /* REVISIT: The MMC buffer increments only when MSB is written.
1263 * Return error for blksz which is non multiple of four.
1267 BUG_ON(host->dma_ch != -1);
1269 chan = omap_hsmmc_get_dma_chan(host, data);
1271 ret = dmaengine_slave_config(chan, &cfg);
1275 ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan);
1279 tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len,
1280 data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
1281 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1283 dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n");
1284 /* FIXME: cleanup */
1288 tx->callback = omap_hsmmc_dma_callback;
1289 tx->callback_param = host;
1292 dmaengine_submit(tx);
1299 static void set_data_timeout(struct omap_hsmmc_host *host,
1300 unsigned long long timeout_ns,
1301 unsigned int timeout_clks)
1303 unsigned long long timeout = timeout_ns;
1304 unsigned int cycle_ns;
1305 uint32_t reg, clkd, dto = 0;
1307 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1308 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1312 cycle_ns = 1000000000 / (host->clk_rate / clkd);
1313 do_div(timeout, cycle_ns);
1314 timeout += timeout_clks;
1316 while ((timeout & 0x80000000) == 0) {
1333 reg |= dto << DTO_SHIFT;
1334 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1337 static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host)
1339 struct mmc_request *req = host->mrq;
1340 struct dma_chan *chan;
1344 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1345 | (req->data->blocks << 16));
1346 set_data_timeout(host, req->data->timeout_ns,
1347 req->data->timeout_clks);
1348 chan = omap_hsmmc_get_dma_chan(host, req->data);
1349 dma_async_issue_pending(chan);
1353 * Configure block length for MMC/SD cards and initiate the transfer.
1356 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1359 unsigned long long timeout;
1361 host->data = req->data;
1363 if (req->data == NULL) {
1364 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1365 if (req->cmd->flags & MMC_RSP_BUSY) {
1366 timeout = req->cmd->busy_timeout * NSEC_PER_MSEC;
1369 * Set an arbitrary 100ms data timeout for commands with
1370 * busy signal and no indication of busy_timeout.
1373 timeout = 100000000U;
1375 set_data_timeout(host, timeout, 0);
1380 if (host->use_dma) {
1381 ret = omap_hsmmc_setup_dma_transfer(host, req);
1383 dev_err(mmc_dev(host->mmc), "MMC start dma failure\n");
1390 static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1393 struct omap_hsmmc_host *host = mmc_priv(mmc);
1394 struct mmc_data *data = mrq->data;
1396 if (host->use_dma && data->host_cookie) {
1397 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data);
1399 dma_unmap_sg(c->device->dev, data->sg, data->sg_len,
1400 mmc_get_dma_dir(data));
1401 data->host_cookie = 0;
1405 static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
1407 struct omap_hsmmc_host *host = mmc_priv(mmc);
1409 if (mrq->data->host_cookie) {
1410 mrq->data->host_cookie = 0;
1414 if (host->use_dma) {
1415 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data);
1417 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1418 &host->next_data, c))
1419 mrq->data->host_cookie = 0;
1424 * Request function. for read/write operation
1426 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1428 struct omap_hsmmc_host *host = mmc_priv(mmc);
1431 BUG_ON(host->req_in_progress);
1432 BUG_ON(host->dma_ch != -1);
1433 if (host->reqs_blocked)
1434 host->reqs_blocked = 0;
1435 WARN_ON(host->mrq != NULL);
1437 host->clk_rate = clk_get_rate(host->fclk);
1438 err = omap_hsmmc_prepare_data(host, req);
1440 req->cmd->error = err;
1442 req->data->error = err;
1444 mmc_request_done(mmc, req);
1447 if (req->sbc && !(host->flags & AUTO_CMD23)) {
1448 omap_hsmmc_start_command(host, req->sbc, NULL);
1452 omap_hsmmc_start_dma_transfer(host);
1453 omap_hsmmc_start_command(host, req->cmd, req->data);
1456 /* Routine to configure clock values. Exposed API to core */
1457 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1459 struct omap_hsmmc_host *host = mmc_priv(mmc);
1460 int do_send_init_stream = 0;
1462 if (ios->power_mode != host->power_mode) {
1463 switch (ios->power_mode) {
1465 omap_hsmmc_set_power(host, 0);
1468 omap_hsmmc_set_power(host, 1);
1471 do_send_init_stream = 1;
1474 host->power_mode = ios->power_mode;
1477 /* FIXME: set registers based only on changes to ios */
1479 omap_hsmmc_set_bus_width(host);
1481 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1482 /* Only MMC1 can interface at 3V without some flavor
1483 * of external transceiver; but they all handle 1.8V.
1485 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1486 (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1488 * The mmc_select_voltage fn of the core does
1489 * not seem to set the power_mode to
1490 * MMC_POWER_UP upon recalculating the voltage.
1493 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1494 dev_dbg(mmc_dev(host->mmc),
1495 "Switch operation failed\n");
1499 omap_hsmmc_set_clock(host);
1501 if (do_send_init_stream)
1502 send_init_stream(host);
1504 omap_hsmmc_set_bus_mode(host);
1507 static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1509 struct omap_hsmmc_host *host = mmc_priv(mmc);
1511 if (card->type == MMC_TYPE_SDIO || card->type == MMC_TYPE_SD_COMBO) {
1512 struct device_node *np = mmc_dev(mmc)->of_node;
1515 * REVISIT: should be moved to sdio core and made more
1516 * general e.g. by expanding the DT bindings of child nodes
1517 * to provide a mechanism to provide this information:
1518 * Documentation/devicetree/bindings/mmc/mmc-card.txt
1521 np = of_get_compatible_child(np, "ti,wl1251");
1524 * We have TI wl1251 attached to MMC3. Pass this
1525 * information to the SDIO core because it can't be
1526 * probed by normal methods.
1529 dev_info(host->dev, "found wl1251\n");
1530 card->quirks |= MMC_QUIRK_NONSTD_SDIO;
1531 card->cccr.wide_bus = 1;
1532 card->cis.vendor = 0x104c;
1533 card->cis.device = 0x9066;
1534 card->cis.blksize = 512;
1535 card->cis.max_dtr = 24000000;
1542 static void omap_hsmmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
1544 struct omap_hsmmc_host *host = mmc_priv(mmc);
1546 unsigned long flags;
1548 spin_lock_irqsave(&host->irq_lock, flags);
1550 con = OMAP_HSMMC_READ(host->base, CON);
1551 irq_mask = OMAP_HSMMC_READ(host->base, ISE);
1553 host->flags |= HSMMC_SDIO_IRQ_ENABLED;
1554 irq_mask |= CIRQ_EN;
1555 con |= CTPL | CLKEXTFREE;
1557 host->flags &= ~HSMMC_SDIO_IRQ_ENABLED;
1558 irq_mask &= ~CIRQ_EN;
1559 con &= ~(CTPL | CLKEXTFREE);
1561 OMAP_HSMMC_WRITE(host->base, CON, con);
1562 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
1565 * if enable, piggy back detection on current request
1566 * but always disable immediately
1568 if (!host->req_in_progress || !enable)
1569 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
1571 /* flush posted write */
1572 OMAP_HSMMC_READ(host->base, IE);
1574 spin_unlock_irqrestore(&host->irq_lock, flags);
1577 static int omap_hsmmc_configure_wake_irq(struct omap_hsmmc_host *host)
1582 * For omaps with wake-up path, wakeirq will be irq from pinctrl and
1583 * for other omaps, wakeirq will be from GPIO (dat line remuxed to
1584 * gpio). wakeirq is needed to detect sdio irq in runtime suspend state
1585 * with functional clock disabled.
1587 if (!host->dev->of_node || !host->wake_irq)
1590 ret = dev_pm_set_dedicated_wake_irq(host->dev, host->wake_irq);
1592 dev_err(mmc_dev(host->mmc), "Unable to request wake IRQ\n");
1597 * Some omaps don't have wake-up path from deeper idle states
1598 * and need to remux SDIO DAT1 to GPIO for wake-up from idle.
1600 if (host->pdata->controller_flags & OMAP_HSMMC_SWAKEUP_MISSING) {
1601 struct pinctrl *p = devm_pinctrl_get(host->dev);
1607 if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_IDLE))) {
1608 dev_info(host->dev, "missing idle pinctrl state\n");
1609 devm_pinctrl_put(p);
1613 devm_pinctrl_put(p);
1616 OMAP_HSMMC_WRITE(host->base, HCTL,
1617 OMAP_HSMMC_READ(host->base, HCTL) | IWE);
1621 dev_pm_clear_wake_irq(host->dev);
1623 dev_warn(host->dev, "no SDIO IRQ support, falling back to polling\n");
1628 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1630 u32 hctl, capa, value;
1632 /* Only MMC1 supports 3.0V */
1633 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1641 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1642 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1644 value = OMAP_HSMMC_READ(host->base, CAPA);
1645 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1647 /* Set SD bus power bit */
1648 set_sd_bus_power(host);
1651 static int omap_hsmmc_multi_io_quirk(struct mmc_card *card,
1652 unsigned int direction, int blk_size)
1654 /* This controller can't do multiblock reads due to hw bugs */
1655 if (direction == MMC_DATA_READ)
1661 static struct mmc_host_ops omap_hsmmc_ops = {
1662 .post_req = omap_hsmmc_post_req,
1663 .pre_req = omap_hsmmc_pre_req,
1664 .request = omap_hsmmc_request,
1665 .set_ios = omap_hsmmc_set_ios,
1666 .get_cd = mmc_gpio_get_cd,
1667 .get_ro = mmc_gpio_get_ro,
1668 .init_card = omap_hsmmc_init_card,
1669 .enable_sdio_irq = omap_hsmmc_enable_sdio_irq,
1672 #ifdef CONFIG_DEBUG_FS
1674 static int mmc_regs_show(struct seq_file *s, void *data)
1676 struct mmc_host *mmc = s->private;
1677 struct omap_hsmmc_host *host = mmc_priv(mmc);
1679 seq_printf(s, "mmc%d:\n", mmc->index);
1680 seq_printf(s, "sdio irq mode\t%s\n",
1681 (mmc->caps & MMC_CAP_SDIO_IRQ) ? "interrupt" : "polling");
1683 if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1684 seq_printf(s, "sdio irq \t%s\n",
1685 (host->flags & HSMMC_SDIO_IRQ_ENABLED) ? "enabled"
1688 seq_printf(s, "ctx_loss:\t%d\n", host->context_loss);
1690 pm_runtime_get_sync(host->dev);
1691 seq_puts(s, "\nregs:\n");
1692 seq_printf(s, "CON:\t\t0x%08x\n",
1693 OMAP_HSMMC_READ(host->base, CON));
1694 seq_printf(s, "PSTATE:\t\t0x%08x\n",
1695 OMAP_HSMMC_READ(host->base, PSTATE));
1696 seq_printf(s, "HCTL:\t\t0x%08x\n",
1697 OMAP_HSMMC_READ(host->base, HCTL));
1698 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1699 OMAP_HSMMC_READ(host->base, SYSCTL));
1700 seq_printf(s, "IE:\t\t0x%08x\n",
1701 OMAP_HSMMC_READ(host->base, IE));
1702 seq_printf(s, "ISE:\t\t0x%08x\n",
1703 OMAP_HSMMC_READ(host->base, ISE));
1704 seq_printf(s, "CAPA:\t\t0x%08x\n",
1705 OMAP_HSMMC_READ(host->base, CAPA));
1707 pm_runtime_mark_last_busy(host->dev);
1708 pm_runtime_put_autosuspend(host->dev);
1713 DEFINE_SHOW_ATTRIBUTE(mmc_regs);
1715 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1717 if (mmc->debugfs_root)
1718 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1719 mmc, &mmc_regs_fops);
1724 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1731 static const struct omap_mmc_of_data omap3_pre_es3_mmc_of_data = {
1732 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1733 .controller_flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1736 static const struct omap_mmc_of_data omap4_mmc_of_data = {
1737 .reg_offset = 0x100,
1739 static const struct omap_mmc_of_data am33xx_mmc_of_data = {
1740 .reg_offset = 0x100,
1741 .controller_flags = OMAP_HSMMC_SWAKEUP_MISSING,
1744 static const struct of_device_id omap_mmc_of_match[] = {
1746 .compatible = "ti,omap2-hsmmc",
1749 .compatible = "ti,omap3-pre-es3-hsmmc",
1750 .data = &omap3_pre_es3_mmc_of_data,
1753 .compatible = "ti,omap3-hsmmc",
1756 .compatible = "ti,omap4-hsmmc",
1757 .data = &omap4_mmc_of_data,
1760 .compatible = "ti,am33xx-hsmmc",
1761 .data = &am33xx_mmc_of_data,
1765 MODULE_DEVICE_TABLE(of, omap_mmc_of_match);
1767 static struct omap_hsmmc_platform_data *of_get_hsmmc_pdata(struct device *dev)
1769 struct omap_hsmmc_platform_data *pdata, *legacy;
1770 struct device_node *np = dev->of_node;
1772 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
1774 return ERR_PTR(-ENOMEM); /* out of memory */
1776 legacy = dev_get_platdata(dev);
1777 if (legacy && legacy->name)
1778 pdata->name = legacy->name;
1780 if (of_find_property(np, "ti,dual-volt", NULL))
1781 pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1783 if (of_find_property(np, "ti,non-removable", NULL)) {
1784 pdata->nonremovable = true;
1785 pdata->no_regulator_off_init = true;
1788 if (of_find_property(np, "ti,needs-special-reset", NULL))
1789 pdata->features |= HSMMC_HAS_UPDATED_RESET;
1791 if (of_find_property(np, "ti,needs-special-hs-handling", NULL))
1792 pdata->features |= HSMMC_HAS_HSPE_SUPPORT;
1797 static inline struct omap_hsmmc_platform_data
1798 *of_get_hsmmc_pdata(struct device *dev)
1800 return ERR_PTR(-EINVAL);
1804 static int omap_hsmmc_probe(struct platform_device *pdev)
1806 struct omap_hsmmc_platform_data *pdata = pdev->dev.platform_data;
1807 struct mmc_host *mmc;
1808 struct omap_hsmmc_host *host = NULL;
1809 struct resource *res;
1811 const struct of_device_id *match;
1812 const struct omap_mmc_of_data *data;
1815 match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev);
1817 pdata = of_get_hsmmc_pdata(&pdev->dev);
1820 return PTR_ERR(pdata);
1824 pdata->reg_offset = data->reg_offset;
1825 pdata->controller_flags |= data->controller_flags;
1829 if (pdata == NULL) {
1830 dev_err(&pdev->dev, "Platform Data is missing\n");
1834 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1837 irq = platform_get_irq(pdev, 0);
1841 base = devm_ioremap_resource(&pdev->dev, res);
1843 return PTR_ERR(base);
1845 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
1851 ret = mmc_of_parse(mmc);
1855 host = mmc_priv(mmc);
1857 host->pdata = pdata;
1858 host->dev = &pdev->dev;
1862 host->mapbase = res->start + pdata->reg_offset;
1863 host->base = base + pdata->reg_offset;
1864 host->power_mode = MMC_POWER_OFF;
1865 host->next_data.cookie = 1;
1866 host->pbias_enabled = 0;
1867 host->vqmmc_enabled = 0;
1869 platform_set_drvdata(pdev, host);
1871 if (pdev->dev.of_node)
1872 host->wake_irq = irq_of_parse_and_map(pdev->dev.of_node, 1);
1874 mmc->ops = &omap_hsmmc_ops;
1876 mmc->f_min = OMAP_MMC_MIN_CLOCK;
1878 if (pdata->max_freq > 0)
1879 mmc->f_max = pdata->max_freq;
1880 else if (mmc->f_max == 0)
1881 mmc->f_max = OMAP_MMC_MAX_CLOCK;
1883 spin_lock_init(&host->irq_lock);
1885 host->fclk = devm_clk_get(&pdev->dev, "fck");
1886 if (IS_ERR(host->fclk)) {
1887 ret = PTR_ERR(host->fclk);
1892 if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
1893 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
1894 omap_hsmmc_ops.multi_io_quirk = omap_hsmmc_multi_io_quirk;
1897 device_init_wakeup(&pdev->dev, true);
1898 pm_runtime_enable(host->dev);
1899 pm_runtime_get_sync(host->dev);
1900 pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
1901 pm_runtime_use_autosuspend(host->dev);
1903 omap_hsmmc_context_save(host);
1905 host->dbclk = devm_clk_get(&pdev->dev, "mmchsdb_fck");
1907 * MMC can still work without debounce clock.
1909 if (IS_ERR(host->dbclk)) {
1911 } else if (clk_prepare_enable(host->dbclk) != 0) {
1912 dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n");
1916 /* Set this to a value that allows allocating an entire descriptor
1917 * list within a page (zero order allocation). */
1920 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
1921 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
1922 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1924 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
1925 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_CMD23;
1927 mmc->caps |= mmc_pdata(host)->caps;
1928 if (mmc->caps & MMC_CAP_8_BIT_DATA)
1929 mmc->caps |= MMC_CAP_4_BIT_DATA;
1931 if (mmc_pdata(host)->nonremovable)
1932 mmc->caps |= MMC_CAP_NONREMOVABLE;
1934 mmc->pm_caps |= mmc_pdata(host)->pm_caps;
1936 omap_hsmmc_conf_bus_power(host);
1938 host->rx_chan = dma_request_chan(&pdev->dev, "rx");
1939 if (IS_ERR(host->rx_chan)) {
1940 dev_err(mmc_dev(host->mmc), "RX DMA channel request failed\n");
1941 ret = PTR_ERR(host->rx_chan);
1945 host->tx_chan = dma_request_chan(&pdev->dev, "tx");
1946 if (IS_ERR(host->tx_chan)) {
1947 dev_err(mmc_dev(host->mmc), "TX DMA channel request failed\n");
1948 ret = PTR_ERR(host->tx_chan);
1953 * Limit the maximum segment size to the lower of the request size
1954 * and the DMA engine device segment size limits. In reality, with
1955 * 32-bit transfers, the DMA engine can do longer segments than this
1956 * but there is no way to represent that in the DMA model - if we
1957 * increase this figure here, we get warnings from the DMA API debug.
1959 mmc->max_seg_size = min3(mmc->max_req_size,
1960 dma_get_max_seg_size(host->rx_chan->device->dev),
1961 dma_get_max_seg_size(host->tx_chan->device->dev));
1963 /* Request IRQ for MMC operations */
1964 ret = devm_request_irq(&pdev->dev, host->irq, omap_hsmmc_irq, 0,
1965 mmc_hostname(mmc), host);
1967 dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1971 ret = omap_hsmmc_reg_get(host);
1975 if (!mmc->ocr_avail)
1976 mmc->ocr_avail = mmc_pdata(host)->ocr_mask;
1978 omap_hsmmc_disable_irq(host);
1981 * For now, only support SDIO interrupt if we have a separate
1982 * wake-up interrupt configured from device tree. This is because
1983 * the wake-up interrupt is needed for idle state and some
1984 * platforms need special quirks. And we don't want to add new
1985 * legacy mux platform init code callbacks any longer as we
1986 * are moving to DT based booting anyways.
1988 ret = omap_hsmmc_configure_wake_irq(host);
1990 mmc->caps |= MMC_CAP_SDIO_IRQ;
1992 ret = mmc_add_host(mmc);
1996 if (mmc_pdata(host)->name != NULL) {
1997 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
2002 omap_hsmmc_debugfs(mmc);
2003 pm_runtime_mark_last_busy(host->dev);
2004 pm_runtime_put_autosuspend(host->dev);
2009 mmc_remove_host(mmc);
2011 device_init_wakeup(&pdev->dev, false);
2012 if (!IS_ERR_OR_NULL(host->tx_chan))
2013 dma_release_channel(host->tx_chan);
2014 if (!IS_ERR_OR_NULL(host->rx_chan))
2015 dma_release_channel(host->rx_chan);
2016 pm_runtime_dont_use_autosuspend(host->dev);
2017 pm_runtime_put_sync(host->dev);
2018 pm_runtime_disable(host->dev);
2019 clk_disable_unprepare(host->dbclk);
2026 static int omap_hsmmc_remove(struct platform_device *pdev)
2028 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2030 pm_runtime_get_sync(host->dev);
2031 mmc_remove_host(host->mmc);
2033 dma_release_channel(host->tx_chan);
2034 dma_release_channel(host->rx_chan);
2036 dev_pm_clear_wake_irq(host->dev);
2037 pm_runtime_dont_use_autosuspend(host->dev);
2038 pm_runtime_put_sync(host->dev);
2039 pm_runtime_disable(host->dev);
2040 device_init_wakeup(&pdev->dev, false);
2041 clk_disable_unprepare(host->dbclk);
2043 mmc_free_host(host->mmc);
2048 #ifdef CONFIG_PM_SLEEP
2049 static int omap_hsmmc_suspend(struct device *dev)
2051 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2056 pm_runtime_get_sync(host->dev);
2058 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
2059 OMAP_HSMMC_WRITE(host->base, ISE, 0);
2060 OMAP_HSMMC_WRITE(host->base, IE, 0);
2061 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2062 OMAP_HSMMC_WRITE(host->base, HCTL,
2063 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2066 clk_disable_unprepare(host->dbclk);
2068 pm_runtime_put_sync(host->dev);
2072 /* Routine to resume the MMC device */
2073 static int omap_hsmmc_resume(struct device *dev)
2075 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2080 pm_runtime_get_sync(host->dev);
2082 clk_prepare_enable(host->dbclk);
2084 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
2085 omap_hsmmc_conf_bus_power(host);
2087 pm_runtime_mark_last_busy(host->dev);
2088 pm_runtime_put_autosuspend(host->dev);
2093 static int omap_hsmmc_runtime_suspend(struct device *dev)
2095 struct omap_hsmmc_host *host;
2096 unsigned long flags;
2099 host = dev_get_drvdata(dev);
2100 omap_hsmmc_context_save(host);
2101 dev_dbg(dev, "disabled\n");
2103 spin_lock_irqsave(&host->irq_lock, flags);
2104 if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2105 (host->flags & HSMMC_SDIO_IRQ_ENABLED)) {
2106 /* disable sdio irq handling to prevent race */
2107 OMAP_HSMMC_WRITE(host->base, ISE, 0);
2108 OMAP_HSMMC_WRITE(host->base, IE, 0);
2110 if (!(OMAP_HSMMC_READ(host->base, PSTATE) & DLEV_DAT(1))) {
2112 * dat1 line low, pending sdio irq
2113 * race condition: possible irq handler running on
2116 dev_dbg(dev, "pending sdio irq, abort suspend\n");
2117 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2118 OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN);
2119 OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN);
2120 pm_runtime_mark_last_busy(dev);
2125 pinctrl_pm_select_idle_state(dev);
2127 pinctrl_pm_select_idle_state(dev);
2131 spin_unlock_irqrestore(&host->irq_lock, flags);
2135 static int omap_hsmmc_runtime_resume(struct device *dev)
2137 struct omap_hsmmc_host *host;
2138 unsigned long flags;
2140 host = dev_get_drvdata(dev);
2141 omap_hsmmc_context_restore(host);
2142 dev_dbg(dev, "enabled\n");
2144 spin_lock_irqsave(&host->irq_lock, flags);
2145 if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2146 (host->flags & HSMMC_SDIO_IRQ_ENABLED)) {
2148 pinctrl_select_default_state(host->dev);
2150 /* irq lost, if pinmux incorrect */
2151 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2152 OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN);
2153 OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN);
2155 pinctrl_select_default_state(host->dev);
2157 spin_unlock_irqrestore(&host->irq_lock, flags);
2161 static const struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
2162 SET_SYSTEM_SLEEP_PM_OPS(omap_hsmmc_suspend, omap_hsmmc_resume)
2163 .runtime_suspend = omap_hsmmc_runtime_suspend,
2164 .runtime_resume = omap_hsmmc_runtime_resume,
2167 static struct platform_driver omap_hsmmc_driver = {
2168 .probe = omap_hsmmc_probe,
2169 .remove = omap_hsmmc_remove,
2171 .name = DRIVER_NAME,
2172 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
2173 .pm = &omap_hsmmc_dev_pm_ops,
2174 .of_match_table = of_match_ptr(omap_mmc_of_match),
2178 module_platform_driver(omap_hsmmc_driver);
2179 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2180 MODULE_LICENSE("GPL");
2181 MODULE_ALIAS("platform:" DRIVER_NAME);
2182 MODULE_AUTHOR("Texas Instruments Inc");