2 * drivers/mmc/host/omap_hsmmc.c
4 * Driver for OMAP2430/3430 MMC controller.
6 * Copyright (C) 2007 Texas Instruments.
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/kernel.h>
21 #include <linux/debugfs.h>
22 #include <linux/dmaengine.h>
23 #include <linux/seq_file.h>
24 #include <linux/sizes.h>
25 #include <linux/interrupt.h>
26 #include <linux/delay.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/platform_device.h>
29 #include <linux/timer.h>
30 #include <linux/clk.h>
32 #include <linux/of_irq.h>
33 #include <linux/of_gpio.h>
34 #include <linux/of_device.h>
35 #include <linux/mmc/host.h>
36 #include <linux/mmc/core.h>
37 #include <linux/mmc/mmc.h>
38 #include <linux/mmc/slot-gpio.h>
40 #include <linux/irq.h>
41 #include <linux/gpio.h>
42 #include <linux/regulator/consumer.h>
43 #include <linux/pinctrl/consumer.h>
44 #include <linux/pm_runtime.h>
45 #include <linux/pm_wakeirq.h>
46 #include <linux/platform_data/hsmmc-omap.h>
48 /* OMAP HSMMC Host Controller Registers */
49 #define OMAP_HSMMC_SYSSTATUS 0x0014
50 #define OMAP_HSMMC_CON 0x002C
51 #define OMAP_HSMMC_SDMASA 0x0100
52 #define OMAP_HSMMC_BLK 0x0104
53 #define OMAP_HSMMC_ARG 0x0108
54 #define OMAP_HSMMC_CMD 0x010C
55 #define OMAP_HSMMC_RSP10 0x0110
56 #define OMAP_HSMMC_RSP32 0x0114
57 #define OMAP_HSMMC_RSP54 0x0118
58 #define OMAP_HSMMC_RSP76 0x011C
59 #define OMAP_HSMMC_DATA 0x0120
60 #define OMAP_HSMMC_PSTATE 0x0124
61 #define OMAP_HSMMC_HCTL 0x0128
62 #define OMAP_HSMMC_SYSCTL 0x012C
63 #define OMAP_HSMMC_STAT 0x0130
64 #define OMAP_HSMMC_IE 0x0134
65 #define OMAP_HSMMC_ISE 0x0138
66 #define OMAP_HSMMC_AC12 0x013C
67 #define OMAP_HSMMC_CAPA 0x0140
69 #define VS18 (1 << 26)
70 #define VS30 (1 << 25)
72 #define SDVS18 (0x5 << 9)
73 #define SDVS30 (0x6 << 9)
74 #define SDVS33 (0x7 << 9)
75 #define SDVS_MASK 0x00000E00
76 #define SDVSCLR 0xFFFFF1FF
77 #define SDVSDET 0x00000400
84 #define CLKD_MAX 0x3FF /* max clock divisor: 1023 */
85 #define CLKD_MASK 0x0000FFC0
87 #define DTO_MASK 0x000F0000
89 #define INIT_STREAM (1 << 1)
90 #define ACEN_ACMD23 (2 << 2)
91 #define DP_SELECT (1 << 21)
96 #define FOUR_BIT (1 << 1)
100 #define CLKEXTFREE (1 << 16)
101 #define CTPL (1 << 11)
104 #define STAT_CLEAR 0xFFFFFFFF
105 #define INIT_STREAM_CMD 0x00000000
106 #define DUAL_VOLT_OCR_BIT 7
107 #define SRC (1 << 25)
108 #define SRD (1 << 26)
109 #define SOFTRESET (1 << 1)
112 #define DLEV_DAT(x) (1 << (20 + (x)))
114 /* Interrupt masks for IE and ISE register */
115 #define CC_EN (1 << 0)
116 #define TC_EN (1 << 1)
117 #define BWR_EN (1 << 4)
118 #define BRR_EN (1 << 5)
119 #define CIRQ_EN (1 << 8)
120 #define ERR_EN (1 << 15)
121 #define CTO_EN (1 << 16)
122 #define CCRC_EN (1 << 17)
123 #define CEB_EN (1 << 18)
124 #define CIE_EN (1 << 19)
125 #define DTO_EN (1 << 20)
126 #define DCRC_EN (1 << 21)
127 #define DEB_EN (1 << 22)
128 #define ACE_EN (1 << 24)
129 #define CERR_EN (1 << 28)
130 #define BADA_EN (1 << 29)
132 #define INT_EN_MASK (BADA_EN | CERR_EN | ACE_EN | DEB_EN | DCRC_EN |\
133 DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \
134 BRR_EN | BWR_EN | TC_EN | CC_EN)
137 #define ACIE (1 << 4)
138 #define ACEB (1 << 3)
139 #define ACCE (1 << 2)
140 #define ACTO (1 << 1)
141 #define ACNE (1 << 0)
143 #define MMC_AUTOSUSPEND_DELAY 100
144 #define MMC_TIMEOUT_MS 20 /* 20 mSec */
145 #define MMC_TIMEOUT_US 20000 /* 20000 micro Sec */
146 #define OMAP_MMC_MIN_CLOCK 400000
147 #define OMAP_MMC_MAX_CLOCK 52000000
148 #define DRIVER_NAME "omap_hsmmc"
150 #define VDD_1V8 1800000 /* 180000 uV */
151 #define VDD_3V0 3000000 /* 300000 uV */
152 #define VDD_165_195 (ffs(MMC_VDD_165_195) - 1)
155 * One controller can have multiple slots, like on some omap boards using
156 * omap.c controller driver. Luckily this is not currently done on any known
157 * omap_hsmmc.c device.
159 #define mmc_pdata(host) host->pdata
162 * MMC Host controller read/write API's
164 #define OMAP_HSMMC_READ(base, reg) \
165 __raw_readl((base) + OMAP_HSMMC_##reg)
167 #define OMAP_HSMMC_WRITE(base, reg, val) \
168 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
170 struct omap_hsmmc_next {
171 unsigned int dma_len;
175 struct omap_hsmmc_host {
177 struct mmc_host *mmc;
178 struct mmc_request *mrq;
179 struct mmc_command *cmd;
180 struct mmc_data *data;
183 struct regulator *pbias;
187 resource_size_t mapbase;
188 spinlock_t irq_lock; /* Prevent races with irq handler */
189 unsigned int dma_len;
190 unsigned int dma_sg_idx;
191 unsigned char bus_mode;
192 unsigned char power_mode;
201 struct dma_chan *tx_chan;
202 struct dma_chan *rx_chan;
208 unsigned long clk_rate;
210 #define AUTO_CMD23 (1 << 0) /* Auto CMD23 support */
211 #define HSMMC_SDIO_IRQ_ENABLED (1 << 1) /* SDIO irq enabled */
212 struct omap_hsmmc_next next_data;
213 struct omap_hsmmc_platform_data *pdata;
215 /* return MMC cover switch state, can be NULL if not supported.
217 * possible return values:
221 int (*get_cover_state)(struct device *dev);
223 int (*card_detect)(struct device *dev);
226 struct omap_mmc_of_data {
231 static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host);
233 static int omap_hsmmc_card_detect(struct device *dev)
235 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
237 return mmc_gpio_get_cd(host->mmc);
240 static int omap_hsmmc_get_cover_state(struct device *dev)
242 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
244 return mmc_gpio_get_cd(host->mmc);
247 static int omap_hsmmc_enable_supply(struct mmc_host *mmc)
250 struct omap_hsmmc_host *host = mmc_priv(mmc);
251 struct mmc_ios *ios = &mmc->ios;
253 if (mmc->supply.vmmc) {
254 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
259 /* Enable interface voltage rail, if needed */
260 if (mmc->supply.vqmmc && !host->vqmmc_enabled) {
261 ret = regulator_enable(mmc->supply.vqmmc);
263 dev_err(mmc_dev(mmc), "vmmc_aux reg enable failed\n");
266 host->vqmmc_enabled = 1;
272 if (mmc->supply.vmmc)
273 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
278 static int omap_hsmmc_disable_supply(struct mmc_host *mmc)
282 struct omap_hsmmc_host *host = mmc_priv(mmc);
284 if (mmc->supply.vqmmc && host->vqmmc_enabled) {
285 ret = regulator_disable(mmc->supply.vqmmc);
287 dev_err(mmc_dev(mmc), "vmmc_aux reg disable failed\n");
290 host->vqmmc_enabled = 0;
293 if (mmc->supply.vmmc) {
294 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
302 if (mmc->supply.vqmmc) {
303 status = regulator_enable(mmc->supply.vqmmc);
305 dev_err(mmc_dev(mmc), "vmmc_aux re-enable failed\n");
311 static int omap_hsmmc_set_pbias(struct omap_hsmmc_host *host, bool power_on,
320 if (vdd <= VDD_165_195)
321 ret = regulator_set_voltage(host->pbias, VDD_1V8,
324 ret = regulator_set_voltage(host->pbias, VDD_3V0,
327 dev_err(host->dev, "pbias set voltage fail\n");
331 if (host->pbias_enabled == 0) {
332 ret = regulator_enable(host->pbias);
334 dev_err(host->dev, "pbias reg enable fail\n");
337 host->pbias_enabled = 1;
340 if (host->pbias_enabled == 1) {
341 ret = regulator_disable(host->pbias);
343 dev_err(host->dev, "pbias reg disable fail\n");
346 host->pbias_enabled = 0;
353 static int omap_hsmmc_set_power(struct omap_hsmmc_host *host, int power_on,
356 struct mmc_host *mmc = host->mmc;
359 if (mmc_pdata(host)->set_power)
360 return mmc_pdata(host)->set_power(host->dev, power_on, vdd);
363 * If we don't see a Vcc regulator, assume it's a fixed
364 * voltage always-on regulator.
366 if (!mmc->supply.vmmc)
369 if (mmc_pdata(host)->before_set_reg)
370 mmc_pdata(host)->before_set_reg(host->dev, power_on, vdd);
372 ret = omap_hsmmc_set_pbias(host, false, 0);
377 * Assume Vcc regulator is used only to power the card ... OMAP
378 * VDDS is used to power the pins, optionally with a transceiver to
379 * support cards using voltages other than VDDS (1.8V nominal). When a
380 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
382 * In some cases this regulator won't support enable/disable;
383 * e.g. it's a fixed rail for a WLAN chip.
385 * In other cases vcc_aux switches interface power. Example, for
386 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
387 * chips/cards need an interface voltage rail too.
390 ret = omap_hsmmc_enable_supply(mmc);
394 ret = omap_hsmmc_set_pbias(host, true, vdd);
396 goto err_set_voltage;
398 ret = omap_hsmmc_disable_supply(mmc);
403 if (mmc_pdata(host)->after_set_reg)
404 mmc_pdata(host)->after_set_reg(host->dev, power_on, vdd);
409 omap_hsmmc_disable_supply(mmc);
414 static int omap_hsmmc_disable_boot_regulator(struct regulator *reg)
421 if (regulator_is_enabled(reg)) {
422 ret = regulator_enable(reg);
426 ret = regulator_disable(reg);
434 static int omap_hsmmc_disable_boot_regulators(struct omap_hsmmc_host *host)
436 struct mmc_host *mmc = host->mmc;
440 * disable regulators enabled during boot and get the usecount
441 * right so that regulators can be enabled/disabled by checking
442 * the return value of regulator_is_enabled
444 ret = omap_hsmmc_disable_boot_regulator(mmc->supply.vmmc);
446 dev_err(host->dev, "fail to disable boot enabled vmmc reg\n");
450 ret = omap_hsmmc_disable_boot_regulator(mmc->supply.vqmmc);
453 "fail to disable boot enabled vmmc_aux reg\n");
457 ret = omap_hsmmc_disable_boot_regulator(host->pbias);
460 "failed to disable boot enabled pbias reg\n");
467 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
471 struct mmc_host *mmc = host->mmc;
473 if (mmc_pdata(host)->set_power)
476 mmc->supply.vmmc = devm_regulator_get_optional(host->dev, "vmmc");
477 if (IS_ERR(mmc->supply.vmmc)) {
478 ret = PTR_ERR(mmc->supply.vmmc);
479 if ((ret != -ENODEV) && host->dev->of_node)
481 dev_dbg(host->dev, "unable to get vmmc regulator %ld\n",
482 PTR_ERR(mmc->supply.vmmc));
483 mmc->supply.vmmc = NULL;
485 ocr_value = mmc_regulator_get_ocrmask(mmc->supply.vmmc);
487 mmc_pdata(host)->ocr_mask = ocr_value;
490 /* Allow an aux regulator */
491 mmc->supply.vqmmc = devm_regulator_get_optional(host->dev, "vmmc_aux");
492 if (IS_ERR(mmc->supply.vqmmc)) {
493 ret = PTR_ERR(mmc->supply.vqmmc);
494 if ((ret != -ENODEV) && host->dev->of_node)
496 dev_dbg(host->dev, "unable to get vmmc_aux regulator %ld\n",
497 PTR_ERR(mmc->supply.vqmmc));
498 mmc->supply.vqmmc = NULL;
501 host->pbias = devm_regulator_get_optional(host->dev, "pbias");
502 if (IS_ERR(host->pbias)) {
503 ret = PTR_ERR(host->pbias);
504 if ((ret != -ENODEV) && host->dev->of_node) {
506 "SD card detect fail? enable CONFIG_REGULATOR_PBIAS\n");
509 dev_dbg(host->dev, "unable to get pbias regulator %ld\n",
510 PTR_ERR(host->pbias));
514 /* For eMMC do not power off when not in sleep state */
515 if (mmc_pdata(host)->no_regulator_off_init)
518 ret = omap_hsmmc_disable_boot_regulators(host);
525 static irqreturn_t omap_hsmmc_cover_irq(int irq, void *dev_id);
527 static int omap_hsmmc_gpio_init(struct mmc_host *mmc,
528 struct omap_hsmmc_host *host,
529 struct omap_hsmmc_platform_data *pdata)
533 if (gpio_is_valid(pdata->gpio_cod)) {
534 ret = mmc_gpio_request_cd(mmc, pdata->gpio_cod, 0);
538 host->get_cover_state = omap_hsmmc_get_cover_state;
539 mmc_gpio_set_cd_isr(mmc, omap_hsmmc_cover_irq);
540 } else if (gpio_is_valid(pdata->gpio_cd)) {
541 ret = mmc_gpio_request_cd(mmc, pdata->gpio_cd, 0);
545 host->card_detect = omap_hsmmc_card_detect;
548 if (gpio_is_valid(pdata->gpio_wp)) {
549 ret = mmc_gpio_request_ro(mmc, pdata->gpio_wp);
558 * Start clock to the card
560 static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
562 OMAP_HSMMC_WRITE(host->base, SYSCTL,
563 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
567 * Stop clock to the card
569 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
571 OMAP_HSMMC_WRITE(host->base, SYSCTL,
572 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
573 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
574 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n");
577 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
578 struct mmc_command *cmd)
580 u32 irq_mask = INT_EN_MASK;
584 irq_mask &= ~(BRR_EN | BWR_EN);
586 /* Disable timeout for erases */
587 if (cmd->opcode == MMC_ERASE)
590 spin_lock_irqsave(&host->irq_lock, flags);
591 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
592 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
594 /* latch pending CIRQ, but don't signal MMC core */
595 if (host->flags & HSMMC_SDIO_IRQ_ENABLED)
597 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
598 spin_unlock_irqrestore(&host->irq_lock, flags);
601 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
606 spin_lock_irqsave(&host->irq_lock, flags);
607 /* no transfer running but need to keep cirq if enabled */
608 if (host->flags & HSMMC_SDIO_IRQ_ENABLED)
610 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
611 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
612 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
613 spin_unlock_irqrestore(&host->irq_lock, flags);
616 /* Calculate divisor for the given clock frequency */
617 static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
622 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
630 static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
632 struct mmc_ios *ios = &host->mmc->ios;
633 unsigned long regval;
634 unsigned long timeout;
635 unsigned long clkdiv;
637 dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
639 omap_hsmmc_stop_clock(host);
641 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
642 regval = regval & ~(CLKD_MASK | DTO_MASK);
643 clkdiv = calc_divisor(host, ios);
644 regval = regval | (clkdiv << 6) | (DTO << 16);
645 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
646 OMAP_HSMMC_WRITE(host->base, SYSCTL,
647 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
649 /* Wait till the ICS bit is set */
650 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
651 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
652 && time_before(jiffies, timeout))
656 * Enable High-Speed Support
658 * - Controller should support High-Speed-Enable Bit
659 * - Controller should not be using DDR Mode
660 * - Controller should advertise that it supports High Speed
661 * in capabilities register
662 * - MMC/SD clock coming out of controller > 25MHz
664 if ((mmc_pdata(host)->features & HSMMC_HAS_HSPE_SUPPORT) &&
665 (ios->timing != MMC_TIMING_MMC_DDR52) &&
666 (ios->timing != MMC_TIMING_UHS_DDR50) &&
667 ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) {
668 regval = OMAP_HSMMC_READ(host->base, HCTL);
669 if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000)
674 OMAP_HSMMC_WRITE(host->base, HCTL, regval);
677 omap_hsmmc_start_clock(host);
680 static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
682 struct mmc_ios *ios = &host->mmc->ios;
685 con = OMAP_HSMMC_READ(host->base, CON);
686 if (ios->timing == MMC_TIMING_MMC_DDR52 ||
687 ios->timing == MMC_TIMING_UHS_DDR50)
688 con |= DDR; /* configure in DDR mode */
691 switch (ios->bus_width) {
692 case MMC_BUS_WIDTH_8:
693 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
695 case MMC_BUS_WIDTH_4:
696 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
697 OMAP_HSMMC_WRITE(host->base, HCTL,
698 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
700 case MMC_BUS_WIDTH_1:
701 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
702 OMAP_HSMMC_WRITE(host->base, HCTL,
703 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
708 static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
710 struct mmc_ios *ios = &host->mmc->ios;
713 con = OMAP_HSMMC_READ(host->base, CON);
714 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
715 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
717 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
723 * Restore the MMC host context, if it was lost as result of a
724 * power state change.
726 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
728 struct mmc_ios *ios = &host->mmc->ios;
730 unsigned long timeout;
732 if (host->con == OMAP_HSMMC_READ(host->base, CON) &&
733 host->hctl == OMAP_HSMMC_READ(host->base, HCTL) &&
734 host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) &&
735 host->capa == OMAP_HSMMC_READ(host->base, CAPA))
738 host->context_loss++;
740 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
741 if (host->power_mode != MMC_POWER_OFF &&
742 (1 << ios->vdd) <= MMC_VDD_23_24)
752 if (host->mmc->caps & MMC_CAP_SDIO_IRQ)
755 OMAP_HSMMC_WRITE(host->base, HCTL,
756 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
758 OMAP_HSMMC_WRITE(host->base, CAPA,
759 OMAP_HSMMC_READ(host->base, CAPA) | capa);
761 OMAP_HSMMC_WRITE(host->base, HCTL,
762 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
764 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
765 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
766 && time_before(jiffies, timeout))
769 OMAP_HSMMC_WRITE(host->base, ISE, 0);
770 OMAP_HSMMC_WRITE(host->base, IE, 0);
771 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
773 /* Do not initialize card-specific things if the power is off */
774 if (host->power_mode == MMC_POWER_OFF)
777 omap_hsmmc_set_bus_width(host);
779 omap_hsmmc_set_clock(host);
781 omap_hsmmc_set_bus_mode(host);
784 dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n",
790 * Save the MMC host context (store the number of power state changes so far).
792 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
794 host->con = OMAP_HSMMC_READ(host->base, CON);
795 host->hctl = OMAP_HSMMC_READ(host->base, HCTL);
796 host->sysctl = OMAP_HSMMC_READ(host->base, SYSCTL);
797 host->capa = OMAP_HSMMC_READ(host->base, CAPA);
802 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
807 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
814 * Send init stream sequence to card
815 * before sending IDLE command
817 static void send_init_stream(struct omap_hsmmc_host *host)
820 unsigned long timeout;
822 if (host->protect_card)
825 disable_irq(host->irq);
827 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
828 OMAP_HSMMC_WRITE(host->base, CON,
829 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
830 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
832 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
833 while ((reg != CC_EN) && time_before(jiffies, timeout))
834 reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN;
836 OMAP_HSMMC_WRITE(host->base, CON,
837 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
839 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
840 OMAP_HSMMC_READ(host->base, STAT);
842 enable_irq(host->irq);
846 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
850 if (host->get_cover_state)
851 r = host->get_cover_state(host->dev);
856 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
859 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
860 struct omap_hsmmc_host *host = mmc_priv(mmc);
862 return sprintf(buf, "%s\n",
863 omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
866 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
869 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
872 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
873 struct omap_hsmmc_host *host = mmc_priv(mmc);
875 return sprintf(buf, "%s\n", mmc_pdata(host)->name);
878 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
881 * Configure the response type and send the cmd.
884 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
885 struct mmc_data *data)
887 int cmdreg = 0, resptype = 0, cmdtype = 0;
889 dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
890 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
893 omap_hsmmc_enable_irq(host, cmd);
895 host->response_busy = 0;
896 if (cmd->flags & MMC_RSP_PRESENT) {
897 if (cmd->flags & MMC_RSP_136)
899 else if (cmd->flags & MMC_RSP_BUSY) {
901 host->response_busy = 1;
907 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
908 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
909 * a val of 0x3, rest 0x0.
911 if (cmd == host->mrq->stop)
914 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
916 if ((host->flags & AUTO_CMD23) && mmc_op_multi(cmd->opcode) &&
918 cmdreg |= ACEN_ACMD23;
919 OMAP_HSMMC_WRITE(host->base, SDMASA, host->mrq->sbc->arg);
922 cmdreg |= DP_SELECT | MSBS | BCE;
923 if (data->flags & MMC_DATA_READ)
932 host->req_in_progress = 1;
934 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
935 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
939 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
941 if (data->flags & MMC_DATA_WRITE)
942 return DMA_TO_DEVICE;
944 return DMA_FROM_DEVICE;
947 static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host,
948 struct mmc_data *data)
950 return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
953 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
958 spin_lock_irqsave(&host->irq_lock, flags);
959 host->req_in_progress = 0;
960 dma_ch = host->dma_ch;
961 spin_unlock_irqrestore(&host->irq_lock, flags);
963 omap_hsmmc_disable_irq(host);
964 /* Do not complete the request if DMA is still in progress */
965 if (mrq->data && host->use_dma && dma_ch != -1)
968 mmc_request_done(host->mmc, mrq);
972 * Notify the transfer complete to MMC core
975 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
978 struct mmc_request *mrq = host->mrq;
980 /* TC before CC from CMD6 - don't know why, but it happens */
981 if (host->cmd && host->cmd->opcode == 6 &&
982 host->response_busy) {
983 host->response_busy = 0;
987 omap_hsmmc_request_done(host, mrq);
994 data->bytes_xfered += data->blocks * (data->blksz);
996 data->bytes_xfered = 0;
998 if (data->stop && (data->error || !host->mrq->sbc))
999 omap_hsmmc_start_command(host, data->stop, NULL);
1001 omap_hsmmc_request_done(host, data->mrq);
1005 * Notify the core about command completion
1008 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
1010 if (host->mrq->sbc && (host->cmd == host->mrq->sbc) &&
1011 !host->mrq->sbc->error && !(host->flags & AUTO_CMD23)) {
1013 omap_hsmmc_start_dma_transfer(host);
1014 omap_hsmmc_start_command(host, host->mrq->cmd,
1021 if (cmd->flags & MMC_RSP_PRESENT) {
1022 if (cmd->flags & MMC_RSP_136) {
1023 /* response type 2 */
1024 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
1025 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
1026 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
1027 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
1029 /* response types 1, 1b, 3, 4, 5, 6 */
1030 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
1033 if ((host->data == NULL && !host->response_busy) || cmd->error)
1034 omap_hsmmc_request_done(host, host->mrq);
1038 * DMA clean up for command errors
1040 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
1043 unsigned long flags;
1045 host->data->error = errno;
1047 spin_lock_irqsave(&host->irq_lock, flags);
1048 dma_ch = host->dma_ch;
1050 spin_unlock_irqrestore(&host->irq_lock, flags);
1052 if (host->use_dma && dma_ch != -1) {
1053 struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data);
1055 dmaengine_terminate_all(chan);
1056 dma_unmap_sg(chan->device->dev,
1057 host->data->sg, host->data->sg_len,
1058 omap_hsmmc_get_dma_dir(host, host->data));
1060 host->data->host_cookie = 0;
1066 * Readable error output
1068 #ifdef CONFIG_MMC_DEBUG
1069 static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
1071 /* --- means reserved bit without definition at documentation */
1072 static const char *omap_hsmmc_status_bits[] = {
1073 "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
1074 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
1075 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
1076 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
1082 len = sprintf(buf, "MMC IRQ 0x%x :", status);
1085 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
1086 if (status & (1 << i)) {
1087 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
1091 dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
1094 static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
1098 #endif /* CONFIG_MMC_DEBUG */
1101 * MMC controller internal state machines reset
1103 * Used to reset command or data internal state machines, using respectively
1104 * SRC or SRD bit of SYSCTL register
1105 * Can be called from interrupt context
1107 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
1110 unsigned long i = 0;
1111 unsigned long limit = MMC_TIMEOUT_US;
1113 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1114 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
1117 * OMAP4 ES2 and greater has an updated reset logic.
1118 * Monitor a 0->1 transition first
1120 if (mmc_pdata(host)->features & HSMMC_HAS_UPDATED_RESET) {
1121 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
1127 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
1131 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
1132 dev_err(mmc_dev(host->mmc),
1133 "Timeout waiting on controller reset in %s\n",
1137 static void hsmmc_command_incomplete(struct omap_hsmmc_host *host,
1138 int err, int end_cmd)
1141 omap_hsmmc_reset_controller_fsm(host, SRC);
1143 host->cmd->error = err;
1147 omap_hsmmc_reset_controller_fsm(host, SRD);
1148 omap_hsmmc_dma_cleanup(host, err);
1149 } else if (host->mrq && host->mrq->cmd)
1150 host->mrq->cmd->error = err;
1153 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
1155 struct mmc_data *data;
1156 int end_cmd = 0, end_trans = 0;
1160 dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1162 if (status & ERR_EN) {
1163 omap_hsmmc_dbg_report_irq(host, status);
1165 if (status & (CTO_EN | CCRC_EN))
1167 if (host->data || host->response_busy) {
1168 end_trans = !end_cmd;
1169 host->response_busy = 0;
1171 if (status & (CTO_EN | DTO_EN))
1172 hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd);
1173 else if (status & (CCRC_EN | DCRC_EN | DEB_EN | CEB_EN |
1175 hsmmc_command_incomplete(host, -EILSEQ, end_cmd);
1177 if (status & ACE_EN) {
1179 ac12 = OMAP_HSMMC_READ(host->base, AC12);
1180 if (!(ac12 & ACNE) && host->mrq->sbc) {
1184 else if (ac12 & (ACCE | ACEB | ACIE))
1186 host->mrq->sbc->error = error;
1187 hsmmc_command_incomplete(host, error, end_cmd);
1189 dev_dbg(mmc_dev(host->mmc), "AC12 err: 0x%x\n", ac12);
1193 OMAP_HSMMC_WRITE(host->base, STAT, status);
1194 if (end_cmd || ((status & CC_EN) && host->cmd))
1195 omap_hsmmc_cmd_done(host, host->cmd);
1196 if ((end_trans || (status & TC_EN)) && host->mrq)
1197 omap_hsmmc_xfer_done(host, data);
1201 * MMC controller IRQ handler
1203 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1205 struct omap_hsmmc_host *host = dev_id;
1208 status = OMAP_HSMMC_READ(host->base, STAT);
1209 while (status & (INT_EN_MASK | CIRQ_EN)) {
1210 if (host->req_in_progress)
1211 omap_hsmmc_do_irq(host, status);
1213 if (status & CIRQ_EN)
1214 mmc_signal_sdio_irq(host->mmc);
1216 /* Flush posted write */
1217 status = OMAP_HSMMC_READ(host->base, STAT);
1223 static void set_sd_bus_power(struct omap_hsmmc_host *host)
1227 OMAP_HSMMC_WRITE(host->base, HCTL,
1228 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1229 for (i = 0; i < loops_per_jiffy; i++) {
1230 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1237 * Switch MMC interface voltage ... only relevant for MMC1.
1239 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1240 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1241 * Some chips, like eMMC ones, use internal transceivers.
1243 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1248 /* Disable the clocks */
1250 clk_disable_unprepare(host->dbclk);
1252 /* Turn the power off */
1253 ret = omap_hsmmc_set_power(host, 0, 0);
1255 /* Turn the power ON with given VDD 1.8 or 3.0v */
1257 ret = omap_hsmmc_set_power(host, 1, vdd);
1259 clk_prepare_enable(host->dbclk);
1264 OMAP_HSMMC_WRITE(host->base, HCTL,
1265 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1266 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1269 * If a MMC dual voltage card is detected, the set_ios fn calls
1270 * this fn with VDD bit set for 1.8V. Upon card removal from the
1271 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1273 * Cope with a bit of slop in the range ... per data sheets:
1274 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1275 * but recommended values are 1.71V to 1.89V
1276 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1277 * but recommended values are 2.7V to 3.3V
1279 * Board setup code shouldn't permit anything very out-of-range.
1280 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1281 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1283 if ((1 << vdd) <= MMC_VDD_23_24)
1288 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1289 set_sd_bus_power(host);
1293 dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1297 /* Protect the card while the cover is open */
1298 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1300 if (!host->get_cover_state)
1303 host->reqs_blocked = 0;
1304 if (host->get_cover_state(host->dev)) {
1305 if (host->protect_card) {
1306 dev_info(host->dev, "%s: cover is closed, "
1307 "card is now accessible\n",
1308 mmc_hostname(host->mmc));
1309 host->protect_card = 0;
1312 if (!host->protect_card) {
1313 dev_info(host->dev, "%s: cover is open, "
1314 "card is now inaccessible\n",
1315 mmc_hostname(host->mmc));
1316 host->protect_card = 1;
1322 * irq handler when (cell-phone) cover is mounted/removed
1324 static irqreturn_t omap_hsmmc_cover_irq(int irq, void *dev_id)
1326 struct omap_hsmmc_host *host = dev_id;
1328 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
1330 omap_hsmmc_protect_card(host);
1331 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
1335 static void omap_hsmmc_dma_callback(void *param)
1337 struct omap_hsmmc_host *host = param;
1338 struct dma_chan *chan;
1339 struct mmc_data *data;
1340 int req_in_progress;
1342 spin_lock_irq(&host->irq_lock);
1343 if (host->dma_ch < 0) {
1344 spin_unlock_irq(&host->irq_lock);
1348 data = host->mrq->data;
1349 chan = omap_hsmmc_get_dma_chan(host, data);
1350 if (!data->host_cookie)
1351 dma_unmap_sg(chan->device->dev,
1352 data->sg, data->sg_len,
1353 omap_hsmmc_get_dma_dir(host, data));
1355 req_in_progress = host->req_in_progress;
1357 spin_unlock_irq(&host->irq_lock);
1359 /* If DMA has finished after TC, complete the request */
1360 if (!req_in_progress) {
1361 struct mmc_request *mrq = host->mrq;
1364 mmc_request_done(host->mmc, mrq);
1368 static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1369 struct mmc_data *data,
1370 struct omap_hsmmc_next *next,
1371 struct dma_chan *chan)
1375 if (!next && data->host_cookie &&
1376 data->host_cookie != host->next_data.cookie) {
1377 dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d"
1378 " host->next_data.cookie %d\n",
1379 __func__, data->host_cookie, host->next_data.cookie);
1380 data->host_cookie = 0;
1383 /* Check if next job is already prepared */
1384 if (next || data->host_cookie != host->next_data.cookie) {
1385 dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len,
1386 omap_hsmmc_get_dma_dir(host, data));
1389 dma_len = host->next_data.dma_len;
1390 host->next_data.dma_len = 0;
1398 next->dma_len = dma_len;
1399 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1401 host->dma_len = dma_len;
1407 * Routine to configure and start DMA for the MMC card
1409 static int omap_hsmmc_setup_dma_transfer(struct omap_hsmmc_host *host,
1410 struct mmc_request *req)
1412 struct dma_async_tx_descriptor *tx;
1414 struct mmc_data *data = req->data;
1415 struct dma_chan *chan;
1416 struct dma_slave_config cfg = {
1417 .src_addr = host->mapbase + OMAP_HSMMC_DATA,
1418 .dst_addr = host->mapbase + OMAP_HSMMC_DATA,
1419 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
1420 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
1421 .src_maxburst = data->blksz / 4,
1422 .dst_maxburst = data->blksz / 4,
1425 /* Sanity check: all the SG entries must be aligned by block size. */
1426 for (i = 0; i < data->sg_len; i++) {
1427 struct scatterlist *sgl;
1430 if (sgl->length % data->blksz)
1433 if ((data->blksz % 4) != 0)
1434 /* REVISIT: The MMC buffer increments only when MSB is written.
1435 * Return error for blksz which is non multiple of four.
1439 BUG_ON(host->dma_ch != -1);
1441 chan = omap_hsmmc_get_dma_chan(host, data);
1443 ret = dmaengine_slave_config(chan, &cfg);
1447 ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan);
1451 tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len,
1452 data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
1453 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1455 dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n");
1456 /* FIXME: cleanup */
1460 tx->callback = omap_hsmmc_dma_callback;
1461 tx->callback_param = host;
1464 dmaengine_submit(tx);
1471 static void set_data_timeout(struct omap_hsmmc_host *host,
1472 unsigned int timeout_ns,
1473 unsigned int timeout_clks)
1475 unsigned int timeout, cycle_ns;
1476 uint32_t reg, clkd, dto = 0;
1478 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1479 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1483 cycle_ns = 1000000000 / (host->clk_rate / clkd);
1484 timeout = timeout_ns / cycle_ns;
1485 timeout += timeout_clks;
1487 while ((timeout & 0x80000000) == 0) {
1504 reg |= dto << DTO_SHIFT;
1505 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1508 static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host)
1510 struct mmc_request *req = host->mrq;
1511 struct dma_chan *chan;
1515 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1516 | (req->data->blocks << 16));
1517 set_data_timeout(host, req->data->timeout_ns,
1518 req->data->timeout_clks);
1519 chan = omap_hsmmc_get_dma_chan(host, req->data);
1520 dma_async_issue_pending(chan);
1524 * Configure block length for MMC/SD cards and initiate the transfer.
1527 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1530 host->data = req->data;
1532 if (req->data == NULL) {
1533 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1535 * Set an arbitrary 100ms data timeout for commands with
1538 if (req->cmd->flags & MMC_RSP_BUSY)
1539 set_data_timeout(host, 100000000U, 0);
1543 if (host->use_dma) {
1544 ret = omap_hsmmc_setup_dma_transfer(host, req);
1546 dev_err(mmc_dev(host->mmc), "MMC start dma failure\n");
1553 static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1556 struct omap_hsmmc_host *host = mmc_priv(mmc);
1557 struct mmc_data *data = mrq->data;
1559 if (host->use_dma && data->host_cookie) {
1560 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data);
1562 dma_unmap_sg(c->device->dev, data->sg, data->sg_len,
1563 omap_hsmmc_get_dma_dir(host, data));
1564 data->host_cookie = 0;
1568 static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1571 struct omap_hsmmc_host *host = mmc_priv(mmc);
1573 if (mrq->data->host_cookie) {
1574 mrq->data->host_cookie = 0;
1578 if (host->use_dma) {
1579 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data);
1581 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1582 &host->next_data, c))
1583 mrq->data->host_cookie = 0;
1588 * Request function. for read/write operation
1590 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1592 struct omap_hsmmc_host *host = mmc_priv(mmc);
1595 BUG_ON(host->req_in_progress);
1596 BUG_ON(host->dma_ch != -1);
1597 if (host->protect_card) {
1598 if (host->reqs_blocked < 3) {
1600 * Ensure the controller is left in a consistent
1601 * state by resetting the command and data state
1604 omap_hsmmc_reset_controller_fsm(host, SRD);
1605 omap_hsmmc_reset_controller_fsm(host, SRC);
1606 host->reqs_blocked += 1;
1608 req->cmd->error = -EBADF;
1610 req->data->error = -EBADF;
1611 req->cmd->retries = 0;
1612 mmc_request_done(mmc, req);
1614 } else if (host->reqs_blocked)
1615 host->reqs_blocked = 0;
1616 WARN_ON(host->mrq != NULL);
1618 host->clk_rate = clk_get_rate(host->fclk);
1619 err = omap_hsmmc_prepare_data(host, req);
1621 req->cmd->error = err;
1623 req->data->error = err;
1625 mmc_request_done(mmc, req);
1628 if (req->sbc && !(host->flags & AUTO_CMD23)) {
1629 omap_hsmmc_start_command(host, req->sbc, NULL);
1633 omap_hsmmc_start_dma_transfer(host);
1634 omap_hsmmc_start_command(host, req->cmd, req->data);
1637 /* Routine to configure clock values. Exposed API to core */
1638 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1640 struct omap_hsmmc_host *host = mmc_priv(mmc);
1641 int do_send_init_stream = 0;
1643 if (ios->power_mode != host->power_mode) {
1644 switch (ios->power_mode) {
1646 omap_hsmmc_set_power(host, 0, 0);
1649 omap_hsmmc_set_power(host, 1, ios->vdd);
1652 do_send_init_stream = 1;
1655 host->power_mode = ios->power_mode;
1658 /* FIXME: set registers based only on changes to ios */
1660 omap_hsmmc_set_bus_width(host);
1662 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1663 /* Only MMC1 can interface at 3V without some flavor
1664 * of external transceiver; but they all handle 1.8V.
1666 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1667 (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1669 * The mmc_select_voltage fn of the core does
1670 * not seem to set the power_mode to
1671 * MMC_POWER_UP upon recalculating the voltage.
1674 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1675 dev_dbg(mmc_dev(host->mmc),
1676 "Switch operation failed\n");
1680 omap_hsmmc_set_clock(host);
1682 if (do_send_init_stream)
1683 send_init_stream(host);
1685 omap_hsmmc_set_bus_mode(host);
1688 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1690 struct omap_hsmmc_host *host = mmc_priv(mmc);
1692 if (!host->card_detect)
1694 return host->card_detect(host->dev);
1697 static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1699 struct omap_hsmmc_host *host = mmc_priv(mmc);
1701 if (mmc_pdata(host)->init_card)
1702 mmc_pdata(host)->init_card(card);
1703 else if (card->type == MMC_TYPE_SDIO ||
1704 card->type == MMC_TYPE_SD_COMBO) {
1705 struct device_node *np = mmc_dev(mmc)->of_node;
1708 * REVISIT: should be moved to sdio core and made more
1709 * general e.g. by expanding the DT bindings of child nodes
1710 * to provide a mechanism to provide this information:
1711 * Documentation/devicetree/bindings/mmc/mmc-card.txt
1714 np = of_get_compatible_child(np, "ti,wl1251");
1717 * We have TI wl1251 attached to MMC3. Pass this
1718 * information to the SDIO core because it can't be
1719 * probed by normal methods.
1722 dev_info(host->dev, "found wl1251\n");
1723 card->quirks |= MMC_QUIRK_NONSTD_SDIO;
1724 card->cccr.wide_bus = 1;
1725 card->cis.vendor = 0x104c;
1726 card->cis.device = 0x9066;
1727 card->cis.blksize = 512;
1728 card->cis.max_dtr = 24000000;
1735 static void omap_hsmmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
1737 struct omap_hsmmc_host *host = mmc_priv(mmc);
1739 unsigned long flags;
1741 spin_lock_irqsave(&host->irq_lock, flags);
1743 con = OMAP_HSMMC_READ(host->base, CON);
1744 irq_mask = OMAP_HSMMC_READ(host->base, ISE);
1746 host->flags |= HSMMC_SDIO_IRQ_ENABLED;
1747 irq_mask |= CIRQ_EN;
1748 con |= CTPL | CLKEXTFREE;
1750 host->flags &= ~HSMMC_SDIO_IRQ_ENABLED;
1751 irq_mask &= ~CIRQ_EN;
1752 con &= ~(CTPL | CLKEXTFREE);
1754 OMAP_HSMMC_WRITE(host->base, CON, con);
1755 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
1758 * if enable, piggy back detection on current request
1759 * but always disable immediately
1761 if (!host->req_in_progress || !enable)
1762 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
1764 /* flush posted write */
1765 OMAP_HSMMC_READ(host->base, IE);
1767 spin_unlock_irqrestore(&host->irq_lock, flags);
1770 static int omap_hsmmc_configure_wake_irq(struct omap_hsmmc_host *host)
1775 * For omaps with wake-up path, wakeirq will be irq from pinctrl and
1776 * for other omaps, wakeirq will be from GPIO (dat line remuxed to
1777 * gpio). wakeirq is needed to detect sdio irq in runtime suspend state
1778 * with functional clock disabled.
1780 if (!host->dev->of_node || !host->wake_irq)
1783 ret = dev_pm_set_dedicated_wake_irq(host->dev, host->wake_irq);
1785 dev_err(mmc_dev(host->mmc), "Unable to request wake IRQ\n");
1790 * Some omaps don't have wake-up path from deeper idle states
1791 * and need to remux SDIO DAT1 to GPIO for wake-up from idle.
1793 if (host->pdata->controller_flags & OMAP_HSMMC_SWAKEUP_MISSING) {
1794 struct pinctrl *p = devm_pinctrl_get(host->dev);
1799 if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_DEFAULT))) {
1800 dev_info(host->dev, "missing default pinctrl state\n");
1801 devm_pinctrl_put(p);
1806 if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_IDLE))) {
1807 dev_info(host->dev, "missing idle pinctrl state\n");
1808 devm_pinctrl_put(p);
1812 devm_pinctrl_put(p);
1815 OMAP_HSMMC_WRITE(host->base, HCTL,
1816 OMAP_HSMMC_READ(host->base, HCTL) | IWE);
1820 dev_pm_clear_wake_irq(host->dev);
1822 dev_warn(host->dev, "no SDIO IRQ support, falling back to polling\n");
1827 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1829 u32 hctl, capa, value;
1831 /* Only MMC1 supports 3.0V */
1832 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1840 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1841 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1843 value = OMAP_HSMMC_READ(host->base, CAPA);
1844 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1846 /* Set SD bus power bit */
1847 set_sd_bus_power(host);
1850 static int omap_hsmmc_multi_io_quirk(struct mmc_card *card,
1851 unsigned int direction, int blk_size)
1853 /* This controller can't do multiblock reads due to hw bugs */
1854 if (direction == MMC_DATA_READ)
1860 static struct mmc_host_ops omap_hsmmc_ops = {
1861 .post_req = omap_hsmmc_post_req,
1862 .pre_req = omap_hsmmc_pre_req,
1863 .request = omap_hsmmc_request,
1864 .set_ios = omap_hsmmc_set_ios,
1865 .get_cd = omap_hsmmc_get_cd,
1866 .get_ro = mmc_gpio_get_ro,
1867 .init_card = omap_hsmmc_init_card,
1868 .enable_sdio_irq = omap_hsmmc_enable_sdio_irq,
1871 #ifdef CONFIG_DEBUG_FS
1873 static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
1875 struct mmc_host *mmc = s->private;
1876 struct omap_hsmmc_host *host = mmc_priv(mmc);
1878 seq_printf(s, "mmc%d:\n", mmc->index);
1879 seq_printf(s, "sdio irq mode\t%s\n",
1880 (mmc->caps & MMC_CAP_SDIO_IRQ) ? "interrupt" : "polling");
1882 if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1883 seq_printf(s, "sdio irq \t%s\n",
1884 (host->flags & HSMMC_SDIO_IRQ_ENABLED) ? "enabled"
1887 seq_printf(s, "ctx_loss:\t%d\n", host->context_loss);
1889 pm_runtime_get_sync(host->dev);
1890 seq_puts(s, "\nregs:\n");
1891 seq_printf(s, "CON:\t\t0x%08x\n",
1892 OMAP_HSMMC_READ(host->base, CON));
1893 seq_printf(s, "PSTATE:\t\t0x%08x\n",
1894 OMAP_HSMMC_READ(host->base, PSTATE));
1895 seq_printf(s, "HCTL:\t\t0x%08x\n",
1896 OMAP_HSMMC_READ(host->base, HCTL));
1897 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1898 OMAP_HSMMC_READ(host->base, SYSCTL));
1899 seq_printf(s, "IE:\t\t0x%08x\n",
1900 OMAP_HSMMC_READ(host->base, IE));
1901 seq_printf(s, "ISE:\t\t0x%08x\n",
1902 OMAP_HSMMC_READ(host->base, ISE));
1903 seq_printf(s, "CAPA:\t\t0x%08x\n",
1904 OMAP_HSMMC_READ(host->base, CAPA));
1906 pm_runtime_mark_last_busy(host->dev);
1907 pm_runtime_put_autosuspend(host->dev);
1912 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
1914 return single_open(file, omap_hsmmc_regs_show, inode->i_private);
1917 static const struct file_operations mmc_regs_fops = {
1918 .open = omap_hsmmc_regs_open,
1920 .llseek = seq_lseek,
1921 .release = single_release,
1924 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1926 if (mmc->debugfs_root)
1927 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1928 mmc, &mmc_regs_fops);
1933 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1940 static const struct omap_mmc_of_data omap3_pre_es3_mmc_of_data = {
1941 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1942 .controller_flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1945 static const struct omap_mmc_of_data omap4_mmc_of_data = {
1946 .reg_offset = 0x100,
1948 static const struct omap_mmc_of_data am33xx_mmc_of_data = {
1949 .reg_offset = 0x100,
1950 .controller_flags = OMAP_HSMMC_SWAKEUP_MISSING,
1953 static const struct of_device_id omap_mmc_of_match[] = {
1955 .compatible = "ti,omap2-hsmmc",
1958 .compatible = "ti,omap3-pre-es3-hsmmc",
1959 .data = &omap3_pre_es3_mmc_of_data,
1962 .compatible = "ti,omap3-hsmmc",
1965 .compatible = "ti,omap4-hsmmc",
1966 .data = &omap4_mmc_of_data,
1969 .compatible = "ti,am33xx-hsmmc",
1970 .data = &am33xx_mmc_of_data,
1974 MODULE_DEVICE_TABLE(of, omap_mmc_of_match);
1976 static struct omap_hsmmc_platform_data *of_get_hsmmc_pdata(struct device *dev)
1978 struct omap_hsmmc_platform_data *pdata, *legacy;
1979 struct device_node *np = dev->of_node;
1981 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
1983 return ERR_PTR(-ENOMEM); /* out of memory */
1985 legacy = dev_get_platdata(dev);
1986 if (legacy && legacy->name)
1987 pdata->name = legacy->name;
1989 if (of_find_property(np, "ti,dual-volt", NULL))
1990 pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1992 pdata->gpio_cd = -EINVAL;
1993 pdata->gpio_cod = -EINVAL;
1994 pdata->gpio_wp = -EINVAL;
1996 if (of_find_property(np, "ti,non-removable", NULL)) {
1997 pdata->nonremovable = true;
1998 pdata->no_regulator_off_init = true;
2001 if (of_find_property(np, "ti,needs-special-reset", NULL))
2002 pdata->features |= HSMMC_HAS_UPDATED_RESET;
2004 if (of_find_property(np, "ti,needs-special-hs-handling", NULL))
2005 pdata->features |= HSMMC_HAS_HSPE_SUPPORT;
2010 static inline struct omap_hsmmc_platform_data
2011 *of_get_hsmmc_pdata(struct device *dev)
2013 return ERR_PTR(-EINVAL);
2017 static int omap_hsmmc_probe(struct platform_device *pdev)
2019 struct omap_hsmmc_platform_data *pdata = pdev->dev.platform_data;
2020 struct mmc_host *mmc;
2021 struct omap_hsmmc_host *host = NULL;
2022 struct resource *res;
2024 const struct of_device_id *match;
2025 const struct omap_mmc_of_data *data;
2028 match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev);
2030 pdata = of_get_hsmmc_pdata(&pdev->dev);
2033 return PTR_ERR(pdata);
2037 pdata->reg_offset = data->reg_offset;
2038 pdata->controller_flags |= data->controller_flags;
2042 if (pdata == NULL) {
2043 dev_err(&pdev->dev, "Platform Data is missing\n");
2047 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2048 irq = platform_get_irq(pdev, 0);
2049 if (res == NULL || irq < 0)
2052 base = devm_ioremap_resource(&pdev->dev, res);
2054 return PTR_ERR(base);
2056 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
2062 ret = mmc_of_parse(mmc);
2066 host = mmc_priv(mmc);
2068 host->pdata = pdata;
2069 host->dev = &pdev->dev;
2073 host->mapbase = res->start + pdata->reg_offset;
2074 host->base = base + pdata->reg_offset;
2075 host->power_mode = MMC_POWER_OFF;
2076 host->next_data.cookie = 1;
2077 host->pbias_enabled = 0;
2078 host->vqmmc_enabled = 0;
2080 ret = omap_hsmmc_gpio_init(mmc, host, pdata);
2084 platform_set_drvdata(pdev, host);
2086 if (pdev->dev.of_node)
2087 host->wake_irq = irq_of_parse_and_map(pdev->dev.of_node, 1);
2089 mmc->ops = &omap_hsmmc_ops;
2091 mmc->f_min = OMAP_MMC_MIN_CLOCK;
2093 if (pdata->max_freq > 0)
2094 mmc->f_max = pdata->max_freq;
2095 else if (mmc->f_max == 0)
2096 mmc->f_max = OMAP_MMC_MAX_CLOCK;
2098 spin_lock_init(&host->irq_lock);
2100 host->fclk = devm_clk_get(&pdev->dev, "fck");
2101 if (IS_ERR(host->fclk)) {
2102 ret = PTR_ERR(host->fclk);
2107 if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
2108 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
2109 omap_hsmmc_ops.multi_io_quirk = omap_hsmmc_multi_io_quirk;
2112 device_init_wakeup(&pdev->dev, true);
2113 pm_runtime_enable(host->dev);
2114 pm_runtime_get_sync(host->dev);
2115 pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
2116 pm_runtime_use_autosuspend(host->dev);
2118 omap_hsmmc_context_save(host);
2120 host->dbclk = devm_clk_get(&pdev->dev, "mmchsdb_fck");
2122 * MMC can still work without debounce clock.
2124 if (IS_ERR(host->dbclk)) {
2126 } else if (clk_prepare_enable(host->dbclk) != 0) {
2127 dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n");
2131 /* Since we do only SG emulation, we can have as many segs
2133 mmc->max_segs = 1024;
2135 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
2136 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
2137 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2139 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
2140 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
2142 mmc->caps |= mmc_pdata(host)->caps;
2143 if (mmc->caps & MMC_CAP_8_BIT_DATA)
2144 mmc->caps |= MMC_CAP_4_BIT_DATA;
2146 if (mmc_pdata(host)->nonremovable)
2147 mmc->caps |= MMC_CAP_NONREMOVABLE;
2149 mmc->pm_caps |= mmc_pdata(host)->pm_caps;
2151 omap_hsmmc_conf_bus_power(host);
2153 host->rx_chan = dma_request_chan(&pdev->dev, "rx");
2154 if (IS_ERR(host->rx_chan)) {
2155 dev_err(mmc_dev(host->mmc), "RX DMA channel request failed\n");
2156 ret = PTR_ERR(host->rx_chan);
2160 host->tx_chan = dma_request_chan(&pdev->dev, "tx");
2161 if (IS_ERR(host->tx_chan)) {
2162 dev_err(mmc_dev(host->mmc), "TX DMA channel request failed\n");
2163 ret = PTR_ERR(host->tx_chan);
2168 * Limit the maximum segment size to the lower of the request size
2169 * and the DMA engine device segment size limits. In reality, with
2170 * 32-bit transfers, the DMA engine can do longer segments than this
2171 * but there is no way to represent that in the DMA model - if we
2172 * increase this figure here, we get warnings from the DMA API debug.
2174 mmc->max_seg_size = min3(mmc->max_req_size,
2175 dma_get_max_seg_size(host->rx_chan->device->dev),
2176 dma_get_max_seg_size(host->tx_chan->device->dev));
2178 /* Request IRQ for MMC operations */
2179 ret = devm_request_irq(&pdev->dev, host->irq, omap_hsmmc_irq, 0,
2180 mmc_hostname(mmc), host);
2182 dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
2186 ret = omap_hsmmc_reg_get(host);
2190 mmc->ocr_avail = mmc_pdata(host)->ocr_mask;
2192 omap_hsmmc_disable_irq(host);
2195 * For now, only support SDIO interrupt if we have a separate
2196 * wake-up interrupt configured from device tree. This is because
2197 * the wake-up interrupt is needed for idle state and some
2198 * platforms need special quirks. And we don't want to add new
2199 * legacy mux platform init code callbacks any longer as we
2200 * are moving to DT based booting anyways.
2202 ret = omap_hsmmc_configure_wake_irq(host);
2204 mmc->caps |= MMC_CAP_SDIO_IRQ;
2206 omap_hsmmc_protect_card(host);
2210 if (mmc_pdata(host)->name != NULL) {
2211 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
2215 if (host->get_cover_state) {
2216 ret = device_create_file(&mmc->class_dev,
2217 &dev_attr_cover_switch);
2222 omap_hsmmc_debugfs(mmc);
2223 pm_runtime_mark_last_busy(host->dev);
2224 pm_runtime_put_autosuspend(host->dev);
2229 mmc_remove_host(mmc);
2231 device_init_wakeup(&pdev->dev, false);
2232 if (!IS_ERR_OR_NULL(host->tx_chan))
2233 dma_release_channel(host->tx_chan);
2234 if (!IS_ERR_OR_NULL(host->rx_chan))
2235 dma_release_channel(host->rx_chan);
2236 pm_runtime_dont_use_autosuspend(host->dev);
2237 pm_runtime_put_sync(host->dev);
2238 pm_runtime_disable(host->dev);
2240 clk_disable_unprepare(host->dbclk);
2248 static int omap_hsmmc_remove(struct platform_device *pdev)
2250 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2252 pm_runtime_get_sync(host->dev);
2253 mmc_remove_host(host->mmc);
2255 dma_release_channel(host->tx_chan);
2256 dma_release_channel(host->rx_chan);
2258 dev_pm_clear_wake_irq(host->dev);
2259 pm_runtime_dont_use_autosuspend(host->dev);
2260 pm_runtime_put_sync(host->dev);
2261 pm_runtime_disable(host->dev);
2262 device_init_wakeup(&pdev->dev, false);
2264 clk_disable_unprepare(host->dbclk);
2266 mmc_free_host(host->mmc);
2271 #ifdef CONFIG_PM_SLEEP
2272 static int omap_hsmmc_suspend(struct device *dev)
2274 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2279 pm_runtime_get_sync(host->dev);
2281 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
2282 OMAP_HSMMC_WRITE(host->base, ISE, 0);
2283 OMAP_HSMMC_WRITE(host->base, IE, 0);
2284 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2285 OMAP_HSMMC_WRITE(host->base, HCTL,
2286 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2290 clk_disable_unprepare(host->dbclk);
2292 pm_runtime_put_sync(host->dev);
2296 /* Routine to resume the MMC device */
2297 static int omap_hsmmc_resume(struct device *dev)
2299 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2304 pm_runtime_get_sync(host->dev);
2307 clk_prepare_enable(host->dbclk);
2309 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
2310 omap_hsmmc_conf_bus_power(host);
2312 omap_hsmmc_protect_card(host);
2313 pm_runtime_mark_last_busy(host->dev);
2314 pm_runtime_put_autosuspend(host->dev);
2319 static int omap_hsmmc_runtime_suspend(struct device *dev)
2321 struct omap_hsmmc_host *host;
2322 unsigned long flags;
2325 host = platform_get_drvdata(to_platform_device(dev));
2326 omap_hsmmc_context_save(host);
2327 dev_dbg(dev, "disabled\n");
2329 spin_lock_irqsave(&host->irq_lock, flags);
2330 if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2331 (host->flags & HSMMC_SDIO_IRQ_ENABLED)) {
2332 /* disable sdio irq handling to prevent race */
2333 OMAP_HSMMC_WRITE(host->base, ISE, 0);
2334 OMAP_HSMMC_WRITE(host->base, IE, 0);
2336 if (!(OMAP_HSMMC_READ(host->base, PSTATE) & DLEV_DAT(1))) {
2338 * dat1 line low, pending sdio irq
2339 * race condition: possible irq handler running on
2342 dev_dbg(dev, "pending sdio irq, abort suspend\n");
2343 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2344 OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN);
2345 OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN);
2346 pm_runtime_mark_last_busy(dev);
2351 pinctrl_pm_select_idle_state(dev);
2353 pinctrl_pm_select_idle_state(dev);
2357 spin_unlock_irqrestore(&host->irq_lock, flags);
2361 static int omap_hsmmc_runtime_resume(struct device *dev)
2363 struct omap_hsmmc_host *host;
2364 unsigned long flags;
2366 host = platform_get_drvdata(to_platform_device(dev));
2367 omap_hsmmc_context_restore(host);
2368 dev_dbg(dev, "enabled\n");
2370 spin_lock_irqsave(&host->irq_lock, flags);
2371 if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2372 (host->flags & HSMMC_SDIO_IRQ_ENABLED)) {
2374 pinctrl_pm_select_default_state(host->dev);
2376 /* irq lost, if pinmux incorrect */
2377 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2378 OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN);
2379 OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN);
2381 pinctrl_pm_select_default_state(host->dev);
2383 spin_unlock_irqrestore(&host->irq_lock, flags);
2387 static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
2388 SET_SYSTEM_SLEEP_PM_OPS(omap_hsmmc_suspend, omap_hsmmc_resume)
2389 .runtime_suspend = omap_hsmmc_runtime_suspend,
2390 .runtime_resume = omap_hsmmc_runtime_resume,
2393 static struct platform_driver omap_hsmmc_driver = {
2394 .probe = omap_hsmmc_probe,
2395 .remove = omap_hsmmc_remove,
2397 .name = DRIVER_NAME,
2398 .pm = &omap_hsmmc_dev_pm_ops,
2399 .of_match_table = of_match_ptr(omap_mmc_of_match),
2403 module_platform_driver(omap_hsmmc_driver);
2404 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2405 MODULE_LICENSE("GPL");
2406 MODULE_ALIAS("platform:" DRIVER_NAME);
2407 MODULE_AUTHOR("Texas Instruments Inc");