drivers/mmc/host/omap_hsmmc.c

   1 /*
   2  * drivers/mmc/host/omap_hsmmc.c
   3  *
   4  * Driver for OMAP2430/3430 MMC controller.
   5  *
   6  * Copyright (C) 2007 Texas Instruments.
   7  *
   8  * Authors:
   9  *      Syed Mohammed Khasim    <x0khasim@ti.com>
  10  *      Madhusudhan             <madhu.cr@ti.com>
  11  *      Mohit Jalori            <mjalori@ti.com>
  12  *
  13  * This file is licensed under the terms of the GNU General Public License
  14  * version 2. This program is licensed "as is" without any warranty of any
  15  * kind, whether express or implied.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/init.h>
  20 #include <linux/kernel.h>
  21 #include <linux/debugfs.h>
  22 #include <linux/dmaengine.h>
  23 #include <linux/seq_file.h>
  24 #include <linux/sizes.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/delay.h>
  27 #include <linux/dma-mapping.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/timer.h>
  30 #include <linux/clk.h>
  31 #include <linux/of.h>
  32 #include <linux/of_irq.h>
  33 #include <linux/of_gpio.h>
  34 #include <linux/of_device.h>
  35 #include <linux/mmc/host.h>
  36 #include <linux/mmc/core.h>
  37 #include <linux/mmc/mmc.h>
  38 #include <linux/mmc/slot-gpio.h>
  39 #include <linux/io.h>
  40 #include <linux/irq.h>
  41 #include <linux/gpio.h>
  42 #include <linux/regulator/consumer.h>
  43 #include <linux/pinctrl/consumer.h>
  44 #include <linux/pm_runtime.h>
  45 #include <linux/pm_wakeirq.h>
  46 #include <linux/platform_data/hsmmc-omap.h>
  47
  48 /* OMAP HSMMC Host Controller Registers */
  49 #define OMAP_HSMMC_SYSSTATUS    0x0014
  50 #define OMAP_HSMMC_CON          0x002C
  51 #define OMAP_HSMMC_SDMASA       0x0100
  52 #define OMAP_HSMMC_BLK          0x0104
  53 #define OMAP_HSMMC_ARG          0x0108
  54 #define OMAP_HSMMC_CMD          0x010C
  55 #define OMAP_HSMMC_RSP10        0x0110
  56 #define OMAP_HSMMC_RSP32        0x0114
  57 #define OMAP_HSMMC_RSP54        0x0118
  58 #define OMAP_HSMMC_RSP76        0x011C
  59 #define OMAP_HSMMC_DATA         0x0120
  60 #define OMAP_HSMMC_PSTATE       0x0124
  61 #define OMAP_HSMMC_HCTL         0x0128
  62 #define OMAP_HSMMC_SYSCTL       0x012C
  63 #define OMAP_HSMMC_STAT         0x0130
  64 #define OMAP_HSMMC_IE           0x0134
  65 #define OMAP_HSMMC_ISE          0x0138
  66 #define OMAP_HSMMC_AC12         0x013C
  67 #define OMAP_HSMMC_CAPA         0x0140
  68
  69 #define VS18                    (1 << 26)
  70 #define VS30                    (1 << 25)
  71 #define HSS                     (1 << 21)
  72 #define SDVS18                  (0x5 << 9)
  73 #define SDVS30                  (0x6 << 9)
  74 #define SDVS33                  (0x7 << 9)
  75 #define SDVS_MASK               0x00000E00
  76 #define SDVSCLR                 0xFFFFF1FF
  77 #define SDVSDET                 0x00000400
  78 #define AUTOIDLE                0x1
  79 #define SDBP                    (1 << 8)
  80 #define DTO                     0xe
  81 #define ICE                     0x1
  82 #define ICS                     0x2
  83 #define CEN                     (1 << 2)
  84 #define CLKD_MAX                0x3FF           /* max clock divisor: 1023 */
  85 #define CLKD_MASK               0x0000FFC0
  86 #define CLKD_SHIFT              6
  87 #define DTO_MASK                0x000F0000
  88 #define DTO_SHIFT               16
  89 #define INIT_STREAM             (1 << 1)
  90 #define ACEN_ACMD23             (2 << 2)
  91 #define DP_SELECT               (1 << 21)
  92 #define DDIR                    (1 << 4)
  93 #define DMAE                    0x1
  94 #define MSBS                    (1 << 5)
  95 #define BCE                     (1 << 1)
  96 #define FOUR_BIT                (1 << 1)
  97 #define HSPE                    (1 << 2)
  98 #define IWE                     (1 << 24)
  99 #define DDR                     (1 << 19)
 100 #define CLKEXTFREE              (1 << 16)
 101 #define CTPL                    (1 << 11)
 102 #define DW8                     (1 << 5)
 103 #define OD                      0x1
 104 #define STAT_CLEAR              0xFFFFFFFF
 105 #define INIT_STREAM_CMD         0x00000000
 106 #define DUAL_VOLT_OCR_BIT       7
 107 #define SRC                     (1 << 25)
 108 #define SRD                     (1 << 26)
 109 #define SOFTRESET               (1 << 1)
 110
 111 /* PSTATE */
 112 #define DLEV_DAT(x)             (1 << (20 + (x)))
 113
 114 /* Interrupt masks for IE and ISE register */
 115 #define CC_EN                   (1 << 0)
 116 #define TC_EN                   (1 << 1)
 117 #define BWR_EN                  (1 << 4)
 118 #define BRR_EN                  (1 << 5)
 119 #define CIRQ_EN                 (1 << 8)
 120 #define ERR_EN                  (1 << 15)
 121 #define CTO_EN                  (1 << 16)
 122 #define CCRC_EN                 (1 << 17)
 123 #define CEB_EN                  (1 << 18)
 124 #define CIE_EN                  (1 << 19)
 125 #define DTO_EN                  (1 << 20)
 126 #define DCRC_EN                 (1 << 21)
 127 #define DEB_EN                  (1 << 22)
 128 #define ACE_EN                  (1 << 24)
 129 #define CERR_EN                 (1 << 28)
 130 #define BADA_EN                 (1 << 29)
 131
 132 #define INT_EN_MASK (BADA_EN | CERR_EN | ACE_EN | DEB_EN | DCRC_EN |\
 133                 DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \
 134                 BRR_EN | BWR_EN | TC_EN | CC_EN)
 135
 136 #define CNI     (1 << 7)
 137 #define ACIE    (1 << 4)
 138 #define ACEB    (1 << 3)
 139 #define ACCE    (1 << 2)
 140 #define ACTO    (1 << 1)
 141 #define ACNE    (1 << 0)
 142
 143 #define MMC_AUTOSUSPEND_DELAY   100
 144 #define MMC_TIMEOUT_MS          20              /* 20 mSec */
 145 #define MMC_TIMEOUT_US          20000           /* 20000 micro Sec */
 146 #define OMAP_MMC_MIN_CLOCK      400000
 147 #define OMAP_MMC_MAX_CLOCK      52000000
 148 #define DRIVER_NAME             "omap_hsmmc"
 149
 150 /*
 151  * One controller can have multiple slots, like on some omap boards using
 152  * omap.c controller driver. Luckily this is not currently done on any known
 153  * omap_hsmmc.c device.
 154  */
 155 #define mmc_pdata(host)         host->pdata
 156
 157 /*
 158  * MMC Host controller read/write API's
 159  */
 160 #define OMAP_HSMMC_READ(base, reg)      \
 161         __raw_readl((base) + OMAP_HSMMC_##reg)
 162
 163 #define OMAP_HSMMC_WRITE(base, reg, val) \
 164         __raw_writel((val), (base) + OMAP_HSMMC_##reg)
 165
 166 struct omap_hsmmc_next {
 167         unsigned int    dma_len;
 168         s32             cookie;
 169 };
 170
 171 struct omap_hsmmc_host {
 172         struct  device          *dev;
 173         struct  mmc_host        *mmc;
 174         struct  mmc_request     *mrq;
 175         struct  mmc_command     *cmd;
 176         struct  mmc_data        *data;
 177         struct  clk             *fclk;
 178         struct  clk             *dbclk;
 179         struct  regulator       *pbias;
 180         bool                    pbias_enabled;
 181         void    __iomem         *base;
 182         int                     vqmmc_enabled;
 183         resource_size_t         mapbase;
 184         spinlock_t              irq_lock; /* Prevent races with irq handler */
 185         unsigned int            dma_len;
 186         unsigned int            dma_sg_idx;
 187         unsigned char           bus_mode;
 188         unsigned char           power_mode;
 189         int                     suspended;
 190         u32                     con;
 191         u32                     hctl;
 192         u32                     sysctl;
 193         u32                     capa;
 194         int                     irq;
 195         int                     wake_irq;
 196         int                     use_dma, dma_ch;
 197         struct dma_chan         *tx_chan;
 198         struct dma_chan         *rx_chan;
 199         int                     response_busy;
 200         int                     context_loss;
 201         int                     protect_card;
 202         int                     reqs_blocked;
 203         int                     req_in_progress;
 204         unsigned long           clk_rate;
 205         unsigned int            flags;
 206 #define AUTO_CMD23              (1 << 0)        /* Auto CMD23 support */
 207 #define HSMMC_SDIO_IRQ_ENABLED  (1 << 1)        /* SDIO irq enabled */
 208         struct omap_hsmmc_next  next_data;
 209         struct  omap_hsmmc_platform_data        *pdata;
 210
 211         /* return MMC cover switch state, can be NULL if not supported.
 212          *
 213          * possible return values:
 214          *   0 - closed
 215          *   1 - open
 216          */
 217         int (*get_cover_state)(struct device *dev);
 218
 219         int (*card_detect)(struct device *dev);
 220 };
 221
 222 struct omap_mmc_of_data {
 223         u32 reg_offset;
 224         u8 controller_flags;
 225 };
 226
 227 static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host);
 228
 229 static int omap_hsmmc_card_detect(struct device *dev)
 230 {
 231         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
 232
 233         return mmc_gpio_get_cd(host->mmc);
 234 }
 235
 236 static int omap_hsmmc_get_cover_state(struct device *dev)
 237 {
 238         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
 239
 240         return mmc_gpio_get_cd(host->mmc);
 241 }
 242
 243 static int omap_hsmmc_enable_supply(struct mmc_host *mmc)
 244 {
 245         int ret;
 246         struct omap_hsmmc_host *host = mmc_priv(mmc);
 247         struct mmc_ios *ios = &mmc->ios;
 248
 249         if (!IS_ERR(mmc->supply.vmmc)) {
 250                 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
 251                 if (ret)
 252                         return ret;
 253         }
 254
 255         /* Enable interface voltage rail, if needed */
 256         if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
 257                 ret = regulator_enable(mmc->supply.vqmmc);
 258                 if (ret) {
 259                         dev_err(mmc_dev(mmc), "vmmc_aux reg enable failed\n");
 260                         goto err_vqmmc;
 261                 }
 262                 host->vqmmc_enabled = 1;
 263         }
 264
 265         return 0;
 266
 267 err_vqmmc:
 268         if (!IS_ERR(mmc->supply.vmmc))
 269                 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
 270
 271         return ret;
 272 }
 273
 274 static int omap_hsmmc_disable_supply(struct mmc_host *mmc)
 275 {
 276         int ret;
 277         int status;
 278         struct omap_hsmmc_host *host = mmc_priv(mmc);
 279
 280         if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
 281                 ret = regulator_disable(mmc->supply.vqmmc);
 282                 if (ret) {
 283                         dev_err(mmc_dev(mmc), "vmmc_aux reg disable failed\n");
 284                         return ret;
 285                 }
 286                 host->vqmmc_enabled = 0;
 287         }
 288
 289         if (!IS_ERR(mmc->supply.vmmc)) {
 290                 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
 291                 if (ret)
 292                         goto err_set_ocr;
 293         }
 294
 295         return 0;
 296
 297 err_set_ocr:
 298         if (!IS_ERR(mmc->supply.vqmmc)) {
 299                 status = regulator_enable(mmc->supply.vqmmc);
 300                 if (status)
 301                         dev_err(mmc_dev(mmc), "vmmc_aux re-enable failed\n");
 302         }
 303
 304         return ret;
 305 }
 306
 307 static int omap_hsmmc_set_pbias(struct omap_hsmmc_host *host, bool power_on)
 308 {
 309         int ret;
 310
 311         if (IS_ERR(host->pbias))
 312                 return 0;
 313
 314         if (power_on) {
 315                 if (host->pbias_enabled == 0) {
 316                         ret = regulator_enable(host->pbias);
 317                         if (ret) {
 318                                 dev_err(host->dev, "pbias reg enable fail\n");
 319                                 return ret;
 320                         }
 321                         host->pbias_enabled = 1;
 322                 }
 323         } else {
 324                 if (host->pbias_enabled == 1) {
 325                         ret = regulator_disable(host->pbias);
 326                         if (ret) {
 327                                 dev_err(host->dev, "pbias reg disable fail\n");
 328                                 return ret;
 329                         }
 330                         host->pbias_enabled = 0;
 331                 }
 332         }
 333
 334         return 0;
 335 }
 336
 337 static int omap_hsmmc_set_power(struct omap_hsmmc_host *host, int power_on)
 338 {
 339         struct mmc_host *mmc = host->mmc;
 340         int ret = 0;
 341
 342         /*
 343          * If we don't see a Vcc regulator, assume it's a fixed
 344          * voltage always-on regulator.
 345          */
 346         if (IS_ERR(mmc->supply.vmmc))
 347                 return 0;
 348
 349         ret = omap_hsmmc_set_pbias(host, false);
 350         if (ret)
 351                 return ret;
 352
 353         /*
 354          * Assume Vcc regulator is used only to power the card ... OMAP
 355          * VDDS is used to power the pins, optionally with a transceiver to
 356          * support cards using voltages other than VDDS (1.8V nominal).  When a
 357          * transceiver is used, DAT3..7 are muxed as transceiver control pins.
 358          *
 359          * In some cases this regulator won't support enable/disable;
 360          * e.g. it's a fixed rail for a WLAN chip.
 361          *
 362          * In other cases vcc_aux switches interface power.  Example, for
 363          * eMMC cards it represents VccQ.  Sometimes transceivers or SDIO
 364          * chips/cards need an interface voltage rail too.
 365          */
 366         if (power_on) {
 367                 ret = omap_hsmmc_enable_supply(mmc);
 368                 if (ret)
 369                         return ret;
 370
 371                 ret = omap_hsmmc_set_pbias(host, true);
 372                 if (ret)
 373                         goto err_set_voltage;
 374         } else {
 375                 ret = omap_hsmmc_disable_supply(mmc);
 376                 if (ret)
 377                         return ret;
 378         }
 379
 380         return 0;
 381
 382 err_set_voltage:
 383         omap_hsmmc_disable_supply(mmc);
 384
 385         return ret;
 386 }
 387
 388 static int omap_hsmmc_disable_boot_regulator(struct regulator *reg)
 389 {
 390         int ret;
 391
 392         if (IS_ERR(reg))
 393                 return 0;
 394
 395         if (regulator_is_enabled(reg)) {
 396                 ret = regulator_enable(reg);
 397                 if (ret)
 398                         return ret;
 399
 400                 ret = regulator_disable(reg);
 401                 if (ret)
 402                         return ret;
 403         }
 404
 405         return 0;
 406 }
 407
 408 static int omap_hsmmc_disable_boot_regulators(struct omap_hsmmc_host *host)
 409 {
 410         struct mmc_host *mmc = host->mmc;
 411         int ret;
 412
 413         /*
 414          * disable regulators enabled during boot and get the usecount
 415          * right so that regulators can be enabled/disabled by checking
 416          * the return value of regulator_is_enabled
 417          */
 418         ret = omap_hsmmc_disable_boot_regulator(mmc->supply.vmmc);
 419         if (ret) {
 420                 dev_err(host->dev, "fail to disable boot enabled vmmc reg\n");
 421                 return ret;
 422         }
 423
 424         ret = omap_hsmmc_disable_boot_regulator(mmc->supply.vqmmc);
 425         if (ret) {
 426                 dev_err(host->dev,
 427                         "fail to disable boot enabled vmmc_aux reg\n");
 428                 return ret;
 429         }
 430
 431         ret = omap_hsmmc_disable_boot_regulator(host->pbias);
 432         if (ret) {
 433                 dev_err(host->dev,
 434                         "failed to disable boot enabled pbias reg\n");
 435                 return ret;
 436         }
 437
 438         return 0;
 439 }
 440
 441 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
 442 {
 443         int ret;
 444         struct mmc_host *mmc = host->mmc;
 445
 446
 447         ret = mmc_regulator_get_supply(mmc);
 448         if (ret)
 449                 return ret;
 450
 451         /* Allow an aux regulator */
 452         if (IS_ERR(mmc->supply.vqmmc)) {
 453                 mmc->supply.vqmmc = devm_regulator_get_optional(host->dev,
 454                                                                 "vmmc_aux");
 455                 if (IS_ERR(mmc->supply.vqmmc)) {
 456                         ret = PTR_ERR(mmc->supply.vqmmc);
 457                         if ((ret != -ENODEV) && host->dev->of_node)
 458                                 return ret;
 459                         dev_dbg(host->dev, "unable to get vmmc_aux regulator %ld\n",
 460                                 PTR_ERR(mmc->supply.vqmmc));
 461                 }
 462         }
 463
 464         host->pbias = devm_regulator_get_optional(host->dev, "pbias");
 465         if (IS_ERR(host->pbias)) {
 466                 ret = PTR_ERR(host->pbias);
 467                 if ((ret != -ENODEV) && host->dev->of_node) {
 468                         dev_err(host->dev,
 469                         "SD card detect fail? enable CONFIG_REGULATOR_PBIAS\n");
 470                         return ret;
 471                 }
 472                 dev_dbg(host->dev, "unable to get pbias regulator %ld\n",
 473                         PTR_ERR(host->pbias));
 474         }
 475
 476         /* For eMMC do not power off when not in sleep state */
 477         if (mmc_pdata(host)->no_regulator_off_init)
 478                 return 0;
 479
 480         ret = omap_hsmmc_disable_boot_regulators(host);
 481         if (ret)
 482                 return ret;
 483
 484         return 0;
 485 }
 486
 487 static irqreturn_t omap_hsmmc_cover_irq(int irq, void *dev_id);
 488
 489 static int omap_hsmmc_gpio_init(struct mmc_host *mmc,
 490                                 struct omap_hsmmc_host *host,
 491                                 struct omap_hsmmc_platform_data *pdata)
 492 {
 493         int ret;
 494
 495         if (gpio_is_valid(pdata->gpio_cod)) {
 496                 ret = mmc_gpio_request_cd(mmc, pdata->gpio_cod, 0);
 497                 if (ret)
 498                         return ret;
 499
 500                 host->get_cover_state = omap_hsmmc_get_cover_state;
 501                 mmc_gpio_set_cd_isr(mmc, omap_hsmmc_cover_irq);
 502         } else if (gpio_is_valid(pdata->gpio_cd)) {
 503                 ret = mmc_gpio_request_cd(mmc, pdata->gpio_cd, 0);
 504                 if (ret)
 505                         return ret;
 506
 507                 host->card_detect = omap_hsmmc_card_detect;
 508         }
 509
 510         if (gpio_is_valid(pdata->gpio_wp)) {
 511                 ret = mmc_gpio_request_ro(mmc, pdata->gpio_wp);
 512                 if (ret)
 513                         return ret;
 514         }
 515
 516         return 0;
 517 }
 518
 519 /*
 520  * Start clock to the card
 521  */
 522 static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
 523 {
 524         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 525                 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
 526 }
 527
 528 /*
 529  * Stop clock to the card
 530  */
 531 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
 532 {
 533         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 534                 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
 535         if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
 536                 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n");
 537 }
 538
 539 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
 540                                   struct mmc_command *cmd)
 541 {
 542         u32 irq_mask = INT_EN_MASK;
 543         unsigned long flags;
 544
 545         if (host->use_dma)
 546                 irq_mask &= ~(BRR_EN | BWR_EN);
 547
 548         /* Disable timeout for erases */
 549         if (cmd->opcode == MMC_ERASE)
 550                 irq_mask &= ~DTO_EN;
 551
 552         spin_lock_irqsave(&host->irq_lock, flags);
 553         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 554         OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
 555
 556         /* latch pending CIRQ, but don't signal MMC core */
 557         if (host->flags & HSMMC_SDIO_IRQ_ENABLED)
 558                 irq_mask |= CIRQ_EN;
 559         OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
 560         spin_unlock_irqrestore(&host->irq_lock, flags);
 561 }
 562
 563 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
 564 {
 565         u32 irq_mask = 0;
 566         unsigned long flags;
 567
 568         spin_lock_irqsave(&host->irq_lock, flags);
 569         /* no transfer running but need to keep cirq if enabled */
 570         if (host->flags & HSMMC_SDIO_IRQ_ENABLED)
 571                 irq_mask |= CIRQ_EN;
 572         OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
 573         OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
 574         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 575         spin_unlock_irqrestore(&host->irq_lock, flags);
 576 }
 577
 578 /* Calculate divisor for the given clock frequency */
 579 static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
 580 {
 581         u16 dsor = 0;
 582
 583         if (ios->clock) {
 584                 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
 585                 if (dsor > CLKD_MAX)
 586                         dsor = CLKD_MAX;
 587         }
 588
 589         return dsor;
 590 }
 591
 592 static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
 593 {
 594         struct mmc_ios *ios = &host->mmc->ios;
 595         unsigned long regval;
 596         unsigned long timeout;
 597         unsigned long clkdiv;
 598
 599         dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
 600
 601         omap_hsmmc_stop_clock(host);
 602
 603         regval = OMAP_HSMMC_READ(host->base, SYSCTL);
 604         regval = regval & ~(CLKD_MASK | DTO_MASK);
 605         clkdiv = calc_divisor(host, ios);
 606         regval = regval | (clkdiv << 6) | (DTO << 16);
 607         OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
 608         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 609                 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
 610
 611         /* Wait till the ICS bit is set */
 612         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 613         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
 614                 && time_before(jiffies, timeout))
 615                 cpu_relax();
 616
 617         /*
 618          * Enable High-Speed Support
 619          * Pre-Requisites
 620          *      - Controller should support High-Speed-Enable Bit
 621          *      - Controller should not be using DDR Mode
 622          *      - Controller should advertise that it supports High Speed
 623          *        in capabilities register
 624          *      - MMC/SD clock coming out of controller > 25MHz
 625          */
 626         if ((mmc_pdata(host)->features & HSMMC_HAS_HSPE_SUPPORT) &&
 627             (ios->timing != MMC_TIMING_MMC_DDR52) &&
 628             (ios->timing != MMC_TIMING_UHS_DDR50) &&
 629             ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) {
 630                 regval = OMAP_HSMMC_READ(host->base, HCTL);
 631                 if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000)
 632                         regval |= HSPE;
 633                 else
 634                         regval &= ~HSPE;
 635
 636                 OMAP_HSMMC_WRITE(host->base, HCTL, regval);
 637         }
 638
 639         omap_hsmmc_start_clock(host);
 640 }
 641
 642 static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
 643 {
 644         struct mmc_ios *ios = &host->mmc->ios;
 645         u32 con;
 646
 647         con = OMAP_HSMMC_READ(host->base, CON);
 648         if (ios->timing == MMC_TIMING_MMC_DDR52 ||
 649             ios->timing == MMC_TIMING_UHS_DDR50)
 650                 con |= DDR;     /* configure in DDR mode */
 651         else
 652                 con &= ~DDR;
 653         switch (ios->bus_width) {
 654         case MMC_BUS_WIDTH_8:
 655                 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
 656                 break;
 657         case MMC_BUS_WIDTH_4:
 658                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
 659                 OMAP_HSMMC_WRITE(host->base, HCTL,
 660                         OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
 661                 break;
 662         case MMC_BUS_WIDTH_1:
 663                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
 664                 OMAP_HSMMC_WRITE(host->base, HCTL,
 665                         OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
 666                 break;
 667         }
 668 }
 669
 670 static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
 671 {
 672         struct mmc_ios *ios = &host->mmc->ios;
 673         u32 con;
 674
 675         con = OMAP_HSMMC_READ(host->base, CON);
 676         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
 677                 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
 678         else
 679                 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
 680 }
 681
 682 #ifdef CONFIG_PM
 683
 684 /*
 685  * Restore the MMC host context, if it was lost as result of a
 686  * power state change.
 687  */
 688 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
 689 {
 690         struct mmc_ios *ios = &host->mmc->ios;
 691         u32 hctl, capa;
 692         unsigned long timeout;
 693
 694         if (host->con == OMAP_HSMMC_READ(host->base, CON) &&
 695             host->hctl == OMAP_HSMMC_READ(host->base, HCTL) &&
 696             host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) &&
 697             host->capa == OMAP_HSMMC_READ(host->base, CAPA))
 698                 return 0;
 699
 700         host->context_loss++;
 701
 702         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
 703                 if (host->power_mode != MMC_POWER_OFF &&
 704                     (1 << ios->vdd) <= MMC_VDD_23_24)
 705                         hctl = SDVS18;
 706                 else
 707                         hctl = SDVS30;
 708                 capa = VS30 | VS18;
 709         } else {
 710                 hctl = SDVS18;
 711                 capa = VS18;
 712         }
 713
 714         if (host->mmc->caps & MMC_CAP_SDIO_IRQ)
 715                 hctl |= IWE;
 716
 717         OMAP_HSMMC_WRITE(host->base, HCTL,
 718                         OMAP_HSMMC_READ(host->base, HCTL) | hctl);
 719
 720         OMAP_HSMMC_WRITE(host->base, CAPA,
 721                         OMAP_HSMMC_READ(host->base, CAPA) | capa);
 722
 723         OMAP_HSMMC_WRITE(host->base, HCTL,
 724                         OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
 725
 726         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 727         while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
 728                 && time_before(jiffies, timeout))
 729                 ;
 730
 731         OMAP_HSMMC_WRITE(host->base, ISE, 0);
 732         OMAP_HSMMC_WRITE(host->base, IE, 0);
 733         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 734
 735         /* Do not initialize card-specific things if the power is off */
 736         if (host->power_mode == MMC_POWER_OFF)
 737                 goto out;
 738
 739         omap_hsmmc_set_bus_width(host);
 740
 741         omap_hsmmc_set_clock(host);
 742
 743         omap_hsmmc_set_bus_mode(host);
 744
 745 out:
 746         dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n",
 747                 host->context_loss);
 748         return 0;
 749 }
 750
 751 /*
 752  * Save the MMC host context (store the number of power state changes so far).
 753  */
 754 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
 755 {
 756         host->con =  OMAP_HSMMC_READ(host->base, CON);
 757         host->hctl = OMAP_HSMMC_READ(host->base, HCTL);
 758         host->sysctl =  OMAP_HSMMC_READ(host->base, SYSCTL);
 759         host->capa = OMAP_HSMMC_READ(host->base, CAPA);
 760 }
 761
 762 #else
 763
 764 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
 765 {
 766         return 0;
 767 }
 768
 769 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
 770 {
 771 }
 772
 773 #endif
 774
 775 /*
 776  * Send init stream sequence to card
 777  * before sending IDLE command
 778  */
 779 static void send_init_stream(struct omap_hsmmc_host *host)
 780 {
 781         int reg = 0;
 782         unsigned long timeout;
 783
 784         if (host->protect_card)
 785                 return;
 786
 787         disable_irq(host->irq);
 788
 789         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
 790         OMAP_HSMMC_WRITE(host->base, CON,
 791                 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
 792         OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
 793
 794         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 795         while ((reg != CC_EN) && time_before(jiffies, timeout))
 796                 reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN;
 797
 798         OMAP_HSMMC_WRITE(host->base, CON,
 799                 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
 800
 801         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 802         OMAP_HSMMC_READ(host->base, STAT);
 803
 804         enable_irq(host->irq);
 805 }
 806
 807 static inline
 808 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
 809 {
 810         int r = 1;
 811
 812         if (host->get_cover_state)
 813                 r = host->get_cover_state(host->dev);
 814         return r;
 815 }
 816
 817 static ssize_t
 818 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
 819                            char *buf)
 820 {
 821         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 822         struct omap_hsmmc_host *host = mmc_priv(mmc);
 823
 824         return sprintf(buf, "%s\n",
 825                         omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
 826 }
 827
 828 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
 829
 830 static ssize_t
 831 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
 832                         char *buf)
 833 {
 834         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 835         struct omap_hsmmc_host *host = mmc_priv(mmc);
 836
 837         return sprintf(buf, "%s\n", mmc_pdata(host)->name);
 838 }
 839
 840 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
 841
 842 /*
 843  * Configure the response type and send the cmd.
 844  */
 845 static void
 846 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
 847         struct mmc_data *data)
 848 {
 849         int cmdreg = 0, resptype = 0, cmdtype = 0;
 850
 851         dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
 852                 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
 853         host->cmd = cmd;
 854
 855         omap_hsmmc_enable_irq(host, cmd);
 856
 857         host->response_busy = 0;
 858         if (cmd->flags & MMC_RSP_PRESENT) {
 859                 if (cmd->flags & MMC_RSP_136)
 860                         resptype = 1;
 861                 else if (cmd->flags & MMC_RSP_BUSY) {
 862                         resptype = 3;
 863                         host->response_busy = 1;
 864                 } else
 865                         resptype = 2;
 866         }
 867
 868         /*
 869          * Unlike OMAP1 controller, the cmdtype does not seem to be based on
 870          * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
 871          * a val of 0x3, rest 0x0.
 872          */
 873         if (cmd == host->mrq->stop)
 874                 cmdtype = 0x3;
 875
 876         cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
 877
 878         if ((host->flags & AUTO_CMD23) && mmc_op_multi(cmd->opcode) &&
 879             host->mrq->sbc) {
 880                 cmdreg |= ACEN_ACMD23;
 881                 OMAP_HSMMC_WRITE(host->base, SDMASA, host->mrq->sbc->arg);
 882         }
 883         if (data) {
 884                 cmdreg |= DP_SELECT | MSBS | BCE;
 885                 if (data->flags & MMC_DATA_READ)
 886                         cmdreg |= DDIR;
 887                 else
 888                         cmdreg &= ~(DDIR);
 889         }
 890
 891         if (host->use_dma)
 892                 cmdreg |= DMAE;
 893
 894         host->req_in_progress = 1;
 895
 896         OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
 897         OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
 898 }
 899
 900 static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host,
 901         struct mmc_data *data)
 902 {
 903         return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
 904 }
 905
 906 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
 907 {
 908         int dma_ch;
 909         unsigned long flags;
 910
 911         spin_lock_irqsave(&host->irq_lock, flags);
 912         host->req_in_progress = 0;
 913         dma_ch = host->dma_ch;
 914         spin_unlock_irqrestore(&host->irq_lock, flags);
 915
 916         omap_hsmmc_disable_irq(host);
 917         /* Do not complete the request if DMA is still in progress */
 918         if (mrq->data && host->use_dma && dma_ch != -1)
 919                 return;
 920         host->mrq = NULL;
 921         mmc_request_done(host->mmc, mrq);
 922 }
 923
 924 /*
 925  * Notify the transfer complete to MMC core
 926  */
 927 static void
 928 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
 929 {
 930         if (!data) {
 931                 struct mmc_request *mrq = host->mrq;
 932
 933                 /* TC before CC from CMD6 - don't know why, but it happens */
 934                 if (host->cmd && host->cmd->opcode == 6 &&
 935                     host->response_busy) {
 936                         host->response_busy = 0;
 937                         return;
 938                 }
 939
 940                 omap_hsmmc_request_done(host, mrq);
 941                 return;
 942         }
 943
 944         host->data = NULL;
 945
 946         if (!data->error)
 947                 data->bytes_xfered += data->blocks * (data->blksz);
 948         else
 949                 data->bytes_xfered = 0;
 950
 951         if (data->stop && (data->error || !host->mrq->sbc))
 952                 omap_hsmmc_start_command(host, data->stop, NULL);
 953         else
 954                 omap_hsmmc_request_done(host, data->mrq);
 955 }
 956
 957 /*
 958  * Notify the core about command completion
 959  */
 960 static void
 961 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
 962 {
 963         if (host->mrq->sbc && (host->cmd == host->mrq->sbc) &&
 964             !host->mrq->sbc->error && !(host->flags & AUTO_CMD23)) {
 965                 host->cmd = NULL;
 966                 omap_hsmmc_start_dma_transfer(host);
 967                 omap_hsmmc_start_command(host, host->mrq->cmd,
 968                                                 host->mrq->data);
 969                 return;
 970         }
 971
 972         host->cmd = NULL;
 973
 974         if (cmd->flags & MMC_RSP_PRESENT) {
 975                 if (cmd->flags & MMC_RSP_136) {
 976                         /* response type 2 */
 977                         cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
 978                         cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
 979                         cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
 980                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
 981                 } else {
 982                         /* response types 1, 1b, 3, 4, 5, 6 */
 983                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
 984                 }
 985         }
 986         if ((host->data == NULL && !host->response_busy) || cmd->error)
 987                 omap_hsmmc_request_done(host, host->mrq);
 988 }
 989
 990 /*
 991  * DMA clean up for command errors
 992  */
 993 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
 994 {
 995         int dma_ch;
 996         unsigned long flags;
 997
 998         host->data->error = errno;
 999
1000         spin_lock_irqsave(&host->irq_lock, flags);
1001         dma_ch = host->dma_ch;
1002         host->dma_ch = -1;
1003         spin_unlock_irqrestore(&host->irq_lock, flags);
1004
1005         if (host->use_dma && dma_ch != -1) {
1006                 struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data);
1007
1008                 dmaengine_terminate_all(chan);
1009                 dma_unmap_sg(chan->device->dev,
1010                         host->data->sg, host->data->sg_len,
1011                         mmc_get_dma_dir(host->data));
1012
1013                 host->data->host_cookie = 0;
1014         }
1015         host->data = NULL;
1016 }
1017
1018 /*
1019  * Readable error output
1020  */
1021 #ifdef CONFIG_MMC_DEBUG
1022 static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
1023 {
1024         /* --- means reserved bit without definition at documentation */
1025         static const char *omap_hsmmc_status_bits[] = {
1026                 "CC"  , "TC"  , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
1027                 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
1028                 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
1029                 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
1030         };
1031         char res[256];
1032         char *buf = res;
1033         int len, i;
1034
1035         len = sprintf(buf, "MMC IRQ 0x%x :", status);
1036         buf += len;
1037
1038         for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
1039                 if (status & (1 << i)) {
1040                         len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
1041                         buf += len;
1042                 }
1043
1044         dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
1045 }
1046 #else
1047 static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
1048                                              u32 status)
1049 {
1050 }
1051 #endif  /* CONFIG_MMC_DEBUG */
1052
1053 /*
1054  * MMC controller internal state machines reset
1055  *
1056  * Used to reset command or data internal state machines, using respectively
1057  *  SRC or SRD bit of SYSCTL register
1058  * Can be called from interrupt context
1059  */
1060 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
1061                                                    unsigned long bit)
1062 {
1063         unsigned long i = 0;
1064         unsigned long limit = MMC_TIMEOUT_US;
1065
1066         OMAP_HSMMC_WRITE(host->base, SYSCTL,
1067                          OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
1068
1069         /*
1070          * OMAP4 ES2 and greater has an updated reset logic.
1071          * Monitor a 0->1 transition first
1072          */
1073         if (mmc_pdata(host)->features & HSMMC_HAS_UPDATED_RESET) {
1074                 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
1075                                         && (i++ < limit))
1076                         udelay(1);
1077         }
1078         i = 0;
1079
1080         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
1081                 (i++ < limit))
1082                 udelay(1);
1083
1084         if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
1085                 dev_err(mmc_dev(host->mmc),
1086                         "Timeout waiting on controller reset in %s\n",
1087                         __func__);
1088 }
1089
1090 static void hsmmc_command_incomplete(struct omap_hsmmc_host *host,
1091                                         int err, int end_cmd)
1092 {
1093         if (end_cmd) {
1094                 omap_hsmmc_reset_controller_fsm(host, SRC);
1095                 if (host->cmd)
1096                         host->cmd->error = err;
1097         }
1098
1099         if (host->data) {
1100                 omap_hsmmc_reset_controller_fsm(host, SRD);
1101                 omap_hsmmc_dma_cleanup(host, err);
1102         } else if (host->mrq && host->mrq->cmd)
1103                 host->mrq->cmd->error = err;
1104 }
1105
1106 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
1107 {
1108         struct mmc_data *data;
1109         int end_cmd = 0, end_trans = 0;
1110         int error = 0;
1111
1112         data = host->data;
1113         dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1114
1115         if (status & ERR_EN) {
1116                 omap_hsmmc_dbg_report_irq(host, status);
1117
1118                 if (status & (CTO_EN | CCRC_EN | CEB_EN))
1119                         end_cmd = 1;
1120                 if (host->data || host->response_busy) {
1121                         end_trans = !end_cmd;
1122                         host->response_busy = 0;
1123                 }
1124                 if (status & (CTO_EN | DTO_EN))
1125                         hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd);
1126                 else if (status & (CCRC_EN | DCRC_EN | DEB_EN | CEB_EN |
1127                                    BADA_EN))
1128                         hsmmc_command_incomplete(host, -EILSEQ, end_cmd);
1129
1130                 if (status & ACE_EN) {
1131                         u32 ac12;
1132                         ac12 = OMAP_HSMMC_READ(host->base, AC12);
1133                         if (!(ac12 & ACNE) && host->mrq->sbc) {
1134                                 end_cmd = 1;
1135                                 if (ac12 & ACTO)
1136                                         error =  -ETIMEDOUT;
1137                                 else if (ac12 & (ACCE | ACEB | ACIE))
1138                                         error = -EILSEQ;
1139                                 host->mrq->sbc->error = error;
1140                                 hsmmc_command_incomplete(host, error, end_cmd);
1141                         }
1142                         dev_dbg(mmc_dev(host->mmc), "AC12 err: 0x%x\n", ac12);
1143                 }
1144         }
1145
1146         OMAP_HSMMC_WRITE(host->base, STAT, status);
1147         if (end_cmd || ((status & CC_EN) && host->cmd))
1148                 omap_hsmmc_cmd_done(host, host->cmd);
1149         if ((end_trans || (status & TC_EN)) && host->mrq)
1150                 omap_hsmmc_xfer_done(host, data);
1151 }
1152
1153 /*
1154  * MMC controller IRQ handler
1155  */
1156 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1157 {
1158         struct omap_hsmmc_host *host = dev_id;
1159         int status;
1160
1161         status = OMAP_HSMMC_READ(host->base, STAT);
1162         while (status & (INT_EN_MASK | CIRQ_EN)) {
1163                 if (host->req_in_progress)
1164                         omap_hsmmc_do_irq(host, status);
1165
1166                 if (status & CIRQ_EN)
1167                         mmc_signal_sdio_irq(host->mmc);
1168
1169                 /* Flush posted write */
1170                 status = OMAP_HSMMC_READ(host->base, STAT);
1171         }
1172
1173         return IRQ_HANDLED;
1174 }
1175
1176 static void set_sd_bus_power(struct omap_hsmmc_host *host)
1177 {
1178         unsigned long i;
1179
1180         OMAP_HSMMC_WRITE(host->base, HCTL,
1181                          OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1182         for (i = 0; i < loops_per_jiffy; i++) {
1183                 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1184                         break;
1185                 cpu_relax();
1186         }
1187 }
1188
1189 /*
1190  * Switch MMC interface voltage ... only relevant for MMC1.
1191  *
1192  * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1193  * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1194  * Some chips, like eMMC ones, use internal transceivers.
1195  */
1196 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1197 {
1198         u32 reg_val = 0;
1199         int ret;
1200
1201         /* Disable the clocks */
1202         if (host->dbclk)
1203                 clk_disable_unprepare(host->dbclk);
1204
1205         /* Turn the power off */
1206         ret = omap_hsmmc_set_power(host, 0);
1207
1208         /* Turn the power ON with given VDD 1.8 or 3.0v */
1209         if (!ret)
1210                 ret = omap_hsmmc_set_power(host, 1);
1211         if (host->dbclk)
1212                 clk_prepare_enable(host->dbclk);
1213
1214         if (ret != 0)
1215                 goto err;
1216
1217         OMAP_HSMMC_WRITE(host->base, HCTL,
1218                 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1219         reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1220
1221         /*
1222          * If a MMC dual voltage card is detected, the set_ios fn calls
1223          * this fn with VDD bit set for 1.8V. Upon card removal from the
1224          * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1225          *
1226          * Cope with a bit of slop in the range ... per data sheets:
1227          *  - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1228          *    but recommended values are 1.71V to 1.89V
1229          *  - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1230          *    but recommended values are 2.7V to 3.3V
1231          *
1232          * Board setup code shouldn't permit anything very out-of-range.
1233          * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1234          * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1235          */
1236         if ((1 << vdd) <= MMC_VDD_23_24)
1237                 reg_val |= SDVS18;
1238         else
1239                 reg_val |= SDVS30;
1240
1241         OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1242         set_sd_bus_power(host);
1243
1244         return 0;
1245 err:
1246         dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1247         return ret;
1248 }
1249
1250 /* Protect the card while the cover is open */
1251 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1252 {
1253         if (!host->get_cover_state)
1254                 return;
1255
1256         host->reqs_blocked = 0;
1257         if (host->get_cover_state(host->dev)) {
1258                 if (host->protect_card) {
1259                         dev_info(host->dev, "%s: cover is closed, "
1260                                          "card is now accessible\n",
1261                                          mmc_hostname(host->mmc));
1262                         host->protect_card = 0;
1263                 }
1264         } else {
1265                 if (!host->protect_card) {
1266                         dev_info(host->dev, "%s: cover is open, "
1267                                          "card is now inaccessible\n",
1268                                          mmc_hostname(host->mmc));
1269                         host->protect_card = 1;
1270                 }
1271         }
1272 }
1273
1274 /*
1275  * irq handler when (cell-phone) cover is mounted/removed
1276  */
1277 static irqreturn_t omap_hsmmc_cover_irq(int irq, void *dev_id)
1278 {
1279         struct omap_hsmmc_host *host = dev_id;
1280
1281         sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
1282
1283         omap_hsmmc_protect_card(host);
1284         mmc_detect_change(host->mmc, (HZ * 200) / 1000);
1285         return IRQ_HANDLED;
1286 }
1287
1288 static void omap_hsmmc_dma_callback(void *param)
1289 {
1290         struct omap_hsmmc_host *host = param;
1291         struct dma_chan *chan;
1292         struct mmc_data *data;
1293         int req_in_progress;
1294
1295         spin_lock_irq(&host->irq_lock);
1296         if (host->dma_ch < 0) {
1297                 spin_unlock_irq(&host->irq_lock);
1298                 return;
1299         }
1300
1301         data = host->mrq->data;
1302         chan = omap_hsmmc_get_dma_chan(host, data);
1303         if (!data->host_cookie)
1304                 dma_unmap_sg(chan->device->dev,
1305                              data->sg, data->sg_len,
1306                              mmc_get_dma_dir(data));
1307
1308         req_in_progress = host->req_in_progress;
1309         host->dma_ch = -1;
1310         spin_unlock_irq(&host->irq_lock);
1311
1312         /* If DMA has finished after TC, complete the request */
1313         if (!req_in_progress) {
1314                 struct mmc_request *mrq = host->mrq;
1315
1316                 host->mrq = NULL;
1317                 mmc_request_done(host->mmc, mrq);
1318         }
1319 }
1320
1321 static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1322                                        struct mmc_data *data,
1323                                        struct omap_hsmmc_next *next,
1324                                        struct dma_chan *chan)
1325 {
1326         int dma_len;
1327
1328         if (!next && data->host_cookie &&
1329             data->host_cookie != host->next_data.cookie) {
1330                 dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d"
1331                        " host->next_data.cookie %d\n",
1332                        __func__, data->host_cookie, host->next_data.cookie);
1333                 data->host_cookie = 0;
1334         }
1335
1336         /* Check if next job is already prepared */
1337         if (next || data->host_cookie != host->next_data.cookie) {
1338                 dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len,
1339                                      mmc_get_dma_dir(data));
1340
1341         } else {
1342                 dma_len = host->next_data.dma_len;
1343                 host->next_data.dma_len = 0;
1344         }
1345
1346
1347         if (dma_len == 0)
1348                 return -EINVAL;
1349
1350         if (next) {
1351                 next->dma_len = dma_len;
1352                 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1353         } else
1354                 host->dma_len = dma_len;
1355
1356         return 0;
1357 }
1358
1359 /*
1360  * Routine to configure and start DMA for the MMC card
1361  */
1362 static int omap_hsmmc_setup_dma_transfer(struct omap_hsmmc_host *host,
1363                                         struct mmc_request *req)
1364 {
1365         struct dma_async_tx_descriptor *tx;
1366         int ret = 0, i;
1367         struct mmc_data *data = req->data;
1368         struct dma_chan *chan;
1369         struct dma_slave_config cfg = {
1370                 .src_addr = host->mapbase + OMAP_HSMMC_DATA,
1371                 .dst_addr = host->mapbase + OMAP_HSMMC_DATA,
1372                 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
1373                 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
1374                 .src_maxburst = data->blksz / 4,
1375                 .dst_maxburst = data->blksz / 4,
1376         };
1377
1378         /* Sanity check: all the SG entries must be aligned by block size. */
1379         for (i = 0; i < data->sg_len; i++) {
1380                 struct scatterlist *sgl;
1381
1382                 sgl = data->sg + i;
1383                 if (sgl->length % data->blksz)
1384                         return -EINVAL;
1385         }
1386         if ((data->blksz % 4) != 0)
1387                 /* REVISIT: The MMC buffer increments only when MSB is written.
1388                  * Return error for blksz which is non multiple of four.
1389                  */
1390                 return -EINVAL;
1391
1392         BUG_ON(host->dma_ch != -1);
1393
1394         chan = omap_hsmmc_get_dma_chan(host, data);
1395
1396         ret = dmaengine_slave_config(chan, &cfg);
1397         if (ret)
1398                 return ret;
1399
1400         ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan);
1401         if (ret)
1402                 return ret;
1403
1404         tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len,
1405                 data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
1406                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1407         if (!tx) {
1408                 dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n");
1409                 /* FIXME: cleanup */
1410                 return -1;
1411         }
1412
1413         tx->callback = omap_hsmmc_dma_callback;
1414         tx->callback_param = host;
1415
1416         /* Does not fail */
1417         dmaengine_submit(tx);
1418
1419         host->dma_ch = 1;
1420
1421         return 0;
1422 }
1423
1424 static void set_data_timeout(struct omap_hsmmc_host *host,
1425                              unsigned long long timeout_ns,
1426                              unsigned int timeout_clks)
1427 {
1428         unsigned long long timeout = timeout_ns;
1429         unsigned int cycle_ns;
1430         uint32_t reg, clkd, dto = 0;
1431
1432         reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1433         clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1434         if (clkd == 0)
1435                 clkd = 1;
1436
1437         cycle_ns = 1000000000 / (host->clk_rate / clkd);
1438         do_div(timeout, cycle_ns);
1439         timeout += timeout_clks;
1440         if (timeout) {
1441                 while ((timeout & 0x80000000) == 0) {
1442                         dto += 1;
1443                         timeout <<= 1;
1444                 }
1445                 dto = 31 - dto;
1446                 timeout <<= 1;
1447                 if (timeout && dto)
1448                         dto += 1;
1449                 if (dto >= 13)
1450                         dto -= 13;
1451                 else
1452                         dto = 0;
1453                 if (dto > 14)
1454                         dto = 14;
1455         }
1456
1457         reg &= ~DTO_MASK;
1458         reg |= dto << DTO_SHIFT;
1459         OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1460 }
1461
1462 static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host)
1463 {
1464         struct mmc_request *req = host->mrq;
1465         struct dma_chan *chan;
1466
1467         if (!req->data)
1468                 return;
1469         OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1470                                 | (req->data->blocks << 16));
1471         set_data_timeout(host, req->data->timeout_ns,
1472                                 req->data->timeout_clks);
1473         chan = omap_hsmmc_get_dma_chan(host, req->data);
1474         dma_async_issue_pending(chan);
1475 }
1476
1477 /*
1478  * Configure block length for MMC/SD cards and initiate the transfer.
1479  */
1480 static int
1481 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1482 {
1483         int ret;
1484         unsigned long long timeout;
1485
1486         host->data = req->data;
1487
1488         if (req->data == NULL) {
1489                 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1490                 if (req->cmd->flags & MMC_RSP_BUSY) {
1491                         timeout = req->cmd->busy_timeout * NSEC_PER_MSEC;
1492
1493                         /*
1494                          * Set an arbitrary 100ms data timeout for commands with
1495                          * busy signal and no indication of busy_timeout.
1496                          */
1497                         if (!timeout)
1498                                 timeout = 100000000U;
1499
1500                         set_data_timeout(host, timeout, 0);
1501                 }
1502                 return 0;
1503         }
1504
1505         if (host->use_dma) {
1506                 ret = omap_hsmmc_setup_dma_transfer(host, req);
1507                 if (ret != 0) {
1508                         dev_err(mmc_dev(host->mmc), "MMC start dma failure\n");
1509                         return ret;
1510                 }
1511         }
1512         return 0;
1513 }
1514
1515 static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1516                                 int err)
1517 {
1518         struct omap_hsmmc_host *host = mmc_priv(mmc);
1519         struct mmc_data *data = mrq->data;
1520
1521         if (host->use_dma && data->host_cookie) {
1522                 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data);
1523
1524                 dma_unmap_sg(c->device->dev, data->sg, data->sg_len,
1525                              mmc_get_dma_dir(data));
1526                 data->host_cookie = 0;
1527         }
1528 }
1529
1530 static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
1531 {
1532         struct omap_hsmmc_host *host = mmc_priv(mmc);
1533
1534         if (mrq->data->host_cookie) {
1535                 mrq->data->host_cookie = 0;
1536                 return ;
1537         }
1538
1539         if (host->use_dma) {
1540                 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data);
1541
1542                 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1543                                                 &host->next_data, c))
1544                         mrq->data->host_cookie = 0;
1545         }
1546 }
1547
1548 /*
1549  * Request function. for read/write operation
1550  */
1551 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1552 {
1553         struct omap_hsmmc_host *host = mmc_priv(mmc);
1554         int err;
1555
1556         BUG_ON(host->req_in_progress);
1557         BUG_ON(host->dma_ch != -1);
1558         if (host->protect_card) {
1559                 if (host->reqs_blocked < 3) {
1560                         /*
1561                          * Ensure the controller is left in a consistent
1562                          * state by resetting the command and data state
1563                          * machines.
1564                          */
1565                         omap_hsmmc_reset_controller_fsm(host, SRD);
1566                         omap_hsmmc_reset_controller_fsm(host, SRC);
1567                         host->reqs_blocked += 1;
1568                 }
1569                 req->cmd->error = -EBADF;
1570                 if (req->data)
1571                         req->data->error = -EBADF;
1572                 req->cmd->retries = 0;
1573                 mmc_request_done(mmc, req);
1574                 return;
1575         } else if (host->reqs_blocked)
1576                 host->reqs_blocked = 0;
1577         WARN_ON(host->mrq != NULL);
1578         host->mrq = req;
1579         host->clk_rate = clk_get_rate(host->fclk);
1580         err = omap_hsmmc_prepare_data(host, req);
1581         if (err) {
1582                 req->cmd->error = err;
1583                 if (req->data)
1584                         req->data->error = err;
1585                 host->mrq = NULL;
1586                 mmc_request_done(mmc, req);
1587                 return;
1588         }
1589         if (req->sbc && !(host->flags & AUTO_CMD23)) {
1590                 omap_hsmmc_start_command(host, req->sbc, NULL);
1591                 return;
1592         }
1593
1594         omap_hsmmc_start_dma_transfer(host);
1595         omap_hsmmc_start_command(host, req->cmd, req->data);
1596 }
1597
1598 /* Routine to configure clock values. Exposed API to core */
1599 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1600 {
1601         struct omap_hsmmc_host *host = mmc_priv(mmc);
1602         int do_send_init_stream = 0;
1603
1604         if (ios->power_mode != host->power_mode) {
1605                 switch (ios->power_mode) {
1606                 case MMC_POWER_OFF:
1607                         omap_hsmmc_set_power(host, 0);
1608                         break;
1609                 case MMC_POWER_UP:
1610                         omap_hsmmc_set_power(host, 1);
1611                         break;
1612                 case MMC_POWER_ON:
1613                         do_send_init_stream = 1;
1614                         break;
1615                 }
1616                 host->power_mode = ios->power_mode;
1617         }
1618
1619         /* FIXME: set registers based only on changes to ios */
1620
1621         omap_hsmmc_set_bus_width(host);
1622
1623         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1624                 /* Only MMC1 can interface at 3V without some flavor
1625                  * of external transceiver; but they all handle 1.8V.
1626                  */
1627                 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1628                         (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1629                                 /*
1630                                  * The mmc_select_voltage fn of the core does
1631                                  * not seem to set the power_mode to
1632                                  * MMC_POWER_UP upon recalculating the voltage.
1633                                  * vdd 1.8v.
1634                                  */
1635                         if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1636                                 dev_dbg(mmc_dev(host->mmc),
1637                                                 "Switch operation failed\n");
1638                 }
1639         }
1640
1641         omap_hsmmc_set_clock(host);
1642
1643         if (do_send_init_stream)
1644                 send_init_stream(host);
1645
1646         omap_hsmmc_set_bus_mode(host);
1647 }
1648
1649 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1650 {
1651         struct omap_hsmmc_host *host = mmc_priv(mmc);
1652
1653         if (!host->card_detect)
1654                 return -ENOSYS;
1655         return host->card_detect(host->dev);
1656 }
1657
1658 static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1659 {
1660         struct omap_hsmmc_host *host = mmc_priv(mmc);
1661
1662         if (mmc_pdata(host)->init_card)
1663                 mmc_pdata(host)->init_card(card);
1664         else if (card->type == MMC_TYPE_SDIO ||
1665                  card->type == MMC_TYPE_SD_COMBO) {
1666                 struct device_node *np = mmc_dev(mmc)->of_node;
1667
1668                 /*
1669                  * REVISIT: should be moved to sdio core and made more
1670                  * general e.g. by expanding the DT bindings of child nodes
1671                  * to provide a mechanism to provide this information:
1672                  * Documentation/devicetree/bindings/mmc/mmc-card.txt
1673                  */
1674
1675                 np = of_get_compatible_child(np, "ti,wl1251");
1676                 if (np) {
1677                         /*
1678                          * We have TI wl1251 attached to MMC3. Pass this
1679                          * information to the SDIO core because it can't be
1680                          * probed by normal methods.
1681                          */
1682
1683                         dev_info(host->dev, "found wl1251\n");
1684                         card->quirks |= MMC_QUIRK_NONSTD_SDIO;
1685                         card->cccr.wide_bus = 1;
1686                         card->cis.vendor = 0x104c;
1687                         card->cis.device = 0x9066;
1688                         card->cis.blksize = 512;
1689                         card->cis.max_dtr = 24000000;
1690                         card->ocr = 0x80;
1691                         of_node_put(np);
1692                 }
1693         }
1694 }
1695
1696 static void omap_hsmmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
1697 {
1698         struct omap_hsmmc_host *host = mmc_priv(mmc);
1699         u32 irq_mask, con;
1700         unsigned long flags;
1701
1702         spin_lock_irqsave(&host->irq_lock, flags);
1703
1704         con = OMAP_HSMMC_READ(host->base, CON);
1705         irq_mask = OMAP_HSMMC_READ(host->base, ISE);
1706         if (enable) {
1707                 host->flags |= HSMMC_SDIO_IRQ_ENABLED;
1708                 irq_mask |= CIRQ_EN;
1709                 con |= CTPL | CLKEXTFREE;
1710         } else {
1711                 host->flags &= ~HSMMC_SDIO_IRQ_ENABLED;
1712                 irq_mask &= ~CIRQ_EN;
1713                 con &= ~(CTPL | CLKEXTFREE);
1714         }
1715         OMAP_HSMMC_WRITE(host->base, CON, con);
1716         OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
1717
1718         /*
1719          * if enable, piggy back detection on current request
1720          * but always disable immediately
1721          */
1722         if (!host->req_in_progress || !enable)
1723                 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
1724
1725         /* flush posted write */
1726         OMAP_HSMMC_READ(host->base, IE);
1727
1728         spin_unlock_irqrestore(&host->irq_lock, flags);
1729 }
1730
1731 static int omap_hsmmc_configure_wake_irq(struct omap_hsmmc_host *host)
1732 {
1733         int ret;
1734
1735         /*
1736          * For omaps with wake-up path, wakeirq will be irq from pinctrl and
1737          * for other omaps, wakeirq will be from GPIO (dat line remuxed to
1738          * gpio). wakeirq is needed to detect sdio irq in runtime suspend state
1739          * with functional clock disabled.
1740          */
1741         if (!host->dev->of_node || !host->wake_irq)
1742                 return -ENODEV;
1743
1744         ret = dev_pm_set_dedicated_wake_irq(host->dev, host->wake_irq);
1745         if (ret) {
1746                 dev_err(mmc_dev(host->mmc), "Unable to request wake IRQ\n");
1747                 goto err;
1748         }
1749
1750         /*
1751          * Some omaps don't have wake-up path from deeper idle states
1752          * and need to remux SDIO DAT1 to GPIO for wake-up from idle.
1753          */
1754         if (host->pdata->controller_flags & OMAP_HSMMC_SWAKEUP_MISSING) {
1755                 struct pinctrl *p = devm_pinctrl_get(host->dev);
1756                 if (IS_ERR(p)) {
1757                         ret = PTR_ERR(p);
1758                         goto err_free_irq;
1759                 }
1760                 if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_DEFAULT))) {
1761                         dev_info(host->dev, "missing default pinctrl state\n");
1762                         devm_pinctrl_put(p);
1763                         ret = -EINVAL;
1764                         goto err_free_irq;
1765                 }
1766
1767                 if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_IDLE))) {
1768                         dev_info(host->dev, "missing idle pinctrl state\n");
1769                         devm_pinctrl_put(p);
1770                         ret = -EINVAL;
1771                         goto err_free_irq;
1772                 }
1773                 devm_pinctrl_put(p);
1774         }
1775
1776         OMAP_HSMMC_WRITE(host->base, HCTL,
1777                          OMAP_HSMMC_READ(host->base, HCTL) | IWE);
1778         return 0;
1779
1780 err_free_irq:
1781         dev_pm_clear_wake_irq(host->dev);
1782 err:
1783         dev_warn(host->dev, "no SDIO IRQ support, falling back to polling\n");
1784         host->wake_irq = 0;
1785         return ret;
1786 }
1787
1788 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1789 {
1790         u32 hctl, capa, value;
1791
1792         /* Only MMC1 supports 3.0V */
1793         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1794                 hctl = SDVS30;
1795                 capa = VS30 | VS18;
1796         } else {
1797                 hctl = SDVS18;
1798                 capa = VS18;
1799         }
1800
1801         value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1802         OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1803
1804         value = OMAP_HSMMC_READ(host->base, CAPA);
1805         OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1806
1807         /* Set SD bus power bit */
1808         set_sd_bus_power(host);
1809 }
1810
1811 static int omap_hsmmc_multi_io_quirk(struct mmc_card *card,
1812                                      unsigned int direction, int blk_size)
1813 {
1814         /* This controller can't do multiblock reads due to hw bugs */
1815         if (direction == MMC_DATA_READ)
1816                 return 1;
1817
1818         return blk_size;
1819 }
1820
1821 static struct mmc_host_ops omap_hsmmc_ops = {
1822         .post_req = omap_hsmmc_post_req,
1823         .pre_req = omap_hsmmc_pre_req,
1824         .request = omap_hsmmc_request,
1825         .set_ios = omap_hsmmc_set_ios,
1826         .get_cd = omap_hsmmc_get_cd,
1827         .get_ro = mmc_gpio_get_ro,
1828         .init_card = omap_hsmmc_init_card,
1829         .enable_sdio_irq = omap_hsmmc_enable_sdio_irq,
1830 };
1831
1832 #ifdef CONFIG_DEBUG_FS
1833
1834 static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
1835 {
1836         struct mmc_host *mmc = s->private;
1837         struct omap_hsmmc_host *host = mmc_priv(mmc);
1838
1839         seq_printf(s, "mmc%d:\n", mmc->index);
1840         seq_printf(s, "sdio irq mode\t%s\n",
1841                    (mmc->caps & MMC_CAP_SDIO_IRQ) ? "interrupt" : "polling");
1842
1843         if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1844                 seq_printf(s, "sdio irq \t%s\n",
1845                            (host->flags & HSMMC_SDIO_IRQ_ENABLED) ?  "enabled"
1846                            : "disabled");
1847         }
1848         seq_printf(s, "ctx_loss:\t%d\n", host->context_loss);
1849
1850         pm_runtime_get_sync(host->dev);
1851         seq_puts(s, "\nregs:\n");
1852         seq_printf(s, "CON:\t\t0x%08x\n",
1853                         OMAP_HSMMC_READ(host->base, CON));
1854         seq_printf(s, "PSTATE:\t\t0x%08x\n",
1855                    OMAP_HSMMC_READ(host->base, PSTATE));
1856         seq_printf(s, "HCTL:\t\t0x%08x\n",
1857                         OMAP_HSMMC_READ(host->base, HCTL));
1858         seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1859                         OMAP_HSMMC_READ(host->base, SYSCTL));
1860         seq_printf(s, "IE:\t\t0x%08x\n",
1861                         OMAP_HSMMC_READ(host->base, IE));
1862         seq_printf(s, "ISE:\t\t0x%08x\n",
1863                         OMAP_HSMMC_READ(host->base, ISE));
1864         seq_printf(s, "CAPA:\t\t0x%08x\n",
1865                         OMAP_HSMMC_READ(host->base, CAPA));
1866
1867         pm_runtime_mark_last_busy(host->dev);
1868         pm_runtime_put_autosuspend(host->dev);
1869
1870         return 0;
1871 }
1872
1873 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
1874 {
1875         return single_open(file, omap_hsmmc_regs_show, inode->i_private);
1876 }
1877
1878 static const struct file_operations mmc_regs_fops = {
1879         .open           = omap_hsmmc_regs_open,
1880         .read           = seq_read,
1881         .llseek         = seq_lseek,
1882         .release        = single_release,
1883 };
1884
1885 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1886 {
1887         if (mmc->debugfs_root)
1888                 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1889                         mmc, &mmc_regs_fops);
1890 }
1891
1892 #else
1893
1894 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1895 {
1896 }
1897
1898 #endif
1899
1900 #ifdef CONFIG_OF
1901 static const struct omap_mmc_of_data omap3_pre_es3_mmc_of_data = {
1902         /* See 35xx errata 2.1.1.128 in SPRZ278F */
1903         .controller_flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1904 };
1905
1906 static const struct omap_mmc_of_data omap4_mmc_of_data = {
1907         .reg_offset = 0x100,
1908 };
1909 static const struct omap_mmc_of_data am33xx_mmc_of_data = {
1910         .reg_offset = 0x100,
1911         .controller_flags = OMAP_HSMMC_SWAKEUP_MISSING,
1912 };
1913
1914 static const struct of_device_id omap_mmc_of_match[] = {
1915         {
1916                 .compatible = "ti,omap2-hsmmc",
1917         },
1918         {
1919                 .compatible = "ti,omap3-pre-es3-hsmmc",
1920                 .data = &omap3_pre_es3_mmc_of_data,
1921         },
1922         {
1923                 .compatible = "ti,omap3-hsmmc",
1924         },
1925         {
1926                 .compatible = "ti,omap4-hsmmc",
1927                 .data = &omap4_mmc_of_data,
1928         },
1929         {
1930                 .compatible = "ti,am33xx-hsmmc",
1931                 .data = &am33xx_mmc_of_data,
1932         },
1933         {},
1934 };
1935 MODULE_DEVICE_TABLE(of, omap_mmc_of_match);
1936
1937 static struct omap_hsmmc_platform_data *of_get_hsmmc_pdata(struct device *dev)
1938 {
1939         struct omap_hsmmc_platform_data *pdata, *legacy;
1940         struct device_node *np = dev->of_node;
1941
1942         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
1943         if (!pdata)
1944                 return ERR_PTR(-ENOMEM); /* out of memory */
1945
1946         legacy = dev_get_platdata(dev);
1947         if (legacy && legacy->name)
1948                 pdata->name = legacy->name;
1949
1950         if (of_find_property(np, "ti,dual-volt", NULL))
1951                 pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1952
1953         pdata->gpio_cd = -EINVAL;
1954         pdata->gpio_cod = -EINVAL;
1955         pdata->gpio_wp = -EINVAL;
1956
1957         if (of_find_property(np, "ti,non-removable", NULL)) {
1958                 pdata->nonremovable = true;
1959                 pdata->no_regulator_off_init = true;
1960         }
1961
1962         if (of_find_property(np, "ti,needs-special-reset", NULL))
1963                 pdata->features |= HSMMC_HAS_UPDATED_RESET;
1964
1965         if (of_find_property(np, "ti,needs-special-hs-handling", NULL))
1966                 pdata->features |= HSMMC_HAS_HSPE_SUPPORT;
1967
1968         return pdata;
1969 }
1970 #else
1971 static inline struct omap_hsmmc_platform_data
1972                         *of_get_hsmmc_pdata(struct device *dev)
1973 {
1974         return ERR_PTR(-EINVAL);
1975 }
1976 #endif
1977
1978 static int omap_hsmmc_probe(struct platform_device *pdev)
1979 {
1980         struct omap_hsmmc_platform_data *pdata = pdev->dev.platform_data;
1981         struct mmc_host *mmc;
1982         struct omap_hsmmc_host *host = NULL;
1983         struct resource *res;
1984         int ret, irq;
1985         const struct of_device_id *match;
1986         const struct omap_mmc_of_data *data;
1987         void __iomem *base;
1988
1989         match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev);
1990         if (match) {
1991                 pdata = of_get_hsmmc_pdata(&pdev->dev);
1992
1993                 if (IS_ERR(pdata))
1994                         return PTR_ERR(pdata);
1995
1996                 if (match->data) {
1997                         data = match->data;
1998                         pdata->reg_offset = data->reg_offset;
1999                         pdata->controller_flags |= data->controller_flags;
2000                 }
2001         }
2002
2003         if (pdata == NULL) {
2004                 dev_err(&pdev->dev, "Platform Data is missing\n");
2005                 return -ENXIO;
2006         }
2007
2008         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2009         irq = platform_get_irq(pdev, 0);
2010         if (res == NULL || irq < 0)
2011                 return -ENXIO;
2012
2013         base = devm_ioremap_resource(&pdev->dev, res);
2014         if (IS_ERR(base))
2015                 return PTR_ERR(base);
2016
2017         mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
2018         if (!mmc) {
2019                 ret = -ENOMEM;
2020                 goto err;
2021         }
2022
2023         ret = mmc_of_parse(mmc);
2024         if (ret)
2025                 goto err1;
2026
2027         host            = mmc_priv(mmc);
2028         host->mmc       = mmc;
2029         host->pdata     = pdata;
2030         host->dev       = &pdev->dev;
2031         host->use_dma   = 1;
2032         host->dma_ch    = -1;
2033         host->irq       = irq;
2034         host->mapbase   = res->start + pdata->reg_offset;
2035         host->base      = base + pdata->reg_offset;
2036         host->power_mode = MMC_POWER_OFF;
2037         host->next_data.cookie = 1;
2038         host->pbias_enabled = 0;
2039         host->vqmmc_enabled = 0;
2040
2041         ret = omap_hsmmc_gpio_init(mmc, host, pdata);
2042         if (ret)
2043                 goto err_gpio;
2044
2045         platform_set_drvdata(pdev, host);
2046
2047         if (pdev->dev.of_node)
2048                 host->wake_irq = irq_of_parse_and_map(pdev->dev.of_node, 1);
2049
2050         mmc->ops        = &omap_hsmmc_ops;
2051
2052         mmc->f_min = OMAP_MMC_MIN_CLOCK;
2053
2054         if (pdata->max_freq > 0)
2055                 mmc->f_max = pdata->max_freq;
2056         else if (mmc->f_max == 0)
2057                 mmc->f_max = OMAP_MMC_MAX_CLOCK;
2058
2059         spin_lock_init(&host->irq_lock);
2060
2061         host->fclk = devm_clk_get(&pdev->dev, "fck");
2062         if (IS_ERR(host->fclk)) {
2063                 ret = PTR_ERR(host->fclk);
2064                 host->fclk = NULL;
2065                 goto err1;
2066         }
2067
2068         if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
2069                 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
2070                 omap_hsmmc_ops.multi_io_quirk = omap_hsmmc_multi_io_quirk;
2071         }
2072
2073         device_init_wakeup(&pdev->dev, true);
2074         pm_runtime_enable(host->dev);
2075         pm_runtime_get_sync(host->dev);
2076         pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
2077         pm_runtime_use_autosuspend(host->dev);
2078
2079         omap_hsmmc_context_save(host);
2080
2081         host->dbclk = devm_clk_get(&pdev->dev, "mmchsdb_fck");
2082         /*
2083          * MMC can still work without debounce clock.
2084          */
2085         if (IS_ERR(host->dbclk)) {
2086                 host->dbclk = NULL;
2087         } else if (clk_prepare_enable(host->dbclk) != 0) {
2088                 dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n");
2089                 host->dbclk = NULL;
2090         }
2091
2092         /* Set this to a value that allows allocating an entire descriptor
2093          * list within a page (zero order allocation). */
2094         mmc->max_segs = 64;
2095
2096         mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */
2097         mmc->max_blk_count = 0xFFFF;    /* No. of Blocks is 16 bits */
2098         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2099
2100         mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
2101                      MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE | MMC_CAP_CMD23;
2102
2103         mmc->caps |= mmc_pdata(host)->caps;
2104         if (mmc->caps & MMC_CAP_8_BIT_DATA)
2105                 mmc->caps |= MMC_CAP_4_BIT_DATA;
2106
2107         if (mmc_pdata(host)->nonremovable)
2108                 mmc->caps |= MMC_CAP_NONREMOVABLE;
2109
2110         mmc->pm_caps |= mmc_pdata(host)->pm_caps;
2111
2112         omap_hsmmc_conf_bus_power(host);
2113
2114         host->rx_chan = dma_request_chan(&pdev->dev, "rx");
2115         if (IS_ERR(host->rx_chan)) {
2116                 dev_err(mmc_dev(host->mmc), "RX DMA channel request failed\n");
2117                 ret = PTR_ERR(host->rx_chan);
2118                 goto err_irq;
2119         }
2120
2121         host->tx_chan = dma_request_chan(&pdev->dev, "tx");
2122         if (IS_ERR(host->tx_chan)) {
2123                 dev_err(mmc_dev(host->mmc), "TX DMA channel request failed\n");
2124                 ret = PTR_ERR(host->tx_chan);
2125                 goto err_irq;
2126         }
2127
2128         /*
2129          * Limit the maximum segment size to the lower of the request size
2130          * and the DMA engine device segment size limits.  In reality, with
2131          * 32-bit transfers, the DMA engine can do longer segments than this
2132          * but there is no way to represent that in the DMA model - if we
2133          * increase this figure here, we get warnings from the DMA API debug.
2134          */
2135         mmc->max_seg_size = min3(mmc->max_req_size,
2136                         dma_get_max_seg_size(host->rx_chan->device->dev),
2137                         dma_get_max_seg_size(host->tx_chan->device->dev));
2138
2139         /* Request IRQ for MMC operations */
2140         ret = devm_request_irq(&pdev->dev, host->irq, omap_hsmmc_irq, 0,
2141                         mmc_hostname(mmc), host);
2142         if (ret) {
2143                 dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
2144                 goto err_irq;
2145         }
2146
2147         ret = omap_hsmmc_reg_get(host);
2148         if (ret)
2149                 goto err_irq;
2150
2151         if (!mmc->ocr_avail)
2152                 mmc->ocr_avail = mmc_pdata(host)->ocr_mask;
2153
2154         omap_hsmmc_disable_irq(host);
2155
2156         /*
2157          * For now, only support SDIO interrupt if we have a separate
2158          * wake-up interrupt configured from device tree. This is because
2159          * the wake-up interrupt is needed for idle state and some
2160          * platforms need special quirks. And we don't want to add new
2161          * legacy mux platform init code callbacks any longer as we
2162          * are moving to DT based booting anyways.
2163          */
2164         ret = omap_hsmmc_configure_wake_irq(host);
2165         if (!ret)
2166                 mmc->caps |= MMC_CAP_SDIO_IRQ;
2167
2168         omap_hsmmc_protect_card(host);
2169
2170         mmc_add_host(mmc);
2171
2172         if (mmc_pdata(host)->name != NULL) {
2173                 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
2174                 if (ret < 0)
2175                         goto err_slot_name;
2176         }
2177         if (host->get_cover_state) {
2178                 ret = device_create_file(&mmc->class_dev,
2179                                          &dev_attr_cover_switch);
2180                 if (ret < 0)
2181                         goto err_slot_name;
2182         }
2183
2184         omap_hsmmc_debugfs(mmc);
2185         pm_runtime_mark_last_busy(host->dev);
2186         pm_runtime_put_autosuspend(host->dev);
2187
2188         return 0;
2189
2190 err_slot_name:
2191         mmc_remove_host(mmc);
2192 err_irq:
2193         device_init_wakeup(&pdev->dev, false);
2194         if (!IS_ERR_OR_NULL(host->tx_chan))
2195                 dma_release_channel(host->tx_chan);
2196         if (!IS_ERR_OR_NULL(host->rx_chan))
2197                 dma_release_channel(host->rx_chan);
2198         pm_runtime_dont_use_autosuspend(host->dev);
2199         pm_runtime_put_sync(host->dev);
2200         pm_runtime_disable(host->dev);
2201         if (host->dbclk)
2202                 clk_disable_unprepare(host->dbclk);
2203 err1:
2204 err_gpio:
2205         mmc_free_host(mmc);
2206 err:
2207         return ret;
2208 }
2209
2210 static int omap_hsmmc_remove(struct platform_device *pdev)
2211 {
2212         struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2213
2214         pm_runtime_get_sync(host->dev);
2215         mmc_remove_host(host->mmc);
2216
2217         dma_release_channel(host->tx_chan);
2218         dma_release_channel(host->rx_chan);
2219
2220         dev_pm_clear_wake_irq(host->dev);
2221         pm_runtime_dont_use_autosuspend(host->dev);
2222         pm_runtime_put_sync(host->dev);
2223         pm_runtime_disable(host->dev);
2224         device_init_wakeup(&pdev->dev, false);
2225         if (host->dbclk)
2226                 clk_disable_unprepare(host->dbclk);
2227
2228         mmc_free_host(host->mmc);
2229
2230         return 0;
2231 }
2232
2233 #ifdef CONFIG_PM_SLEEP
2234 static int omap_hsmmc_suspend(struct device *dev)
2235 {
2236         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2237
2238         if (!host)
2239                 return 0;
2240
2241         pm_runtime_get_sync(host->dev);
2242
2243         if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
2244                 OMAP_HSMMC_WRITE(host->base, ISE, 0);
2245                 OMAP_HSMMC_WRITE(host->base, IE, 0);
2246                 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2247                 OMAP_HSMMC_WRITE(host->base, HCTL,
2248                                 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2249         }
2250
2251         if (host->dbclk)
2252                 clk_disable_unprepare(host->dbclk);
2253
2254         pm_runtime_put_sync(host->dev);
2255         return 0;
2256 }
2257
2258 /* Routine to resume the MMC device */
2259 static int omap_hsmmc_resume(struct device *dev)
2260 {
2261         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2262
2263         if (!host)
2264                 return 0;
2265
2266         pm_runtime_get_sync(host->dev);
2267
2268         if (host->dbclk)
2269                 clk_prepare_enable(host->dbclk);
2270
2271         if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
2272                 omap_hsmmc_conf_bus_power(host);
2273
2274         omap_hsmmc_protect_card(host);
2275         pm_runtime_mark_last_busy(host->dev);
2276         pm_runtime_put_autosuspend(host->dev);
2277         return 0;
2278 }
2279 #endif
2280
2281 static int omap_hsmmc_runtime_suspend(struct device *dev)
2282 {
2283         struct omap_hsmmc_host *host;
2284         unsigned long flags;
2285         int ret = 0;
2286
2287         host = platform_get_drvdata(to_platform_device(dev));
2288         omap_hsmmc_context_save(host);
2289         dev_dbg(dev, "disabled\n");
2290
2291         spin_lock_irqsave(&host->irq_lock, flags);
2292         if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2293             (host->flags & HSMMC_SDIO_IRQ_ENABLED)) {
2294                 /* disable sdio irq handling to prevent race */
2295                 OMAP_HSMMC_WRITE(host->base, ISE, 0);
2296                 OMAP_HSMMC_WRITE(host->base, IE, 0);
2297
2298                 if (!(OMAP_HSMMC_READ(host->base, PSTATE) & DLEV_DAT(1))) {
2299                         /*
2300                          * dat1 line low, pending sdio irq
2301                          * race condition: possible irq handler running on
2302                          * multi-core, abort
2303                          */
2304                         dev_dbg(dev, "pending sdio irq, abort suspend\n");
2305                         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2306                         OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN);
2307                         OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN);
2308                         pm_runtime_mark_last_busy(dev);
2309                         ret = -EBUSY;
2310                         goto abort;
2311                 }
2312
2313                 pinctrl_pm_select_idle_state(dev);
2314         } else {
2315                 pinctrl_pm_select_idle_state(dev);
2316         }
2317
2318 abort:
2319         spin_unlock_irqrestore(&host->irq_lock, flags);
2320         return ret;
2321 }
2322
2323 static int omap_hsmmc_runtime_resume(struct device *dev)
2324 {
2325         struct omap_hsmmc_host *host;
2326         unsigned long flags;
2327
2328         host = platform_get_drvdata(to_platform_device(dev));
2329         omap_hsmmc_context_restore(host);
2330         dev_dbg(dev, "enabled\n");
2331
2332         spin_lock_irqsave(&host->irq_lock, flags);
2333         if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2334             (host->flags & HSMMC_SDIO_IRQ_ENABLED)) {
2335
2336                 pinctrl_pm_select_default_state(host->dev);
2337
2338                 /* irq lost, if pinmux incorrect */
2339                 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2340                 OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN);
2341                 OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN);
2342         } else {
2343                 pinctrl_pm_select_default_state(host->dev);
2344         }
2345         spin_unlock_irqrestore(&host->irq_lock, flags);
2346         return 0;
2347 }
2348
2349 static const struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
2350         SET_SYSTEM_SLEEP_PM_OPS(omap_hsmmc_suspend, omap_hsmmc_resume)
2351         .runtime_suspend = omap_hsmmc_runtime_suspend,
2352         .runtime_resume = omap_hsmmc_runtime_resume,
2353 };
2354
2355 static struct platform_driver omap_hsmmc_driver = {
2356         .probe          = omap_hsmmc_probe,
2357         .remove         = omap_hsmmc_remove,
2358         .driver         = {
2359                 .name = DRIVER_NAME,
2360                 .pm = &omap_hsmmc_dev_pm_ops,
2361                 .of_match_table = of_match_ptr(omap_mmc_of_match),
2362         },
2363 };
2364
2365 module_platform_driver(omap_hsmmc_driver);
2366 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2367 MODULE_LICENSE("GPL");
2368 MODULE_ALIAS("platform:" DRIVER_NAME);
2369 MODULE_AUTHOR("Texas Instruments Inc");