2 * Copyright (c) 2014-2015 MediaTek Inc.
3 * Author: Chaotian.Jing <chaotian.jing@mediatek.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #include <linux/module.h>
16 #include <linux/clk.h>
17 #include <linux/delay.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/ioport.h>
20 #include <linux/irq.h>
21 #include <linux/of_address.h>
22 #include <linux/of_irq.h>
23 #include <linux/of_gpio.h>
24 #include <linux/pinctrl/consumer.h>
25 #include <linux/platform_device.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/regulator/consumer.h>
29 #include <linux/slab.h>
30 #include <linux/spinlock.h>
31 #include <linux/interrupt.h>
33 #include <linux/mmc/card.h>
34 #include <linux/mmc/core.h>
35 #include <linux/mmc/host.h>
36 #include <linux/mmc/mmc.h>
37 #include <linux/mmc/sd.h>
38 #include <linux/mmc/sdio.h>
39 #include <linux/mmc/slot-gpio.h>
41 #define MAX_BD_NUM 1024
43 /*--------------------------------------------------------------------------*/
44 /* Common Definition */
45 /*--------------------------------------------------------------------------*/
46 #define MSDC_BUS_1BITS 0x0
47 #define MSDC_BUS_4BITS 0x1
48 #define MSDC_BUS_8BITS 0x2
50 #define MSDC_BURST_64B 0x6
52 /*--------------------------------------------------------------------------*/
54 /*--------------------------------------------------------------------------*/
56 #define MSDC_IOCON 0x04
59 #define MSDC_INTEN 0x10
60 #define MSDC_FIFOCS 0x14
65 #define SDC_RESP0 0x40
66 #define SDC_RESP1 0x44
67 #define SDC_RESP2 0x48
68 #define SDC_RESP3 0x4c
69 #define SDC_BLK_NUM 0x50
70 #define EMMC_IOCON 0x7c
71 #define SDC_ACMD_RESP 0x80
72 #define MSDC_DMA_SA 0x90
73 #define MSDC_DMA_CTRL 0x98
74 #define MSDC_DMA_CFG 0x9c
75 #define MSDC_PATCH_BIT 0xb0
76 #define MSDC_PATCH_BIT1 0xb4
77 #define MSDC_PAD_TUNE 0xec
78 #define PAD_DS_TUNE 0x188
79 #define PAD_CMD_TUNE 0x18c
80 #define EMMC50_CFG0 0x208
82 /*--------------------------------------------------------------------------*/
84 /*--------------------------------------------------------------------------*/
87 #define MSDC_CFG_MODE (0x1 << 0) /* RW */
88 #define MSDC_CFG_CKPDN (0x1 << 1) /* RW */
89 #define MSDC_CFG_RST (0x1 << 2) /* RW */
90 #define MSDC_CFG_PIO (0x1 << 3) /* RW */
91 #define MSDC_CFG_CKDRVEN (0x1 << 4) /* RW */
92 #define MSDC_CFG_BV18SDT (0x1 << 5) /* RW */
93 #define MSDC_CFG_BV18PSS (0x1 << 6) /* R */
94 #define MSDC_CFG_CKSTB (0x1 << 7) /* R */
95 #define MSDC_CFG_CKDIV (0xff << 8) /* RW */
96 #define MSDC_CFG_CKMOD (0x3 << 16) /* RW */
97 #define MSDC_CFG_HS400_CK_MODE (0x1 << 18) /* RW */
100 #define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */
101 #define MSDC_IOCON_RSPL (0x1 << 1) /* RW */
102 #define MSDC_IOCON_DSPL (0x1 << 2) /* RW */
103 #define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */
104 #define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */
105 #define MSDC_IOCON_DSPLSEL (0x1 << 5) /* RW */
106 #define MSDC_IOCON_W_DSPL (0x1 << 8) /* RW */
107 #define MSDC_IOCON_D0SPL (0x1 << 16) /* RW */
108 #define MSDC_IOCON_D1SPL (0x1 << 17) /* RW */
109 #define MSDC_IOCON_D2SPL (0x1 << 18) /* RW */
110 #define MSDC_IOCON_D3SPL (0x1 << 19) /* RW */
111 #define MSDC_IOCON_D4SPL (0x1 << 20) /* RW */
112 #define MSDC_IOCON_D5SPL (0x1 << 21) /* RW */
113 #define MSDC_IOCON_D6SPL (0x1 << 22) /* RW */
114 #define MSDC_IOCON_D7SPL (0x1 << 23) /* RW */
115 #define MSDC_IOCON_RISCSZ (0x3 << 24) /* RW */
118 #define MSDC_PS_CDEN (0x1 << 0) /* RW */
119 #define MSDC_PS_CDSTS (0x1 << 1) /* R */
120 #define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */
121 #define MSDC_PS_DAT (0xff << 16) /* R */
122 #define MSDC_PS_CMD (0x1 << 24) /* R */
123 #define MSDC_PS_WP (0x1 << 31) /* R */
126 #define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */
127 #define MSDC_INT_CDSC (0x1 << 1) /* W1C */
128 #define MSDC_INT_ACMDRDY (0x1 << 3) /* W1C */
129 #define MSDC_INT_ACMDTMO (0x1 << 4) /* W1C */
130 #define MSDC_INT_ACMDCRCERR (0x1 << 5) /* W1C */
131 #define MSDC_INT_DMAQ_EMPTY (0x1 << 6) /* W1C */
132 #define MSDC_INT_SDIOIRQ (0x1 << 7) /* W1C */
133 #define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */
134 #define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */
135 #define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */
136 #define MSDC_INT_CSTA (0x1 << 11) /* R */
137 #define MSDC_INT_XFER_COMPL (0x1 << 12) /* W1C */
138 #define MSDC_INT_DXFER_DONE (0x1 << 13) /* W1C */
139 #define MSDC_INT_DATTMO (0x1 << 14) /* W1C */
140 #define MSDC_INT_DATCRCERR (0x1 << 15) /* W1C */
141 #define MSDC_INT_ACMD19_DONE (0x1 << 16) /* W1C */
142 #define MSDC_INT_DMA_BDCSERR (0x1 << 17) /* W1C */
143 #define MSDC_INT_DMA_GPDCSERR (0x1 << 18) /* W1C */
144 #define MSDC_INT_DMA_PROTECT (0x1 << 19) /* W1C */
146 /* MSDC_INTEN mask */
147 #define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */
148 #define MSDC_INTEN_CDSC (0x1 << 1) /* RW */
149 #define MSDC_INTEN_ACMDRDY (0x1 << 3) /* RW */
150 #define MSDC_INTEN_ACMDTMO (0x1 << 4) /* RW */
151 #define MSDC_INTEN_ACMDCRCERR (0x1 << 5) /* RW */
152 #define MSDC_INTEN_DMAQ_EMPTY (0x1 << 6) /* RW */
153 #define MSDC_INTEN_SDIOIRQ (0x1 << 7) /* RW */
154 #define MSDC_INTEN_CMDRDY (0x1 << 8) /* RW */
155 #define MSDC_INTEN_CMDTMO (0x1 << 9) /* RW */
156 #define MSDC_INTEN_RSPCRCERR (0x1 << 10) /* RW */
157 #define MSDC_INTEN_CSTA (0x1 << 11) /* RW */
158 #define MSDC_INTEN_XFER_COMPL (0x1 << 12) /* RW */
159 #define MSDC_INTEN_DXFER_DONE (0x1 << 13) /* RW */
160 #define MSDC_INTEN_DATTMO (0x1 << 14) /* RW */
161 #define MSDC_INTEN_DATCRCERR (0x1 << 15) /* RW */
162 #define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */
163 #define MSDC_INTEN_DMA_BDCSERR (0x1 << 17) /* RW */
164 #define MSDC_INTEN_DMA_GPDCSERR (0x1 << 18) /* RW */
165 #define MSDC_INTEN_DMA_PROTECT (0x1 << 19) /* RW */
167 /* MSDC_FIFOCS mask */
168 #define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */
169 #define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */
170 #define MSDC_FIFOCS_CLR (0x1 << 31) /* RW */
173 #define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */
174 #define SDC_CFG_INSWKUP (0x1 << 1) /* RW */
175 #define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */
176 #define SDC_CFG_SDIO (0x1 << 19) /* RW */
177 #define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */
178 #define SDC_CFG_INTATGAP (0x1 << 21) /* RW */
179 #define SDC_CFG_DTOC (0xff << 24) /* RW */
182 #define SDC_STS_SDCBUSY (0x1 << 0) /* RW */
183 #define SDC_STS_CMDBUSY (0x1 << 1) /* RW */
184 #define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */
186 /* MSDC_DMA_CTRL mask */
187 #define MSDC_DMA_CTRL_START (0x1 << 0) /* W */
188 #define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */
189 #define MSDC_DMA_CTRL_RESUME (0x1 << 2) /* W */
190 #define MSDC_DMA_CTRL_MODE (0x1 << 8) /* RW */
191 #define MSDC_DMA_CTRL_LASTBUF (0x1 << 10) /* RW */
192 #define MSDC_DMA_CTRL_BRUSTSZ (0x7 << 12) /* RW */
194 /* MSDC_DMA_CFG mask */
195 #define MSDC_DMA_CFG_STS (0x1 << 0) /* R */
196 #define MSDC_DMA_CFG_DECSEN (0x1 << 1) /* RW */
197 #define MSDC_DMA_CFG_AHBHPROT2 (0x2 << 8) /* RW */
198 #define MSDC_DMA_CFG_ACTIVEEN (0x2 << 12) /* RW */
199 #define MSDC_DMA_CFG_CS12B16B (0x1 << 16) /* RW */
201 /* MSDC_PATCH_BIT mask */
202 #define MSDC_PATCH_BIT_ODDSUPP (0x1 << 1) /* RW */
203 #define MSDC_INT_DAT_LATCH_CK_SEL (0x7 << 7)
204 #define MSDC_CKGEN_MSDC_DLY_SEL (0x1f << 10)
205 #define MSDC_PATCH_BIT_IODSSEL (0x1 << 16) /* RW */
206 #define MSDC_PATCH_BIT_IOINTSEL (0x1 << 17) /* RW */
207 #define MSDC_PATCH_BIT_BUSYDLY (0xf << 18) /* RW */
208 #define MSDC_PATCH_BIT_WDOD (0xf << 22) /* RW */
209 #define MSDC_PATCH_BIT_IDRTSEL (0x1 << 26) /* RW */
210 #define MSDC_PATCH_BIT_CMDFSEL (0x1 << 27) /* RW */
211 #define MSDC_PATCH_BIT_INTDLSEL (0x1 << 28) /* RW */
212 #define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */
213 #define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */
215 #define MSDC_PATCH_BIT1_CMDTA (0x7 << 3) /* RW */
217 #define MSDC_PAD_TUNE_DATWRDLY (0x1f << 0) /* RW */
218 #define MSDC_PAD_TUNE_DATRRDLY (0x1f << 8) /* RW */
219 #define MSDC_PAD_TUNE_CMDRDLY (0x1f << 16) /* RW */
220 #define MSDC_PAD_TUNE_CMDRRDLY (0x1f << 22) /* RW */
221 #define MSDC_PAD_TUNE_CLKTDLY (0x1f << 27) /* RW */
223 #define PAD_DS_TUNE_DLY1 (0x1f << 2) /* RW */
224 #define PAD_DS_TUNE_DLY2 (0x1f << 7) /* RW */
225 #define PAD_DS_TUNE_DLY3 (0x1f << 12) /* RW */
227 #define PAD_CMD_TUNE_RX_DLY3 (0x1f << 1) /* RW */
229 #define EMMC50_CFG_PADCMD_LATCHCK (0x1 << 0) /* RW */
230 #define EMMC50_CFG_CRCSTS_EDGE (0x1 << 3) /* RW */
231 #define EMMC50_CFG_CFCSTS_SEL (0x1 << 4) /* RW */
233 #define REQ_CMD_EIO (0x1 << 0)
234 #define REQ_CMD_TMO (0x1 << 1)
235 #define REQ_DAT_ERR (0x1 << 2)
236 #define REQ_STOP_EIO (0x1 << 3)
237 #define REQ_STOP_TMO (0x1 << 4)
238 #define REQ_CMD_BUSY (0x1 << 5)
240 #define MSDC_PREPARE_FLAG (0x1 << 0)
241 #define MSDC_ASYNC_FLAG (0x1 << 1)
242 #define MSDC_MMAP_FLAG (0x1 << 2)
244 #define MTK_MMC_AUTOSUSPEND_DELAY 50
245 #define CMD_TIMEOUT (HZ/10 * 5) /* 100ms x5 */
246 #define DAT_TIMEOUT (HZ * 5) /* 1000ms x5 */
248 #define PAD_DELAY_MAX 32 /* PAD delay cells */
249 /*--------------------------------------------------------------------------*/
250 /* Descriptor Structure */
251 /*--------------------------------------------------------------------------*/
252 struct mt_gpdma_desc {
254 #define GPDMA_DESC_HWO (0x1 << 0)
255 #define GPDMA_DESC_BDP (0x1 << 1)
256 #define GPDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */
257 #define GPDMA_DESC_INT (0x1 << 16)
261 #define GPDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */
262 #define GPDMA_DESC_EXTLEN (0xff << 16) /* bit16 ~ bit23 */
268 struct mt_bdma_desc {
270 #define BDMA_DESC_EOL (0x1 << 0)
271 #define BDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */
272 #define BDMA_DESC_BLKPAD (0x1 << 17)
273 #define BDMA_DESC_DWPAD (0x1 << 18)
277 #define BDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */
281 struct scatterlist *sg; /* I/O scatter list */
282 struct mt_gpdma_desc *gpd; /* pointer to gpd array */
283 struct mt_bdma_desc *bd; /* pointer to bd array */
284 dma_addr_t gpd_addr; /* the physical address of gpd array */
285 dma_addr_t bd_addr; /* the physical address of bd array */
288 struct msdc_save_para {
300 struct msdc_tune_para {
306 struct msdc_delay_phase {
314 struct mmc_host *mmc; /* mmc structure */
318 struct mmc_request *mrq;
319 struct mmc_command *cmd;
320 struct mmc_data *data;
323 void __iomem *base; /* host base address */
325 struct msdc_dma dma; /* dma channel */
328 u32 timeout_ns; /* data timeout ns */
329 u32 timeout_clks; /* data timeout clks */
331 struct pinctrl *pinctrl;
332 struct pinctrl_state *pins_default;
333 struct pinctrl_state *pins_uhs;
334 struct delayed_work req_timeout;
335 int irq; /* host interrupt */
337 struct clk *src_clk; /* msdc source clock */
338 struct clk *h_clk; /* msdc h_clk */
339 u32 mclk; /* mmc subsystem clock frequency */
340 u32 src_clk_freq; /* source clock frequency */
341 u32 sclk; /* SD/MS bus clock frequency */
342 unsigned char timing;
345 u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */
346 u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */
347 bool hs400_cmd_resp_sel_rising;
348 /* cmd response sample selection for HS400 */
349 bool hs400_mode; /* current eMMC will run at hs400 mode */
350 struct msdc_save_para save_para; /* used when gate HCLK */
351 struct msdc_tune_para def_tune_para; /* default tune setting */
352 struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */
355 static void sdr_set_bits(void __iomem *reg, u32 bs)
357 u32 val = readl(reg);
363 static void sdr_clr_bits(void __iomem *reg, u32 bs)
365 u32 val = readl(reg);
371 static void sdr_set_field(void __iomem *reg, u32 field, u32 val)
373 unsigned int tv = readl(reg);
376 tv |= ((val) << (ffs((unsigned int)field) - 1));
380 static void sdr_get_field(void __iomem *reg, u32 field, u32 *val)
382 unsigned int tv = readl(reg);
384 *val = ((tv & field) >> (ffs((unsigned int)field) - 1));
387 static void msdc_reset_hw(struct msdc_host *host)
391 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST);
392 while (readl(host->base + MSDC_CFG) & MSDC_CFG_RST)
395 sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR);
396 while (readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_CLR)
399 val = readl(host->base + MSDC_INT);
400 writel(val, host->base + MSDC_INT);
403 static void msdc_cmd_next(struct msdc_host *host,
404 struct mmc_request *mrq, struct mmc_command *cmd);
406 static const u32 cmd_ints_mask = MSDC_INTEN_CMDRDY | MSDC_INTEN_RSPCRCERR |
407 MSDC_INTEN_CMDTMO | MSDC_INTEN_ACMDRDY |
408 MSDC_INTEN_ACMDCRCERR | MSDC_INTEN_ACMDTMO;
409 static const u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO |
410 MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR |
411 MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT;
413 static u8 msdc_dma_calcs(u8 *buf, u32 len)
417 for (i = 0; i < len; i++)
419 return 0xff - (u8) sum;
422 static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma,
423 struct mmc_data *data)
425 unsigned int j, dma_len;
426 dma_addr_t dma_address;
428 struct scatterlist *sg;
429 struct mt_gpdma_desc *gpd;
430 struct mt_bdma_desc *bd;
438 gpd->gpd_info |= GPDMA_DESC_HWO;
439 gpd->gpd_info |= GPDMA_DESC_BDP;
440 /* need to clear first. use these bits to calc checksum */
441 gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM;
442 gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8;
445 for_each_sg(data->sg, sg, data->sg_count, j) {
446 dma_address = sg_dma_address(sg);
447 dma_len = sg_dma_len(sg);
450 bd[j].bd_info &= ~BDMA_DESC_BLKPAD;
451 bd[j].bd_info &= ~BDMA_DESC_DWPAD;
452 bd[j].ptr = (u32)dma_address;
453 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN;
454 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN);
456 if (j == data->sg_count - 1) /* the last bd */
457 bd[j].bd_info |= BDMA_DESC_EOL;
459 bd[j].bd_info &= ~BDMA_DESC_EOL;
461 /* checksume need to clear first */
462 bd[j].bd_info &= ~BDMA_DESC_CHECKSUM;
463 bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8;
466 sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1);
467 dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL);
468 dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE);
469 dma_ctrl |= (MSDC_BURST_64B << 12 | 1 << 8);
470 writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL);
471 writel((u32)dma->gpd_addr, host->base + MSDC_DMA_SA);
474 static void msdc_prepare_data(struct msdc_host *host, struct mmc_request *mrq)
476 struct mmc_data *data = mrq->data;
478 if (!(data->host_cookie & MSDC_PREPARE_FLAG)) {
479 data->host_cookie |= MSDC_PREPARE_FLAG;
480 data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len,
481 mmc_get_dma_dir(data));
485 static void msdc_unprepare_data(struct msdc_host *host, struct mmc_request *mrq)
487 struct mmc_data *data = mrq->data;
489 if (data->host_cookie & MSDC_ASYNC_FLAG)
492 if (data->host_cookie & MSDC_PREPARE_FLAG) {
493 dma_unmap_sg(host->dev, data->sg, data->sg_len,
494 mmc_get_dma_dir(data));
495 data->host_cookie &= ~MSDC_PREPARE_FLAG;
499 /* clock control primitives */
500 static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks)
505 host->timeout_ns = ns;
506 host->timeout_clks = clks;
507 if (host->sclk == 0) {
510 clk_ns = 1000000000UL / host->sclk;
511 timeout = (ns + clk_ns - 1) / clk_ns + clks;
512 /* in 1048576 sclk cycle unit */
513 timeout = (timeout + (0x1 << 20) - 1) >> 20;
514 sdr_get_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD, &mode);
515 /*DDR mode will double the clk cycles for data timeout */
516 timeout = mode >= 2 ? timeout * 2 : timeout;
517 timeout = timeout > 1 ? timeout - 1 : 0;
518 timeout = timeout > 255 ? 255 : timeout;
520 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, timeout);
523 static void msdc_gate_clock(struct msdc_host *host)
525 clk_disable_unprepare(host->src_clk);
526 clk_disable_unprepare(host->h_clk);
529 static void msdc_ungate_clock(struct msdc_host *host)
531 clk_prepare_enable(host->h_clk);
532 clk_prepare_enable(host->src_clk);
533 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))
537 static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
545 dev_dbg(host->dev, "set mclk to 0\n");
547 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
551 flags = readl(host->base + MSDC_INTEN);
552 sdr_clr_bits(host->base + MSDC_INTEN, flags);
553 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE);
554 if (timing == MMC_TIMING_UHS_DDR50 ||
555 timing == MMC_TIMING_MMC_DDR52 ||
556 timing == MMC_TIMING_MMC_HS400) {
557 if (timing == MMC_TIMING_MMC_HS400)
560 mode = 0x2; /* ddr mode and use divisor */
562 if (hz >= (host->src_clk_freq >> 2)) {
563 div = 0; /* mean div = 1/4 */
564 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */
566 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2);
567 sclk = (host->src_clk_freq >> 2) / div;
571 if (timing == MMC_TIMING_MMC_HS400 &&
572 hz >= (host->src_clk_freq >> 1)) {
573 sdr_set_bits(host->base + MSDC_CFG,
574 MSDC_CFG_HS400_CK_MODE);
575 sclk = host->src_clk_freq >> 1;
576 div = 0; /* div is ignore when bit18 is set */
578 } else if (hz >= host->src_clk_freq) {
579 mode = 0x1; /* no divisor */
581 sclk = host->src_clk_freq;
583 mode = 0x0; /* use divisor */
584 if (hz >= (host->src_clk_freq >> 1)) {
585 div = 0; /* mean div = 1/2 */
586 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */
588 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2);
589 sclk = (host->src_clk_freq >> 2) / div;
592 sdr_set_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD | MSDC_CFG_CKDIV,
594 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
595 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))
599 host->timing = timing;
600 /* need because clk changed. */
601 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks);
602 sdr_set_bits(host->base + MSDC_INTEN, flags);
605 * mmc_select_hs400() will drop to 50Mhz and High speed mode,
606 * tune result of hs200/200Mhz is not suitable for 50Mhz
608 if (host->sclk <= 52000000) {
609 writel(host->def_tune_para.iocon, host->base + MSDC_IOCON);
610 writel(host->def_tune_para.pad_tune, host->base + MSDC_PAD_TUNE);
612 writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON);
613 writel(host->saved_tune_para.pad_tune, host->base + MSDC_PAD_TUNE);
614 writel(host->saved_tune_para.pad_cmd_tune,
615 host->base + PAD_CMD_TUNE);
618 if (timing == MMC_TIMING_MMC_HS400)
619 sdr_set_field(host->base + PAD_CMD_TUNE,
620 MSDC_PAD_TUNE_CMDRRDLY,
621 host->hs400_cmd_int_delay);
622 dev_dbg(host->dev, "sclk: %d, timing: %d\n", host->sclk, timing);
625 static inline u32 msdc_cmd_find_resp(struct msdc_host *host,
626 struct mmc_request *mrq, struct mmc_command *cmd)
630 switch (mmc_resp_type(cmd)) {
631 /* Actually, R1, R5, R6, R7 are the same */
653 static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host,
654 struct mmc_request *mrq, struct mmc_command *cmd)
657 * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 |
658 * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode
660 u32 opcode = cmd->opcode;
661 u32 resp = msdc_cmd_find_resp(host, mrq, cmd);
662 u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7);
664 host->cmd_rsp = resp;
666 if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) ||
667 opcode == MMC_STOP_TRANSMISSION)
668 rawcmd |= (0x1 << 14);
669 else if (opcode == SD_SWITCH_VOLTAGE)
670 rawcmd |= (0x1 << 30);
671 else if (opcode == SD_APP_SEND_SCR ||
672 opcode == SD_APP_SEND_NUM_WR_BLKS ||
673 (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) ||
674 (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) ||
675 (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC))
676 rawcmd |= (0x1 << 11);
679 struct mmc_data *data = cmd->data;
681 if (mmc_op_multi(opcode)) {
682 if (mmc_card_mmc(host->mmc->card) && mrq->sbc &&
683 !(mrq->sbc->arg & 0xFFFF0000))
684 rawcmd |= 0x2 << 28; /* AutoCMD23 */
687 rawcmd |= ((data->blksz & 0xFFF) << 16);
688 if (data->flags & MMC_DATA_WRITE)
689 rawcmd |= (0x1 << 13);
690 if (data->blocks > 1)
691 rawcmd |= (0x2 << 11);
693 rawcmd |= (0x1 << 11);
694 /* Always use dma mode */
695 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO);
697 if (host->timeout_ns != data->timeout_ns ||
698 host->timeout_clks != data->timeout_clks)
699 msdc_set_timeout(host, data->timeout_ns,
702 writel(data->blocks, host->base + SDC_BLK_NUM);
707 static void msdc_start_data(struct msdc_host *host, struct mmc_request *mrq,
708 struct mmc_command *cmd, struct mmc_data *data)
714 read = data->flags & MMC_DATA_READ;
716 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT);
717 msdc_dma_setup(host, &host->dma, data);
718 sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask);
719 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1);
720 dev_dbg(host->dev, "DMA start\n");
721 dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n",
722 __func__, cmd->opcode, data->blocks, read);
725 static int msdc_auto_cmd_done(struct msdc_host *host, int events,
726 struct mmc_command *cmd)
728 u32 *rsp = cmd->resp;
730 rsp[0] = readl(host->base + SDC_ACMD_RESP);
732 if (events & MSDC_INT_ACMDRDY) {
736 if (events & MSDC_INT_ACMDCRCERR) {
737 cmd->error = -EILSEQ;
738 host->error |= REQ_STOP_EIO;
739 } else if (events & MSDC_INT_ACMDTMO) {
740 cmd->error = -ETIMEDOUT;
741 host->error |= REQ_STOP_TMO;
744 "%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n",
745 __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error);
750 static void msdc_track_cmd_data(struct msdc_host *host,
751 struct mmc_command *cmd, struct mmc_data *data)
754 dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n",
755 __func__, cmd->opcode, cmd->arg, host->error);
758 static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq)
763 * No need check the return value of cancel_delayed_work, as only ONE
766 cancel_delayed_work(&host->req_timeout);
768 spin_lock_irqsave(&host->lock, flags);
770 spin_unlock_irqrestore(&host->lock, flags);
772 msdc_track_cmd_data(host, mrq->cmd, mrq->data);
774 msdc_unprepare_data(host, mrq);
775 mmc_request_done(host->mmc, mrq);
778 /* returns true if command is fully handled; returns false otherwise */
779 static bool msdc_cmd_done(struct msdc_host *host, int events,
780 struct mmc_request *mrq, struct mmc_command *cmd)
787 if (mrq->sbc && cmd == mrq->cmd &&
788 (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR
789 | MSDC_INT_ACMDTMO)))
790 msdc_auto_cmd_done(host, events, mrq->sbc);
792 sbc_error = mrq->sbc && mrq->sbc->error;
794 if (!sbc_error && !(events & (MSDC_INT_CMDRDY
799 spin_lock_irqsave(&host->lock, flags);
802 spin_unlock_irqrestore(&host->lock, flags);
808 sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask);
810 if (cmd->flags & MMC_RSP_PRESENT) {
811 if (cmd->flags & MMC_RSP_136) {
812 rsp[0] = readl(host->base + SDC_RESP3);
813 rsp[1] = readl(host->base + SDC_RESP2);
814 rsp[2] = readl(host->base + SDC_RESP1);
815 rsp[3] = readl(host->base + SDC_RESP0);
817 rsp[0] = readl(host->base + SDC_RESP0);
821 if (!sbc_error && !(events & MSDC_INT_CMDRDY)) {
822 if (cmd->opcode != MMC_SEND_TUNING_BLOCK &&
823 cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200)
825 * should not clear fifo/interrupt as the tune data
826 * may have alreay come.
829 if (events & MSDC_INT_RSPCRCERR) {
830 cmd->error = -EILSEQ;
831 host->error |= REQ_CMD_EIO;
832 } else if (events & MSDC_INT_CMDTMO) {
833 cmd->error = -ETIMEDOUT;
834 host->error |= REQ_CMD_TMO;
839 "%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n",
840 __func__, cmd->opcode, cmd->arg, rsp[0],
843 msdc_cmd_next(host, mrq, cmd);
847 /* It is the core layer's responsibility to ensure card status
848 * is correct before issue a request. but host design do below
849 * checks recommended.
851 static inline bool msdc_cmd_is_ready(struct msdc_host *host,
852 struct mmc_request *mrq, struct mmc_command *cmd)
854 /* The max busy time we can endure is 20ms */
855 unsigned long tmo = jiffies + msecs_to_jiffies(20);
857 while ((readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) &&
858 time_before(jiffies, tmo))
860 if (readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) {
861 dev_err(host->dev, "CMD bus busy detected\n");
862 host->error |= REQ_CMD_BUSY;
863 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
867 if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) {
868 tmo = jiffies + msecs_to_jiffies(20);
869 /* R1B or with data, should check SDCBUSY */
870 while ((readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) &&
871 time_before(jiffies, tmo))
873 if (readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) {
874 dev_err(host->dev, "Controller busy detected\n");
875 host->error |= REQ_CMD_BUSY;
876 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
883 static void msdc_start_command(struct msdc_host *host,
884 struct mmc_request *mrq, struct mmc_command *cmd)
891 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT);
892 if (!msdc_cmd_is_ready(host, mrq, cmd))
895 if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 ||
896 readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) {
897 dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n");
902 rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd);
904 sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask);
905 writel(cmd->arg, host->base + SDC_ARG);
906 writel(rawcmd, host->base + SDC_CMD);
909 static void msdc_cmd_next(struct msdc_host *host,
910 struct mmc_request *mrq, struct mmc_command *cmd)
913 !(cmd->error == -EILSEQ &&
914 (cmd->opcode == MMC_SEND_TUNING_BLOCK ||
915 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))) ||
916 (mrq->sbc && mrq->sbc->error))
917 msdc_request_done(host, mrq);
918 else if (cmd == mrq->sbc)
919 msdc_start_command(host, mrq, mrq->cmd);
921 msdc_request_done(host, mrq);
923 msdc_start_data(host, mrq, cmd, cmd->data);
926 static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq)
928 struct msdc_host *host = mmc_priv(mmc);
935 msdc_prepare_data(host, mrq);
937 /* if SBC is required, we have HW option and SW option.
938 * if HW option is enabled, and SBC does not have "special" flags,
939 * use HW option, otherwise use SW option
941 if (mrq->sbc && (!mmc_card_mmc(mmc->card) ||
942 (mrq->sbc->arg & 0xFFFF0000)))
943 msdc_start_command(host, mrq, mrq->sbc);
945 msdc_start_command(host, mrq, mrq->cmd);
948 static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
950 struct msdc_host *host = mmc_priv(mmc);
951 struct mmc_data *data = mrq->data;
956 msdc_prepare_data(host, mrq);
957 data->host_cookie |= MSDC_ASYNC_FLAG;
960 static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
963 struct msdc_host *host = mmc_priv(mmc);
964 struct mmc_data *data;
969 if (data->host_cookie) {
970 data->host_cookie &= ~MSDC_ASYNC_FLAG;
971 msdc_unprepare_data(host, mrq);
975 static void msdc_data_xfer_next(struct msdc_host *host,
976 struct mmc_request *mrq, struct mmc_data *data)
978 if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error &&
980 msdc_start_command(host, mrq, mrq->stop);
982 msdc_request_done(host, mrq);
985 static bool msdc_data_xfer_done(struct msdc_host *host, u32 events,
986 struct mmc_request *mrq, struct mmc_data *data)
988 struct mmc_command *stop;
991 unsigned int check_data = events &
992 (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO
993 | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR
994 | MSDC_INT_DMA_PROTECT);
996 spin_lock_irqsave(&host->lock, flags);
1000 spin_unlock_irqrestore(&host->lock, flags);
1006 if (check_data || (stop && stop->error)) {
1007 dev_dbg(host->dev, "DMA status: 0x%8X\n",
1008 readl(host->base + MSDC_DMA_CFG));
1009 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP,
1011 while (readl(host->base + MSDC_DMA_CFG) & MSDC_DMA_CFG_STS)
1013 sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask);
1014 dev_dbg(host->dev, "DMA stop\n");
1016 if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) {
1017 data->bytes_xfered = data->blocks * data->blksz;
1019 dev_dbg(host->dev, "interrupt events: %x\n", events);
1020 msdc_reset_hw(host);
1021 host->error |= REQ_DAT_ERR;
1022 data->bytes_xfered = 0;
1024 if (events & MSDC_INT_DATTMO)
1025 data->error = -ETIMEDOUT;
1026 else if (events & MSDC_INT_DATCRCERR)
1027 data->error = -EILSEQ;
1029 dev_dbg(host->dev, "%s: cmd=%d; blocks=%d",
1030 __func__, mrq->cmd->opcode, data->blocks);
1031 dev_dbg(host->dev, "data_error=%d xfer_size=%d\n",
1032 (int)data->error, data->bytes_xfered);
1035 msdc_data_xfer_next(host, mrq, data);
1041 static void msdc_set_buswidth(struct msdc_host *host, u32 width)
1043 u32 val = readl(host->base + SDC_CFG);
1045 val &= ~SDC_CFG_BUSWIDTH;
1049 case MMC_BUS_WIDTH_1:
1050 val |= (MSDC_BUS_1BITS << 16);
1052 case MMC_BUS_WIDTH_4:
1053 val |= (MSDC_BUS_4BITS << 16);
1055 case MMC_BUS_WIDTH_8:
1056 val |= (MSDC_BUS_8BITS << 16);
1060 writel(val, host->base + SDC_CFG);
1061 dev_dbg(host->dev, "Bus Width = %d", width);
1064 static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios)
1066 struct msdc_host *host = mmc_priv(mmc);
1069 if (!IS_ERR(mmc->supply.vqmmc)) {
1070 if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 &&
1071 ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) {
1072 dev_err(host->dev, "Unsupported signal voltage!\n");
1076 ret = mmc_regulator_set_vqmmc(mmc, ios);
1078 dev_dbg(host->dev, "Regulator set error %d (%d)\n",
1079 ret, ios->signal_voltage);
1081 /* Apply different pinctrl settings for different signal voltage */
1082 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
1083 pinctrl_select_state(host->pinctrl, host->pins_uhs);
1085 pinctrl_select_state(host->pinctrl, host->pins_default);
1091 static int msdc_card_busy(struct mmc_host *mmc)
1093 struct msdc_host *host = mmc_priv(mmc);
1094 u32 status = readl(host->base + MSDC_PS);
1096 /* only check if data0 is low */
1097 return !(status & BIT(16));
1100 static void msdc_request_timeout(struct work_struct *work)
1102 struct msdc_host *host = container_of(work, struct msdc_host,
1105 /* simulate HW timeout status */
1106 dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__);
1108 dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__,
1109 host->mrq, host->mrq->cmd->opcode);
1111 dev_err(host->dev, "%s: aborting cmd=%d\n",
1112 __func__, host->cmd->opcode);
1113 msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq,
1115 } else if (host->data) {
1116 dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n",
1117 __func__, host->mrq->cmd->opcode,
1118 host->data->blocks);
1119 msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq,
1125 static irqreturn_t msdc_irq(int irq, void *dev_id)
1127 struct msdc_host *host = (struct msdc_host *) dev_id;
1130 unsigned long flags;
1131 struct mmc_request *mrq;
1132 struct mmc_command *cmd;
1133 struct mmc_data *data;
1134 u32 events, event_mask;
1136 spin_lock_irqsave(&host->lock, flags);
1137 events = readl(host->base + MSDC_INT);
1138 event_mask = readl(host->base + MSDC_INTEN);
1139 /* clear interrupts */
1140 writel(events & event_mask, host->base + MSDC_INT);
1145 spin_unlock_irqrestore(&host->lock, flags);
1147 if (!(events & event_mask))
1152 "%s: MRQ=NULL; events=%08X; event_mask=%08X\n",
1153 __func__, events, event_mask);
1158 dev_dbg(host->dev, "%s: events=%08X\n", __func__, events);
1161 msdc_cmd_done(host, events, mrq, cmd);
1163 msdc_data_xfer_done(host, events, mrq, data);
1169 static void msdc_init_hw(struct msdc_host *host)
1173 /* Configure to MMC/SD mode, clock free running */
1174 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN);
1177 msdc_reset_hw(host);
1179 /* Disable card detection */
1180 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1182 /* Disable and clear all interrupts */
1183 writel(0, host->base + MSDC_INTEN);
1184 val = readl(host->base + MSDC_INT);
1185 writel(val, host->base + MSDC_INT);
1187 writel(0, host->base + MSDC_PAD_TUNE);
1188 writel(0, host->base + MSDC_IOCON);
1189 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0);
1190 writel(0x403c0046, host->base + MSDC_PATCH_BIT);
1191 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1);
1192 writel(0xffff0089, host->base + MSDC_PATCH_BIT1);
1193 sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL);
1195 /* Configure to enable SDIO mode.
1196 * it's must otherwise sdio cmd5 failed
1198 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO);
1200 /* disable detect SDIO device interrupt function */
1201 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1203 /* Configure to default data timeout */
1204 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3);
1206 host->def_tune_para.iocon = readl(host->base + MSDC_IOCON);
1207 host->def_tune_para.pad_tune = readl(host->base + MSDC_PAD_TUNE);
1208 dev_dbg(host->dev, "init hardware done!");
1211 static void msdc_deinit_hw(struct msdc_host *host)
1214 /* Disable and clear all interrupts */
1215 writel(0, host->base + MSDC_INTEN);
1217 val = readl(host->base + MSDC_INT);
1218 writel(val, host->base + MSDC_INT);
1221 /* init gpd and bd list in msdc_drv_probe */
1222 static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma)
1224 struct mt_gpdma_desc *gpd = dma->gpd;
1225 struct mt_bdma_desc *bd = dma->bd;
1228 memset(gpd, 0, sizeof(struct mt_gpdma_desc) * 2);
1230 gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */
1231 gpd->ptr = (u32)dma->bd_addr; /* physical address */
1232 /* gpd->next is must set for desc DMA
1233 * That's why must alloc 2 gpd structure.
1235 gpd->next = (u32)dma->gpd_addr + sizeof(struct mt_gpdma_desc);
1236 memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM);
1237 for (i = 0; i < (MAX_BD_NUM - 1); i++)
1238 bd[i].next = (u32)dma->bd_addr + sizeof(*bd) * (i + 1);
1241 static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1243 struct msdc_host *host = mmc_priv(mmc);
1246 msdc_set_buswidth(host, ios->bus_width);
1248 /* Suspend/Resume will do power off/on */
1249 switch (ios->power_mode) {
1251 if (!IS_ERR(mmc->supply.vmmc)) {
1253 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1256 dev_err(host->dev, "Failed to set vmmc power!\n");
1262 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
1263 ret = regulator_enable(mmc->supply.vqmmc);
1265 dev_err(host->dev, "Failed to set vqmmc power!\n");
1267 host->vqmmc_enabled = true;
1271 if (!IS_ERR(mmc->supply.vmmc))
1272 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1274 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
1275 regulator_disable(mmc->supply.vqmmc);
1276 host->vqmmc_enabled = false;
1283 if (host->mclk != ios->clock || host->timing != ios->timing)
1284 msdc_set_mclk(host, ios->timing, ios->clock);
1287 static u32 test_delay_bit(u32 delay, u32 bit)
1289 bit %= PAD_DELAY_MAX;
1290 return delay & (1 << bit);
1293 static int get_delay_len(u32 delay, u32 start_bit)
1297 for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) {
1298 if (test_delay_bit(delay, start_bit + i) == 0)
1301 return PAD_DELAY_MAX - start_bit;
1304 static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay)
1306 int start = 0, len = 0;
1307 int start_final = 0, len_final = 0;
1308 u8 final_phase = 0xff;
1309 struct msdc_delay_phase delay_phase = { 0, };
1312 dev_err(host->dev, "phase error: [map:%x]\n", delay);
1313 delay_phase.final_phase = final_phase;
1317 while (start < PAD_DELAY_MAX) {
1318 len = get_delay_len(delay, start);
1319 if (len_final < len) {
1320 start_final = start;
1323 start += len ? len : 1;
1324 if (len >= 12 && start_final < 4)
1328 /* The rule is that to find the smallest delay cell */
1329 if (start_final == 0)
1330 final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX;
1332 final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX;
1333 dev_info(host->dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n",
1334 delay, len_final, final_phase);
1336 delay_phase.maxlen = len_final;
1337 delay_phase.start = start_final;
1338 delay_phase.final_phase = final_phase;
1342 static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)
1344 struct msdc_host *host = mmc_priv(mmc);
1345 u32 rise_delay = 0, fall_delay = 0;
1346 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
1347 struct msdc_delay_phase internal_delay_phase;
1348 u8 final_delay, final_maxlen;
1349 u32 internal_delay = 0;
1353 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
1354 mmc->ios.timing == MMC_TIMING_UHS_SDR104)
1355 sdr_set_field(host->base + MSDC_PAD_TUNE,
1356 MSDC_PAD_TUNE_CMDRRDLY,
1357 host->hs200_cmd_int_delay);
1359 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1360 for (i = 0 ; i < PAD_DELAY_MAX; i++) {
1361 sdr_set_field(host->base + MSDC_PAD_TUNE,
1362 MSDC_PAD_TUNE_CMDRDLY, i);
1364 * Using the same parameters, it may sometimes pass the test,
1365 * but sometimes it may fail. To make sure the parameters are
1366 * more stable, we test each set of parameters 3 times.
1368 for (j = 0; j < 3; j++) {
1369 mmc_send_tuning(mmc, opcode, &cmd_err);
1371 rise_delay |= (1 << i);
1373 rise_delay &= ~(1 << i);
1378 final_rise_delay = get_best_delay(host, rise_delay);
1379 /* if rising edge has enough margin, then do not scan falling edge */
1380 if (final_rise_delay.maxlen >= 12 && final_rise_delay.start < 4)
1383 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1384 for (i = 0; i < PAD_DELAY_MAX; i++) {
1385 sdr_set_field(host->base + MSDC_PAD_TUNE,
1386 MSDC_PAD_TUNE_CMDRDLY, i);
1388 * Using the same parameters, it may sometimes pass the test,
1389 * but sometimes it may fail. To make sure the parameters are
1390 * more stable, we test each set of parameters 3 times.
1392 for (j = 0; j < 3; j++) {
1393 mmc_send_tuning(mmc, opcode, &cmd_err);
1395 fall_delay |= (1 << i);
1397 fall_delay &= ~(1 << i);
1402 final_fall_delay = get_best_delay(host, fall_delay);
1405 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
1406 if (final_fall_delay.maxlen >= 12 && final_fall_delay.start < 4)
1407 final_maxlen = final_fall_delay.maxlen;
1408 if (final_maxlen == final_rise_delay.maxlen) {
1409 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1410 sdr_set_field(host->base + MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRDLY,
1411 final_rise_delay.final_phase);
1412 final_delay = final_rise_delay.final_phase;
1414 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1415 sdr_set_field(host->base + MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRDLY,
1416 final_fall_delay.final_phase);
1417 final_delay = final_fall_delay.final_phase;
1419 if (host->hs200_cmd_int_delay)
1422 for (i = 0; i < PAD_DELAY_MAX; i++) {
1423 sdr_set_field(host->base + MSDC_PAD_TUNE,
1424 MSDC_PAD_TUNE_CMDRRDLY, i);
1425 mmc_send_tuning(mmc, opcode, &cmd_err);
1427 internal_delay |= (1 << i);
1429 dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay);
1430 internal_delay_phase = get_best_delay(host, internal_delay);
1431 sdr_set_field(host->base + MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRRDLY,
1432 internal_delay_phase.final_phase);
1434 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay);
1435 return final_delay == 0xff ? -EIO : 0;
1438 static int hs400_tune_response(struct mmc_host *mmc, u32 opcode)
1440 struct msdc_host *host = mmc_priv(mmc);
1442 struct msdc_delay_phase final_cmd_delay = { 0,};
1447 /* select EMMC50 PAD CMD tune */
1448 sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0));
1449 sdr_set_field(host->base + MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMDTA, 2);
1451 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
1452 mmc->ios.timing == MMC_TIMING_UHS_SDR104)
1453 sdr_set_field(host->base + MSDC_PAD_TUNE,
1454 MSDC_PAD_TUNE_CMDRRDLY,
1455 host->hs200_cmd_int_delay);
1457 if (host->hs400_cmd_resp_sel_rising)
1458 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1460 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1461 for (i = 0 ; i < PAD_DELAY_MAX; i++) {
1462 sdr_set_field(host->base + PAD_CMD_TUNE,
1463 PAD_CMD_TUNE_RX_DLY3, i);
1465 * Using the same parameters, it may sometimes pass the test,
1466 * but sometimes it may fail. To make sure the parameters are
1467 * more stable, we test each set of parameters 3 times.
1469 for (j = 0; j < 3; j++) {
1470 mmc_send_tuning(mmc, opcode, &cmd_err);
1472 cmd_delay |= (1 << i);
1474 cmd_delay &= ~(1 << i);
1479 final_cmd_delay = get_best_delay(host, cmd_delay);
1480 sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3,
1481 final_cmd_delay.final_phase);
1482 final_delay = final_cmd_delay.final_phase;
1484 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay);
1485 return final_delay == 0xff ? -EIO : 0;
1488 static int msdc_tune_data(struct mmc_host *mmc, u32 opcode)
1490 struct msdc_host *host = mmc_priv(mmc);
1491 u32 rise_delay = 0, fall_delay = 0;
1492 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
1493 u8 final_delay, final_maxlen;
1496 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
1497 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
1498 for (i = 0 ; i < PAD_DELAY_MAX; i++) {
1499 sdr_set_field(host->base + MSDC_PAD_TUNE,
1500 MSDC_PAD_TUNE_DATRRDLY, i);
1501 ret = mmc_send_tuning(mmc, opcode, NULL);
1503 rise_delay |= (1 << i);
1505 final_rise_delay = get_best_delay(host, rise_delay);
1506 /* if rising edge has enough margin, then do not scan falling edge */
1507 if (final_rise_delay.maxlen >= 12 ||
1508 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
1511 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
1512 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
1513 for (i = 0; i < PAD_DELAY_MAX; i++) {
1514 sdr_set_field(host->base + MSDC_PAD_TUNE,
1515 MSDC_PAD_TUNE_DATRRDLY, i);
1516 ret = mmc_send_tuning(mmc, opcode, NULL);
1518 fall_delay |= (1 << i);
1520 final_fall_delay = get_best_delay(host, fall_delay);
1523 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
1524 if (final_maxlen == final_rise_delay.maxlen) {
1525 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
1526 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
1527 sdr_set_field(host->base + MSDC_PAD_TUNE,
1528 MSDC_PAD_TUNE_DATRRDLY,
1529 final_rise_delay.final_phase);
1530 final_delay = final_rise_delay.final_phase;
1532 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
1533 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
1534 sdr_set_field(host->base + MSDC_PAD_TUNE,
1535 MSDC_PAD_TUNE_DATRRDLY,
1536 final_fall_delay.final_phase);
1537 final_delay = final_fall_delay.final_phase;
1540 dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay);
1541 return final_delay == 0xff ? -EIO : 0;
1544 static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode)
1546 struct msdc_host *host = mmc_priv(mmc);
1549 if (host->hs400_mode)
1550 ret = hs400_tune_response(mmc, opcode);
1552 ret = msdc_tune_response(mmc, opcode);
1554 dev_err(host->dev, "Tune response fail!\n");
1557 if (host->hs400_mode == false) {
1558 ret = msdc_tune_data(mmc, opcode);
1560 dev_err(host->dev, "Tune data fail!\n");
1563 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
1564 host->saved_tune_para.pad_tune = readl(host->base + MSDC_PAD_TUNE);
1565 host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
1569 static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
1571 struct msdc_host *host = mmc_priv(mmc);
1572 host->hs400_mode = true;
1574 writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE);
1578 static void msdc_hw_reset(struct mmc_host *mmc)
1580 struct msdc_host *host = mmc_priv(mmc);
1582 sdr_set_bits(host->base + EMMC_IOCON, 1);
1583 udelay(10); /* 10us is enough */
1584 sdr_clr_bits(host->base + EMMC_IOCON, 1);
1587 static const struct mmc_host_ops mt_msdc_ops = {
1588 .post_req = msdc_post_req,
1589 .pre_req = msdc_pre_req,
1590 .request = msdc_ops_request,
1591 .set_ios = msdc_ops_set_ios,
1592 .get_ro = mmc_gpio_get_ro,
1593 .get_cd = mmc_gpio_get_cd,
1594 .start_signal_voltage_switch = msdc_ops_switch_volt,
1595 .card_busy = msdc_card_busy,
1596 .execute_tuning = msdc_execute_tuning,
1597 .prepare_hs400_tuning = msdc_prepare_hs400_tuning,
1598 .hw_reset = msdc_hw_reset,
1601 static void msdc_of_property_parse(struct platform_device *pdev,
1602 struct msdc_host *host)
1604 of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay",
1605 &host->hs400_ds_delay);
1607 of_property_read_u32(pdev->dev.of_node, "mediatek,hs200-cmd-int-delay",
1608 &host->hs200_cmd_int_delay);
1610 of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-cmd-int-delay",
1611 &host->hs400_cmd_int_delay);
1613 if (of_property_read_bool(pdev->dev.of_node,
1614 "mediatek,hs400-cmd-resp-sel-rising"))
1615 host->hs400_cmd_resp_sel_rising = true;
1617 host->hs400_cmd_resp_sel_rising = false;
1620 static int msdc_drv_probe(struct platform_device *pdev)
1622 struct mmc_host *mmc;
1623 struct msdc_host *host;
1624 struct resource *res;
1627 if (!pdev->dev.of_node) {
1628 dev_err(&pdev->dev, "No DT found\n");
1631 /* Allocate MMC host for this device */
1632 mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev);
1636 host = mmc_priv(mmc);
1637 ret = mmc_of_parse(mmc);
1641 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1642 host->base = devm_ioremap_resource(&pdev->dev, res);
1643 if (IS_ERR(host->base)) {
1644 ret = PTR_ERR(host->base);
1648 ret = mmc_regulator_get_supply(mmc);
1649 if (ret == -EPROBE_DEFER)
1652 host->src_clk = devm_clk_get(&pdev->dev, "source");
1653 if (IS_ERR(host->src_clk)) {
1654 ret = PTR_ERR(host->src_clk);
1658 host->h_clk = devm_clk_get(&pdev->dev, "hclk");
1659 if (IS_ERR(host->h_clk)) {
1660 ret = PTR_ERR(host->h_clk);
1664 host->irq = platform_get_irq(pdev, 0);
1665 if (host->irq < 0) {
1670 host->pinctrl = devm_pinctrl_get(&pdev->dev);
1671 if (IS_ERR(host->pinctrl)) {
1672 ret = PTR_ERR(host->pinctrl);
1673 dev_err(&pdev->dev, "Cannot find pinctrl!\n");
1677 host->pins_default = pinctrl_lookup_state(host->pinctrl, "default");
1678 if (IS_ERR(host->pins_default)) {
1679 ret = PTR_ERR(host->pins_default);
1680 dev_err(&pdev->dev, "Cannot find pinctrl default!\n");
1684 host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs");
1685 if (IS_ERR(host->pins_uhs)) {
1686 ret = PTR_ERR(host->pins_uhs);
1687 dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n");
1691 msdc_of_property_parse(pdev, host);
1693 host->dev = &pdev->dev;
1695 host->src_clk_freq = clk_get_rate(host->src_clk);
1696 /* Set host parameters to mmc */
1697 mmc->ops = &mt_msdc_ops;
1698 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255);
1700 mmc->caps |= MMC_CAP_ERASE | MMC_CAP_CMD23;
1701 /* MMC core transfer sizes tunable parameters */
1702 mmc->max_segs = MAX_BD_NUM;
1703 mmc->max_seg_size = BDMA_DESC_BUFLEN;
1704 mmc->max_blk_size = 2048;
1705 mmc->max_req_size = 512 * 1024;
1706 mmc->max_blk_count = mmc->max_req_size / 512;
1707 host->dma_mask = DMA_BIT_MASK(32);
1708 mmc_dev(mmc)->dma_mask = &host->dma_mask;
1710 host->timeout_clks = 3 * 1048576;
1711 host->dma.gpd = dma_alloc_coherent(&pdev->dev,
1712 2 * sizeof(struct mt_gpdma_desc),
1713 &host->dma.gpd_addr, GFP_KERNEL);
1714 host->dma.bd = dma_alloc_coherent(&pdev->dev,
1715 MAX_BD_NUM * sizeof(struct mt_bdma_desc),
1716 &host->dma.bd_addr, GFP_KERNEL);
1717 if (!host->dma.gpd || !host->dma.bd) {
1721 msdc_init_gpd_bd(host, &host->dma);
1722 INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout);
1723 spin_lock_init(&host->lock);
1725 platform_set_drvdata(pdev, mmc);
1726 msdc_ungate_clock(host);
1729 ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq,
1730 IRQF_TRIGGER_LOW | IRQF_ONESHOT, pdev->name, host);
1734 pm_runtime_set_active(host->dev);
1735 pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY);
1736 pm_runtime_use_autosuspend(host->dev);
1737 pm_runtime_enable(host->dev);
1738 ret = mmc_add_host(mmc);
1745 pm_runtime_disable(host->dev);
1747 platform_set_drvdata(pdev, NULL);
1748 msdc_deinit_hw(host);
1749 msdc_gate_clock(host);
1752 dma_free_coherent(&pdev->dev,
1753 2 * sizeof(struct mt_gpdma_desc),
1754 host->dma.gpd, host->dma.gpd_addr);
1756 dma_free_coherent(&pdev->dev,
1757 MAX_BD_NUM * sizeof(struct mt_bdma_desc),
1758 host->dma.bd, host->dma.bd_addr);
1765 static int msdc_drv_remove(struct platform_device *pdev)
1767 struct mmc_host *mmc;
1768 struct msdc_host *host;
1770 mmc = platform_get_drvdata(pdev);
1771 host = mmc_priv(mmc);
1773 pm_runtime_get_sync(host->dev);
1775 platform_set_drvdata(pdev, NULL);
1776 mmc_remove_host(host->mmc);
1777 msdc_deinit_hw(host);
1778 msdc_gate_clock(host);
1780 pm_runtime_disable(host->dev);
1781 pm_runtime_put_noidle(host->dev);
1782 dma_free_coherent(&pdev->dev,
1783 2 * sizeof(struct mt_gpdma_desc),
1784 host->dma.gpd, host->dma.gpd_addr);
1785 dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc),
1786 host->dma.bd, host->dma.bd_addr);
1788 mmc_free_host(host->mmc);
1794 static void msdc_save_reg(struct msdc_host *host)
1796 host->save_para.msdc_cfg = readl(host->base + MSDC_CFG);
1797 host->save_para.iocon = readl(host->base + MSDC_IOCON);
1798 host->save_para.sdc_cfg = readl(host->base + SDC_CFG);
1799 host->save_para.pad_tune = readl(host->base + MSDC_PAD_TUNE);
1800 host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT);
1801 host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1);
1802 host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE);
1803 host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
1804 host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0);
1807 static void msdc_restore_reg(struct msdc_host *host)
1809 writel(host->save_para.msdc_cfg, host->base + MSDC_CFG);
1810 writel(host->save_para.iocon, host->base + MSDC_IOCON);
1811 writel(host->save_para.sdc_cfg, host->base + SDC_CFG);
1812 writel(host->save_para.pad_tune, host->base + MSDC_PAD_TUNE);
1813 writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT);
1814 writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1);
1815 writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE);
1816 writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE);
1817 writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0);
1820 static int msdc_runtime_suspend(struct device *dev)
1822 struct mmc_host *mmc = dev_get_drvdata(dev);
1823 struct msdc_host *host = mmc_priv(mmc);
1825 msdc_save_reg(host);
1826 msdc_gate_clock(host);
1830 static int msdc_runtime_resume(struct device *dev)
1832 struct mmc_host *mmc = dev_get_drvdata(dev);
1833 struct msdc_host *host = mmc_priv(mmc);
1835 msdc_ungate_clock(host);
1836 msdc_restore_reg(host);
1841 static const struct dev_pm_ops msdc_dev_pm_ops = {
1842 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1843 pm_runtime_force_resume)
1844 SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL)
1847 static const struct of_device_id msdc_of_ids[] = {
1848 { .compatible = "mediatek,mt8135-mmc", },
1851 MODULE_DEVICE_TABLE(of, msdc_of_ids);
1853 static struct platform_driver mt_msdc_driver = {
1854 .probe = msdc_drv_probe,
1855 .remove = msdc_drv_remove,
1858 .of_match_table = msdc_of_ids,
1859 .pm = &msdc_dev_pm_ops,
1863 module_platform_driver(mt_msdc_driver);
1864 MODULE_LICENSE("GPL v2");
1865 MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver");