2 * Copyright (c) 2014-2015 MediaTek Inc.
3 * Author: Chaotian.Jing <chaotian.jing@mediatek.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #include <linux/module.h>
16 #include <linux/clk.h>
17 #include <linux/delay.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/ioport.h>
20 #include <linux/irq.h>
21 #include <linux/of_address.h>
22 #include <linux/of_irq.h>
23 #include <linux/of_gpio.h>
24 #include <linux/pinctrl/consumer.h>
25 #include <linux/platform_device.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/regulator/consumer.h>
29 #include <linux/slab.h>
30 #include <linux/spinlock.h>
32 #include <linux/mmc/card.h>
33 #include <linux/mmc/core.h>
34 #include <linux/mmc/host.h>
35 #include <linux/mmc/mmc.h>
36 #include <linux/mmc/sd.h>
37 #include <linux/mmc/sdio.h>
39 #define MAX_BD_NUM 1024
41 /*--------------------------------------------------------------------------*/
42 /* Common Definition */
43 /*--------------------------------------------------------------------------*/
44 #define MSDC_BUS_1BITS 0x0
45 #define MSDC_BUS_4BITS 0x1
46 #define MSDC_BUS_8BITS 0x2
48 #define MSDC_BURST_64B 0x6
50 /*--------------------------------------------------------------------------*/
52 /*--------------------------------------------------------------------------*/
54 #define MSDC_IOCON 0x04
57 #define MSDC_INTEN 0x10
58 #define MSDC_FIFOCS 0x14
63 #define SDC_RESP0 0x40
64 #define SDC_RESP1 0x44
65 #define SDC_RESP2 0x48
66 #define SDC_RESP3 0x4c
67 #define SDC_BLK_NUM 0x50
68 #define EMMC_IOCON 0x7c
69 #define SDC_ACMD_RESP 0x80
70 #define MSDC_DMA_SA 0x90
71 #define MSDC_DMA_CTRL 0x98
72 #define MSDC_DMA_CFG 0x9c
73 #define MSDC_PATCH_BIT 0xb0
74 #define MSDC_PATCH_BIT1 0xb4
75 #define MSDC_PAD_TUNE 0xec
76 #define PAD_DS_TUNE 0x188
77 #define EMMC50_CFG0 0x208
79 /*--------------------------------------------------------------------------*/
81 /*--------------------------------------------------------------------------*/
84 #define MSDC_CFG_MODE (0x1 << 0) /* RW */
85 #define MSDC_CFG_CKPDN (0x1 << 1) /* RW */
86 #define MSDC_CFG_RST (0x1 << 2) /* RW */
87 #define MSDC_CFG_PIO (0x1 << 3) /* RW */
88 #define MSDC_CFG_CKDRVEN (0x1 << 4) /* RW */
89 #define MSDC_CFG_BV18SDT (0x1 << 5) /* RW */
90 #define MSDC_CFG_BV18PSS (0x1 << 6) /* R */
91 #define MSDC_CFG_CKSTB (0x1 << 7) /* R */
92 #define MSDC_CFG_CKDIV (0xff << 8) /* RW */
93 #define MSDC_CFG_CKMOD (0x3 << 16) /* RW */
94 #define MSDC_CFG_HS400_CK_MODE (0x1 << 18) /* RW */
97 #define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */
98 #define MSDC_IOCON_RSPL (0x1 << 1) /* RW */
99 #define MSDC_IOCON_DSPL (0x1 << 2) /* RW */
100 #define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */
101 #define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */
102 #define MSDC_IOCON_DSPLSEL (0x1 << 5) /* RW */
103 #define MSDC_IOCON_W_DSPL (0x1 << 8) /* RW */
104 #define MSDC_IOCON_D0SPL (0x1 << 16) /* RW */
105 #define MSDC_IOCON_D1SPL (0x1 << 17) /* RW */
106 #define MSDC_IOCON_D2SPL (0x1 << 18) /* RW */
107 #define MSDC_IOCON_D3SPL (0x1 << 19) /* RW */
108 #define MSDC_IOCON_D4SPL (0x1 << 20) /* RW */
109 #define MSDC_IOCON_D5SPL (0x1 << 21) /* RW */
110 #define MSDC_IOCON_D6SPL (0x1 << 22) /* RW */
111 #define MSDC_IOCON_D7SPL (0x1 << 23) /* RW */
112 #define MSDC_IOCON_RISCSZ (0x3 << 24) /* RW */
115 #define MSDC_PS_CDEN (0x1 << 0) /* RW */
116 #define MSDC_PS_CDSTS (0x1 << 1) /* R */
117 #define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */
118 #define MSDC_PS_DAT (0xff << 16) /* R */
119 #define MSDC_PS_CMD (0x1 << 24) /* R */
120 #define MSDC_PS_WP (0x1 << 31) /* R */
123 #define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */
124 #define MSDC_INT_CDSC (0x1 << 1) /* W1C */
125 #define MSDC_INT_ACMDRDY (0x1 << 3) /* W1C */
126 #define MSDC_INT_ACMDTMO (0x1 << 4) /* W1C */
127 #define MSDC_INT_ACMDCRCERR (0x1 << 5) /* W1C */
128 #define MSDC_INT_DMAQ_EMPTY (0x1 << 6) /* W1C */
129 #define MSDC_INT_SDIOIRQ (0x1 << 7) /* W1C */
130 #define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */
131 #define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */
132 #define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */
133 #define MSDC_INT_CSTA (0x1 << 11) /* R */
134 #define MSDC_INT_XFER_COMPL (0x1 << 12) /* W1C */
135 #define MSDC_INT_DXFER_DONE (0x1 << 13) /* W1C */
136 #define MSDC_INT_DATTMO (0x1 << 14) /* W1C */
137 #define MSDC_INT_DATCRCERR (0x1 << 15) /* W1C */
138 #define MSDC_INT_ACMD19_DONE (0x1 << 16) /* W1C */
139 #define MSDC_INT_DMA_BDCSERR (0x1 << 17) /* W1C */
140 #define MSDC_INT_DMA_GPDCSERR (0x1 << 18) /* W1C */
141 #define MSDC_INT_DMA_PROTECT (0x1 << 19) /* W1C */
143 /* MSDC_INTEN mask */
144 #define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */
145 #define MSDC_INTEN_CDSC (0x1 << 1) /* RW */
146 #define MSDC_INTEN_ACMDRDY (0x1 << 3) /* RW */
147 #define MSDC_INTEN_ACMDTMO (0x1 << 4) /* RW */
148 #define MSDC_INTEN_ACMDCRCERR (0x1 << 5) /* RW */
149 #define MSDC_INTEN_DMAQ_EMPTY (0x1 << 6) /* RW */
150 #define MSDC_INTEN_SDIOIRQ (0x1 << 7) /* RW */
151 #define MSDC_INTEN_CMDRDY (0x1 << 8) /* RW */
152 #define MSDC_INTEN_CMDTMO (0x1 << 9) /* RW */
153 #define MSDC_INTEN_RSPCRCERR (0x1 << 10) /* RW */
154 #define MSDC_INTEN_CSTA (0x1 << 11) /* RW */
155 #define MSDC_INTEN_XFER_COMPL (0x1 << 12) /* RW */
156 #define MSDC_INTEN_DXFER_DONE (0x1 << 13) /* RW */
157 #define MSDC_INTEN_DATTMO (0x1 << 14) /* RW */
158 #define MSDC_INTEN_DATCRCERR (0x1 << 15) /* RW */
159 #define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */
160 #define MSDC_INTEN_DMA_BDCSERR (0x1 << 17) /* RW */
161 #define MSDC_INTEN_DMA_GPDCSERR (0x1 << 18) /* RW */
162 #define MSDC_INTEN_DMA_PROTECT (0x1 << 19) /* RW */
164 /* MSDC_FIFOCS mask */
165 #define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */
166 #define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */
167 #define MSDC_FIFOCS_CLR (0x1 << 31) /* RW */
170 #define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */
171 #define SDC_CFG_INSWKUP (0x1 << 1) /* RW */
172 #define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */
173 #define SDC_CFG_SDIO (0x1 << 19) /* RW */
174 #define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */
175 #define SDC_CFG_INTATGAP (0x1 << 21) /* RW */
176 #define SDC_CFG_DTOC (0xff << 24) /* RW */
179 #define SDC_STS_SDCBUSY (0x1 << 0) /* RW */
180 #define SDC_STS_CMDBUSY (0x1 << 1) /* RW */
181 #define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */
183 /* MSDC_DMA_CTRL mask */
184 #define MSDC_DMA_CTRL_START (0x1 << 0) /* W */
185 #define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */
186 #define MSDC_DMA_CTRL_RESUME (0x1 << 2) /* W */
187 #define MSDC_DMA_CTRL_MODE (0x1 << 8) /* RW */
188 #define MSDC_DMA_CTRL_LASTBUF (0x1 << 10) /* RW */
189 #define MSDC_DMA_CTRL_BRUSTSZ (0x7 << 12) /* RW */
191 /* MSDC_DMA_CFG mask */
192 #define MSDC_DMA_CFG_STS (0x1 << 0) /* R */
193 #define MSDC_DMA_CFG_DECSEN (0x1 << 1) /* RW */
194 #define MSDC_DMA_CFG_AHBHPROT2 (0x2 << 8) /* RW */
195 #define MSDC_DMA_CFG_ACTIVEEN (0x2 << 12) /* RW */
196 #define MSDC_DMA_CFG_CS12B16B (0x1 << 16) /* RW */
198 /* MSDC_PATCH_BIT mask */
199 #define MSDC_PATCH_BIT_ODDSUPP (0x1 << 1) /* RW */
200 #define MSDC_INT_DAT_LATCH_CK_SEL (0x7 << 7)
201 #define MSDC_CKGEN_MSDC_DLY_SEL (0x1f << 10)
202 #define MSDC_PATCH_BIT_IODSSEL (0x1 << 16) /* RW */
203 #define MSDC_PATCH_BIT_IOINTSEL (0x1 << 17) /* RW */
204 #define MSDC_PATCH_BIT_BUSYDLY (0xf << 18) /* RW */
205 #define MSDC_PATCH_BIT_WDOD (0xf << 22) /* RW */
206 #define MSDC_PATCH_BIT_IDRTSEL (0x1 << 26) /* RW */
207 #define MSDC_PATCH_BIT_CMDFSEL (0x1 << 27) /* RW */
208 #define MSDC_PATCH_BIT_INTDLSEL (0x1 << 28) /* RW */
209 #define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */
210 #define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */
212 #define MSDC_PAD_TUNE_DATRRDLY (0x1f << 8) /* RW */
213 #define MSDC_PAD_TUNE_CMDRDLY (0x1f << 16) /* RW */
215 #define PAD_DS_TUNE_DLY1 (0x1f << 2) /* RW */
216 #define PAD_DS_TUNE_DLY2 (0x1f << 7) /* RW */
217 #define PAD_DS_TUNE_DLY3 (0x1f << 12) /* RW */
219 #define EMMC50_CFG_PADCMD_LATCHCK (0x1 << 0) /* RW */
220 #define EMMC50_CFG_CRCSTS_EDGE (0x1 << 3) /* RW */
221 #define EMMC50_CFG_CFCSTS_SEL (0x1 << 4) /* RW */
223 #define REQ_CMD_EIO (0x1 << 0)
224 #define REQ_CMD_TMO (0x1 << 1)
225 #define REQ_DAT_ERR (0x1 << 2)
226 #define REQ_STOP_EIO (0x1 << 3)
227 #define REQ_STOP_TMO (0x1 << 4)
228 #define REQ_CMD_BUSY (0x1 << 5)
230 #define MSDC_PREPARE_FLAG (0x1 << 0)
231 #define MSDC_ASYNC_FLAG (0x1 << 1)
232 #define MSDC_MMAP_FLAG (0x1 << 2)
234 #define MTK_MMC_AUTOSUSPEND_DELAY 50
235 #define CMD_TIMEOUT (HZ/10 * 5) /* 100ms x5 */
236 #define DAT_TIMEOUT (HZ * 5) /* 1000ms x5 */
238 #define PAD_DELAY_MAX 32 /* PAD delay cells */
239 /*--------------------------------------------------------------------------*/
240 /* Descriptor Structure */
241 /*--------------------------------------------------------------------------*/
242 struct mt_gpdma_desc {
244 #define GPDMA_DESC_HWO (0x1 << 0)
245 #define GPDMA_DESC_BDP (0x1 << 1)
246 #define GPDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */
247 #define GPDMA_DESC_INT (0x1 << 16)
251 #define GPDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */
252 #define GPDMA_DESC_EXTLEN (0xff << 16) /* bit16 ~ bit23 */
258 struct mt_bdma_desc {
260 #define BDMA_DESC_EOL (0x1 << 0)
261 #define BDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */
262 #define BDMA_DESC_BLKPAD (0x1 << 17)
263 #define BDMA_DESC_DWPAD (0x1 << 18)
267 #define BDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */
271 struct scatterlist *sg; /* I/O scatter list */
272 struct mt_gpdma_desc *gpd; /* pointer to gpd array */
273 struct mt_bdma_desc *bd; /* pointer to bd array */
274 dma_addr_t gpd_addr; /* the physical address of gpd array */
275 dma_addr_t bd_addr; /* the physical address of bd array */
278 struct msdc_save_para {
289 struct msdc_delay_phase {
297 struct mmc_host *mmc; /* mmc structure */
301 struct mmc_request *mrq;
302 struct mmc_command *cmd;
303 struct mmc_data *data;
306 void __iomem *base; /* host base address */
308 struct msdc_dma dma; /* dma channel */
311 u32 timeout_ns; /* data timeout ns */
312 u32 timeout_clks; /* data timeout clks */
314 struct pinctrl *pinctrl;
315 struct pinctrl_state *pins_default;
316 struct pinctrl_state *pins_uhs;
317 struct delayed_work req_timeout;
318 int irq; /* host interrupt */
320 struct clk *src_clk; /* msdc source clock */
321 struct clk *h_clk; /* msdc h_clk */
322 u32 mclk; /* mmc subsystem clock frequency */
323 u32 src_clk_freq; /* source clock frequency */
324 u32 sclk; /* SD/MS bus clock frequency */
325 unsigned char timing;
328 struct msdc_save_para save_para; /* used when gate HCLK */
331 static void sdr_set_bits(void __iomem *reg, u32 bs)
333 u32 val = readl(reg);
339 static void sdr_clr_bits(void __iomem *reg, u32 bs)
341 u32 val = readl(reg);
347 static void sdr_set_field(void __iomem *reg, u32 field, u32 val)
349 unsigned int tv = readl(reg);
352 tv |= ((val) << (ffs((unsigned int)field) - 1));
356 static void sdr_get_field(void __iomem *reg, u32 field, u32 *val)
358 unsigned int tv = readl(reg);
360 *val = ((tv & field) >> (ffs((unsigned int)field) - 1));
363 static void msdc_reset_hw(struct msdc_host *host)
367 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST);
368 while (readl(host->base + MSDC_CFG) & MSDC_CFG_RST)
371 sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR);
372 while (readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_CLR)
375 val = readl(host->base + MSDC_INT);
376 writel(val, host->base + MSDC_INT);
379 static void msdc_cmd_next(struct msdc_host *host,
380 struct mmc_request *mrq, struct mmc_command *cmd);
382 static const u32 cmd_ints_mask = MSDC_INTEN_CMDRDY | MSDC_INTEN_RSPCRCERR |
383 MSDC_INTEN_CMDTMO | MSDC_INTEN_ACMDRDY |
384 MSDC_INTEN_ACMDCRCERR | MSDC_INTEN_ACMDTMO;
385 static const u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO |
386 MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR |
387 MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT;
389 static u8 msdc_dma_calcs(u8 *buf, u32 len)
393 for (i = 0; i < len; i++)
395 return 0xff - (u8) sum;
398 static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma,
399 struct mmc_data *data)
401 unsigned int j, dma_len;
402 dma_addr_t dma_address;
404 struct scatterlist *sg;
405 struct mt_gpdma_desc *gpd;
406 struct mt_bdma_desc *bd;
414 gpd->gpd_info |= GPDMA_DESC_HWO;
415 gpd->gpd_info |= GPDMA_DESC_BDP;
416 /* need to clear first. use these bits to calc checksum */
417 gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM;
418 gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8;
421 for_each_sg(data->sg, sg, data->sg_count, j) {
422 dma_address = sg_dma_address(sg);
423 dma_len = sg_dma_len(sg);
426 bd[j].bd_info &= ~BDMA_DESC_BLKPAD;
427 bd[j].bd_info &= ~BDMA_DESC_DWPAD;
428 bd[j].ptr = (u32)dma_address;
429 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN;
430 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN);
432 if (j == data->sg_count - 1) /* the last bd */
433 bd[j].bd_info |= BDMA_DESC_EOL;
435 bd[j].bd_info &= ~BDMA_DESC_EOL;
437 /* checksume need to clear first */
438 bd[j].bd_info &= ~BDMA_DESC_CHECKSUM;
439 bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8;
442 sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1);
443 dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL);
444 dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE);
445 dma_ctrl |= (MSDC_BURST_64B << 12 | 1 << 8);
446 writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL);
447 writel((u32)dma->gpd_addr, host->base + MSDC_DMA_SA);
450 static void msdc_prepare_data(struct msdc_host *host, struct mmc_request *mrq)
452 struct mmc_data *data = mrq->data;
454 if (!(data->host_cookie & MSDC_PREPARE_FLAG)) {
455 bool read = (data->flags & MMC_DATA_READ) != 0;
457 data->host_cookie |= MSDC_PREPARE_FLAG;
458 data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len,
459 read ? DMA_FROM_DEVICE : DMA_TO_DEVICE);
463 static void msdc_unprepare_data(struct msdc_host *host, struct mmc_request *mrq)
465 struct mmc_data *data = mrq->data;
467 if (data->host_cookie & MSDC_ASYNC_FLAG)
470 if (data->host_cookie & MSDC_PREPARE_FLAG) {
471 bool read = (data->flags & MMC_DATA_READ) != 0;
473 dma_unmap_sg(host->dev, data->sg, data->sg_len,
474 read ? DMA_FROM_DEVICE : DMA_TO_DEVICE);
475 data->host_cookie &= ~MSDC_PREPARE_FLAG;
479 /* clock control primitives */
480 static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks)
485 host->timeout_ns = ns;
486 host->timeout_clks = clks;
487 if (host->sclk == 0) {
490 clk_ns = 1000000000UL / host->sclk;
491 timeout = (ns + clk_ns - 1) / clk_ns + clks;
492 /* in 1048576 sclk cycle unit */
493 timeout = (timeout + (0x1 << 20) - 1) >> 20;
494 sdr_get_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD, &mode);
495 /*DDR mode will double the clk cycles for data timeout */
496 timeout = mode >= 2 ? timeout * 2 : timeout;
497 timeout = timeout > 1 ? timeout - 1 : 0;
498 timeout = timeout > 255 ? 255 : timeout;
500 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, timeout);
503 static void msdc_gate_clock(struct msdc_host *host)
505 clk_disable_unprepare(host->src_clk);
506 clk_disable_unprepare(host->h_clk);
509 static void msdc_ungate_clock(struct msdc_host *host)
511 clk_prepare_enable(host->h_clk);
512 clk_prepare_enable(host->src_clk);
513 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))
517 static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
525 dev_dbg(host->dev, "set mclk to 0\n");
527 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
531 flags = readl(host->base + MSDC_INTEN);
532 sdr_clr_bits(host->base + MSDC_INTEN, flags);
533 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE);
534 if (timing == MMC_TIMING_UHS_DDR50 ||
535 timing == MMC_TIMING_MMC_DDR52 ||
536 timing == MMC_TIMING_MMC_HS400) {
537 if (timing == MMC_TIMING_MMC_HS400)
540 mode = 0x2; /* ddr mode and use divisor */
542 if (hz >= (host->src_clk_freq >> 2)) {
543 div = 0; /* mean div = 1/4 */
544 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */
546 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2);
547 sclk = (host->src_clk_freq >> 2) / div;
551 if (timing == MMC_TIMING_MMC_HS400 &&
552 hz >= (host->src_clk_freq >> 1)) {
553 sdr_set_bits(host->base + MSDC_CFG,
554 MSDC_CFG_HS400_CK_MODE);
555 sclk = host->src_clk_freq >> 1;
556 div = 0; /* div is ignore when bit18 is set */
558 } else if (hz >= host->src_clk_freq) {
559 mode = 0x1; /* no divisor */
561 sclk = host->src_clk_freq;
563 mode = 0x0; /* use divisor */
564 if (hz >= (host->src_clk_freq >> 1)) {
565 div = 0; /* mean div = 1/2 */
566 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */
568 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2);
569 sclk = (host->src_clk_freq >> 2) / div;
572 sdr_set_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD | MSDC_CFG_CKDIV,
574 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
575 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))
579 host->timing = timing;
580 /* need because clk changed. */
581 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks);
582 sdr_set_bits(host->base + MSDC_INTEN, flags);
584 dev_dbg(host->dev, "sclk: %d, timing: %d\n", host->sclk, timing);
587 static inline u32 msdc_cmd_find_resp(struct msdc_host *host,
588 struct mmc_request *mrq, struct mmc_command *cmd)
592 switch (mmc_resp_type(cmd)) {
593 /* Actually, R1, R5, R6, R7 are the same */
615 static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host,
616 struct mmc_request *mrq, struct mmc_command *cmd)
619 * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 |
620 * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode
622 u32 opcode = cmd->opcode;
623 u32 resp = msdc_cmd_find_resp(host, mrq, cmd);
624 u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7);
626 host->cmd_rsp = resp;
628 if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) ||
629 opcode == MMC_STOP_TRANSMISSION)
630 rawcmd |= (0x1 << 14);
631 else if (opcode == SD_SWITCH_VOLTAGE)
632 rawcmd |= (0x1 << 30);
633 else if (opcode == SD_APP_SEND_SCR ||
634 opcode == SD_APP_SEND_NUM_WR_BLKS ||
635 (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) ||
636 (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) ||
637 (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC))
638 rawcmd |= (0x1 << 11);
641 struct mmc_data *data = cmd->data;
643 if (mmc_op_multi(opcode)) {
644 if (mmc_card_mmc(host->mmc->card) && mrq->sbc &&
645 !(mrq->sbc->arg & 0xFFFF0000))
646 rawcmd |= 0x2 << 28; /* AutoCMD23 */
649 rawcmd |= ((data->blksz & 0xFFF) << 16);
650 if (data->flags & MMC_DATA_WRITE)
651 rawcmd |= (0x1 << 13);
652 if (data->blocks > 1)
653 rawcmd |= (0x2 << 11);
655 rawcmd |= (0x1 << 11);
656 /* Always use dma mode */
657 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO);
659 if (host->timeout_ns != data->timeout_ns ||
660 host->timeout_clks != data->timeout_clks)
661 msdc_set_timeout(host, data->timeout_ns,
664 writel(data->blocks, host->base + SDC_BLK_NUM);
669 static void msdc_start_data(struct msdc_host *host, struct mmc_request *mrq,
670 struct mmc_command *cmd, struct mmc_data *data)
676 read = data->flags & MMC_DATA_READ;
678 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT);
679 msdc_dma_setup(host, &host->dma, data);
680 sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask);
681 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1);
682 dev_dbg(host->dev, "DMA start\n");
683 dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n",
684 __func__, cmd->opcode, data->blocks, read);
687 static int msdc_auto_cmd_done(struct msdc_host *host, int events,
688 struct mmc_command *cmd)
690 u32 *rsp = cmd->resp;
692 rsp[0] = readl(host->base + SDC_ACMD_RESP);
694 if (events & MSDC_INT_ACMDRDY) {
698 if (events & MSDC_INT_ACMDCRCERR) {
699 cmd->error = -EILSEQ;
700 host->error |= REQ_STOP_EIO;
701 } else if (events & MSDC_INT_ACMDTMO) {
702 cmd->error = -ETIMEDOUT;
703 host->error |= REQ_STOP_TMO;
706 "%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n",
707 __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error);
712 static void msdc_track_cmd_data(struct msdc_host *host,
713 struct mmc_command *cmd, struct mmc_data *data)
716 dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n",
717 __func__, cmd->opcode, cmd->arg, host->error);
720 static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq)
725 * No need check the return value of cancel_delayed_work, as only ONE
728 cancel_delayed_work(&host->req_timeout);
730 spin_lock_irqsave(&host->lock, flags);
732 spin_unlock_irqrestore(&host->lock, flags);
734 msdc_track_cmd_data(host, mrq->cmd, mrq->data);
736 msdc_unprepare_data(host, mrq);
737 mmc_request_done(host->mmc, mrq);
739 pm_runtime_mark_last_busy(host->dev);
740 pm_runtime_put_autosuspend(host->dev);
743 /* returns true if command is fully handled; returns false otherwise */
744 static bool msdc_cmd_done(struct msdc_host *host, int events,
745 struct mmc_request *mrq, struct mmc_command *cmd)
752 if (mrq->sbc && cmd == mrq->cmd &&
753 (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR
754 | MSDC_INT_ACMDTMO)))
755 msdc_auto_cmd_done(host, events, mrq->sbc);
757 sbc_error = mrq->sbc && mrq->sbc->error;
759 if (!sbc_error && !(events & (MSDC_INT_CMDRDY
764 spin_lock_irqsave(&host->lock, flags);
767 spin_unlock_irqrestore(&host->lock, flags);
773 sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask);
775 if (cmd->flags & MMC_RSP_PRESENT) {
776 if (cmd->flags & MMC_RSP_136) {
777 rsp[0] = readl(host->base + SDC_RESP3);
778 rsp[1] = readl(host->base + SDC_RESP2);
779 rsp[2] = readl(host->base + SDC_RESP1);
780 rsp[3] = readl(host->base + SDC_RESP0);
782 rsp[0] = readl(host->base + SDC_RESP0);
786 if (!sbc_error && !(events & MSDC_INT_CMDRDY)) {
788 if (events & MSDC_INT_RSPCRCERR) {
789 cmd->error = -EILSEQ;
790 host->error |= REQ_CMD_EIO;
791 } else if (events & MSDC_INT_CMDTMO) {
792 cmd->error = -ETIMEDOUT;
793 host->error |= REQ_CMD_TMO;
798 "%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n",
799 __func__, cmd->opcode, cmd->arg, rsp[0],
802 msdc_cmd_next(host, mrq, cmd);
806 /* It is the core layer's responsibility to ensure card status
807 * is correct before issue a request. but host design do below
808 * checks recommended.
810 static inline bool msdc_cmd_is_ready(struct msdc_host *host,
811 struct mmc_request *mrq, struct mmc_command *cmd)
813 /* The max busy time we can endure is 20ms */
814 unsigned long tmo = jiffies + msecs_to_jiffies(20);
816 while ((readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) &&
817 time_before(jiffies, tmo))
819 if (readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) {
820 dev_err(host->dev, "CMD bus busy detected\n");
821 host->error |= REQ_CMD_BUSY;
822 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
826 if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) {
827 tmo = jiffies + msecs_to_jiffies(20);
828 /* R1B or with data, should check SDCBUSY */
829 while ((readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) &&
830 time_before(jiffies, tmo))
832 if (readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) {
833 dev_err(host->dev, "Controller busy detected\n");
834 host->error |= REQ_CMD_BUSY;
835 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
842 static void msdc_start_command(struct msdc_host *host,
843 struct mmc_request *mrq, struct mmc_command *cmd)
850 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT);
851 if (!msdc_cmd_is_ready(host, mrq, cmd))
854 if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 ||
855 readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) {
856 dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n");
861 rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd);
863 sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask);
864 writel(cmd->arg, host->base + SDC_ARG);
865 writel(rawcmd, host->base + SDC_CMD);
868 static void msdc_cmd_next(struct msdc_host *host,
869 struct mmc_request *mrq, struct mmc_command *cmd)
871 if (cmd->error || (mrq->sbc && mrq->sbc->error))
872 msdc_request_done(host, mrq);
873 else if (cmd == mrq->sbc)
874 msdc_start_command(host, mrq, mrq->cmd);
876 msdc_request_done(host, mrq);
878 msdc_start_data(host, mrq, cmd, cmd->data);
881 static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq)
883 struct msdc_host *host = mmc_priv(mmc);
889 pm_runtime_get_sync(host->dev);
892 msdc_prepare_data(host, mrq);
894 /* if SBC is required, we have HW option and SW option.
895 * if HW option is enabled, and SBC does not have "special" flags,
896 * use HW option, otherwise use SW option
898 if (mrq->sbc && (!mmc_card_mmc(mmc->card) ||
899 (mrq->sbc->arg & 0xFFFF0000)))
900 msdc_start_command(host, mrq, mrq->sbc);
902 msdc_start_command(host, mrq, mrq->cmd);
905 static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
908 struct msdc_host *host = mmc_priv(mmc);
909 struct mmc_data *data = mrq->data;
914 msdc_prepare_data(host, mrq);
915 data->host_cookie |= MSDC_ASYNC_FLAG;
918 static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
921 struct msdc_host *host = mmc_priv(mmc);
922 struct mmc_data *data;
927 if (data->host_cookie) {
928 data->host_cookie &= ~MSDC_ASYNC_FLAG;
929 msdc_unprepare_data(host, mrq);
933 static void msdc_data_xfer_next(struct msdc_host *host,
934 struct mmc_request *mrq, struct mmc_data *data)
936 if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error &&
938 msdc_start_command(host, mrq, mrq->stop);
940 msdc_request_done(host, mrq);
943 static bool msdc_data_xfer_done(struct msdc_host *host, u32 events,
944 struct mmc_request *mrq, struct mmc_data *data)
946 struct mmc_command *stop;
949 unsigned int check_data = events &
950 (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO
951 | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR
952 | MSDC_INT_DMA_PROTECT);
954 spin_lock_irqsave(&host->lock, flags);
958 spin_unlock_irqrestore(&host->lock, flags);
964 if (check_data || (stop && stop->error)) {
965 dev_dbg(host->dev, "DMA status: 0x%8X\n",
966 readl(host->base + MSDC_DMA_CFG));
967 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP,
969 while (readl(host->base + MSDC_DMA_CFG) & MSDC_DMA_CFG_STS)
971 sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask);
972 dev_dbg(host->dev, "DMA stop\n");
974 if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) {
975 data->bytes_xfered = data->blocks * data->blksz;
977 dev_err(host->dev, "interrupt events: %x\n", events);
979 host->error |= REQ_DAT_ERR;
980 data->bytes_xfered = 0;
982 if (events & MSDC_INT_DATTMO)
983 data->error = -ETIMEDOUT;
984 else if (events & MSDC_INT_DATCRCERR)
985 data->error = -EILSEQ;
987 dev_err(host->dev, "%s: cmd=%d; blocks=%d",
988 __func__, mrq->cmd->opcode, data->blocks);
989 dev_err(host->dev, "data_error=%d xfer_size=%d\n",
990 (int)data->error, data->bytes_xfered);
993 msdc_data_xfer_next(host, mrq, data);
999 static void msdc_set_buswidth(struct msdc_host *host, u32 width)
1001 u32 val = readl(host->base + SDC_CFG);
1003 val &= ~SDC_CFG_BUSWIDTH;
1007 case MMC_BUS_WIDTH_1:
1008 val |= (MSDC_BUS_1BITS << 16);
1010 case MMC_BUS_WIDTH_4:
1011 val |= (MSDC_BUS_4BITS << 16);
1013 case MMC_BUS_WIDTH_8:
1014 val |= (MSDC_BUS_8BITS << 16);
1018 writel(val, host->base + SDC_CFG);
1019 dev_dbg(host->dev, "Bus Width = %d", width);
1022 static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios)
1024 struct msdc_host *host = mmc_priv(mmc);
1028 if (!IS_ERR(mmc->supply.vqmmc)) {
1029 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
1032 } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
1036 dev_err(host->dev, "Unsupported signal voltage!\n");
1040 ret = regulator_set_voltage(mmc->supply.vqmmc, min_uv, max_uv);
1043 "Regulator set error %d: %d - %d\n",
1044 ret, min_uv, max_uv);
1046 /* Apply different pinctrl settings for different signal voltage */
1047 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
1048 pinctrl_select_state(host->pinctrl, host->pins_uhs);
1050 pinctrl_select_state(host->pinctrl, host->pins_default);
1056 static int msdc_card_busy(struct mmc_host *mmc)
1058 struct msdc_host *host = mmc_priv(mmc);
1059 u32 status = readl(host->base + MSDC_PS);
1061 /* check if any pin between dat[0:3] is low */
1062 if (((status >> 16) & 0xf) != 0xf)
1068 static void msdc_request_timeout(struct work_struct *work)
1070 struct msdc_host *host = container_of(work, struct msdc_host,
1073 /* simulate HW timeout status */
1074 dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__);
1076 dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__,
1077 host->mrq, host->mrq->cmd->opcode);
1079 dev_err(host->dev, "%s: aborting cmd=%d\n",
1080 __func__, host->cmd->opcode);
1081 msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq,
1083 } else if (host->data) {
1084 dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n",
1085 __func__, host->mrq->cmd->opcode,
1086 host->data->blocks);
1087 msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq,
1093 static irqreturn_t msdc_irq(int irq, void *dev_id)
1095 struct msdc_host *host = (struct msdc_host *) dev_id;
1098 unsigned long flags;
1099 struct mmc_request *mrq;
1100 struct mmc_command *cmd;
1101 struct mmc_data *data;
1102 u32 events, event_mask;
1104 spin_lock_irqsave(&host->lock, flags);
1105 events = readl(host->base + MSDC_INT);
1106 event_mask = readl(host->base + MSDC_INTEN);
1107 /* clear interrupts */
1108 writel(events & event_mask, host->base + MSDC_INT);
1113 spin_unlock_irqrestore(&host->lock, flags);
1115 if (!(events & event_mask))
1120 "%s: MRQ=NULL; events=%08X; event_mask=%08X\n",
1121 __func__, events, event_mask);
1126 dev_dbg(host->dev, "%s: events=%08X\n", __func__, events);
1129 msdc_cmd_done(host, events, mrq, cmd);
1131 msdc_data_xfer_done(host, events, mrq, data);
1137 static void msdc_init_hw(struct msdc_host *host)
1141 /* Configure to MMC/SD mode, clock free running */
1142 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN);
1145 msdc_reset_hw(host);
1147 /* Disable card detection */
1148 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1150 /* Disable and clear all interrupts */
1151 writel(0, host->base + MSDC_INTEN);
1152 val = readl(host->base + MSDC_INT);
1153 writel(val, host->base + MSDC_INT);
1155 writel(0, host->base + MSDC_PAD_TUNE);
1156 writel(0, host->base + MSDC_IOCON);
1157 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0);
1158 writel(0x403c0046, host->base + MSDC_PATCH_BIT);
1159 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1);
1160 writel(0xffff0089, host->base + MSDC_PATCH_BIT1);
1161 sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL);
1163 /* Configure to enable SDIO mode.
1164 * it's must otherwise sdio cmd5 failed
1166 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO);
1168 /* disable detect SDIO device interrupt function */
1169 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1171 /* Configure to default data timeout */
1172 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3);
1174 dev_dbg(host->dev, "init hardware done!");
1177 static void msdc_deinit_hw(struct msdc_host *host)
1180 /* Disable and clear all interrupts */
1181 writel(0, host->base + MSDC_INTEN);
1183 val = readl(host->base + MSDC_INT);
1184 writel(val, host->base + MSDC_INT);
1187 /* init gpd and bd list in msdc_drv_probe */
1188 static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma)
1190 struct mt_gpdma_desc *gpd = dma->gpd;
1191 struct mt_bdma_desc *bd = dma->bd;
1194 memset(gpd, 0, sizeof(struct mt_gpdma_desc) * 2);
1196 gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */
1197 gpd->ptr = (u32)dma->bd_addr; /* physical address */
1198 /* gpd->next is must set for desc DMA
1199 * That's why must alloc 2 gpd structure.
1201 gpd->next = (u32)dma->gpd_addr + sizeof(struct mt_gpdma_desc);
1202 memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM);
1203 for (i = 0; i < (MAX_BD_NUM - 1); i++)
1204 bd[i].next = (u32)dma->bd_addr + sizeof(*bd) * (i + 1);
1207 static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1209 struct msdc_host *host = mmc_priv(mmc);
1212 pm_runtime_get_sync(host->dev);
1214 msdc_set_buswidth(host, ios->bus_width);
1216 /* Suspend/Resume will do power off/on */
1217 switch (ios->power_mode) {
1219 if (!IS_ERR(mmc->supply.vmmc)) {
1221 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1224 dev_err(host->dev, "Failed to set vmmc power!\n");
1230 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
1231 ret = regulator_enable(mmc->supply.vqmmc);
1233 dev_err(host->dev, "Failed to set vqmmc power!\n");
1235 host->vqmmc_enabled = true;
1239 if (!IS_ERR(mmc->supply.vmmc))
1240 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1242 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
1243 regulator_disable(mmc->supply.vqmmc);
1244 host->vqmmc_enabled = false;
1251 if (host->mclk != ios->clock || host->timing != ios->timing)
1252 msdc_set_mclk(host, ios->timing, ios->clock);
1255 pm_runtime_mark_last_busy(host->dev);
1256 pm_runtime_put_autosuspend(host->dev);
1259 static u32 test_delay_bit(u32 delay, u32 bit)
1261 bit %= PAD_DELAY_MAX;
1262 return delay & (1 << bit);
1265 static int get_delay_len(u32 delay, u32 start_bit)
1269 for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) {
1270 if (test_delay_bit(delay, start_bit + i) == 0)
1273 return PAD_DELAY_MAX - start_bit;
1276 static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay)
1278 int start = 0, len = 0;
1279 int start_final = 0, len_final = 0;
1280 u8 final_phase = 0xff;
1281 struct msdc_delay_phase delay_phase = { 0, };
1284 dev_err(host->dev, "phase error: [map:%x]\n", delay);
1285 delay_phase.final_phase = final_phase;
1289 while (start < PAD_DELAY_MAX) {
1290 len = get_delay_len(delay, start);
1291 if (len_final < len) {
1292 start_final = start;
1295 start += len ? len : 1;
1296 if (len >= 8 && start_final < 4)
1300 /* The rule is that to find the smallest delay cell */
1301 if (start_final == 0)
1302 final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX;
1304 final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX;
1305 dev_info(host->dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n",
1306 delay, len_final, final_phase);
1308 delay_phase.maxlen = len_final;
1309 delay_phase.start = start_final;
1310 delay_phase.final_phase = final_phase;
1314 static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)
1316 struct msdc_host *host = mmc_priv(mmc);
1317 u32 rise_delay = 0, fall_delay = 0;
1318 struct msdc_delay_phase final_rise_delay, final_fall_delay;
1319 u8 final_delay, final_maxlen;
1323 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1324 for (i = 0 ; i < PAD_DELAY_MAX; i++) {
1325 sdr_set_field(host->base + MSDC_PAD_TUNE,
1326 MSDC_PAD_TUNE_CMDRDLY, i);
1327 mmc_send_tuning(mmc, opcode, &cmd_err);
1329 rise_delay |= (1 << i);
1332 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1333 for (i = 0; i < PAD_DELAY_MAX; i++) {
1334 sdr_set_field(host->base + MSDC_PAD_TUNE,
1335 MSDC_PAD_TUNE_CMDRDLY, i);
1336 mmc_send_tuning(mmc, opcode, &cmd_err);
1338 fall_delay |= (1 << i);
1341 final_rise_delay = get_best_delay(host, rise_delay);
1342 final_fall_delay = get_best_delay(host, fall_delay);
1344 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
1345 if (final_maxlen == final_rise_delay.maxlen) {
1346 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1347 sdr_set_field(host->base + MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRDLY,
1348 final_rise_delay.final_phase);
1349 final_delay = final_rise_delay.final_phase;
1351 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1352 sdr_set_field(host->base + MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRDLY,
1353 final_fall_delay.final_phase);
1354 final_delay = final_fall_delay.final_phase;
1357 return final_delay == 0xff ? -EIO : 0;
1360 static int msdc_tune_data(struct mmc_host *mmc, u32 opcode)
1362 struct msdc_host *host = mmc_priv(mmc);
1363 u32 rise_delay = 0, fall_delay = 0;
1364 struct msdc_delay_phase final_rise_delay, final_fall_delay;
1365 u8 final_delay, final_maxlen;
1368 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
1369 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
1370 for (i = 0 ; i < PAD_DELAY_MAX; i++) {
1371 sdr_set_field(host->base + MSDC_PAD_TUNE,
1372 MSDC_PAD_TUNE_DATRRDLY, i);
1373 ret = mmc_send_tuning(mmc, opcode, NULL);
1375 rise_delay |= (1 << i);
1378 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
1379 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
1380 for (i = 0; i < PAD_DELAY_MAX; i++) {
1381 sdr_set_field(host->base + MSDC_PAD_TUNE,
1382 MSDC_PAD_TUNE_DATRRDLY, i);
1383 ret = mmc_send_tuning(mmc, opcode, NULL);
1385 fall_delay |= (1 << i);
1388 final_rise_delay = get_best_delay(host, rise_delay);
1389 final_fall_delay = get_best_delay(host, fall_delay);
1391 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
1392 /* Rising edge is more stable, prefer to use it */
1393 if (final_rise_delay.maxlen >= 10)
1394 final_maxlen = final_rise_delay.maxlen;
1395 if (final_maxlen == final_rise_delay.maxlen) {
1396 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
1397 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
1398 sdr_set_field(host->base + MSDC_PAD_TUNE,
1399 MSDC_PAD_TUNE_DATRRDLY,
1400 final_rise_delay.final_phase);
1401 final_delay = final_rise_delay.final_phase;
1403 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
1404 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
1405 sdr_set_field(host->base + MSDC_PAD_TUNE,
1406 MSDC_PAD_TUNE_DATRRDLY,
1407 final_fall_delay.final_phase);
1408 final_delay = final_fall_delay.final_phase;
1411 return final_delay == 0xff ? -EIO : 0;
1414 static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode)
1416 struct msdc_host *host = mmc_priv(mmc);
1419 pm_runtime_get_sync(host->dev);
1420 ret = msdc_tune_response(mmc, opcode);
1422 dev_err(host->dev, "Tune response fail!\n");
1425 ret = msdc_tune_data(mmc, opcode);
1427 dev_err(host->dev, "Tune data fail!\n");
1430 pm_runtime_mark_last_busy(host->dev);
1431 pm_runtime_put_autosuspend(host->dev);
1435 static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
1437 struct msdc_host *host = mmc_priv(mmc);
1439 writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE);
1443 static void msdc_hw_reset(struct mmc_host *mmc)
1445 struct msdc_host *host = mmc_priv(mmc);
1447 sdr_set_bits(host->base + EMMC_IOCON, 1);
1448 udelay(10); /* 10us is enough */
1449 sdr_clr_bits(host->base + EMMC_IOCON, 1);
1452 static struct mmc_host_ops mt_msdc_ops = {
1453 .post_req = msdc_post_req,
1454 .pre_req = msdc_pre_req,
1455 .request = msdc_ops_request,
1456 .set_ios = msdc_ops_set_ios,
1457 .start_signal_voltage_switch = msdc_ops_switch_volt,
1458 .card_busy = msdc_card_busy,
1459 .execute_tuning = msdc_execute_tuning,
1460 .prepare_hs400_tuning = msdc_prepare_hs400_tuning,
1461 .hw_reset = msdc_hw_reset,
1464 static int msdc_drv_probe(struct platform_device *pdev)
1466 struct mmc_host *mmc;
1467 struct msdc_host *host;
1468 struct resource *res;
1471 if (!pdev->dev.of_node) {
1472 dev_err(&pdev->dev, "No DT found\n");
1475 /* Allocate MMC host for this device */
1476 mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev);
1480 host = mmc_priv(mmc);
1481 ret = mmc_of_parse(mmc);
1485 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1486 host->base = devm_ioremap_resource(&pdev->dev, res);
1487 if (IS_ERR(host->base)) {
1488 ret = PTR_ERR(host->base);
1492 ret = mmc_regulator_get_supply(mmc);
1493 if (ret == -EPROBE_DEFER)
1496 host->src_clk = devm_clk_get(&pdev->dev, "source");
1497 if (IS_ERR(host->src_clk)) {
1498 ret = PTR_ERR(host->src_clk);
1502 host->h_clk = devm_clk_get(&pdev->dev, "hclk");
1503 if (IS_ERR(host->h_clk)) {
1504 ret = PTR_ERR(host->h_clk);
1508 host->irq = platform_get_irq(pdev, 0);
1509 if (host->irq < 0) {
1514 host->pinctrl = devm_pinctrl_get(&pdev->dev);
1515 if (IS_ERR(host->pinctrl)) {
1516 ret = PTR_ERR(host->pinctrl);
1517 dev_err(&pdev->dev, "Cannot find pinctrl!\n");
1521 host->pins_default = pinctrl_lookup_state(host->pinctrl, "default");
1522 if (IS_ERR(host->pins_default)) {
1523 ret = PTR_ERR(host->pins_default);
1524 dev_err(&pdev->dev, "Cannot find pinctrl default!\n");
1528 host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs");
1529 if (IS_ERR(host->pins_uhs)) {
1530 ret = PTR_ERR(host->pins_uhs);
1531 dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n");
1535 if (!of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay",
1536 &host->hs400_ds_delay))
1537 dev_dbg(&pdev->dev, "hs400-ds-delay: %x\n",
1538 host->hs400_ds_delay);
1540 host->dev = &pdev->dev;
1542 host->src_clk_freq = clk_get_rate(host->src_clk);
1543 /* Set host parameters to mmc */
1544 mmc->ops = &mt_msdc_ops;
1545 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255);
1547 mmc->caps |= MMC_CAP_ERASE | MMC_CAP_CMD23;
1548 mmc->caps |= MMC_CAP_RUNTIME_RESUME;
1549 /* MMC core transfer sizes tunable parameters */
1550 mmc->max_segs = MAX_BD_NUM;
1551 mmc->max_seg_size = BDMA_DESC_BUFLEN;
1552 mmc->max_blk_size = 2048;
1553 mmc->max_req_size = 512 * 1024;
1554 mmc->max_blk_count = mmc->max_req_size / 512;
1555 host->dma_mask = DMA_BIT_MASK(32);
1556 mmc_dev(mmc)->dma_mask = &host->dma_mask;
1558 host->timeout_clks = 3 * 1048576;
1559 host->dma.gpd = dma_alloc_coherent(&pdev->dev,
1560 2 * sizeof(struct mt_gpdma_desc),
1561 &host->dma.gpd_addr, GFP_KERNEL);
1562 host->dma.bd = dma_alloc_coherent(&pdev->dev,
1563 MAX_BD_NUM * sizeof(struct mt_bdma_desc),
1564 &host->dma.bd_addr, GFP_KERNEL);
1565 if (!host->dma.gpd || !host->dma.bd) {
1569 msdc_init_gpd_bd(host, &host->dma);
1570 INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout);
1571 spin_lock_init(&host->lock);
1573 platform_set_drvdata(pdev, mmc);
1574 msdc_ungate_clock(host);
1577 ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq,
1578 IRQF_TRIGGER_LOW | IRQF_ONESHOT, pdev->name, host);
1582 pm_runtime_set_active(host->dev);
1583 pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY);
1584 pm_runtime_use_autosuspend(host->dev);
1585 pm_runtime_enable(host->dev);
1586 ret = mmc_add_host(mmc);
1593 pm_runtime_disable(host->dev);
1595 platform_set_drvdata(pdev, NULL);
1596 msdc_deinit_hw(host);
1597 msdc_gate_clock(host);
1600 dma_free_coherent(&pdev->dev,
1601 2 * sizeof(struct mt_gpdma_desc),
1602 host->dma.gpd, host->dma.gpd_addr);
1604 dma_free_coherent(&pdev->dev,
1605 MAX_BD_NUM * sizeof(struct mt_bdma_desc),
1606 host->dma.bd, host->dma.bd_addr);
1613 static int msdc_drv_remove(struct platform_device *pdev)
1615 struct mmc_host *mmc;
1616 struct msdc_host *host;
1618 mmc = platform_get_drvdata(pdev);
1619 host = mmc_priv(mmc);
1621 pm_runtime_get_sync(host->dev);
1623 platform_set_drvdata(pdev, NULL);
1624 mmc_remove_host(host->mmc);
1625 msdc_deinit_hw(host);
1626 msdc_gate_clock(host);
1628 pm_runtime_disable(host->dev);
1629 pm_runtime_put_noidle(host->dev);
1630 dma_free_coherent(&pdev->dev,
1631 sizeof(struct mt_gpdma_desc),
1632 host->dma.gpd, host->dma.gpd_addr);
1633 dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc),
1634 host->dma.bd, host->dma.bd_addr);
1636 mmc_free_host(host->mmc);
1642 static void msdc_save_reg(struct msdc_host *host)
1644 host->save_para.msdc_cfg = readl(host->base + MSDC_CFG);
1645 host->save_para.iocon = readl(host->base + MSDC_IOCON);
1646 host->save_para.sdc_cfg = readl(host->base + SDC_CFG);
1647 host->save_para.pad_tune = readl(host->base + MSDC_PAD_TUNE);
1648 host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT);
1649 host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1);
1650 host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE);
1651 host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0);
1654 static void msdc_restore_reg(struct msdc_host *host)
1656 writel(host->save_para.msdc_cfg, host->base + MSDC_CFG);
1657 writel(host->save_para.iocon, host->base + MSDC_IOCON);
1658 writel(host->save_para.sdc_cfg, host->base + SDC_CFG);
1659 writel(host->save_para.pad_tune, host->base + MSDC_PAD_TUNE);
1660 writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT);
1661 writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1);
1662 writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE);
1663 writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0);
1666 static int msdc_runtime_suspend(struct device *dev)
1668 struct mmc_host *mmc = dev_get_drvdata(dev);
1669 struct msdc_host *host = mmc_priv(mmc);
1671 msdc_save_reg(host);
1672 msdc_gate_clock(host);
1676 static int msdc_runtime_resume(struct device *dev)
1678 struct mmc_host *mmc = dev_get_drvdata(dev);
1679 struct msdc_host *host = mmc_priv(mmc);
1681 msdc_ungate_clock(host);
1682 msdc_restore_reg(host);
1687 static const struct dev_pm_ops msdc_dev_pm_ops = {
1688 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1689 pm_runtime_force_resume)
1690 SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL)
1693 static const struct of_device_id msdc_of_ids[] = {
1694 { .compatible = "mediatek,mt8135-mmc", },
1698 static struct platform_driver mt_msdc_driver = {
1699 .probe = msdc_drv_probe,
1700 .remove = msdc_drv_remove,
1703 .of_match_table = msdc_of_ids,
1704 .pm = &msdc_dev_pm_ops,
1708 module_platform_driver(mt_msdc_driver);
1709 MODULE_LICENSE("GPL v2");
1710 MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver");