2 * Copyright (c) 2014-2015 MediaTek Inc.
3 * Author: Chaotian.Jing <chaotian.jing@mediatek.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #include <linux/module.h>
16 #include <linux/clk.h>
17 #include <linux/delay.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/ioport.h>
20 #include <linux/irq.h>
21 #include <linux/of_address.h>
22 #include <linux/of_irq.h>
23 #include <linux/of_gpio.h>
24 #include <linux/pinctrl/consumer.h>
25 #include <linux/platform_device.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/regulator/consumer.h>
29 #include <linux/slab.h>
30 #include <linux/spinlock.h>
32 #include <linux/mmc/card.h>
33 #include <linux/mmc/core.h>
34 #include <linux/mmc/host.h>
35 #include <linux/mmc/mmc.h>
36 #include <linux/mmc/sd.h>
37 #include <linux/mmc/sdio.h>
38 #include <linux/mmc/slot-gpio.h>
40 #define MAX_BD_NUM 1024
42 /*--------------------------------------------------------------------------*/
43 /* Common Definition */
44 /*--------------------------------------------------------------------------*/
45 #define MSDC_BUS_1BITS 0x0
46 #define MSDC_BUS_4BITS 0x1
47 #define MSDC_BUS_8BITS 0x2
49 #define MSDC_BURST_64B 0x6
51 /*--------------------------------------------------------------------------*/
53 /*--------------------------------------------------------------------------*/
55 #define MSDC_IOCON 0x04
58 #define MSDC_INTEN 0x10
59 #define MSDC_FIFOCS 0x14
64 #define SDC_RESP0 0x40
65 #define SDC_RESP1 0x44
66 #define SDC_RESP2 0x48
67 #define SDC_RESP3 0x4c
68 #define SDC_BLK_NUM 0x50
69 #define EMMC_IOCON 0x7c
70 #define SDC_ACMD_RESP 0x80
71 #define MSDC_DMA_SA 0x90
72 #define MSDC_DMA_CTRL 0x98
73 #define MSDC_DMA_CFG 0x9c
74 #define MSDC_PATCH_BIT 0xb0
75 #define MSDC_PATCH_BIT1 0xb4
76 #define MSDC_PAD_TUNE 0xec
77 #define PAD_DS_TUNE 0x188
78 #define EMMC50_CFG0 0x208
80 /*--------------------------------------------------------------------------*/
82 /*--------------------------------------------------------------------------*/
85 #define MSDC_CFG_MODE (0x1 << 0) /* RW */
86 #define MSDC_CFG_CKPDN (0x1 << 1) /* RW */
87 #define MSDC_CFG_RST (0x1 << 2) /* RW */
88 #define MSDC_CFG_PIO (0x1 << 3) /* RW */
89 #define MSDC_CFG_CKDRVEN (0x1 << 4) /* RW */
90 #define MSDC_CFG_BV18SDT (0x1 << 5) /* RW */
91 #define MSDC_CFG_BV18PSS (0x1 << 6) /* R */
92 #define MSDC_CFG_CKSTB (0x1 << 7) /* R */
93 #define MSDC_CFG_CKDIV (0xff << 8) /* RW */
94 #define MSDC_CFG_CKMOD (0x3 << 16) /* RW */
95 #define MSDC_CFG_HS400_CK_MODE (0x1 << 18) /* RW */
98 #define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */
99 #define MSDC_IOCON_RSPL (0x1 << 1) /* RW */
100 #define MSDC_IOCON_DSPL (0x1 << 2) /* RW */
101 #define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */
102 #define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */
103 #define MSDC_IOCON_DSPLSEL (0x1 << 5) /* RW */
104 #define MSDC_IOCON_W_DSPL (0x1 << 8) /* RW */
105 #define MSDC_IOCON_D0SPL (0x1 << 16) /* RW */
106 #define MSDC_IOCON_D1SPL (0x1 << 17) /* RW */
107 #define MSDC_IOCON_D2SPL (0x1 << 18) /* RW */
108 #define MSDC_IOCON_D3SPL (0x1 << 19) /* RW */
109 #define MSDC_IOCON_D4SPL (0x1 << 20) /* RW */
110 #define MSDC_IOCON_D5SPL (0x1 << 21) /* RW */
111 #define MSDC_IOCON_D6SPL (0x1 << 22) /* RW */
112 #define MSDC_IOCON_D7SPL (0x1 << 23) /* RW */
113 #define MSDC_IOCON_RISCSZ (0x3 << 24) /* RW */
116 #define MSDC_PS_CDEN (0x1 << 0) /* RW */
117 #define MSDC_PS_CDSTS (0x1 << 1) /* R */
118 #define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */
119 #define MSDC_PS_DAT (0xff << 16) /* R */
120 #define MSDC_PS_CMD (0x1 << 24) /* R */
121 #define MSDC_PS_WP (0x1 << 31) /* R */
124 #define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */
125 #define MSDC_INT_CDSC (0x1 << 1) /* W1C */
126 #define MSDC_INT_ACMDRDY (0x1 << 3) /* W1C */
127 #define MSDC_INT_ACMDTMO (0x1 << 4) /* W1C */
128 #define MSDC_INT_ACMDCRCERR (0x1 << 5) /* W1C */
129 #define MSDC_INT_DMAQ_EMPTY (0x1 << 6) /* W1C */
130 #define MSDC_INT_SDIOIRQ (0x1 << 7) /* W1C */
131 #define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */
132 #define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */
133 #define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */
134 #define MSDC_INT_CSTA (0x1 << 11) /* R */
135 #define MSDC_INT_XFER_COMPL (0x1 << 12) /* W1C */
136 #define MSDC_INT_DXFER_DONE (0x1 << 13) /* W1C */
137 #define MSDC_INT_DATTMO (0x1 << 14) /* W1C */
138 #define MSDC_INT_DATCRCERR (0x1 << 15) /* W1C */
139 #define MSDC_INT_ACMD19_DONE (0x1 << 16) /* W1C */
140 #define MSDC_INT_DMA_BDCSERR (0x1 << 17) /* W1C */
141 #define MSDC_INT_DMA_GPDCSERR (0x1 << 18) /* W1C */
142 #define MSDC_INT_DMA_PROTECT (0x1 << 19) /* W1C */
144 /* MSDC_INTEN mask */
145 #define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */
146 #define MSDC_INTEN_CDSC (0x1 << 1) /* RW */
147 #define MSDC_INTEN_ACMDRDY (0x1 << 3) /* RW */
148 #define MSDC_INTEN_ACMDTMO (0x1 << 4) /* RW */
149 #define MSDC_INTEN_ACMDCRCERR (0x1 << 5) /* RW */
150 #define MSDC_INTEN_DMAQ_EMPTY (0x1 << 6) /* RW */
151 #define MSDC_INTEN_SDIOIRQ (0x1 << 7) /* RW */
152 #define MSDC_INTEN_CMDRDY (0x1 << 8) /* RW */
153 #define MSDC_INTEN_CMDTMO (0x1 << 9) /* RW */
154 #define MSDC_INTEN_RSPCRCERR (0x1 << 10) /* RW */
155 #define MSDC_INTEN_CSTA (0x1 << 11) /* RW */
156 #define MSDC_INTEN_XFER_COMPL (0x1 << 12) /* RW */
157 #define MSDC_INTEN_DXFER_DONE (0x1 << 13) /* RW */
158 #define MSDC_INTEN_DATTMO (0x1 << 14) /* RW */
159 #define MSDC_INTEN_DATCRCERR (0x1 << 15) /* RW */
160 #define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */
161 #define MSDC_INTEN_DMA_BDCSERR (0x1 << 17) /* RW */
162 #define MSDC_INTEN_DMA_GPDCSERR (0x1 << 18) /* RW */
163 #define MSDC_INTEN_DMA_PROTECT (0x1 << 19) /* RW */
165 /* MSDC_FIFOCS mask */
166 #define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */
167 #define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */
168 #define MSDC_FIFOCS_CLR (0x1 << 31) /* RW */
171 #define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */
172 #define SDC_CFG_INSWKUP (0x1 << 1) /* RW */
173 #define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */
174 #define SDC_CFG_SDIO (0x1 << 19) /* RW */
175 #define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */
176 #define SDC_CFG_INTATGAP (0x1 << 21) /* RW */
177 #define SDC_CFG_DTOC (0xff << 24) /* RW */
180 #define SDC_STS_SDCBUSY (0x1 << 0) /* RW */
181 #define SDC_STS_CMDBUSY (0x1 << 1) /* RW */
182 #define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */
184 /* MSDC_DMA_CTRL mask */
185 #define MSDC_DMA_CTRL_START (0x1 << 0) /* W */
186 #define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */
187 #define MSDC_DMA_CTRL_RESUME (0x1 << 2) /* W */
188 #define MSDC_DMA_CTRL_MODE (0x1 << 8) /* RW */
189 #define MSDC_DMA_CTRL_LASTBUF (0x1 << 10) /* RW */
190 #define MSDC_DMA_CTRL_BRUSTSZ (0x7 << 12) /* RW */
192 /* MSDC_DMA_CFG mask */
193 #define MSDC_DMA_CFG_STS (0x1 << 0) /* R */
194 #define MSDC_DMA_CFG_DECSEN (0x1 << 1) /* RW */
195 #define MSDC_DMA_CFG_AHBHPROT2 (0x2 << 8) /* RW */
196 #define MSDC_DMA_CFG_ACTIVEEN (0x2 << 12) /* RW */
197 #define MSDC_DMA_CFG_CS12B16B (0x1 << 16) /* RW */
199 /* MSDC_PATCH_BIT mask */
200 #define MSDC_PATCH_BIT_ODDSUPP (0x1 << 1) /* RW */
201 #define MSDC_INT_DAT_LATCH_CK_SEL (0x7 << 7)
202 #define MSDC_CKGEN_MSDC_DLY_SEL (0x1f << 10)
203 #define MSDC_PATCH_BIT_IODSSEL (0x1 << 16) /* RW */
204 #define MSDC_PATCH_BIT_IOINTSEL (0x1 << 17) /* RW */
205 #define MSDC_PATCH_BIT_BUSYDLY (0xf << 18) /* RW */
206 #define MSDC_PATCH_BIT_WDOD (0xf << 22) /* RW */
207 #define MSDC_PATCH_BIT_IDRTSEL (0x1 << 26) /* RW */
208 #define MSDC_PATCH_BIT_CMDFSEL (0x1 << 27) /* RW */
209 #define MSDC_PATCH_BIT_INTDLSEL (0x1 << 28) /* RW */
210 #define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */
211 #define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */
213 #define MSDC_PAD_TUNE_DATRRDLY (0x1f << 8) /* RW */
214 #define MSDC_PAD_TUNE_CMDRDLY (0x1f << 16) /* RW */
216 #define PAD_DS_TUNE_DLY1 (0x1f << 2) /* RW */
217 #define PAD_DS_TUNE_DLY2 (0x1f << 7) /* RW */
218 #define PAD_DS_TUNE_DLY3 (0x1f << 12) /* RW */
220 #define EMMC50_CFG_PADCMD_LATCHCK (0x1 << 0) /* RW */
221 #define EMMC50_CFG_CRCSTS_EDGE (0x1 << 3) /* RW */
222 #define EMMC50_CFG_CFCSTS_SEL (0x1 << 4) /* RW */
224 #define REQ_CMD_EIO (0x1 << 0)
225 #define REQ_CMD_TMO (0x1 << 1)
226 #define REQ_DAT_ERR (0x1 << 2)
227 #define REQ_STOP_EIO (0x1 << 3)
228 #define REQ_STOP_TMO (0x1 << 4)
229 #define REQ_CMD_BUSY (0x1 << 5)
231 #define MSDC_PREPARE_FLAG (0x1 << 0)
232 #define MSDC_ASYNC_FLAG (0x1 << 1)
233 #define MSDC_MMAP_FLAG (0x1 << 2)
235 #define MTK_MMC_AUTOSUSPEND_DELAY 50
236 #define CMD_TIMEOUT (HZ/10 * 5) /* 100ms x5 */
237 #define DAT_TIMEOUT (HZ * 5) /* 1000ms x5 */
239 #define PAD_DELAY_MAX 32 /* PAD delay cells */
240 /*--------------------------------------------------------------------------*/
241 /* Descriptor Structure */
242 /*--------------------------------------------------------------------------*/
243 struct mt_gpdma_desc {
245 #define GPDMA_DESC_HWO (0x1 << 0)
246 #define GPDMA_DESC_BDP (0x1 << 1)
247 #define GPDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */
248 #define GPDMA_DESC_INT (0x1 << 16)
252 #define GPDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */
253 #define GPDMA_DESC_EXTLEN (0xff << 16) /* bit16 ~ bit23 */
259 struct mt_bdma_desc {
261 #define BDMA_DESC_EOL (0x1 << 0)
262 #define BDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */
263 #define BDMA_DESC_BLKPAD (0x1 << 17)
264 #define BDMA_DESC_DWPAD (0x1 << 18)
268 #define BDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */
272 struct scatterlist *sg; /* I/O scatter list */
273 struct mt_gpdma_desc *gpd; /* pointer to gpd array */
274 struct mt_bdma_desc *bd; /* pointer to bd array */
275 dma_addr_t gpd_addr; /* the physical address of gpd array */
276 dma_addr_t bd_addr; /* the physical address of bd array */
279 struct msdc_save_para {
290 struct msdc_tune_para {
295 struct msdc_delay_phase {
303 struct mmc_host *mmc; /* mmc structure */
307 struct mmc_request *mrq;
308 struct mmc_command *cmd;
309 struct mmc_data *data;
312 void __iomem *base; /* host base address */
314 struct msdc_dma dma; /* dma channel */
317 u32 timeout_ns; /* data timeout ns */
318 u32 timeout_clks; /* data timeout clks */
320 struct pinctrl *pinctrl;
321 struct pinctrl_state *pins_default;
322 struct pinctrl_state *pins_uhs;
323 struct delayed_work req_timeout;
324 int irq; /* host interrupt */
326 struct clk *src_clk; /* msdc source clock */
327 struct clk *h_clk; /* msdc h_clk */
328 u32 mclk; /* mmc subsystem clock frequency */
329 u32 src_clk_freq; /* source clock frequency */
330 u32 sclk; /* SD/MS bus clock frequency */
331 unsigned char timing;
334 bool hs400_mode; /* current eMMC will run at hs400 mode */
335 struct msdc_save_para save_para; /* used when gate HCLK */
336 struct msdc_tune_para def_tune_para; /* default tune setting */
337 struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */
340 static void sdr_set_bits(void __iomem *reg, u32 bs)
342 u32 val = readl(reg);
348 static void sdr_clr_bits(void __iomem *reg, u32 bs)
350 u32 val = readl(reg);
356 static void sdr_set_field(void __iomem *reg, u32 field, u32 val)
358 unsigned int tv = readl(reg);
361 tv |= ((val) << (ffs((unsigned int)field) - 1));
365 static void sdr_get_field(void __iomem *reg, u32 field, u32 *val)
367 unsigned int tv = readl(reg);
369 *val = ((tv & field) >> (ffs((unsigned int)field) - 1));
372 static void msdc_reset_hw(struct msdc_host *host)
376 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST);
377 while (readl(host->base + MSDC_CFG) & MSDC_CFG_RST)
380 sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR);
381 while (readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_CLR)
384 val = readl(host->base + MSDC_INT);
385 writel(val, host->base + MSDC_INT);
388 static void msdc_cmd_next(struct msdc_host *host,
389 struct mmc_request *mrq, struct mmc_command *cmd);
391 static const u32 cmd_ints_mask = MSDC_INTEN_CMDRDY | MSDC_INTEN_RSPCRCERR |
392 MSDC_INTEN_CMDTMO | MSDC_INTEN_ACMDRDY |
393 MSDC_INTEN_ACMDCRCERR | MSDC_INTEN_ACMDTMO;
394 static const u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO |
395 MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR |
396 MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT;
398 static u8 msdc_dma_calcs(u8 *buf, u32 len)
402 for (i = 0; i < len; i++)
404 return 0xff - (u8) sum;
407 static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma,
408 struct mmc_data *data)
410 unsigned int j, dma_len;
411 dma_addr_t dma_address;
413 struct scatterlist *sg;
414 struct mt_gpdma_desc *gpd;
415 struct mt_bdma_desc *bd;
423 gpd->gpd_info |= GPDMA_DESC_HWO;
424 gpd->gpd_info |= GPDMA_DESC_BDP;
425 /* need to clear first. use these bits to calc checksum */
426 gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM;
427 gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8;
430 for_each_sg(data->sg, sg, data->sg_count, j) {
431 dma_address = sg_dma_address(sg);
432 dma_len = sg_dma_len(sg);
435 bd[j].bd_info &= ~BDMA_DESC_BLKPAD;
436 bd[j].bd_info &= ~BDMA_DESC_DWPAD;
437 bd[j].ptr = (u32)dma_address;
438 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN;
439 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN);
441 if (j == data->sg_count - 1) /* the last bd */
442 bd[j].bd_info |= BDMA_DESC_EOL;
444 bd[j].bd_info &= ~BDMA_DESC_EOL;
446 /* checksume need to clear first */
447 bd[j].bd_info &= ~BDMA_DESC_CHECKSUM;
448 bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8;
451 sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1);
452 dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL);
453 dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE);
454 dma_ctrl |= (MSDC_BURST_64B << 12 | 1 << 8);
455 writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL);
456 writel((u32)dma->gpd_addr, host->base + MSDC_DMA_SA);
459 static void msdc_prepare_data(struct msdc_host *host, struct mmc_request *mrq)
461 struct mmc_data *data = mrq->data;
463 if (!(data->host_cookie & MSDC_PREPARE_FLAG)) {
464 bool read = (data->flags & MMC_DATA_READ) != 0;
466 data->host_cookie |= MSDC_PREPARE_FLAG;
467 data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len,
468 read ? DMA_FROM_DEVICE : DMA_TO_DEVICE);
472 static void msdc_unprepare_data(struct msdc_host *host, struct mmc_request *mrq)
474 struct mmc_data *data = mrq->data;
476 if (data->host_cookie & MSDC_ASYNC_FLAG)
479 if (data->host_cookie & MSDC_PREPARE_FLAG) {
480 bool read = (data->flags & MMC_DATA_READ) != 0;
482 dma_unmap_sg(host->dev, data->sg, data->sg_len,
483 read ? DMA_FROM_DEVICE : DMA_TO_DEVICE);
484 data->host_cookie &= ~MSDC_PREPARE_FLAG;
488 /* clock control primitives */
489 static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks)
494 host->timeout_ns = ns;
495 host->timeout_clks = clks;
496 if (host->sclk == 0) {
499 clk_ns = 1000000000UL / host->sclk;
500 timeout = (ns + clk_ns - 1) / clk_ns + clks;
501 /* in 1048576 sclk cycle unit */
502 timeout = (timeout + (0x1 << 20) - 1) >> 20;
503 sdr_get_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD, &mode);
504 /*DDR mode will double the clk cycles for data timeout */
505 timeout = mode >= 2 ? timeout * 2 : timeout;
506 timeout = timeout > 1 ? timeout - 1 : 0;
507 timeout = timeout > 255 ? 255 : timeout;
509 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, timeout);
512 static void msdc_gate_clock(struct msdc_host *host)
514 clk_disable_unprepare(host->src_clk);
515 clk_disable_unprepare(host->h_clk);
518 static void msdc_ungate_clock(struct msdc_host *host)
520 clk_prepare_enable(host->h_clk);
521 clk_prepare_enable(host->src_clk);
522 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))
526 static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
534 dev_dbg(host->dev, "set mclk to 0\n");
536 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
540 flags = readl(host->base + MSDC_INTEN);
541 sdr_clr_bits(host->base + MSDC_INTEN, flags);
542 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE);
543 if (timing == MMC_TIMING_UHS_DDR50 ||
544 timing == MMC_TIMING_MMC_DDR52 ||
545 timing == MMC_TIMING_MMC_HS400) {
546 if (timing == MMC_TIMING_MMC_HS400)
549 mode = 0x2; /* ddr mode and use divisor */
551 if (hz >= (host->src_clk_freq >> 2)) {
552 div = 0; /* mean div = 1/4 */
553 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */
555 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2);
556 sclk = (host->src_clk_freq >> 2) / div;
560 if (timing == MMC_TIMING_MMC_HS400 &&
561 hz >= (host->src_clk_freq >> 1)) {
562 sdr_set_bits(host->base + MSDC_CFG,
563 MSDC_CFG_HS400_CK_MODE);
564 sclk = host->src_clk_freq >> 1;
565 div = 0; /* div is ignore when bit18 is set */
567 } else if (hz >= host->src_clk_freq) {
568 mode = 0x1; /* no divisor */
570 sclk = host->src_clk_freq;
572 mode = 0x0; /* use divisor */
573 if (hz >= (host->src_clk_freq >> 1)) {
574 div = 0; /* mean div = 1/2 */
575 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */
577 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2);
578 sclk = (host->src_clk_freq >> 2) / div;
581 sdr_set_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD | MSDC_CFG_CKDIV,
583 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
584 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))
588 host->timing = timing;
589 /* need because clk changed. */
590 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks);
591 sdr_set_bits(host->base + MSDC_INTEN, flags);
594 * mmc_select_hs400() will drop to 50Mhz and High speed mode,
595 * tune result of hs200/200Mhz is not suitable for 50Mhz
597 if (host->sclk <= 52000000) {
598 writel(host->def_tune_para.iocon, host->base + MSDC_IOCON);
599 writel(host->def_tune_para.pad_tune, host->base + MSDC_PAD_TUNE);
601 writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON);
602 writel(host->saved_tune_para.pad_tune, host->base + MSDC_PAD_TUNE);
605 dev_dbg(host->dev, "sclk: %d, timing: %d\n", host->sclk, timing);
608 static inline u32 msdc_cmd_find_resp(struct msdc_host *host,
609 struct mmc_request *mrq, struct mmc_command *cmd)
613 switch (mmc_resp_type(cmd)) {
614 /* Actually, R1, R5, R6, R7 are the same */
636 static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host,
637 struct mmc_request *mrq, struct mmc_command *cmd)
640 * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 |
641 * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode
643 u32 opcode = cmd->opcode;
644 u32 resp = msdc_cmd_find_resp(host, mrq, cmd);
645 u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7);
647 host->cmd_rsp = resp;
649 if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) ||
650 opcode == MMC_STOP_TRANSMISSION)
651 rawcmd |= (0x1 << 14);
652 else if (opcode == SD_SWITCH_VOLTAGE)
653 rawcmd |= (0x1 << 30);
654 else if (opcode == SD_APP_SEND_SCR ||
655 opcode == SD_APP_SEND_NUM_WR_BLKS ||
656 (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) ||
657 (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) ||
658 (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC))
659 rawcmd |= (0x1 << 11);
662 struct mmc_data *data = cmd->data;
664 if (mmc_op_multi(opcode)) {
665 if (mmc_card_mmc(host->mmc->card) && mrq->sbc &&
666 !(mrq->sbc->arg & 0xFFFF0000))
667 rawcmd |= 0x2 << 28; /* AutoCMD23 */
670 rawcmd |= ((data->blksz & 0xFFF) << 16);
671 if (data->flags & MMC_DATA_WRITE)
672 rawcmd |= (0x1 << 13);
673 if (data->blocks > 1)
674 rawcmd |= (0x2 << 11);
676 rawcmd |= (0x1 << 11);
677 /* Always use dma mode */
678 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO);
680 if (host->timeout_ns != data->timeout_ns ||
681 host->timeout_clks != data->timeout_clks)
682 msdc_set_timeout(host, data->timeout_ns,
685 writel(data->blocks, host->base + SDC_BLK_NUM);
690 static void msdc_start_data(struct msdc_host *host, struct mmc_request *mrq,
691 struct mmc_command *cmd, struct mmc_data *data)
697 read = data->flags & MMC_DATA_READ;
699 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT);
700 msdc_dma_setup(host, &host->dma, data);
701 sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask);
702 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1);
703 dev_dbg(host->dev, "DMA start\n");
704 dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n",
705 __func__, cmd->opcode, data->blocks, read);
708 static int msdc_auto_cmd_done(struct msdc_host *host, int events,
709 struct mmc_command *cmd)
711 u32 *rsp = cmd->resp;
713 rsp[0] = readl(host->base + SDC_ACMD_RESP);
715 if (events & MSDC_INT_ACMDRDY) {
719 if (events & MSDC_INT_ACMDCRCERR) {
720 cmd->error = -EILSEQ;
721 host->error |= REQ_STOP_EIO;
722 } else if (events & MSDC_INT_ACMDTMO) {
723 cmd->error = -ETIMEDOUT;
724 host->error |= REQ_STOP_TMO;
727 "%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n",
728 __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error);
733 static void msdc_track_cmd_data(struct msdc_host *host,
734 struct mmc_command *cmd, struct mmc_data *data)
737 dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n",
738 __func__, cmd->opcode, cmd->arg, host->error);
741 static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq)
746 * No need check the return value of cancel_delayed_work, as only ONE
749 cancel_delayed_work(&host->req_timeout);
751 spin_lock_irqsave(&host->lock, flags);
753 spin_unlock_irqrestore(&host->lock, flags);
755 msdc_track_cmd_data(host, mrq->cmd, mrq->data);
757 msdc_unprepare_data(host, mrq);
758 mmc_request_done(host->mmc, mrq);
761 /* returns true if command is fully handled; returns false otherwise */
762 static bool msdc_cmd_done(struct msdc_host *host, int events,
763 struct mmc_request *mrq, struct mmc_command *cmd)
770 if (mrq->sbc && cmd == mrq->cmd &&
771 (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR
772 | MSDC_INT_ACMDTMO)))
773 msdc_auto_cmd_done(host, events, mrq->sbc);
775 sbc_error = mrq->sbc && mrq->sbc->error;
777 if (!sbc_error && !(events & (MSDC_INT_CMDRDY
782 spin_lock_irqsave(&host->lock, flags);
785 spin_unlock_irqrestore(&host->lock, flags);
791 sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask);
793 if (cmd->flags & MMC_RSP_PRESENT) {
794 if (cmd->flags & MMC_RSP_136) {
795 rsp[0] = readl(host->base + SDC_RESP3);
796 rsp[1] = readl(host->base + SDC_RESP2);
797 rsp[2] = readl(host->base + SDC_RESP1);
798 rsp[3] = readl(host->base + SDC_RESP0);
800 rsp[0] = readl(host->base + SDC_RESP0);
804 if (!sbc_error && !(events & MSDC_INT_CMDRDY)) {
805 if (cmd->opcode != MMC_SEND_TUNING_BLOCK &&
806 cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200)
808 * should not clear fifo/interrupt as the tune data
809 * may have alreay come.
812 if (events & MSDC_INT_RSPCRCERR) {
813 cmd->error = -EILSEQ;
814 host->error |= REQ_CMD_EIO;
815 } else if (events & MSDC_INT_CMDTMO) {
816 cmd->error = -ETIMEDOUT;
817 host->error |= REQ_CMD_TMO;
822 "%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n",
823 __func__, cmd->opcode, cmd->arg, rsp[0],
826 msdc_cmd_next(host, mrq, cmd);
830 /* It is the core layer's responsibility to ensure card status
831 * is correct before issue a request. but host design do below
832 * checks recommended.
834 static inline bool msdc_cmd_is_ready(struct msdc_host *host,
835 struct mmc_request *mrq, struct mmc_command *cmd)
837 /* The max busy time we can endure is 20ms */
838 unsigned long tmo = jiffies + msecs_to_jiffies(20);
840 while ((readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) &&
841 time_before(jiffies, tmo))
843 if (readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) {
844 dev_err(host->dev, "CMD bus busy detected\n");
845 host->error |= REQ_CMD_BUSY;
846 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
850 if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) {
851 tmo = jiffies + msecs_to_jiffies(20);
852 /* R1B or with data, should check SDCBUSY */
853 while ((readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) &&
854 time_before(jiffies, tmo))
856 if (readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) {
857 dev_err(host->dev, "Controller busy detected\n");
858 host->error |= REQ_CMD_BUSY;
859 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
866 static void msdc_start_command(struct msdc_host *host,
867 struct mmc_request *mrq, struct mmc_command *cmd)
874 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT);
875 if (!msdc_cmd_is_ready(host, mrq, cmd))
878 if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 ||
879 readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) {
880 dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n");
885 rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd);
887 sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask);
888 writel(cmd->arg, host->base + SDC_ARG);
889 writel(rawcmd, host->base + SDC_CMD);
892 static void msdc_cmd_next(struct msdc_host *host,
893 struct mmc_request *mrq, struct mmc_command *cmd)
896 !(cmd->error == -EILSEQ &&
897 (cmd->opcode == MMC_SEND_TUNING_BLOCK ||
898 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))) ||
899 (mrq->sbc && mrq->sbc->error))
900 msdc_request_done(host, mrq);
901 else if (cmd == mrq->sbc)
902 msdc_start_command(host, mrq, mrq->cmd);
904 msdc_request_done(host, mrq);
906 msdc_start_data(host, mrq, cmd, cmd->data);
909 static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq)
911 struct msdc_host *host = mmc_priv(mmc);
918 msdc_prepare_data(host, mrq);
920 /* if SBC is required, we have HW option and SW option.
921 * if HW option is enabled, and SBC does not have "special" flags,
922 * use HW option, otherwise use SW option
924 if (mrq->sbc && (!mmc_card_mmc(mmc->card) ||
925 (mrq->sbc->arg & 0xFFFF0000)))
926 msdc_start_command(host, mrq, mrq->sbc);
928 msdc_start_command(host, mrq, mrq->cmd);
931 static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
934 struct msdc_host *host = mmc_priv(mmc);
935 struct mmc_data *data = mrq->data;
940 msdc_prepare_data(host, mrq);
941 data->host_cookie |= MSDC_ASYNC_FLAG;
944 static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
947 struct msdc_host *host = mmc_priv(mmc);
948 struct mmc_data *data;
953 if (data->host_cookie) {
954 data->host_cookie &= ~MSDC_ASYNC_FLAG;
955 msdc_unprepare_data(host, mrq);
959 static void msdc_data_xfer_next(struct msdc_host *host,
960 struct mmc_request *mrq, struct mmc_data *data)
962 if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error &&
964 msdc_start_command(host, mrq, mrq->stop);
966 msdc_request_done(host, mrq);
969 static bool msdc_data_xfer_done(struct msdc_host *host, u32 events,
970 struct mmc_request *mrq, struct mmc_data *data)
972 struct mmc_command *stop;
975 unsigned int check_data = events &
976 (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO
977 | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR
978 | MSDC_INT_DMA_PROTECT);
980 spin_lock_irqsave(&host->lock, flags);
984 spin_unlock_irqrestore(&host->lock, flags);
990 if (check_data || (stop && stop->error)) {
991 dev_dbg(host->dev, "DMA status: 0x%8X\n",
992 readl(host->base + MSDC_DMA_CFG));
993 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP,
995 while (readl(host->base + MSDC_DMA_CFG) & MSDC_DMA_CFG_STS)
997 sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask);
998 dev_dbg(host->dev, "DMA stop\n");
1000 if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) {
1001 data->bytes_xfered = data->blocks * data->blksz;
1003 dev_dbg(host->dev, "interrupt events: %x\n", events);
1004 msdc_reset_hw(host);
1005 host->error |= REQ_DAT_ERR;
1006 data->bytes_xfered = 0;
1008 if (events & MSDC_INT_DATTMO)
1009 data->error = -ETIMEDOUT;
1010 else if (events & MSDC_INT_DATCRCERR)
1011 data->error = -EILSEQ;
1013 dev_dbg(host->dev, "%s: cmd=%d; blocks=%d",
1014 __func__, mrq->cmd->opcode, data->blocks);
1015 dev_dbg(host->dev, "data_error=%d xfer_size=%d\n",
1016 (int)data->error, data->bytes_xfered);
1019 msdc_data_xfer_next(host, mrq, data);
1025 static void msdc_set_buswidth(struct msdc_host *host, u32 width)
1027 u32 val = readl(host->base + SDC_CFG);
1029 val &= ~SDC_CFG_BUSWIDTH;
1033 case MMC_BUS_WIDTH_1:
1034 val |= (MSDC_BUS_1BITS << 16);
1036 case MMC_BUS_WIDTH_4:
1037 val |= (MSDC_BUS_4BITS << 16);
1039 case MMC_BUS_WIDTH_8:
1040 val |= (MSDC_BUS_8BITS << 16);
1044 writel(val, host->base + SDC_CFG);
1045 dev_dbg(host->dev, "Bus Width = %d", width);
1048 static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios)
1050 struct msdc_host *host = mmc_priv(mmc);
1053 if (!IS_ERR(mmc->supply.vqmmc)) {
1054 if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 &&
1055 ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) {
1056 dev_err(host->dev, "Unsupported signal voltage!\n");
1060 ret = mmc_regulator_set_vqmmc(mmc, ios);
1062 dev_dbg(host->dev, "Regulator set error %d (%d)\n",
1063 ret, ios->signal_voltage);
1065 /* Apply different pinctrl settings for different signal voltage */
1066 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
1067 pinctrl_select_state(host->pinctrl, host->pins_uhs);
1069 pinctrl_select_state(host->pinctrl, host->pins_default);
1075 static int msdc_card_busy(struct mmc_host *mmc)
1077 struct msdc_host *host = mmc_priv(mmc);
1078 u32 status = readl(host->base + MSDC_PS);
1080 /* check if any pin between dat[0:3] is low */
1081 if (((status >> 16) & 0xf) != 0xf)
1087 static void msdc_request_timeout(struct work_struct *work)
1089 struct msdc_host *host = container_of(work, struct msdc_host,
1092 /* simulate HW timeout status */
1093 dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__);
1095 dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__,
1096 host->mrq, host->mrq->cmd->opcode);
1098 dev_err(host->dev, "%s: aborting cmd=%d\n",
1099 __func__, host->cmd->opcode);
1100 msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq,
1102 } else if (host->data) {
1103 dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n",
1104 __func__, host->mrq->cmd->opcode,
1105 host->data->blocks);
1106 msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq,
1112 static irqreturn_t msdc_irq(int irq, void *dev_id)
1114 struct msdc_host *host = (struct msdc_host *) dev_id;
1117 unsigned long flags;
1118 struct mmc_request *mrq;
1119 struct mmc_command *cmd;
1120 struct mmc_data *data;
1121 u32 events, event_mask;
1123 spin_lock_irqsave(&host->lock, flags);
1124 events = readl(host->base + MSDC_INT);
1125 event_mask = readl(host->base + MSDC_INTEN);
1126 /* clear interrupts */
1127 writel(events & event_mask, host->base + MSDC_INT);
1132 spin_unlock_irqrestore(&host->lock, flags);
1134 if (!(events & event_mask))
1139 "%s: MRQ=NULL; events=%08X; event_mask=%08X\n",
1140 __func__, events, event_mask);
1145 dev_dbg(host->dev, "%s: events=%08X\n", __func__, events);
1148 msdc_cmd_done(host, events, mrq, cmd);
1150 msdc_data_xfer_done(host, events, mrq, data);
1156 static void msdc_init_hw(struct msdc_host *host)
1160 /* Configure to MMC/SD mode, clock free running */
1161 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN);
1164 msdc_reset_hw(host);
1166 /* Disable card detection */
1167 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1169 /* Disable and clear all interrupts */
1170 writel(0, host->base + MSDC_INTEN);
1171 val = readl(host->base + MSDC_INT);
1172 writel(val, host->base + MSDC_INT);
1174 writel(0, host->base + MSDC_PAD_TUNE);
1175 writel(0, host->base + MSDC_IOCON);
1176 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0);
1177 writel(0x403c0046, host->base + MSDC_PATCH_BIT);
1178 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1);
1179 writel(0xffff0089, host->base + MSDC_PATCH_BIT1);
1180 sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL);
1182 /* Configure to enable SDIO mode.
1183 * it's must otherwise sdio cmd5 failed
1185 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO);
1187 /* disable detect SDIO device interrupt function */
1188 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1190 /* Configure to default data timeout */
1191 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3);
1193 host->def_tune_para.iocon = readl(host->base + MSDC_IOCON);
1194 host->def_tune_para.pad_tune = readl(host->base + MSDC_PAD_TUNE);
1195 dev_dbg(host->dev, "init hardware done!");
1198 static void msdc_deinit_hw(struct msdc_host *host)
1201 /* Disable and clear all interrupts */
1202 writel(0, host->base + MSDC_INTEN);
1204 val = readl(host->base + MSDC_INT);
1205 writel(val, host->base + MSDC_INT);
1208 /* init gpd and bd list in msdc_drv_probe */
1209 static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma)
1211 struct mt_gpdma_desc *gpd = dma->gpd;
1212 struct mt_bdma_desc *bd = dma->bd;
1215 memset(gpd, 0, sizeof(struct mt_gpdma_desc) * 2);
1217 gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */
1218 gpd->ptr = (u32)dma->bd_addr; /* physical address */
1219 /* gpd->next is must set for desc DMA
1220 * That's why must alloc 2 gpd structure.
1222 gpd->next = (u32)dma->gpd_addr + sizeof(struct mt_gpdma_desc);
1223 memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM);
1224 for (i = 0; i < (MAX_BD_NUM - 1); i++)
1225 bd[i].next = (u32)dma->bd_addr + sizeof(*bd) * (i + 1);
1228 static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1230 struct msdc_host *host = mmc_priv(mmc);
1233 msdc_set_buswidth(host, ios->bus_width);
1235 /* Suspend/Resume will do power off/on */
1236 switch (ios->power_mode) {
1238 if (!IS_ERR(mmc->supply.vmmc)) {
1240 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1243 dev_err(host->dev, "Failed to set vmmc power!\n");
1249 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
1250 ret = regulator_enable(mmc->supply.vqmmc);
1252 dev_err(host->dev, "Failed to set vqmmc power!\n");
1254 host->vqmmc_enabled = true;
1258 if (!IS_ERR(mmc->supply.vmmc))
1259 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1261 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
1262 regulator_disable(mmc->supply.vqmmc);
1263 host->vqmmc_enabled = false;
1270 if (host->mclk != ios->clock || host->timing != ios->timing)
1271 msdc_set_mclk(host, ios->timing, ios->clock);
1274 static u32 test_delay_bit(u32 delay, u32 bit)
1276 bit %= PAD_DELAY_MAX;
1277 return delay & (1 << bit);
1280 static int get_delay_len(u32 delay, u32 start_bit)
1284 for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) {
1285 if (test_delay_bit(delay, start_bit + i) == 0)
1288 return PAD_DELAY_MAX - start_bit;
1291 static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay)
1293 int start = 0, len = 0;
1294 int start_final = 0, len_final = 0;
1295 u8 final_phase = 0xff;
1296 struct msdc_delay_phase delay_phase = { 0, };
1299 dev_err(host->dev, "phase error: [map:%x]\n", delay);
1300 delay_phase.final_phase = final_phase;
1304 while (start < PAD_DELAY_MAX) {
1305 len = get_delay_len(delay, start);
1306 if (len_final < len) {
1307 start_final = start;
1310 start += len ? len : 1;
1311 if (len >= 8 && start_final < 4)
1315 /* The rule is that to find the smallest delay cell */
1316 if (start_final == 0)
1317 final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX;
1319 final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX;
1320 dev_info(host->dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n",
1321 delay, len_final, final_phase);
1323 delay_phase.maxlen = len_final;
1324 delay_phase.start = start_final;
1325 delay_phase.final_phase = final_phase;
1329 static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)
1331 struct msdc_host *host = mmc_priv(mmc);
1332 u32 rise_delay = 0, fall_delay = 0;
1333 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
1334 u8 final_delay, final_maxlen;
1338 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1339 for (i = 0 ; i < PAD_DELAY_MAX; i++) {
1340 sdr_set_field(host->base + MSDC_PAD_TUNE,
1341 MSDC_PAD_TUNE_CMDRDLY, i);
1342 mmc_send_tuning(mmc, opcode, &cmd_err);
1344 rise_delay |= (1 << i);
1346 final_rise_delay = get_best_delay(host, rise_delay);
1347 /* if rising edge has enough margin, then do not scan falling edge */
1348 if (final_rise_delay.maxlen >= 10 ||
1349 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
1352 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1353 for (i = 0; i < PAD_DELAY_MAX; i++) {
1354 sdr_set_field(host->base + MSDC_PAD_TUNE,
1355 MSDC_PAD_TUNE_CMDRDLY, i);
1356 mmc_send_tuning(mmc, opcode, &cmd_err);
1358 fall_delay |= (1 << i);
1360 final_fall_delay = get_best_delay(host, fall_delay);
1363 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
1364 if (final_maxlen == final_rise_delay.maxlen) {
1365 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1366 sdr_set_field(host->base + MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRDLY,
1367 final_rise_delay.final_phase);
1368 final_delay = final_rise_delay.final_phase;
1370 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1371 sdr_set_field(host->base + MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRDLY,
1372 final_fall_delay.final_phase);
1373 final_delay = final_fall_delay.final_phase;
1376 return final_delay == 0xff ? -EIO : 0;
1379 static int msdc_tune_data(struct mmc_host *mmc, u32 opcode)
1381 struct msdc_host *host = mmc_priv(mmc);
1382 u32 rise_delay = 0, fall_delay = 0;
1383 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
1384 u8 final_delay, final_maxlen;
1387 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
1388 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
1389 for (i = 0 ; i < PAD_DELAY_MAX; i++) {
1390 sdr_set_field(host->base + MSDC_PAD_TUNE,
1391 MSDC_PAD_TUNE_DATRRDLY, i);
1392 ret = mmc_send_tuning(mmc, opcode, NULL);
1394 rise_delay |= (1 << i);
1396 final_rise_delay = get_best_delay(host, rise_delay);
1397 /* if rising edge has enough margin, then do not scan falling edge */
1398 if (final_rise_delay.maxlen >= 10 ||
1399 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
1402 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
1403 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
1404 for (i = 0; i < PAD_DELAY_MAX; i++) {
1405 sdr_set_field(host->base + MSDC_PAD_TUNE,
1406 MSDC_PAD_TUNE_DATRRDLY, i);
1407 ret = mmc_send_tuning(mmc, opcode, NULL);
1409 fall_delay |= (1 << i);
1411 final_fall_delay = get_best_delay(host, fall_delay);
1414 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
1415 if (final_maxlen == final_rise_delay.maxlen) {
1416 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
1417 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
1418 sdr_set_field(host->base + MSDC_PAD_TUNE,
1419 MSDC_PAD_TUNE_DATRRDLY,
1420 final_rise_delay.final_phase);
1421 final_delay = final_rise_delay.final_phase;
1423 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
1424 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
1425 sdr_set_field(host->base + MSDC_PAD_TUNE,
1426 MSDC_PAD_TUNE_DATRRDLY,
1427 final_fall_delay.final_phase);
1428 final_delay = final_fall_delay.final_phase;
1431 return final_delay == 0xff ? -EIO : 0;
1434 static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode)
1436 struct msdc_host *host = mmc_priv(mmc);
1439 ret = msdc_tune_response(mmc, opcode);
1441 dev_err(host->dev, "Tune response fail!\n");
1444 if (host->hs400_mode == false) {
1445 ret = msdc_tune_data(mmc, opcode);
1447 dev_err(host->dev, "Tune data fail!\n");
1450 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
1451 host->saved_tune_para.pad_tune = readl(host->base + MSDC_PAD_TUNE);
1455 static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
1457 struct msdc_host *host = mmc_priv(mmc);
1458 host->hs400_mode = true;
1460 writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE);
1464 static void msdc_hw_reset(struct mmc_host *mmc)
1466 struct msdc_host *host = mmc_priv(mmc);
1468 sdr_set_bits(host->base + EMMC_IOCON, 1);
1469 udelay(10); /* 10us is enough */
1470 sdr_clr_bits(host->base + EMMC_IOCON, 1);
1473 static struct mmc_host_ops mt_msdc_ops = {
1474 .post_req = msdc_post_req,
1475 .pre_req = msdc_pre_req,
1476 .request = msdc_ops_request,
1477 .set_ios = msdc_ops_set_ios,
1478 .get_ro = mmc_gpio_get_ro,
1479 .start_signal_voltage_switch = msdc_ops_switch_volt,
1480 .card_busy = msdc_card_busy,
1481 .execute_tuning = msdc_execute_tuning,
1482 .prepare_hs400_tuning = msdc_prepare_hs400_tuning,
1483 .hw_reset = msdc_hw_reset,
1486 static int msdc_drv_probe(struct platform_device *pdev)
1488 struct mmc_host *mmc;
1489 struct msdc_host *host;
1490 struct resource *res;
1493 if (!pdev->dev.of_node) {
1494 dev_err(&pdev->dev, "No DT found\n");
1497 /* Allocate MMC host for this device */
1498 mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev);
1502 host = mmc_priv(mmc);
1503 ret = mmc_of_parse(mmc);
1507 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1508 host->base = devm_ioremap_resource(&pdev->dev, res);
1509 if (IS_ERR(host->base)) {
1510 ret = PTR_ERR(host->base);
1514 ret = mmc_regulator_get_supply(mmc);
1515 if (ret == -EPROBE_DEFER)
1518 host->src_clk = devm_clk_get(&pdev->dev, "source");
1519 if (IS_ERR(host->src_clk)) {
1520 ret = PTR_ERR(host->src_clk);
1524 host->h_clk = devm_clk_get(&pdev->dev, "hclk");
1525 if (IS_ERR(host->h_clk)) {
1526 ret = PTR_ERR(host->h_clk);
1530 host->irq = platform_get_irq(pdev, 0);
1531 if (host->irq < 0) {
1536 host->pinctrl = devm_pinctrl_get(&pdev->dev);
1537 if (IS_ERR(host->pinctrl)) {
1538 ret = PTR_ERR(host->pinctrl);
1539 dev_err(&pdev->dev, "Cannot find pinctrl!\n");
1543 host->pins_default = pinctrl_lookup_state(host->pinctrl, "default");
1544 if (IS_ERR(host->pins_default)) {
1545 ret = PTR_ERR(host->pins_default);
1546 dev_err(&pdev->dev, "Cannot find pinctrl default!\n");
1550 host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs");
1551 if (IS_ERR(host->pins_uhs)) {
1552 ret = PTR_ERR(host->pins_uhs);
1553 dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n");
1557 if (!of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay",
1558 &host->hs400_ds_delay))
1559 dev_dbg(&pdev->dev, "hs400-ds-delay: %x\n",
1560 host->hs400_ds_delay);
1562 host->dev = &pdev->dev;
1564 host->src_clk_freq = clk_get_rate(host->src_clk);
1565 /* Set host parameters to mmc */
1566 mmc->ops = &mt_msdc_ops;
1567 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255);
1569 mmc->caps |= MMC_CAP_ERASE | MMC_CAP_CMD23;
1570 /* MMC core transfer sizes tunable parameters */
1571 mmc->max_segs = MAX_BD_NUM;
1572 mmc->max_seg_size = BDMA_DESC_BUFLEN;
1573 mmc->max_blk_size = 2048;
1574 mmc->max_req_size = 512 * 1024;
1575 mmc->max_blk_count = mmc->max_req_size / 512;
1576 host->dma_mask = DMA_BIT_MASK(32);
1577 mmc_dev(mmc)->dma_mask = &host->dma_mask;
1579 host->timeout_clks = 3 * 1048576;
1580 host->dma.gpd = dma_alloc_coherent(&pdev->dev,
1581 2 * sizeof(struct mt_gpdma_desc),
1582 &host->dma.gpd_addr, GFP_KERNEL);
1583 host->dma.bd = dma_alloc_coherent(&pdev->dev,
1584 MAX_BD_NUM * sizeof(struct mt_bdma_desc),
1585 &host->dma.bd_addr, GFP_KERNEL);
1586 if (!host->dma.gpd || !host->dma.bd) {
1590 msdc_init_gpd_bd(host, &host->dma);
1591 INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout);
1592 spin_lock_init(&host->lock);
1594 platform_set_drvdata(pdev, mmc);
1595 msdc_ungate_clock(host);
1598 ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq,
1599 IRQF_TRIGGER_LOW | IRQF_ONESHOT, pdev->name, host);
1603 pm_runtime_set_active(host->dev);
1604 pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY);
1605 pm_runtime_use_autosuspend(host->dev);
1606 pm_runtime_enable(host->dev);
1607 ret = mmc_add_host(mmc);
1614 pm_runtime_disable(host->dev);
1616 platform_set_drvdata(pdev, NULL);
1617 msdc_deinit_hw(host);
1618 msdc_gate_clock(host);
1621 dma_free_coherent(&pdev->dev,
1622 2 * sizeof(struct mt_gpdma_desc),
1623 host->dma.gpd, host->dma.gpd_addr);
1625 dma_free_coherent(&pdev->dev,
1626 MAX_BD_NUM * sizeof(struct mt_bdma_desc),
1627 host->dma.bd, host->dma.bd_addr);
1634 static int msdc_drv_remove(struct platform_device *pdev)
1636 struct mmc_host *mmc;
1637 struct msdc_host *host;
1639 mmc = platform_get_drvdata(pdev);
1640 host = mmc_priv(mmc);
1642 pm_runtime_get_sync(host->dev);
1644 platform_set_drvdata(pdev, NULL);
1645 mmc_remove_host(host->mmc);
1646 msdc_deinit_hw(host);
1647 msdc_gate_clock(host);
1649 pm_runtime_disable(host->dev);
1650 pm_runtime_put_noidle(host->dev);
1651 dma_free_coherent(&pdev->dev,
1652 sizeof(struct mt_gpdma_desc),
1653 host->dma.gpd, host->dma.gpd_addr);
1654 dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc),
1655 host->dma.bd, host->dma.bd_addr);
1657 mmc_free_host(host->mmc);
1663 static void msdc_save_reg(struct msdc_host *host)
1665 host->save_para.msdc_cfg = readl(host->base + MSDC_CFG);
1666 host->save_para.iocon = readl(host->base + MSDC_IOCON);
1667 host->save_para.sdc_cfg = readl(host->base + SDC_CFG);
1668 host->save_para.pad_tune = readl(host->base + MSDC_PAD_TUNE);
1669 host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT);
1670 host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1);
1671 host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE);
1672 host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0);
1675 static void msdc_restore_reg(struct msdc_host *host)
1677 writel(host->save_para.msdc_cfg, host->base + MSDC_CFG);
1678 writel(host->save_para.iocon, host->base + MSDC_IOCON);
1679 writel(host->save_para.sdc_cfg, host->base + SDC_CFG);
1680 writel(host->save_para.pad_tune, host->base + MSDC_PAD_TUNE);
1681 writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT);
1682 writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1);
1683 writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE);
1684 writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0);
1687 static int msdc_runtime_suspend(struct device *dev)
1689 struct mmc_host *mmc = dev_get_drvdata(dev);
1690 struct msdc_host *host = mmc_priv(mmc);
1692 msdc_save_reg(host);
1693 msdc_gate_clock(host);
1697 static int msdc_runtime_resume(struct device *dev)
1699 struct mmc_host *mmc = dev_get_drvdata(dev);
1700 struct msdc_host *host = mmc_priv(mmc);
1702 msdc_ungate_clock(host);
1703 msdc_restore_reg(host);
1708 static const struct dev_pm_ops msdc_dev_pm_ops = {
1709 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1710 pm_runtime_force_resume)
1711 SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL)
1714 static const struct of_device_id msdc_of_ids[] = {
1715 { .compatible = "mediatek,mt8135-mmc", },
1719 static struct platform_driver mt_msdc_driver = {
1720 .probe = msdc_drv_probe,
1721 .remove = msdc_drv_remove,
1724 .of_match_table = msdc_of_ids,
1725 .pm = &msdc_dev_pm_ops,
1729 module_platform_driver(mt_msdc_driver);
1730 MODULE_LICENSE("GPL v2");
1731 MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver");