drivers/mmc/host/mmci_stm32_sdmmc.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
   4  * Author: Ludovic.barre@st.com for STMicroelectronics.
   5  */
   6 #include <linux/bitfield.h>
   7 #include <linux/delay.h>
   8 #include <linux/dma-mapping.h>
   9 #include <linux/iopoll.h>
  10 #include <linux/mmc/host.h>
  11 #include <linux/mmc/card.h>
  12 #include <linux/of_address.h>
  13 #include <linux/reset.h>
  14 #include <linux/scatterlist.h>
  15 #include "mmci.h"
  16
  17 #define SDMMC_LLI_BUF_LEN       PAGE_SIZE
  18 #define SDMMC_IDMA_BURST        BIT(MMCI_STM32_IDMABNDT_SHIFT)
  19
  20 #define DLYB_CR                 0x0
  21 #define DLYB_CR_DEN             BIT(0)
  22 #define DLYB_CR_SEN             BIT(1)
  23
  24 #define DLYB_CFGR               0x4
  25 #define DLYB_CFGR_SEL_MASK      GENMASK(3, 0)
  26 #define DLYB_CFGR_UNIT_MASK     GENMASK(14, 8)
  27 #define DLYB_CFGR_LNG_MASK      GENMASK(27, 16)
  28 #define DLYB_CFGR_LNGF          BIT(31)
  29
  30 #define DLYB_NB_DELAY           11
  31 #define DLYB_CFGR_SEL_MAX       (DLYB_NB_DELAY + 1)
  32 #define DLYB_CFGR_UNIT_MAX      127
  33
  34 #define DLYB_LNG_TIMEOUT_US     1000
  35 #define SDMMC_VSWEND_TIMEOUT_US 10000
  36
  37 struct sdmmc_lli_desc {
  38         u32 idmalar;
  39         u32 idmabase;
  40         u32 idmasize;
  41 };
  42
  43 struct sdmmc_idma {
  44         dma_addr_t sg_dma;
  45         void *sg_cpu;
  46         dma_addr_t bounce_dma_addr;
  47         void *bounce_buf;
  48         bool use_bounce_buffer;
  49 };
  50
  51 struct sdmmc_dlyb {
  52         void __iomem *base;
  53         u32 unit;
  54         u32 max;
  55 };
  56
  57 static int sdmmc_idma_validate_data(struct mmci_host *host,
  58                                     struct mmc_data *data)
  59 {
  60         struct sdmmc_idma *idma = host->dma_priv;
  61         struct device *dev = mmc_dev(host->mmc);
  62         struct scatterlist *sg;
  63         int i;
  64
  65         /*
  66          * idma has constraints on idmabase & idmasize for each element
  67          * excepted the last element which has no constraint on idmasize
  68          */
  69         idma->use_bounce_buffer = false;
  70         for_each_sg(data->sg, sg, data->sg_len - 1, i) {
  71                 if (!IS_ALIGNED(sg->offset, sizeof(u32)) ||
  72                     !IS_ALIGNED(sg->length, SDMMC_IDMA_BURST)) {
  73                         dev_dbg(mmc_dev(host->mmc),
  74                                 "unaligned scatterlist: ofst:%x length:%d\n",
  75                                 data->sg->offset, data->sg->length);
  76                         goto use_bounce_buffer;
  77                 }
  78         }
  79
  80         if (!IS_ALIGNED(sg->offset, sizeof(u32))) {
  81                 dev_dbg(mmc_dev(host->mmc),
  82                         "unaligned last scatterlist: ofst:%x length:%d\n",
  83                         data->sg->offset, data->sg->length);
  84                 goto use_bounce_buffer;
  85         }
  86
  87         return 0;
  88
  89 use_bounce_buffer:
  90         if (!idma->bounce_buf) {
  91                 idma->bounce_buf = dmam_alloc_coherent(dev,
  92                                                        host->mmc->max_req_size,
  93                                                        &idma->bounce_dma_addr,
  94                                                        GFP_KERNEL);
  95                 if (!idma->bounce_buf) {
  96                         dev_err(dev, "Unable to map allocate DMA bounce buffer.\n");
  97                         return -ENOMEM;
  98                 }
  99         }
 100
 101         idma->use_bounce_buffer = true;
 102
 103         return 0;
 104 }
 105
 106 static int _sdmmc_idma_prep_data(struct mmci_host *host,
 107                                  struct mmc_data *data)
 108 {
 109         struct sdmmc_idma *idma = host->dma_priv;
 110
 111         if (idma->use_bounce_buffer) {
 112                 if (data->flags & MMC_DATA_WRITE) {
 113                         unsigned int xfer_bytes = data->blksz * data->blocks;
 114
 115                         sg_copy_to_buffer(data->sg, data->sg_len,
 116                                           idma->bounce_buf, xfer_bytes);
 117                         dma_wmb();
 118                 }
 119         } else {
 120                 int n_elem;
 121
 122                 n_elem = dma_map_sg(mmc_dev(host->mmc),
 123                                     data->sg,
 124                                     data->sg_len,
 125                                     mmc_get_dma_dir(data));
 126
 127                 if (!n_elem) {
 128                         dev_err(mmc_dev(host->mmc), "dma_map_sg failed\n");
 129                         return -EINVAL;
 130                 }
 131         }
 132         return 0;
 133 }
 134
 135 static int sdmmc_idma_prep_data(struct mmci_host *host,
 136                                 struct mmc_data *data, bool next)
 137 {
 138         /* Check if job is already prepared. */
 139         if (!next && data->host_cookie == host->next_cookie)
 140                 return 0;
 141
 142         return _sdmmc_idma_prep_data(host, data);
 143 }
 144
 145 static void sdmmc_idma_unprep_data(struct mmci_host *host,
 146                                    struct mmc_data *data, int err)
 147 {
 148         struct sdmmc_idma *idma = host->dma_priv;
 149
 150         if (idma->use_bounce_buffer) {
 151                 if (data->flags & MMC_DATA_READ) {
 152                         unsigned int xfer_bytes = data->blksz * data->blocks;
 153
 154                         sg_copy_from_buffer(data->sg, data->sg_len,
 155                                             idma->bounce_buf, xfer_bytes);
 156                 }
 157         } else {
 158                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
 159                              mmc_get_dma_dir(data));
 160         }
 161 }
 162
 163 static int sdmmc_idma_setup(struct mmci_host *host)
 164 {
 165         struct sdmmc_idma *idma;
 166         struct device *dev = mmc_dev(host->mmc);
 167
 168         idma = devm_kzalloc(dev, sizeof(*idma), GFP_KERNEL);
 169         if (!idma)
 170                 return -ENOMEM;
 171
 172         host->dma_priv = idma;
 173
 174         if (host->variant->dma_lli) {
 175                 idma->sg_cpu = dmam_alloc_coherent(dev, SDMMC_LLI_BUF_LEN,
 176                                                    &idma->sg_dma, GFP_KERNEL);
 177                 if (!idma->sg_cpu) {
 178                         dev_err(dev, "Failed to alloc IDMA descriptor\n");
 179                         return -ENOMEM;
 180                 }
 181                 host->mmc->max_segs = SDMMC_LLI_BUF_LEN /
 182                         sizeof(struct sdmmc_lli_desc);
 183                 host->mmc->max_seg_size = host->variant->stm32_idmabsize_mask;
 184
 185                 host->mmc->max_req_size = SZ_1M;
 186         } else {
 187                 host->mmc->max_segs = 1;
 188                 host->mmc->max_seg_size = host->mmc->max_req_size;
 189         }
 190
 191         return dma_set_max_seg_size(dev, host->mmc->max_seg_size);
 192 }
 193
 194 static int sdmmc_idma_start(struct mmci_host *host, unsigned int *datactrl)
 195
 196 {
 197         struct sdmmc_idma *idma = host->dma_priv;
 198         struct sdmmc_lli_desc *desc = (struct sdmmc_lli_desc *)idma->sg_cpu;
 199         struct mmc_data *data = host->data;
 200         struct scatterlist *sg;
 201         int i;
 202
 203         host->dma_in_progress = true;
 204
 205         if (!host->variant->dma_lli || data->sg_len == 1 ||
 206             idma->use_bounce_buffer) {
 207                 u32 dma_addr;
 208
 209                 if (idma->use_bounce_buffer)
 210                         dma_addr = idma->bounce_dma_addr;
 211                 else
 212                         dma_addr = sg_dma_address(data->sg);
 213
 214                 writel_relaxed(dma_addr,
 215                                host->base + MMCI_STM32_IDMABASE0R);
 216                 writel_relaxed(MMCI_STM32_IDMAEN,
 217                                host->base + MMCI_STM32_IDMACTRLR);
 218                 return 0;
 219         }
 220
 221         for_each_sg(data->sg, sg, data->sg_len, i) {
 222                 desc[i].idmalar = (i + 1) * sizeof(struct sdmmc_lli_desc);
 223                 desc[i].idmalar |= MMCI_STM32_ULA | MMCI_STM32_ULS
 224                         | MMCI_STM32_ABR;
 225                 desc[i].idmabase = sg_dma_address(sg);
 226                 desc[i].idmasize = sg_dma_len(sg);
 227         }
 228
 229         /* notice the end of link list */
 230         desc[data->sg_len - 1].idmalar &= ~MMCI_STM32_ULA;
 231
 232         dma_wmb();
 233         writel_relaxed(idma->sg_dma, host->base + MMCI_STM32_IDMABAR);
 234         writel_relaxed(desc[0].idmalar, host->base + MMCI_STM32_IDMALAR);
 235         writel_relaxed(desc[0].idmabase, host->base + MMCI_STM32_IDMABASE0R);
 236         writel_relaxed(desc[0].idmasize, host->base + MMCI_STM32_IDMABSIZER);
 237         writel_relaxed(MMCI_STM32_IDMAEN | MMCI_STM32_IDMALLIEN,
 238                        host->base + MMCI_STM32_IDMACTRLR);
 239
 240         return 0;
 241 }
 242
 243 static void sdmmc_idma_error(struct mmci_host *host)
 244 {
 245         struct mmc_data *data = host->data;
 246         struct sdmmc_idma *idma = host->dma_priv;
 247
 248         if (!dma_inprogress(host))
 249                 return;
 250
 251         writel_relaxed(0, host->base + MMCI_STM32_IDMACTRLR);
 252         host->dma_in_progress = false;
 253         data->host_cookie = 0;
 254
 255         if (!idma->use_bounce_buffer)
 256                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
 257                              mmc_get_dma_dir(data));
 258 }
 259
 260 static void sdmmc_idma_finalize(struct mmci_host *host, struct mmc_data *data)
 261 {
 262         if (!dma_inprogress(host))
 263                 return;
 264
 265         writel_relaxed(0, host->base + MMCI_STM32_IDMACTRLR);
 266         host->dma_in_progress = false;
 267
 268         if (!data->host_cookie)
 269                 sdmmc_idma_unprep_data(host, data, 0);
 270 }
 271
 272 static void mmci_sdmmc_set_clkreg(struct mmci_host *host, unsigned int desired)
 273 {
 274         unsigned int clk = 0, ddr = 0;
 275
 276         if (host->mmc->ios.timing == MMC_TIMING_MMC_DDR52 ||
 277             host->mmc->ios.timing == MMC_TIMING_UHS_DDR50)
 278                 ddr = MCI_STM32_CLK_DDR;
 279
 280         /*
 281          * cclk = mclk / (2 * clkdiv)
 282          * clkdiv 0 => bypass
 283          * in ddr mode bypass is not possible
 284          */
 285         if (desired) {
 286                 if (desired >= host->mclk && !ddr) {
 287                         host->cclk = host->mclk;
 288                 } else {
 289                         clk = DIV_ROUND_UP(host->mclk, 2 * desired);
 290                         if (clk > MCI_STM32_CLK_CLKDIV_MSK)
 291                                 clk = MCI_STM32_CLK_CLKDIV_MSK;
 292                         host->cclk = host->mclk / (2 * clk);
 293                 }
 294         } else {
 295                 /*
 296                  * while power-on phase the clock can't be define to 0,
 297                  * Only power-off and power-cyc deactivate the clock.
 298                  * if desired clock is 0, set max divider
 299                  */
 300                 clk = MCI_STM32_CLK_CLKDIV_MSK;
 301                 host->cclk = host->mclk / (2 * clk);
 302         }
 303
 304         /* Set actual clock for debug */
 305         if (host->mmc->ios.power_mode == MMC_POWER_ON)
 306                 host->mmc->actual_clock = host->cclk;
 307         else
 308                 host->mmc->actual_clock = 0;
 309
 310         if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4)
 311                 clk |= MCI_STM32_CLK_WIDEBUS_4;
 312         if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
 313                 clk |= MCI_STM32_CLK_WIDEBUS_8;
 314
 315         clk |= MCI_STM32_CLK_HWFCEN;
 316         clk |= host->clk_reg_add;
 317         clk |= ddr;
 318
 319         /*
 320          * SDMMC_FBCK is selected when an external Delay Block is needed
 321          * with SDR104.
 322          */
 323         if (host->mmc->ios.timing >= MMC_TIMING_UHS_SDR50) {
 324                 clk |= MCI_STM32_CLK_BUSSPEED;
 325                 if (host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) {
 326                         clk &= ~MCI_STM32_CLK_SEL_MSK;
 327                         clk |= MCI_STM32_CLK_SELFBCK;
 328                 }
 329         }
 330
 331         mmci_write_clkreg(host, clk);
 332 }
 333
 334 static void sdmmc_dlyb_input_ck(struct sdmmc_dlyb *dlyb)
 335 {
 336         if (!dlyb || !dlyb->base)
 337                 return;
 338
 339         /* Output clock = Input clock */
 340         writel_relaxed(0, dlyb->base + DLYB_CR);
 341 }
 342
 343 static void mmci_sdmmc_set_pwrreg(struct mmci_host *host, unsigned int pwr)
 344 {
 345         struct mmc_ios ios = host->mmc->ios;
 346         struct sdmmc_dlyb *dlyb = host->variant_priv;
 347
 348         /* adds OF options */
 349         pwr = host->pwr_reg_add;
 350
 351         sdmmc_dlyb_input_ck(dlyb);
 352
 353         if (ios.power_mode == MMC_POWER_OFF) {
 354                 /* Only a reset could power-off sdmmc */
 355                 reset_control_assert(host->rst);
 356                 udelay(2);
 357                 reset_control_deassert(host->rst);
 358
 359                 /*
 360                  * Set the SDMMC in Power-cycle state.
 361                  * This will make that the SDMMC_D[7:0], SDMMC_CMD and SDMMC_CK
 362                  * are driven low, to prevent the Card from being supplied
 363                  * through the signal lines.
 364                  */
 365                 mmci_write_pwrreg(host, MCI_STM32_PWR_CYC | pwr);
 366         } else if (ios.power_mode == MMC_POWER_ON) {
 367                 /*
 368                  * After power-off (reset): the irq mask defined in probe
 369                  * functionis lost
 370                  * ault irq mask (probe) must be activated
 371                  */
 372                 writel(MCI_IRQENABLE | host->variant->start_err,
 373                        host->base + MMCIMASK0);
 374
 375                 /* preserves voltage switch bits */
 376                 pwr |= host->pwr_reg & (MCI_STM32_VSWITCHEN |
 377                                         MCI_STM32_VSWITCH);
 378
 379                 /*
 380                  * After a power-cycle state, we must set the SDMMC in
 381                  * Power-off. The SDMMC_D[7:0], SDMMC_CMD and SDMMC_CK are
 382                  * driven high. Then we can set the SDMMC to Power-on state
 383                  */
 384                 mmci_write_pwrreg(host, MCI_PWR_OFF | pwr);
 385                 mdelay(1);
 386                 mmci_write_pwrreg(host, MCI_PWR_ON | pwr);
 387         }
 388 }
 389
 390 static u32 sdmmc_get_dctrl_cfg(struct mmci_host *host)
 391 {
 392         u32 datactrl;
 393
 394         datactrl = mmci_dctrl_blksz(host);
 395
 396         if (host->mmc->card && mmc_card_sdio(host->mmc->card) &&
 397             host->data->blocks == 1)
 398                 datactrl |= MCI_DPSM_STM32_MODE_SDIO;
 399         else if (host->data->stop && !host->mrq->sbc)
 400                 datactrl |= MCI_DPSM_STM32_MODE_BLOCK_STOP;
 401         else
 402                 datactrl |= MCI_DPSM_STM32_MODE_BLOCK;
 403
 404         return datactrl;
 405 }
 406
 407 static bool sdmmc_busy_complete(struct mmci_host *host, u32 status, u32 err_msk)
 408 {
 409         void __iomem *base = host->base;
 410         u32 busy_d0, busy_d0end, mask, sdmmc_status;
 411
 412         mask = readl_relaxed(base + MMCIMASK0);
 413         sdmmc_status = readl_relaxed(base + MMCISTATUS);
 414         busy_d0end = sdmmc_status & MCI_STM32_BUSYD0END;
 415         busy_d0 = sdmmc_status & MCI_STM32_BUSYD0;
 416
 417         /* complete if there is an error or busy_d0end */
 418         if ((status & err_msk) || busy_d0end)
 419                 goto complete;
 420
 421         /*
 422          * On response the busy signaling is reflected in the BUSYD0 flag.
 423          * if busy_d0 is in-progress we must activate busyd0end interrupt
 424          * to wait this completion. Else this request has no busy step.
 425          */
 426         if (busy_d0) {
 427                 if (!host->busy_status) {
 428                         writel_relaxed(mask | host->variant->busy_detect_mask,
 429                                        base + MMCIMASK0);
 430                         host->busy_status = status &
 431                                 (MCI_CMDSENT | MCI_CMDRESPEND);
 432                 }
 433                 return false;
 434         }
 435
 436 complete:
 437         if (host->busy_status) {
 438                 writel_relaxed(mask & ~host->variant->busy_detect_mask,
 439                                base + MMCIMASK0);
 440                 host->busy_status = 0;
 441         }
 442
 443         writel_relaxed(host->variant->busy_detect_mask, base + MMCICLEAR);
 444
 445         return true;
 446 }
 447
 448 static void sdmmc_dlyb_set_cfgr(struct sdmmc_dlyb *dlyb,
 449                                 int unit, int phase, bool sampler)
 450 {
 451         u32 cfgr;
 452
 453         writel_relaxed(DLYB_CR_SEN | DLYB_CR_DEN, dlyb->base + DLYB_CR);
 454
 455         cfgr = FIELD_PREP(DLYB_CFGR_UNIT_MASK, unit) |
 456                FIELD_PREP(DLYB_CFGR_SEL_MASK, phase);
 457         writel_relaxed(cfgr, dlyb->base + DLYB_CFGR);
 458
 459         if (!sampler)
 460                 writel_relaxed(DLYB_CR_DEN, dlyb->base + DLYB_CR);
 461 }
 462
 463 static int sdmmc_dlyb_lng_tuning(struct mmci_host *host)
 464 {
 465         struct sdmmc_dlyb *dlyb = host->variant_priv;
 466         u32 cfgr;
 467         int i, lng, ret;
 468
 469         for (i = 0; i <= DLYB_CFGR_UNIT_MAX; i++) {
 470                 sdmmc_dlyb_set_cfgr(dlyb, i, DLYB_CFGR_SEL_MAX, true);
 471
 472                 ret = readl_relaxed_poll_timeout(dlyb->base + DLYB_CFGR, cfgr,
 473                                                  (cfgr & DLYB_CFGR_LNGF),
 474                                                  1, DLYB_LNG_TIMEOUT_US);
 475                 if (ret) {
 476                         dev_warn(mmc_dev(host->mmc),
 477                                  "delay line cfg timeout unit:%d cfgr:%d\n",
 478                                  i, cfgr);
 479                         continue;
 480                 }
 481
 482                 lng = FIELD_GET(DLYB_CFGR_LNG_MASK, cfgr);
 483                 if (lng < BIT(DLYB_NB_DELAY) && lng > 0)
 484                         break;
 485         }
 486
 487         if (i > DLYB_CFGR_UNIT_MAX)
 488                 return -EINVAL;
 489
 490         dlyb->unit = i;
 491         dlyb->max = __fls(lng);
 492
 493         return 0;
 494 }
 495
 496 static int sdmmc_dlyb_phase_tuning(struct mmci_host *host, u32 opcode)
 497 {
 498         struct sdmmc_dlyb *dlyb = host->variant_priv;
 499         int cur_len = 0, max_len = 0, end_of_len = 0;
 500         int phase;
 501
 502         for (phase = 0; phase <= dlyb->max; phase++) {
 503                 sdmmc_dlyb_set_cfgr(dlyb, dlyb->unit, phase, false);
 504
 505                 if (mmc_send_tuning(host->mmc, opcode, NULL)) {
 506                         cur_len = 0;
 507                 } else {
 508                         cur_len++;
 509                         if (cur_len > max_len) {
 510                                 max_len = cur_len;
 511                                 end_of_len = phase;
 512                         }
 513                 }
 514         }
 515
 516         if (!max_len) {
 517                 dev_err(mmc_dev(host->mmc), "no tuning point found\n");
 518                 return -EINVAL;
 519         }
 520
 521         writel_relaxed(0, dlyb->base + DLYB_CR);
 522
 523         phase = end_of_len - max_len / 2;
 524         sdmmc_dlyb_set_cfgr(dlyb, dlyb->unit, phase, false);
 525
 526         dev_dbg(mmc_dev(host->mmc), "unit:%d max_dly:%d phase:%d\n",
 527                 dlyb->unit, dlyb->max, phase);
 528
 529         return 0;
 530 }
 531
 532 static int sdmmc_execute_tuning(struct mmc_host *mmc, u32 opcode)
 533 {
 534         struct mmci_host *host = mmc_priv(mmc);
 535         struct sdmmc_dlyb *dlyb = host->variant_priv;
 536
 537         if (!dlyb || !dlyb->base)
 538                 return -EINVAL;
 539
 540         if (sdmmc_dlyb_lng_tuning(host))
 541                 return -EINVAL;
 542
 543         return sdmmc_dlyb_phase_tuning(host, opcode);
 544 }
 545
 546 static void sdmmc_pre_sig_volt_vswitch(struct mmci_host *host)
 547 {
 548         /* clear the voltage switch completion flag */
 549         writel_relaxed(MCI_STM32_VSWENDC, host->base + MMCICLEAR);
 550         /* enable Voltage switch procedure */
 551         mmci_write_pwrreg(host, host->pwr_reg | MCI_STM32_VSWITCHEN);
 552 }
 553
 554 static int sdmmc_post_sig_volt_switch(struct mmci_host *host,
 555                                       struct mmc_ios *ios)
 556 {
 557         unsigned long flags;
 558         u32 status;
 559         int ret = 0;
 560
 561         spin_lock_irqsave(&host->lock, flags);
 562         if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180 &&
 563             host->pwr_reg & MCI_STM32_VSWITCHEN) {
 564                 mmci_write_pwrreg(host, host->pwr_reg | MCI_STM32_VSWITCH);
 565                 spin_unlock_irqrestore(&host->lock, flags);
 566
 567                 /* wait voltage switch completion while 10ms */
 568                 ret = readl_relaxed_poll_timeout(host->base + MMCISTATUS,
 569                                                  status,
 570                                                  (status & MCI_STM32_VSWEND),
 571                                                  10, SDMMC_VSWEND_TIMEOUT_US);
 572
 573                 writel_relaxed(MCI_STM32_VSWENDC | MCI_STM32_CKSTOPC,
 574                                host->base + MMCICLEAR);
 575                 spin_lock_irqsave(&host->lock, flags);
 576                 mmci_write_pwrreg(host, host->pwr_reg &
 577                                   ~(MCI_STM32_VSWITCHEN | MCI_STM32_VSWITCH));
 578         }
 579         spin_unlock_irqrestore(&host->lock, flags);
 580
 581         return ret;
 582 }
 583
 584 static struct mmci_host_ops sdmmc_variant_ops = {
 585         .validate_data = sdmmc_idma_validate_data,
 586         .prep_data = sdmmc_idma_prep_data,
 587         .unprep_data = sdmmc_idma_unprep_data,
 588         .get_datactrl_cfg = sdmmc_get_dctrl_cfg,
 589         .dma_setup = sdmmc_idma_setup,
 590         .dma_start = sdmmc_idma_start,
 591         .dma_finalize = sdmmc_idma_finalize,
 592         .dma_error = sdmmc_idma_error,
 593         .set_clkreg = mmci_sdmmc_set_clkreg,
 594         .set_pwrreg = mmci_sdmmc_set_pwrreg,
 595         .busy_complete = sdmmc_busy_complete,
 596         .pre_sig_volt_switch = sdmmc_pre_sig_volt_vswitch,
 597         .post_sig_volt_switch = sdmmc_post_sig_volt_switch,
 598 };
 599
 600 void sdmmc_variant_init(struct mmci_host *host)
 601 {
 602         struct device_node *np = host->mmc->parent->of_node;
 603         void __iomem *base_dlyb;
 604         struct sdmmc_dlyb *dlyb;
 605
 606         host->ops = &sdmmc_variant_ops;
 607         host->pwr_reg = readl_relaxed(host->base + MMCIPOWER);
 608
 609         base_dlyb = devm_of_iomap(mmc_dev(host->mmc), np, 1, NULL);
 610         if (IS_ERR(base_dlyb))
 611                 return;
 612
 613         dlyb = devm_kzalloc(mmc_dev(host->mmc), sizeof(*dlyb), GFP_KERNEL);
 614         if (!dlyb)
 615                 return;
 616
 617         dlyb->base = base_dlyb;
 618         host->variant_priv = dlyb;
 619         host->mmc_ops->execute_tuning = sdmmc_execute_tuning;
 620 }