drivers/mmc/host/mmci.c

   1 /*
   2  *  linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver
   3  *
   4  *  Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
   5  *  Copyright (C) 2010 ST-Ericsson SA
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/init.h>
  14 #include <linux/ioport.h>
  15 #include <linux/device.h>
  16 #include <linux/io.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/kernel.h>
  19 #include <linux/slab.h>
  20 #include <linux/delay.h>
  21 #include <linux/err.h>
  22 #include <linux/highmem.h>
  23 #include <linux/log2.h>
  24 #include <linux/mmc/pm.h>
  25 #include <linux/mmc/host.h>
  26 #include <linux/mmc/card.h>
  27 #include <linux/mmc/slot-gpio.h>
  28 #include <linux/amba/bus.h>
  29 #include <linux/clk.h>
  30 #include <linux/scatterlist.h>
  31 #include <linux/gpio.h>
  32 #include <linux/of_gpio.h>
  33 #include <linux/regulator/consumer.h>
  34 #include <linux/dmaengine.h>
  35 #include <linux/dma-mapping.h>
  36 #include <linux/amba/mmci.h>
  37 #include <linux/pm_runtime.h>
  38 #include <linux/types.h>
  39 #include <linux/pinctrl/consumer.h>
  40
  41 #include <asm/div64.h>
  42 #include <asm/io.h>
  43
  44 #include "mmci.h"
  45 #include "mmci_qcom_dml.h"
  46
  47 #define DRIVER_NAME "mmci-pl18x"
  48
  49 static unsigned int fmax = 515633;
  50
  51 static struct variant_data variant_arm = {
  52         .fifosize               = 16 * 4,
  53         .fifohalfsize           = 8 * 4,
  54         .datalength_bits        = 16,
  55         .pwrreg_powerup         = MCI_PWR_UP,
  56         .f_max                  = 100000000,
  57         .reversed_irq_handling  = true,
  58         .mmcimask1              = true,
  59         .start_err              = MCI_STARTBITERR,
  60         .opendrain              = MCI_ROD,
  61 };
  62
  63 static struct variant_data variant_arm_extended_fifo = {
  64         .fifosize               = 128 * 4,
  65         .fifohalfsize           = 64 * 4,
  66         .datalength_bits        = 16,
  67         .pwrreg_powerup         = MCI_PWR_UP,
  68         .f_max                  = 100000000,
  69         .mmcimask1              = true,
  70         .start_err              = MCI_STARTBITERR,
  71         .opendrain              = MCI_ROD,
  72 };
  73
  74 static struct variant_data variant_arm_extended_fifo_hwfc = {
  75         .fifosize               = 128 * 4,
  76         .fifohalfsize           = 64 * 4,
  77         .clkreg_enable          = MCI_ARM_HWFCEN,
  78         .datalength_bits        = 16,
  79         .pwrreg_powerup         = MCI_PWR_UP,
  80         .f_max                  = 100000000,
  81         .mmcimask1              = true,
  82         .start_err              = MCI_STARTBITERR,
  83         .opendrain              = MCI_ROD,
  84 };
  85
  86 static struct variant_data variant_u300 = {
  87         .fifosize               = 16 * 4,
  88         .fifohalfsize           = 8 * 4,
  89         .clkreg_enable          = MCI_ST_U300_HWFCEN,
  90         .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
  91         .datalength_bits        = 16,
  92         .datactrl_mask_sdio     = MCI_DPSM_ST_SDIOEN,
  93         .st_sdio                        = true,
  94         .pwrreg_powerup         = MCI_PWR_ON,
  95         .f_max                  = 100000000,
  96         .signal_direction       = true,
  97         .pwrreg_clkgate         = true,
  98         .pwrreg_nopower         = true,
  99         .mmcimask1              = true,
 100         .start_err              = MCI_STARTBITERR,
 101         .opendrain              = MCI_OD,
 102 };
 103
 104 static struct variant_data variant_nomadik = {
 105         .fifosize               = 16 * 4,
 106         .fifohalfsize           = 8 * 4,
 107         .clkreg                 = MCI_CLK_ENABLE,
 108         .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
 109         .datalength_bits        = 24,
 110         .datactrl_mask_sdio     = MCI_DPSM_ST_SDIOEN,
 111         .st_sdio                = true,
 112         .st_clkdiv              = true,
 113         .pwrreg_powerup         = MCI_PWR_ON,
 114         .f_max                  = 100000000,
 115         .signal_direction       = true,
 116         .pwrreg_clkgate         = true,
 117         .pwrreg_nopower         = true,
 118         .mmcimask1              = true,
 119         .start_err              = MCI_STARTBITERR,
 120         .opendrain              = MCI_OD,
 121 };
 122
 123 static struct variant_data variant_ux500 = {
 124         .fifosize               = 30 * 4,
 125         .fifohalfsize           = 8 * 4,
 126         .clkreg                 = MCI_CLK_ENABLE,
 127         .clkreg_enable          = MCI_ST_UX500_HWFCEN,
 128         .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
 129         .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE,
 130         .datalength_bits        = 24,
 131         .datactrl_mask_sdio     = MCI_DPSM_ST_SDIOEN,
 132         .st_sdio                = true,
 133         .st_clkdiv              = true,
 134         .pwrreg_powerup         = MCI_PWR_ON,
 135         .f_max                  = 100000000,
 136         .signal_direction       = true,
 137         .pwrreg_clkgate         = true,
 138         .busy_detect            = true,
 139         .busy_dpsm_flag         = MCI_DPSM_ST_BUSYMODE,
 140         .busy_detect_flag       = MCI_ST_CARDBUSY,
 141         .busy_detect_mask       = MCI_ST_BUSYENDMASK,
 142         .pwrreg_nopower         = true,
 143         .mmcimask1              = true,
 144         .start_err              = MCI_STARTBITERR,
 145         .opendrain              = MCI_OD,
 146 };
 147
 148 static struct variant_data variant_ux500v2 = {
 149         .fifosize               = 30 * 4,
 150         .fifohalfsize           = 8 * 4,
 151         .clkreg                 = MCI_CLK_ENABLE,
 152         .clkreg_enable          = MCI_ST_UX500_HWFCEN,
 153         .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
 154         .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE,
 155         .datactrl_mask_ddrmode  = MCI_DPSM_ST_DDRMODE,
 156         .datalength_bits        = 24,
 157         .datactrl_mask_sdio     = MCI_DPSM_ST_SDIOEN,
 158         .st_sdio                = true,
 159         .st_clkdiv              = true,
 160         .blksz_datactrl16       = true,
 161         .pwrreg_powerup         = MCI_PWR_ON,
 162         .f_max                  = 100000000,
 163         .signal_direction       = true,
 164         .pwrreg_clkgate         = true,
 165         .busy_detect            = true,
 166         .busy_dpsm_flag         = MCI_DPSM_ST_BUSYMODE,
 167         .busy_detect_flag       = MCI_ST_CARDBUSY,
 168         .busy_detect_mask       = MCI_ST_BUSYENDMASK,
 169         .pwrreg_nopower         = true,
 170         .mmcimask1              = true,
 171         .start_err              = MCI_STARTBITERR,
 172         .opendrain              = MCI_OD,
 173 };
 174
 175 static struct variant_data variant_stm32 = {
 176         .fifosize               = 32 * 4,
 177         .fifohalfsize           = 8 * 4,
 178         .clkreg                 = MCI_CLK_ENABLE,
 179         .clkreg_enable          = MCI_ST_UX500_HWFCEN,
 180         .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
 181         .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE,
 182         .datalength_bits        = 24,
 183         .datactrl_mask_sdio     = MCI_DPSM_ST_SDIOEN,
 184         .st_sdio                = true,
 185         .st_clkdiv              = true,
 186         .pwrreg_powerup         = MCI_PWR_ON,
 187         .f_max                  = 48000000,
 188         .pwrreg_clkgate         = true,
 189         .pwrreg_nopower         = true,
 190 };
 191
 192 static struct variant_data variant_qcom = {
 193         .fifosize               = 16 * 4,
 194         .fifohalfsize           = 8 * 4,
 195         .clkreg                 = MCI_CLK_ENABLE,
 196         .clkreg_enable          = MCI_QCOM_CLK_FLOWENA |
 197                                   MCI_QCOM_CLK_SELECT_IN_FBCLK,
 198         .clkreg_8bit_bus_enable = MCI_QCOM_CLK_WIDEBUS_8,
 199         .datactrl_mask_ddrmode  = MCI_QCOM_CLK_SELECT_IN_DDR_MODE,
 200         .data_cmd_enable        = MCI_CPSM_QCOM_DATCMD,
 201         .blksz_datactrl4        = true,
 202         .datalength_bits        = 24,
 203         .pwrreg_powerup         = MCI_PWR_UP,
 204         .f_max                  = 208000000,
 205         .explicit_mclk_control  = true,
 206         .qcom_fifo              = true,
 207         .qcom_dml               = true,
 208         .mmcimask1              = true,
 209         .start_err              = MCI_STARTBITERR,
 210         .opendrain              = MCI_ROD,
 211         .init                   = qcom_variant_init,
 212 };
 213
 214 /* Busy detection for the ST Micro variant */
 215 static int mmci_card_busy(struct mmc_host *mmc)
 216 {
 217         struct mmci_host *host = mmc_priv(mmc);
 218         unsigned long flags;
 219         int busy = 0;
 220
 221         spin_lock_irqsave(&host->lock, flags);
 222         if (readl(host->base + MMCISTATUS) & host->variant->busy_detect_flag)
 223                 busy = 1;
 224         spin_unlock_irqrestore(&host->lock, flags);
 225
 226         return busy;
 227 }
 228
 229 /*
 230  * Validate mmc prerequisites
 231  */
 232 static int mmci_validate_data(struct mmci_host *host,
 233                               struct mmc_data *data)
 234 {
 235         if (!data)
 236                 return 0;
 237
 238         if (!is_power_of_2(data->blksz)) {
 239                 dev_err(mmc_dev(host->mmc),
 240                         "unsupported block size (%d bytes)\n", data->blksz);
 241                 return -EINVAL;
 242         }
 243
 244         return 0;
 245 }
 246
 247 static void mmci_reg_delay(struct mmci_host *host)
 248 {
 249         /*
 250          * According to the spec, at least three feedback clock cycles
 251          * of max 52 MHz must pass between two writes to the MMCICLOCK reg.
 252          * Three MCLK clock cycles must pass between two MMCIPOWER reg writes.
 253          * Worst delay time during card init is at 100 kHz => 30 us.
 254          * Worst delay time when up and running is at 25 MHz => 120 ns.
 255          */
 256         if (host->cclk < 25000000)
 257                 udelay(30);
 258         else
 259                 ndelay(120);
 260 }
 261
 262 /*
 263  * This must be called with host->lock held
 264  */
 265 static void mmci_write_clkreg(struct mmci_host *host, u32 clk)
 266 {
 267         if (host->clk_reg != clk) {
 268                 host->clk_reg = clk;
 269                 writel(clk, host->base + MMCICLOCK);
 270         }
 271 }
 272
 273 /*
 274  * This must be called with host->lock held
 275  */
 276 static void mmci_write_pwrreg(struct mmci_host *host, u32 pwr)
 277 {
 278         if (host->pwr_reg != pwr) {
 279                 host->pwr_reg = pwr;
 280                 writel(pwr, host->base + MMCIPOWER);
 281         }
 282 }
 283
 284 /*
 285  * This must be called with host->lock held
 286  */
 287 static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl)
 288 {
 289         /* Keep busy mode in DPSM if enabled */
 290         datactrl |= host->datactrl_reg & host->variant->busy_dpsm_flag;
 291
 292         if (host->datactrl_reg != datactrl) {
 293                 host->datactrl_reg = datactrl;
 294                 writel(datactrl, host->base + MMCIDATACTRL);
 295         }
 296 }
 297
 298 /*
 299  * This must be called with host->lock held
 300  */
 301 static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
 302 {
 303         struct variant_data *variant = host->variant;
 304         u32 clk = variant->clkreg;
 305
 306         /* Make sure cclk reflects the current calculated clock */
 307         host->cclk = 0;
 308
 309         if (desired) {
 310                 if (variant->explicit_mclk_control) {
 311                         host->cclk = host->mclk;
 312                 } else if (desired >= host->mclk) {
 313                         clk = MCI_CLK_BYPASS;
 314                         if (variant->st_clkdiv)
 315                                 clk |= MCI_ST_UX500_NEG_EDGE;
 316                         host->cclk = host->mclk;
 317                 } else if (variant->st_clkdiv) {
 318                         /*
 319                          * DB8500 TRM says f = mclk / (clkdiv + 2)
 320                          * => clkdiv = (mclk / f) - 2
 321                          * Round the divider up so we don't exceed the max
 322                          * frequency
 323                          */
 324                         clk = DIV_ROUND_UP(host->mclk, desired) - 2;
 325                         if (clk >= 256)
 326                                 clk = 255;
 327                         host->cclk = host->mclk / (clk + 2);
 328                 } else {
 329                         /*
 330                          * PL180 TRM says f = mclk / (2 * (clkdiv + 1))
 331                          * => clkdiv = mclk / (2 * f) - 1
 332                          */
 333                         clk = host->mclk / (2 * desired) - 1;
 334                         if (clk >= 256)
 335                                 clk = 255;
 336                         host->cclk = host->mclk / (2 * (clk + 1));
 337                 }
 338
 339                 clk |= variant->clkreg_enable;
 340                 clk |= MCI_CLK_ENABLE;
 341                 /* This hasn't proven to be worthwhile */
 342                 /* clk |= MCI_CLK_PWRSAVE; */
 343         }
 344
 345         /* Set actual clock for debug */
 346         host->mmc->actual_clock = host->cclk;
 347
 348         if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4)
 349                 clk |= MCI_4BIT_BUS;
 350         if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
 351                 clk |= variant->clkreg_8bit_bus_enable;
 352
 353         if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 ||
 354             host->mmc->ios.timing == MMC_TIMING_MMC_DDR52)
 355                 clk |= variant->clkreg_neg_edge_enable;
 356
 357         mmci_write_clkreg(host, clk);
 358 }
 359
 360 static void
 361 mmci_request_end(struct mmci_host *host, struct mmc_request *mrq)
 362 {
 363         writel(0, host->base + MMCICOMMAND);
 364
 365         BUG_ON(host->data);
 366
 367         host->mrq = NULL;
 368         host->cmd = NULL;
 369
 370         mmc_request_done(host->mmc, mrq);
 371 }
 372
 373 static void mmci_set_mask1(struct mmci_host *host, unsigned int mask)
 374 {
 375         void __iomem *base = host->base;
 376         struct variant_data *variant = host->variant;
 377
 378         if (host->singleirq) {
 379                 unsigned int mask0 = readl(base + MMCIMASK0);
 380
 381                 mask0 &= ~MCI_IRQ1MASK;
 382                 mask0 |= mask;
 383
 384                 writel(mask0, base + MMCIMASK0);
 385         }
 386
 387         if (variant->mmcimask1)
 388                 writel(mask, base + MMCIMASK1);
 389
 390         host->mask1_reg = mask;
 391 }
 392
 393 static void mmci_stop_data(struct mmci_host *host)
 394 {
 395         mmci_write_datactrlreg(host, 0);
 396         mmci_set_mask1(host, 0);
 397         host->data = NULL;
 398 }
 399
 400 static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data)
 401 {
 402         unsigned int flags = SG_MITER_ATOMIC;
 403
 404         if (data->flags & MMC_DATA_READ)
 405                 flags |= SG_MITER_TO_SG;
 406         else
 407                 flags |= SG_MITER_FROM_SG;
 408
 409         sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
 410 }
 411
 412 /*
 413  * All the DMA operation mode stuff goes inside this ifdef.
 414  * This assumes that you have a generic DMA device interface,
 415  * no custom DMA interfaces are supported.
 416  */
 417 #ifdef CONFIG_DMA_ENGINE
 418 static void mmci_dma_setup(struct mmci_host *host)
 419 {
 420         const char *rxname, *txname;
 421
 422         host->dma_rx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "rx");
 423         host->dma_tx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "tx");
 424
 425         /* initialize pre request cookie */
 426         host->next_data.cookie = 1;
 427
 428         /*
 429          * If only an RX channel is specified, the driver will
 430          * attempt to use it bidirectionally, however if it is
 431          * is specified but cannot be located, DMA will be disabled.
 432          */
 433         if (host->dma_rx_channel && !host->dma_tx_channel)
 434                 host->dma_tx_channel = host->dma_rx_channel;
 435
 436         if (host->dma_rx_channel)
 437                 rxname = dma_chan_name(host->dma_rx_channel);
 438         else
 439                 rxname = "none";
 440
 441         if (host->dma_tx_channel)
 442                 txname = dma_chan_name(host->dma_tx_channel);
 443         else
 444                 txname = "none";
 445
 446         dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n",
 447                  rxname, txname);
 448
 449         /*
 450          * Limit the maximum segment size in any SG entry according to
 451          * the parameters of the DMA engine device.
 452          */
 453         if (host->dma_tx_channel) {
 454                 struct device *dev = host->dma_tx_channel->device->dev;
 455                 unsigned int max_seg_size = dma_get_max_seg_size(dev);
 456
 457                 if (max_seg_size < host->mmc->max_seg_size)
 458                         host->mmc->max_seg_size = max_seg_size;
 459         }
 460         if (host->dma_rx_channel) {
 461                 struct device *dev = host->dma_rx_channel->device->dev;
 462                 unsigned int max_seg_size = dma_get_max_seg_size(dev);
 463
 464                 if (max_seg_size < host->mmc->max_seg_size)
 465                         host->mmc->max_seg_size = max_seg_size;
 466         }
 467
 468         if (host->ops && host->ops->dma_setup)
 469                 host->ops->dma_setup(host);
 470 }
 471
 472 /*
 473  * This is used in or so inline it
 474  * so it can be discarded.
 475  */
 476 static inline void mmci_dma_release(struct mmci_host *host)
 477 {
 478         if (host->dma_rx_channel)
 479                 dma_release_channel(host->dma_rx_channel);
 480         if (host->dma_tx_channel)
 481                 dma_release_channel(host->dma_tx_channel);
 482         host->dma_rx_channel = host->dma_tx_channel = NULL;
 483 }
 484
 485 static void mmci_dma_data_error(struct mmci_host *host)
 486 {
 487         dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n");
 488         dmaengine_terminate_all(host->dma_current);
 489         host->dma_in_progress = false;
 490         host->dma_current = NULL;
 491         host->dma_desc_current = NULL;
 492         host->data->host_cookie = 0;
 493 }
 494
 495 static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
 496 {
 497         struct dma_chan *chan;
 498
 499         if (data->flags & MMC_DATA_READ)
 500                 chan = host->dma_rx_channel;
 501         else
 502                 chan = host->dma_tx_channel;
 503
 504         dma_unmap_sg(chan->device->dev, data->sg, data->sg_len,
 505                      mmc_get_dma_dir(data));
 506 }
 507
 508 static void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data)
 509 {
 510         u32 status;
 511         int i;
 512
 513         /* Wait up to 1ms for the DMA to complete */
 514         for (i = 0; ; i++) {
 515                 status = readl(host->base + MMCISTATUS);
 516                 if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100)
 517                         break;
 518                 udelay(10);
 519         }
 520
 521         /*
 522          * Check to see whether we still have some data left in the FIFO -
 523          * this catches DMA controllers which are unable to monitor the
 524          * DMALBREQ and DMALSREQ signals while allowing us to DMA to non-
 525          * contiguous buffers.  On TX, we'll get a FIFO underrun error.
 526          */
 527         if (status & MCI_RXDATAAVLBLMASK) {
 528                 mmci_dma_data_error(host);
 529                 if (!data->error)
 530                         data->error = -EIO;
 531         }
 532
 533         if (!data->host_cookie)
 534                 mmci_dma_unmap(host, data);
 535
 536         /*
 537          * Use of DMA with scatter-gather is impossible.
 538          * Give up with DMA and switch back to PIO mode.
 539          */
 540         if (status & MCI_RXDATAAVLBLMASK) {
 541                 dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n");
 542                 mmci_dma_release(host);
 543         }
 544
 545         host->dma_in_progress = false;
 546         host->dma_current = NULL;
 547         host->dma_desc_current = NULL;
 548 }
 549
 550 /* prepares DMA channel and DMA descriptor, returns non-zero on failure */
 551 static int __mmci_dma_prep_data(struct mmci_host *host, struct mmc_data *data,
 552                                 struct dma_chan **dma_chan,
 553                                 struct dma_async_tx_descriptor **dma_desc)
 554 {
 555         struct variant_data *variant = host->variant;
 556         struct dma_slave_config conf = {
 557                 .src_addr = host->phybase + MMCIFIFO,
 558                 .dst_addr = host->phybase + MMCIFIFO,
 559                 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
 560                 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
 561                 .src_maxburst = variant->fifohalfsize >> 2, /* # of words */
 562                 .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */
 563                 .device_fc = false,
 564         };
 565         struct dma_chan *chan;
 566         struct dma_device *device;
 567         struct dma_async_tx_descriptor *desc;
 568         int nr_sg;
 569         unsigned long flags = DMA_CTRL_ACK;
 570
 571         if (data->flags & MMC_DATA_READ) {
 572                 conf.direction = DMA_DEV_TO_MEM;
 573                 chan = host->dma_rx_channel;
 574         } else {
 575                 conf.direction = DMA_MEM_TO_DEV;
 576                 chan = host->dma_tx_channel;
 577         }
 578
 579         /* If there's no DMA channel, fall back to PIO */
 580         if (!chan)
 581                 return -EINVAL;
 582
 583         /* If less than or equal to the fifo size, don't bother with DMA */
 584         if (data->blksz * data->blocks <= variant->fifosize)
 585                 return -EINVAL;
 586
 587         device = chan->device;
 588         nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len,
 589                            mmc_get_dma_dir(data));
 590         if (nr_sg == 0)
 591                 return -EINVAL;
 592
 593         if (host->variant->qcom_dml)
 594                 flags |= DMA_PREP_INTERRUPT;
 595
 596         dmaengine_slave_config(chan, &conf);
 597         desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg,
 598                                             conf.direction, flags);
 599         if (!desc)
 600                 goto unmap_exit;
 601
 602         *dma_chan = chan;
 603         *dma_desc = desc;
 604
 605         return 0;
 606
 607  unmap_exit:
 608         dma_unmap_sg(device->dev, data->sg, data->sg_len,
 609                      mmc_get_dma_dir(data));
 610         return -ENOMEM;
 611 }
 612
 613 static inline int mmci_dma_prep_data(struct mmci_host *host,
 614                                      struct mmc_data *data)
 615 {
 616         /* Check if next job is already prepared. */
 617         if (host->dma_current && host->dma_desc_current)
 618                 return 0;
 619
 620         /* No job were prepared thus do it now. */
 621         return __mmci_dma_prep_data(host, data, &host->dma_current,
 622                                     &host->dma_desc_current);
 623 }
 624
 625 static inline int mmci_dma_prep_next(struct mmci_host *host,
 626                                      struct mmc_data *data)
 627 {
 628         struct mmci_host_next *nd = &host->next_data;
 629         return __mmci_dma_prep_data(host, data, &nd->dma_chan, &nd->dma_desc);
 630 }
 631
 632 static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
 633 {
 634         int ret;
 635         struct mmc_data *data = host->data;
 636
 637         ret = mmci_dma_prep_data(host, host->data);
 638         if (ret)
 639                 return ret;
 640
 641         /* Okay, go for it. */
 642         dev_vdbg(mmc_dev(host->mmc),
 643                  "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n",
 644                  data->sg_len, data->blksz, data->blocks, data->flags);
 645         host->dma_in_progress = true;
 646         dmaengine_submit(host->dma_desc_current);
 647         dma_async_issue_pending(host->dma_current);
 648
 649         if (host->variant->qcom_dml)
 650                 dml_start_xfer(host, data);
 651
 652         datactrl |= MCI_DPSM_DMAENABLE;
 653
 654         /* Trigger the DMA transfer */
 655         mmci_write_datactrlreg(host, datactrl);
 656
 657         /*
 658          * Let the MMCI say when the data is ended and it's time
 659          * to fire next DMA request. When that happens, MMCI will
 660          * call mmci_data_end()
 661          */
 662         writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK,
 663                host->base + MMCIMASK0);
 664         return 0;
 665 }
 666
 667 static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data)
 668 {
 669         struct mmci_host_next *next = &host->next_data;
 670
 671         WARN_ON(data->host_cookie && data->host_cookie != next->cookie);
 672         WARN_ON(!data->host_cookie && (next->dma_desc || next->dma_chan));
 673
 674         host->dma_desc_current = next->dma_desc;
 675         host->dma_current = next->dma_chan;
 676         next->dma_desc = NULL;
 677         next->dma_chan = NULL;
 678 }
 679
 680 static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq)
 681 {
 682         struct mmci_host *host = mmc_priv(mmc);
 683         struct mmc_data *data = mrq->data;
 684         struct mmci_host_next *nd = &host->next_data;
 685
 686         if (!data)
 687                 return;
 688
 689         BUG_ON(data->host_cookie);
 690
 691         if (mmci_validate_data(host, data))
 692                 return;
 693
 694         if (!mmci_dma_prep_next(host, data))
 695                 data->host_cookie = ++nd->cookie < 0 ? 1 : nd->cookie;
 696 }
 697
 698 static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq,
 699                               int err)
 700 {
 701         struct mmci_host *host = mmc_priv(mmc);
 702         struct mmc_data *data = mrq->data;
 703
 704         if (!data || !data->host_cookie)
 705                 return;
 706
 707         mmci_dma_unmap(host, data);
 708
 709         if (err) {
 710                 struct mmci_host_next *next = &host->next_data;
 711                 struct dma_chan *chan;
 712                 if (data->flags & MMC_DATA_READ)
 713                         chan = host->dma_rx_channel;
 714                 else
 715                         chan = host->dma_tx_channel;
 716                 dmaengine_terminate_all(chan);
 717
 718                 if (host->dma_desc_current == next->dma_desc)
 719                         host->dma_desc_current = NULL;
 720
 721                 if (host->dma_current == next->dma_chan) {
 722                         host->dma_in_progress = false;
 723                         host->dma_current = NULL;
 724                 }
 725
 726                 next->dma_desc = NULL;
 727                 next->dma_chan = NULL;
 728                 data->host_cookie = 0;
 729         }
 730 }
 731
 732 #else
 733 /* Blank functions if the DMA engine is not available */
 734 static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data)
 735 {
 736 }
 737 static inline void mmci_dma_setup(struct mmci_host *host)
 738 {
 739 }
 740
 741 static inline void mmci_dma_release(struct mmci_host *host)
 742 {
 743 }
 744
 745 static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
 746 {
 747 }
 748
 749 static inline void mmci_dma_finalize(struct mmci_host *host,
 750                                      struct mmc_data *data)
 751 {
 752 }
 753
 754 static inline void mmci_dma_data_error(struct mmci_host *host)
 755 {
 756 }
 757
 758 static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
 759 {
 760         return -ENOSYS;
 761 }
 762
 763 #define mmci_pre_request NULL
 764 #define mmci_post_request NULL
 765
 766 #endif
 767
 768 static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
 769 {
 770         struct variant_data *variant = host->variant;
 771         unsigned int datactrl, timeout, irqmask;
 772         unsigned long long clks;
 773         void __iomem *base;
 774         int blksz_bits;
 775
 776         dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n",
 777                 data->blksz, data->blocks, data->flags);
 778
 779         host->data = data;
 780         host->size = data->blksz * data->blocks;
 781         data->bytes_xfered = 0;
 782
 783         clks = (unsigned long long)data->timeout_ns * host->cclk;
 784         do_div(clks, NSEC_PER_SEC);
 785
 786         timeout = data->timeout_clks + (unsigned int)clks;
 787
 788         base = host->base;
 789         writel(timeout, base + MMCIDATATIMER);
 790         writel(host->size, base + MMCIDATALENGTH);
 791
 792         blksz_bits = ffs(data->blksz) - 1;
 793         BUG_ON(1 << blksz_bits != data->blksz);
 794
 795         if (variant->blksz_datactrl16)
 796                 datactrl = MCI_DPSM_ENABLE | (data->blksz << 16);
 797         else if (variant->blksz_datactrl4)
 798                 datactrl = MCI_DPSM_ENABLE | (data->blksz << 4);
 799         else
 800                 datactrl = MCI_DPSM_ENABLE | blksz_bits << 4;
 801
 802         if (data->flags & MMC_DATA_READ)
 803                 datactrl |= MCI_DPSM_DIRECTION;
 804
 805         if (host->mmc->card && mmc_card_sdio(host->mmc->card)) {
 806                 u32 clk;
 807
 808                 datactrl |= variant->datactrl_mask_sdio;
 809
 810                 /*
 811                  * The ST Micro variant for SDIO small write transfers
 812                  * needs to have clock H/W flow control disabled,
 813                  * otherwise the transfer will not start. The threshold
 814                  * depends on the rate of MCLK.
 815                  */
 816                 if (variant->st_sdio && data->flags & MMC_DATA_WRITE &&
 817                     (host->size < 8 ||
 818                      (host->size <= 8 && host->mclk > 50000000)))
 819                         clk = host->clk_reg & ~variant->clkreg_enable;
 820                 else
 821                         clk = host->clk_reg | variant->clkreg_enable;
 822
 823                 mmci_write_clkreg(host, clk);
 824         }
 825
 826         if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 ||
 827             host->mmc->ios.timing == MMC_TIMING_MMC_DDR52)
 828                 datactrl |= variant->datactrl_mask_ddrmode;
 829
 830         /*
 831          * Attempt to use DMA operation mode, if this
 832          * should fail, fall back to PIO mode
 833          */
 834         if (!mmci_dma_start_data(host, datactrl))
 835                 return;
 836
 837         /* IRQ mode, map the SG list for CPU reading/writing */
 838         mmci_init_sg(host, data);
 839
 840         if (data->flags & MMC_DATA_READ) {
 841                 irqmask = MCI_RXFIFOHALFFULLMASK;
 842
 843                 /*
 844                  * If we have less than the fifo 'half-full' threshold to
 845                  * transfer, trigger a PIO interrupt as soon as any data
 846                  * is available.
 847                  */
 848                 if (host->size < variant->fifohalfsize)
 849                         irqmask |= MCI_RXDATAAVLBLMASK;
 850         } else {
 851                 /*
 852                  * We don't actually need to include "FIFO empty" here
 853                  * since its implicit in "FIFO half empty".
 854                  */
 855                 irqmask = MCI_TXFIFOHALFEMPTYMASK;
 856         }
 857
 858         mmci_write_datactrlreg(host, datactrl);
 859         writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0);
 860         mmci_set_mask1(host, irqmask);
 861 }
 862
 863 static void
 864 mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c)
 865 {
 866         void __iomem *base = host->base;
 867
 868         dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n",
 869             cmd->opcode, cmd->arg, cmd->flags);
 870
 871         if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) {
 872                 writel(0, base + MMCICOMMAND);
 873                 mmci_reg_delay(host);
 874         }
 875
 876         c |= cmd->opcode | MCI_CPSM_ENABLE;
 877         if (cmd->flags & MMC_RSP_PRESENT) {
 878                 if (cmd->flags & MMC_RSP_136)
 879                         c |= MCI_CPSM_LONGRSP;
 880                 c |= MCI_CPSM_RESPONSE;
 881         }
 882         if (/*interrupt*/0)
 883                 c |= MCI_CPSM_INTERRUPT;
 884
 885         if (mmc_cmd_type(cmd) == MMC_CMD_ADTC)
 886                 c |= host->variant->data_cmd_enable;
 887
 888         host->cmd = cmd;
 889
 890         writel(cmd->arg, base + MMCIARGUMENT);
 891         writel(c, base + MMCICOMMAND);
 892 }
 893
 894 static void
 895 mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
 896               unsigned int status)
 897 {
 898         unsigned int status_err;
 899
 900         /* Make sure we have data to handle */
 901         if (!data)
 902                 return;
 903
 904         /* First check for errors */
 905         status_err = status & (host->variant->start_err |
 906                                MCI_DATACRCFAIL | MCI_DATATIMEOUT |
 907                                MCI_TXUNDERRUN | MCI_RXOVERRUN);
 908
 909         if (status_err) {
 910                 u32 remain, success;
 911
 912                 /* Terminate the DMA transfer */
 913                 if (dma_inprogress(host)) {
 914                         mmci_dma_data_error(host);
 915                         mmci_dma_unmap(host, data);
 916                 }
 917
 918                 /*
 919                  * Calculate how far we are into the transfer.  Note that
 920                  * the data counter gives the number of bytes transferred
 921                  * on the MMC bus, not on the host side.  On reads, this
 922                  * can be as much as a FIFO-worth of data ahead.  This
 923                  * matters for FIFO overruns only.
 924                  */
 925                 remain = readl(host->base + MMCIDATACNT);
 926                 success = data->blksz * data->blocks - remain;
 927
 928                 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n",
 929                         status_err, success);
 930                 if (status_err & MCI_DATACRCFAIL) {
 931                         /* Last block was not successful */
 932                         success -= 1;
 933                         data->error = -EILSEQ;
 934                 } else if (status_err & MCI_DATATIMEOUT) {
 935                         data->error = -ETIMEDOUT;
 936                 } else if (status_err & MCI_STARTBITERR) {
 937                         data->error = -ECOMM;
 938                 } else if (status_err & MCI_TXUNDERRUN) {
 939                         data->error = -EIO;
 940                 } else if (status_err & MCI_RXOVERRUN) {
 941                         if (success > host->variant->fifosize)
 942                                 success -= host->variant->fifosize;
 943                         else
 944                                 success = 0;
 945                         data->error = -EIO;
 946                 }
 947                 data->bytes_xfered = round_down(success, data->blksz);
 948         }
 949
 950         if (status & MCI_DATABLOCKEND)
 951                 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n");
 952
 953         if (status & MCI_DATAEND || data->error) {
 954                 if (dma_inprogress(host))
 955                         mmci_dma_finalize(host, data);
 956                 mmci_stop_data(host);
 957
 958                 if (!data->error)
 959                         /* The error clause is handled above, success! */
 960                         data->bytes_xfered = data->blksz * data->blocks;
 961
 962                 if (!data->stop || host->mrq->sbc) {
 963                         mmci_request_end(host, data->mrq);
 964                 } else {
 965                         mmci_start_command(host, data->stop, 0);
 966                 }
 967         }
 968 }
 969
 970 static void
 971 mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
 972              unsigned int status)
 973 {
 974         void __iomem *base = host->base;
 975         bool sbc;
 976
 977         if (!cmd)
 978                 return;
 979
 980         sbc = (cmd == host->mrq->sbc);
 981
 982         /*
 983          * We need to be one of these interrupts to be considered worth
 984          * handling. Note that we tag on any latent IRQs postponed
 985          * due to waiting for busy status.
 986          */
 987         if (!((status|host->busy_status) &
 988               (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND)))
 989                 return;
 990
 991         /*
 992          * ST Micro variant: handle busy detection.
 993          */
 994         if (host->variant->busy_detect) {
 995                 bool busy_resp = !!(cmd->flags & MMC_RSP_BUSY);
 996
 997                 /* We are busy with a command, return */
 998                 if (host->busy_status &&
 999                     (status & host->variant->busy_detect_flag))
1000                         return;
1001
1002                 /*
1003                  * We were not busy, but we now got a busy response on
1004                  * something that was not an error, and we double-check
1005                  * that the special busy status bit is still set before
1006                  * proceeding.
1007                  */
1008                 if (!host->busy_status && busy_resp &&
1009                     !(status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT)) &&
1010                     (readl(base + MMCISTATUS) & host->variant->busy_detect_flag)) {
1011
1012                         /* Clear the busy start IRQ */
1013                         writel(host->variant->busy_detect_mask,
1014                                host->base + MMCICLEAR);
1015
1016                         /* Unmask the busy end IRQ */
1017                         writel(readl(base + MMCIMASK0) |
1018                                host->variant->busy_detect_mask,
1019                                base + MMCIMASK0);
1020                         /*
1021                          * Now cache the last response status code (until
1022                          * the busy bit goes low), and return.
1023                          */
1024                         host->busy_status =
1025                                 status & (MCI_CMDSENT|MCI_CMDRESPEND);
1026                         return;
1027                 }
1028
1029                 /*
1030                  * At this point we are not busy with a command, we have
1031                  * not received a new busy request, clear and mask the busy
1032                  * end IRQ and fall through to process the IRQ.
1033                  */
1034                 if (host->busy_status) {
1035
1036                         writel(host->variant->busy_detect_mask,
1037                                host->base + MMCICLEAR);
1038
1039                         writel(readl(base + MMCIMASK0) &
1040                                ~host->variant->busy_detect_mask,
1041                                base + MMCIMASK0);
1042                         host->busy_status = 0;
1043                 }
1044         }
1045
1046         host->cmd = NULL;
1047
1048         if (status & MCI_CMDTIMEOUT) {
1049                 cmd->error = -ETIMEDOUT;
1050         } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) {
1051                 cmd->error = -EILSEQ;
1052         } else {
1053                 cmd->resp[0] = readl(base + MMCIRESPONSE0);
1054                 cmd->resp[1] = readl(base + MMCIRESPONSE1);
1055                 cmd->resp[2] = readl(base + MMCIRESPONSE2);
1056                 cmd->resp[3] = readl(base + MMCIRESPONSE3);
1057         }
1058
1059         if ((!sbc && !cmd->data) || cmd->error) {
1060                 if (host->data) {
1061                         /* Terminate the DMA transfer */
1062                         if (dma_inprogress(host)) {
1063                                 mmci_dma_data_error(host);
1064                                 mmci_dma_unmap(host, host->data);
1065                         }
1066                         mmci_stop_data(host);
1067                 }
1068                 mmci_request_end(host, host->mrq);
1069         } else if (sbc) {
1070                 mmci_start_command(host, host->mrq->cmd, 0);
1071         } else if (!(cmd->data->flags & MMC_DATA_READ)) {
1072                 mmci_start_data(host, cmd->data);
1073         }
1074 }
1075
1076 static int mmci_get_rx_fifocnt(struct mmci_host *host, u32 status, int remain)
1077 {
1078         return remain - (readl(host->base + MMCIFIFOCNT) << 2);
1079 }
1080
1081 static int mmci_qcom_get_rx_fifocnt(struct mmci_host *host, u32 status, int r)
1082 {
1083         /*
1084          * on qcom SDCC4 only 8 words are used in each burst so only 8 addresses
1085          * from the fifo range should be used
1086          */
1087         if (status & MCI_RXFIFOHALFFULL)
1088                 return host->variant->fifohalfsize;
1089         else if (status & MCI_RXDATAAVLBL)
1090                 return 4;
1091
1092         return 0;
1093 }
1094
1095 static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain)
1096 {
1097         void __iomem *base = host->base;
1098         char *ptr = buffer;
1099         u32 status = readl(host->base + MMCISTATUS);
1100         int host_remain = host->size;
1101
1102         do {
1103                 int count = host->get_rx_fifocnt(host, status, host_remain);
1104
1105                 if (count > remain)
1106                         count = remain;
1107
1108                 if (count <= 0)
1109                         break;
1110
1111                 /*
1112                  * SDIO especially may want to send something that is
1113                  * not divisible by 4 (as opposed to card sectors
1114                  * etc). Therefore make sure to always read the last bytes
1115                  * while only doing full 32-bit reads towards the FIFO.
1116                  */
1117                 if (unlikely(count & 0x3)) {
1118                         if (count < 4) {
1119                                 unsigned char buf[4];
1120                                 ioread32_rep(base + MMCIFIFO, buf, 1);
1121                                 memcpy(ptr, buf, count);
1122                         } else {
1123                                 ioread32_rep(base + MMCIFIFO, ptr, count >> 2);
1124                                 count &= ~0x3;
1125                         }
1126                 } else {
1127                         ioread32_rep(base + MMCIFIFO, ptr, count >> 2);
1128                 }
1129
1130                 ptr += count;
1131                 remain -= count;
1132                 host_remain -= count;
1133
1134                 if (remain == 0)
1135                         break;
1136
1137                 status = readl(base + MMCISTATUS);
1138         } while (status & MCI_RXDATAAVLBL);
1139
1140         return ptr - buffer;
1141 }
1142
1143 static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status)
1144 {
1145         struct variant_data *variant = host->variant;
1146         void __iomem *base = host->base;
1147         char *ptr = buffer;
1148
1149         do {
1150                 unsigned int count, maxcnt;
1151
1152                 maxcnt = status & MCI_TXFIFOEMPTY ?
1153                          variant->fifosize : variant->fifohalfsize;
1154                 count = min(remain, maxcnt);
1155
1156                 /*
1157                  * SDIO especially may want to send something that is
1158                  * not divisible by 4 (as opposed to card sectors
1159                  * etc), and the FIFO only accept full 32-bit writes.
1160                  * So compensate by adding +3 on the count, a single
1161                  * byte become a 32bit write, 7 bytes will be two
1162                  * 32bit writes etc.
1163                  */
1164                 iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2);
1165
1166                 ptr += count;
1167                 remain -= count;
1168
1169                 if (remain == 0)
1170                         break;
1171
1172                 status = readl(base + MMCISTATUS);
1173         } while (status & MCI_TXFIFOHALFEMPTY);
1174
1175         return ptr - buffer;
1176 }
1177
1178 /*
1179  * PIO data transfer IRQ handler.
1180  */
1181 static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
1182 {
1183         struct mmci_host *host = dev_id;
1184         struct sg_mapping_iter *sg_miter = &host->sg_miter;
1185         struct variant_data *variant = host->variant;
1186         void __iomem *base = host->base;
1187         u32 status;
1188
1189         status = readl(base + MMCISTATUS);
1190
1191         dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status);
1192
1193         do {
1194                 unsigned int remain, len;
1195                 char *buffer;
1196
1197                 /*
1198                  * For write, we only need to test the half-empty flag
1199                  * here - if the FIFO is completely empty, then by
1200                  * definition it is more than half empty.
1201                  *
1202                  * For read, check for data available.
1203                  */
1204                 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL)))
1205                         break;
1206
1207                 if (!sg_miter_next(sg_miter))
1208                         break;
1209
1210                 buffer = sg_miter->addr;
1211                 remain = sg_miter->length;
1212
1213                 len = 0;
1214                 if (status & MCI_RXACTIVE)
1215                         len = mmci_pio_read(host, buffer, remain);
1216                 if (status & MCI_TXACTIVE)
1217                         len = mmci_pio_write(host, buffer, remain, status);
1218
1219                 sg_miter->consumed = len;
1220
1221                 host->size -= len;
1222                 remain -= len;
1223
1224                 if (remain)
1225                         break;
1226
1227                 status = readl(base + MMCISTATUS);
1228         } while (1);
1229
1230         sg_miter_stop(sg_miter);
1231
1232         /*
1233          * If we have less than the fifo 'half-full' threshold to transfer,
1234          * trigger a PIO interrupt as soon as any data is available.
1235          */
1236         if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize)
1237                 mmci_set_mask1(host, MCI_RXDATAAVLBLMASK);
1238
1239         /*
1240          * If we run out of data, disable the data IRQs; this
1241          * prevents a race where the FIFO becomes empty before
1242          * the chip itself has disabled the data path, and
1243          * stops us racing with our data end IRQ.
1244          */
1245         if (host->size == 0) {
1246                 mmci_set_mask1(host, 0);
1247                 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0);
1248         }
1249
1250         return IRQ_HANDLED;
1251 }
1252
1253 /*
1254  * Handle completion of command and data transfers.
1255  */
1256 static irqreturn_t mmci_irq(int irq, void *dev_id)
1257 {
1258         struct mmci_host *host = dev_id;
1259         u32 status;
1260         int ret = 0;
1261
1262         spin_lock(&host->lock);
1263
1264         do {
1265                 status = readl(host->base + MMCISTATUS);
1266
1267                 if (host->singleirq) {
1268                         if (status & host->mask1_reg)
1269                                 mmci_pio_irq(irq, dev_id);
1270
1271                         status &= ~MCI_IRQ1MASK;
1272                 }
1273
1274                 /*
1275                  * We intentionally clear the MCI_ST_CARDBUSY IRQ (if it's
1276                  * enabled) in mmci_cmd_irq() function where ST Micro busy
1277                  * detection variant is handled. Considering the HW seems to be
1278                  * triggering the IRQ on both edges while monitoring DAT0 for
1279                  * busy completion and that same status bit is used to monitor
1280                  * start and end of busy detection, special care must be taken
1281                  * to make sure that both start and end interrupts are always
1282                  * cleared one after the other.
1283                  */
1284                 status &= readl(host->base + MMCIMASK0);
1285                 if (host->variant->busy_detect)
1286                         writel(status & ~host->variant->busy_detect_mask,
1287                                host->base + MMCICLEAR);
1288                 else
1289                         writel(status, host->base + MMCICLEAR);
1290
1291                 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status);
1292
1293                 if (host->variant->reversed_irq_handling) {
1294                         mmci_data_irq(host, host->data, status);
1295                         mmci_cmd_irq(host, host->cmd, status);
1296                 } else {
1297                         mmci_cmd_irq(host, host->cmd, status);
1298                         mmci_data_irq(host, host->data, status);
1299                 }
1300
1301                 /*
1302                  * Busy detection has been handled by mmci_cmd_irq() above.
1303                  * Clear the status bit to prevent polling in IRQ context.
1304                  */
1305                 if (host->variant->busy_detect_flag)
1306                         status &= ~host->variant->busy_detect_flag;
1307
1308                 ret = 1;
1309         } while (status);
1310
1311         spin_unlock(&host->lock);
1312
1313         return IRQ_RETVAL(ret);
1314 }
1315
1316 static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1317 {
1318         struct mmci_host *host = mmc_priv(mmc);
1319         unsigned long flags;
1320
1321         WARN_ON(host->mrq != NULL);
1322
1323         mrq->cmd->error = mmci_validate_data(host, mrq->data);
1324         if (mrq->cmd->error) {
1325                 mmc_request_done(mmc, mrq);
1326                 return;
1327         }
1328
1329         spin_lock_irqsave(&host->lock, flags);
1330
1331         host->mrq = mrq;
1332
1333         if (mrq->data)
1334                 mmci_get_next_data(host, mrq->data);
1335
1336         if (mrq->data && mrq->data->flags & MMC_DATA_READ)
1337                 mmci_start_data(host, mrq->data);
1338
1339         if (mrq->sbc)
1340                 mmci_start_command(host, mrq->sbc, 0);
1341         else
1342                 mmci_start_command(host, mrq->cmd, 0);
1343
1344         spin_unlock_irqrestore(&host->lock, flags);
1345 }
1346
1347 static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1348 {
1349         struct mmci_host *host = mmc_priv(mmc);
1350         struct variant_data *variant = host->variant;
1351         u32 pwr = 0;
1352         unsigned long flags;
1353         int ret;
1354
1355         if (host->plat->ios_handler &&
1356                 host->plat->ios_handler(mmc_dev(mmc), ios))
1357                         dev_err(mmc_dev(mmc), "platform ios_handler failed\n");
1358
1359         switch (ios->power_mode) {
1360         case MMC_POWER_OFF:
1361                 if (!IS_ERR(mmc->supply.vmmc))
1362                         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1363
1364                 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
1365                         regulator_disable(mmc->supply.vqmmc);
1366                         host->vqmmc_enabled = false;
1367                 }
1368
1369                 break;
1370         case MMC_POWER_UP:
1371                 if (!IS_ERR(mmc->supply.vmmc))
1372                         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
1373
1374                 /*
1375                  * The ST Micro variant doesn't have the PL180s MCI_PWR_UP
1376                  * and instead uses MCI_PWR_ON so apply whatever value is
1377                  * configured in the variant data.
1378                  */
1379                 pwr |= variant->pwrreg_powerup;
1380
1381                 break;
1382         case MMC_POWER_ON:
1383                 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
1384                         ret = regulator_enable(mmc->supply.vqmmc);
1385                         if (ret < 0)
1386                                 dev_err(mmc_dev(mmc),
1387                                         "failed to enable vqmmc regulator\n");
1388                         else
1389                                 host->vqmmc_enabled = true;
1390                 }
1391
1392                 pwr |= MCI_PWR_ON;
1393                 break;
1394         }
1395
1396         if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) {
1397                 /*
1398                  * The ST Micro variant has some additional bits
1399                  * indicating signal direction for the signals in
1400                  * the SD/MMC bus and feedback-clock usage.
1401                  */
1402                 pwr |= host->pwr_reg_add;
1403
1404                 if (ios->bus_width == MMC_BUS_WIDTH_4)
1405                         pwr &= ~MCI_ST_DATA74DIREN;
1406                 else if (ios->bus_width == MMC_BUS_WIDTH_1)
1407                         pwr &= (~MCI_ST_DATA74DIREN &
1408                                 ~MCI_ST_DATA31DIREN &
1409                                 ~MCI_ST_DATA2DIREN);
1410         }
1411
1412         if (variant->opendrain) {
1413                 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
1414                         pwr |= variant->opendrain;
1415         } else {
1416                 /*
1417                  * If the variant cannot configure the pads by its own, then we
1418                  * expect the pinctrl to be able to do that for us
1419                  */
1420                 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
1421                         pinctrl_select_state(host->pinctrl, host->pins_opendrain);
1422                 else
1423                         pinctrl_select_state(host->pinctrl, host->pins_default);
1424         }
1425
1426         /*
1427          * If clock = 0 and the variant requires the MMCIPOWER to be used for
1428          * gating the clock, the MCI_PWR_ON bit is cleared.
1429          */
1430         if (!ios->clock && variant->pwrreg_clkgate)
1431                 pwr &= ~MCI_PWR_ON;
1432
1433         if (host->variant->explicit_mclk_control &&
1434             ios->clock != host->clock_cache) {
1435                 ret = clk_set_rate(host->clk, ios->clock);
1436                 if (ret < 0)
1437                         dev_err(mmc_dev(host->mmc),
1438                                 "Error setting clock rate (%d)\n", ret);
1439                 else
1440                         host->mclk = clk_get_rate(host->clk);
1441         }
1442         host->clock_cache = ios->clock;
1443
1444         spin_lock_irqsave(&host->lock, flags);
1445
1446         mmci_set_clkreg(host, ios->clock);
1447         mmci_write_pwrreg(host, pwr);
1448         mmci_reg_delay(host);
1449
1450         spin_unlock_irqrestore(&host->lock, flags);
1451 }
1452
1453 static int mmci_get_cd(struct mmc_host *mmc)
1454 {
1455         struct mmci_host *host = mmc_priv(mmc);
1456         struct mmci_platform_data *plat = host->plat;
1457         unsigned int status = mmc_gpio_get_cd(mmc);
1458
1459         if (status == -ENOSYS) {
1460                 if (!plat->status)
1461                         return 1; /* Assume always present */
1462
1463                 status = plat->status(mmc_dev(host->mmc));
1464         }
1465         return status;
1466 }
1467
1468 static int mmci_sig_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios)
1469 {
1470         int ret = 0;
1471
1472         if (!IS_ERR(mmc->supply.vqmmc)) {
1473
1474                 switch (ios->signal_voltage) {
1475                 case MMC_SIGNAL_VOLTAGE_330:
1476                         ret = regulator_set_voltage(mmc->supply.vqmmc,
1477                                                 2700000, 3600000);
1478                         break;
1479                 case MMC_SIGNAL_VOLTAGE_180:
1480                         ret = regulator_set_voltage(mmc->supply.vqmmc,
1481                                                 1700000, 1950000);
1482                         break;
1483                 case MMC_SIGNAL_VOLTAGE_120:
1484                         ret = regulator_set_voltage(mmc->supply.vqmmc,
1485                                                 1100000, 1300000);
1486                         break;
1487                 }
1488
1489                 if (ret)
1490                         dev_warn(mmc_dev(mmc), "Voltage switch failed\n");
1491         }
1492
1493         return ret;
1494 }
1495
1496 static struct mmc_host_ops mmci_ops = {
1497         .request        = mmci_request,
1498         .pre_req        = mmci_pre_request,
1499         .post_req       = mmci_post_request,
1500         .set_ios        = mmci_set_ios,
1501         .get_ro         = mmc_gpio_get_ro,
1502         .get_cd         = mmci_get_cd,
1503         .start_signal_voltage_switch = mmci_sig_volt_switch,
1504 };
1505
1506 static int mmci_of_parse(struct device_node *np, struct mmc_host *mmc)
1507 {
1508         struct mmci_host *host = mmc_priv(mmc);
1509         int ret = mmc_of_parse(mmc);
1510
1511         if (ret)
1512                 return ret;
1513
1514         if (of_get_property(np, "st,sig-dir-dat0", NULL))
1515                 host->pwr_reg_add |= MCI_ST_DATA0DIREN;
1516         if (of_get_property(np, "st,sig-dir-dat2", NULL))
1517                 host->pwr_reg_add |= MCI_ST_DATA2DIREN;
1518         if (of_get_property(np, "st,sig-dir-dat31", NULL))
1519                 host->pwr_reg_add |= MCI_ST_DATA31DIREN;
1520         if (of_get_property(np, "st,sig-dir-dat74", NULL))
1521                 host->pwr_reg_add |= MCI_ST_DATA74DIREN;
1522         if (of_get_property(np, "st,sig-dir-cmd", NULL))
1523                 host->pwr_reg_add |= MCI_ST_CMDDIREN;
1524         if (of_get_property(np, "st,sig-pin-fbclk", NULL))
1525                 host->pwr_reg_add |= MCI_ST_FBCLKEN;
1526
1527         if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL))
1528                 mmc->caps |= MMC_CAP_MMC_HIGHSPEED;
1529         if (of_get_property(np, "mmc-cap-sd-highspeed", NULL))
1530                 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1531
1532         return 0;
1533 }
1534
1535 static int mmci_probe(struct amba_device *dev,
1536         const struct amba_id *id)
1537 {
1538         struct mmci_platform_data *plat = dev->dev.platform_data;
1539         struct device_node *np = dev->dev.of_node;
1540         struct variant_data *variant = id->data;
1541         struct mmci_host *host;
1542         struct mmc_host *mmc;
1543         int ret;
1544
1545         /* Must have platform data or Device Tree. */
1546         if (!plat && !np) {
1547                 dev_err(&dev->dev, "No plat data or DT found\n");
1548                 return -EINVAL;
1549         }
1550
1551         if (!plat) {
1552                 plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL);
1553                 if (!plat)
1554                         return -ENOMEM;
1555         }
1556
1557         mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev);
1558         if (!mmc)
1559                 return -ENOMEM;
1560
1561         ret = mmci_of_parse(np, mmc);
1562         if (ret)
1563                 goto host_free;
1564
1565         host = mmc_priv(mmc);
1566         host->mmc = mmc;
1567
1568         /*
1569          * Some variant (STM32) doesn't have opendrain bit, nevertheless
1570          * pins can be set accordingly using pinctrl
1571          */
1572         if (!variant->opendrain) {
1573                 host->pinctrl = devm_pinctrl_get(&dev->dev);
1574                 if (IS_ERR(host->pinctrl)) {
1575                         dev_err(&dev->dev, "failed to get pinctrl");
1576                         ret = PTR_ERR(host->pinctrl);
1577                         goto host_free;
1578                 }
1579
1580                 host->pins_default = pinctrl_lookup_state(host->pinctrl,
1581                                                           PINCTRL_STATE_DEFAULT);
1582                 if (IS_ERR(host->pins_default)) {
1583                         dev_err(mmc_dev(mmc), "Can't select default pins\n");
1584                         ret = PTR_ERR(host->pins_default);
1585                         goto host_free;
1586                 }
1587
1588                 host->pins_opendrain = pinctrl_lookup_state(host->pinctrl,
1589                                                             MMCI_PINCTRL_STATE_OPENDRAIN);
1590                 if (IS_ERR(host->pins_opendrain)) {
1591                         dev_err(mmc_dev(mmc), "Can't select opendrain pins\n");
1592                         ret = PTR_ERR(host->pins_opendrain);
1593                         goto host_free;
1594                 }
1595         }
1596
1597         host->hw_designer = amba_manf(dev);
1598         host->hw_revision = amba_rev(dev);
1599         dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer);
1600         dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision);
1601
1602         host->clk = devm_clk_get(&dev->dev, NULL);
1603         if (IS_ERR(host->clk)) {
1604                 ret = PTR_ERR(host->clk);
1605                 goto host_free;
1606         }
1607
1608         ret = clk_prepare_enable(host->clk);
1609         if (ret)
1610                 goto host_free;
1611
1612         if (variant->qcom_fifo)
1613                 host->get_rx_fifocnt = mmci_qcom_get_rx_fifocnt;
1614         else
1615                 host->get_rx_fifocnt = mmci_get_rx_fifocnt;
1616
1617         host->plat = plat;
1618         host->variant = variant;
1619         host->mclk = clk_get_rate(host->clk);
1620         /*
1621          * According to the spec, mclk is max 100 MHz,
1622          * so we try to adjust the clock down to this,
1623          * (if possible).
1624          */
1625         if (host->mclk > variant->f_max) {
1626                 ret = clk_set_rate(host->clk, variant->f_max);
1627                 if (ret < 0)
1628                         goto clk_disable;
1629                 host->mclk = clk_get_rate(host->clk);
1630                 dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n",
1631                         host->mclk);
1632         }
1633
1634         host->phybase = dev->res.start;
1635         host->base = devm_ioremap_resource(&dev->dev, &dev->res);
1636         if (IS_ERR(host->base)) {
1637                 ret = PTR_ERR(host->base);
1638                 goto clk_disable;
1639         }
1640
1641         if (variant->init)
1642                 variant->init(host);
1643
1644         /*
1645          * The ARM and ST versions of the block have slightly different
1646          * clock divider equations which means that the minimum divider
1647          * differs too.
1648          * on Qualcomm like controllers get the nearest minimum clock to 100Khz
1649          */
1650         if (variant->st_clkdiv)
1651                 mmc->f_min = DIV_ROUND_UP(host->mclk, 257);
1652         else if (variant->explicit_mclk_control)
1653                 mmc->f_min = clk_round_rate(host->clk, 100000);
1654         else
1655                 mmc->f_min = DIV_ROUND_UP(host->mclk, 512);
1656         /*
1657          * If no maximum operating frequency is supplied, fall back to use
1658          * the module parameter, which has a (low) default value in case it
1659          * is not specified. Either value must not exceed the clock rate into
1660          * the block, of course.
1661          */
1662         if (mmc->f_max)
1663                 mmc->f_max = variant->explicit_mclk_control ?
1664                                 min(variant->f_max, mmc->f_max) :
1665                                 min(host->mclk, mmc->f_max);
1666         else
1667                 mmc->f_max = variant->explicit_mclk_control ?
1668                                 fmax : min(host->mclk, fmax);
1669
1670
1671         dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max);
1672
1673         /* Get regulators and the supported OCR mask */
1674         ret = mmc_regulator_get_supply(mmc);
1675         if (ret)
1676                 goto clk_disable;
1677
1678         if (!mmc->ocr_avail)
1679                 mmc->ocr_avail = plat->ocr_mask;
1680         else if (plat->ocr_mask)
1681                 dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n");
1682
1683         /* DT takes precedence over platform data. */
1684         if (!np) {
1685                 if (!plat->cd_invert)
1686                         mmc->caps2 |= MMC_CAP2_CD_ACTIVE_HIGH;
1687                 mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
1688         }
1689
1690         /* We support these capabilities. */
1691         mmc->caps |= MMC_CAP_CMD23;
1692
1693         /*
1694          * Enable busy detection.
1695          */
1696         if (variant->busy_detect) {
1697                 mmci_ops.card_busy = mmci_card_busy;
1698                 /*
1699                  * Not all variants have a flag to enable busy detection
1700                  * in the DPSM, but if they do, set it here.
1701                  */
1702                 if (variant->busy_dpsm_flag)
1703                         mmci_write_datactrlreg(host,
1704                                                host->variant->busy_dpsm_flag);
1705                 mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
1706                 mmc->max_busy_timeout = 0;
1707         }
1708
1709         mmc->ops = &mmci_ops;
1710
1711         /* We support these PM capabilities. */
1712         mmc->pm_caps |= MMC_PM_KEEP_POWER;
1713
1714         /*
1715          * We can do SGIO
1716          */
1717         mmc->max_segs = NR_SG;
1718
1719         /*
1720          * Since only a certain number of bits are valid in the data length
1721          * register, we must ensure that we don't exceed 2^num-1 bytes in a
1722          * single request.
1723          */
1724         mmc->max_req_size = (1 << variant->datalength_bits) - 1;
1725
1726         /*
1727          * Set the maximum segment size.  Since we aren't doing DMA
1728          * (yet) we are only limited by the data length register.
1729          */
1730         mmc->max_seg_size = mmc->max_req_size;
1731
1732         /*
1733          * Block size can be up to 2048 bytes, but must be a power of two.
1734          */
1735         mmc->max_blk_size = 1 << 11;
1736
1737         /*
1738          * Limit the number of blocks transferred so that we don't overflow
1739          * the maximum request size.
1740          */
1741         mmc->max_blk_count = mmc->max_req_size >> 11;
1742
1743         spin_lock_init(&host->lock);
1744
1745         writel(0, host->base + MMCIMASK0);
1746
1747         if (variant->mmcimask1)
1748                 writel(0, host->base + MMCIMASK1);
1749
1750         writel(0xfff, host->base + MMCICLEAR);
1751
1752         /*
1753          * If:
1754          * - not using DT but using a descriptor table, or
1755          * - using a table of descriptors ALONGSIDE DT, or
1756          * look up these descriptors named "cd" and "wp" right here, fail
1757          * silently of these do not exist and proceed to try platform data
1758          */
1759         if (!np) {
1760                 ret = mmc_gpiod_request_cd(mmc, "cd", 0, false, 0, NULL);
1761                 if (ret < 0) {
1762                         if (ret == -EPROBE_DEFER)
1763                                 goto clk_disable;
1764                         else if (gpio_is_valid(plat->gpio_cd)) {
1765                                 ret = mmc_gpio_request_cd(mmc, plat->gpio_cd, 0);
1766                                 if (ret)
1767                                         goto clk_disable;
1768                         }
1769                 }
1770
1771                 ret = mmc_gpiod_request_ro(mmc, "wp", 0, false, 0, NULL);
1772                 if (ret < 0) {
1773                         if (ret == -EPROBE_DEFER)
1774                                 goto clk_disable;
1775                         else if (gpio_is_valid(plat->gpio_wp)) {
1776                                 ret = mmc_gpio_request_ro(mmc, plat->gpio_wp);
1777                                 if (ret)
1778                                         goto clk_disable;
1779                         }
1780                 }
1781         }
1782
1783         ret = devm_request_irq(&dev->dev, dev->irq[0], mmci_irq, IRQF_SHARED,
1784                         DRIVER_NAME " (cmd)", host);
1785         if (ret)
1786                 goto clk_disable;
1787
1788         if (!dev->irq[1])
1789                 host->singleirq = true;
1790         else {
1791                 ret = devm_request_irq(&dev->dev, dev->irq[1], mmci_pio_irq,
1792                                 IRQF_SHARED, DRIVER_NAME " (pio)", host);
1793                 if (ret)
1794                         goto clk_disable;
1795         }
1796
1797         writel(MCI_IRQENABLE | variant->start_err, host->base + MMCIMASK0);
1798
1799         amba_set_drvdata(dev, mmc);
1800
1801         dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n",
1802                  mmc_hostname(mmc), amba_part(dev), amba_manf(dev),
1803                  amba_rev(dev), (unsigned long long)dev->res.start,
1804                  dev->irq[0], dev->irq[1]);
1805
1806         mmci_dma_setup(host);
1807
1808         pm_runtime_set_autosuspend_delay(&dev->dev, 50);
1809         pm_runtime_use_autosuspend(&dev->dev);
1810
1811         mmc_add_host(mmc);
1812
1813         pm_runtime_put(&dev->dev);
1814         return 0;
1815
1816  clk_disable:
1817         clk_disable_unprepare(host->clk);
1818  host_free:
1819         mmc_free_host(mmc);
1820         return ret;
1821 }
1822
1823 static int mmci_remove(struct amba_device *dev)
1824 {
1825         struct mmc_host *mmc = amba_get_drvdata(dev);
1826
1827         if (mmc) {
1828                 struct mmci_host *host = mmc_priv(mmc);
1829                 struct variant_data *variant = host->variant;
1830
1831                 /*
1832                  * Undo pm_runtime_put() in probe.  We use the _sync
1833                  * version here so that we can access the primecell.
1834                  */
1835                 pm_runtime_get_sync(&dev->dev);
1836
1837                 mmc_remove_host(mmc);
1838
1839                 writel(0, host->base + MMCIMASK0);
1840
1841                 if (variant->mmcimask1)
1842                         writel(0, host->base + MMCIMASK1);
1843
1844                 writel(0, host->base + MMCICOMMAND);
1845                 writel(0, host->base + MMCIDATACTRL);
1846
1847                 mmci_dma_release(host);
1848                 clk_disable_unprepare(host->clk);
1849                 mmc_free_host(mmc);
1850         }
1851
1852         return 0;
1853 }
1854
1855 #ifdef CONFIG_PM
1856 static void mmci_save(struct mmci_host *host)
1857 {
1858         unsigned long flags;
1859
1860         spin_lock_irqsave(&host->lock, flags);
1861
1862         writel(0, host->base + MMCIMASK0);
1863         if (host->variant->pwrreg_nopower) {
1864                 writel(0, host->base + MMCIDATACTRL);
1865                 writel(0, host->base + MMCIPOWER);
1866                 writel(0, host->base + MMCICLOCK);
1867         }
1868         mmci_reg_delay(host);
1869
1870         spin_unlock_irqrestore(&host->lock, flags);
1871 }
1872
1873 static void mmci_restore(struct mmci_host *host)
1874 {
1875         unsigned long flags;
1876
1877         spin_lock_irqsave(&host->lock, flags);
1878
1879         if (host->variant->pwrreg_nopower) {
1880                 writel(host->clk_reg, host->base + MMCICLOCK);
1881                 writel(host->datactrl_reg, host->base + MMCIDATACTRL);
1882                 writel(host->pwr_reg, host->base + MMCIPOWER);
1883         }
1884         writel(MCI_IRQENABLE | host->variant->start_err,
1885                host->base + MMCIMASK0);
1886         mmci_reg_delay(host);
1887
1888         spin_unlock_irqrestore(&host->lock, flags);
1889 }
1890
1891 static int mmci_runtime_suspend(struct device *dev)
1892 {
1893         struct amba_device *adev = to_amba_device(dev);
1894         struct mmc_host *mmc = amba_get_drvdata(adev);
1895
1896         if (mmc) {
1897                 struct mmci_host *host = mmc_priv(mmc);
1898                 pinctrl_pm_select_sleep_state(dev);
1899                 mmci_save(host);
1900                 clk_disable_unprepare(host->clk);
1901         }
1902
1903         return 0;
1904 }
1905
1906 static int mmci_runtime_resume(struct device *dev)
1907 {
1908         struct amba_device *adev = to_amba_device(dev);
1909         struct mmc_host *mmc = amba_get_drvdata(adev);
1910
1911         if (mmc) {
1912                 struct mmci_host *host = mmc_priv(mmc);
1913                 clk_prepare_enable(host->clk);
1914                 mmci_restore(host);
1915                 pinctrl_pm_select_default_state(dev);
1916         }
1917
1918         return 0;
1919 }
1920 #endif
1921
1922 static const struct dev_pm_ops mmci_dev_pm_ops = {
1923         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1924                                 pm_runtime_force_resume)
1925         SET_RUNTIME_PM_OPS(mmci_runtime_suspend, mmci_runtime_resume, NULL)
1926 };
1927
1928 static const struct amba_id mmci_ids[] = {
1929         {
1930                 .id     = 0x00041180,
1931                 .mask   = 0xff0fffff,
1932                 .data   = &variant_arm,
1933         },
1934         {
1935                 .id     = 0x01041180,
1936                 .mask   = 0xff0fffff,
1937                 .data   = &variant_arm_extended_fifo,
1938         },
1939         {
1940                 .id     = 0x02041180,
1941                 .mask   = 0xff0fffff,
1942                 .data   = &variant_arm_extended_fifo_hwfc,
1943         },
1944         {
1945                 .id     = 0x00041181,
1946                 .mask   = 0x000fffff,
1947                 .data   = &variant_arm,
1948         },
1949         /* ST Micro variants */
1950         {
1951                 .id     = 0x00180180,
1952                 .mask   = 0x00ffffff,
1953                 .data   = &variant_u300,
1954         },
1955         {
1956                 .id     = 0x10180180,
1957                 .mask   = 0xf0ffffff,
1958                 .data   = &variant_nomadik,
1959         },
1960         {
1961                 .id     = 0x00280180,
1962                 .mask   = 0x00ffffff,
1963                 .data   = &variant_nomadik,
1964         },
1965         {
1966                 .id     = 0x00480180,
1967                 .mask   = 0xf0ffffff,
1968                 .data   = &variant_ux500,
1969         },
1970         {
1971                 .id     = 0x10480180,
1972                 .mask   = 0xf0ffffff,
1973                 .data   = &variant_ux500v2,
1974         },
1975         {
1976                 .id     = 0x00880180,
1977                 .mask   = 0x00ffffff,
1978                 .data   = &variant_stm32,
1979         },
1980         /* Qualcomm variants */
1981         {
1982                 .id     = 0x00051180,
1983                 .mask   = 0x000fffff,
1984                 .data   = &variant_qcom,
1985         },
1986         { 0, 0 },
1987 };
1988
1989 MODULE_DEVICE_TABLE(amba, mmci_ids);
1990
1991 static struct amba_driver mmci_driver = {
1992         .drv            = {
1993                 .name   = DRIVER_NAME,
1994                 .pm     = &mmci_dev_pm_ops,
1995         },
1996         .probe          = mmci_probe,
1997         .remove         = mmci_remove,
1998         .id_table       = mmci_ids,
1999 };
2000
2001 module_amba_driver(mmci_driver);
2002
2003 module_param(fmax, uint, 0444);
2004
2005 MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver");
2006 MODULE_LICENSE("GPL");