1 // SPDX-License-Identifier: GPL-2.0+
3 * Amlogic Meson6/Meson8/Meson8b/Meson8m2 SDHC MMC host controller driver.
5 * Copyright (C) 2020 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
9 #include <linux/device.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/interrupt.h>
12 #include <linux/iopoll.h>
13 #include <linux/module.h>
15 #include <linux/platform_device.h>
16 #include <linux/property.h>
17 #include <linux/regmap.h>
18 #include <linux/regulator/consumer.h>
19 #include <linux/types.h>
21 #include <linux/mmc/host.h>
22 #include <linux/mmc/mmc.h>
23 #include <linux/mmc/sdio.h>
24 #include <linux/mmc/slot-gpio.h>
26 #include "meson-mx-sdhc.h"
28 #define MESON_SDHC_NUM_BULK_CLKS 4
29 #define MESON_SDHC_MAX_BLK_SIZE 512
30 #define MESON_SDHC_NUM_TUNING_TRIES 10
32 #define MESON_SDHC_WAIT_CMD_READY_SLEEP_US 1
33 #define MESON_SDHC_WAIT_CMD_READY_TIMEOUT_US 100000
34 #define MESON_SDHC_WAIT_BEFORE_SEND_SLEEP_US 1
35 #define MESON_SDHC_WAIT_BEFORE_SEND_TIMEOUT_US 200
37 struct meson_mx_sdhc_data {
38 void (*init_hw)(struct mmc_host *mmc);
39 void (*set_pdma)(struct mmc_host *mmc);
40 void (*wait_before_send)(struct mmc_host *mmc);
41 bool hardware_flush_all_cmds;
44 struct meson_mx_sdhc_host {
47 struct mmc_request *mrq;
48 struct mmc_command *cmd;
51 struct regmap *regmap;
55 struct clk_bulk_data bulk_clks[MESON_SDHC_NUM_BULK_CLKS];
56 bool bulk_clks_enabled;
58 const struct meson_mx_sdhc_data *platform;
61 static const struct regmap_config meson_mx_sdhc_regmap_config = {
65 .max_register = MESON_SDHC_CLK2,
68 static void meson_mx_sdhc_hw_reset(struct mmc_host *mmc)
70 struct meson_mx_sdhc_host *host = mmc_priv(mmc);
72 regmap_write(host->regmap, MESON_SDHC_SRST, MESON_SDHC_SRST_MAIN_CTRL |
73 MESON_SDHC_SRST_RXFIFO | MESON_SDHC_SRST_TXFIFO |
74 MESON_SDHC_SRST_DPHY_RX | MESON_SDHC_SRST_DPHY_TX |
75 MESON_SDHC_SRST_DMA_IF);
76 usleep_range(10, 100);
78 regmap_write(host->regmap, MESON_SDHC_SRST, 0);
79 usleep_range(10, 100);
82 static void meson_mx_sdhc_clear_fifo(struct mmc_host *mmc)
84 struct meson_mx_sdhc_host *host = mmc_priv(mmc);
87 regmap_read(host->regmap, MESON_SDHC_STAT, &stat);
88 if (!FIELD_GET(MESON_SDHC_STAT_RXFIFO_CNT, stat) &&
89 !FIELD_GET(MESON_SDHC_STAT_TXFIFO_CNT, stat))
92 regmap_write(host->regmap, MESON_SDHC_SRST, MESON_SDHC_SRST_RXFIFO |
93 MESON_SDHC_SRST_TXFIFO | MESON_SDHC_SRST_MAIN_CTRL);
96 regmap_read(host->regmap, MESON_SDHC_STAT, &stat);
97 if (FIELD_GET(MESON_SDHC_STAT_RXFIFO_CNT, stat) ||
98 FIELD_GET(MESON_SDHC_STAT_TXFIFO_CNT, stat))
99 dev_warn(mmc_dev(host->mmc),
100 "Failed to clear FIFOs, RX: %lu, TX: %lu\n",
101 FIELD_GET(MESON_SDHC_STAT_RXFIFO_CNT, stat),
102 FIELD_GET(MESON_SDHC_STAT_TXFIFO_CNT, stat));
105 static void meson_mx_sdhc_wait_cmd_ready(struct mmc_host *mmc)
107 struct meson_mx_sdhc_host *host = mmc_priv(mmc);
111 ret = regmap_read_poll_timeout(host->regmap, MESON_SDHC_STAT, stat,
112 !(stat & MESON_SDHC_STAT_CMD_BUSY),
113 MESON_SDHC_WAIT_CMD_READY_SLEEP_US,
114 MESON_SDHC_WAIT_CMD_READY_TIMEOUT_US);
116 dev_warn(mmc_dev(mmc),
117 "Failed to poll for CMD_BUSY while processing CMD%d\n",
119 meson_mx_sdhc_hw_reset(mmc);
122 ret = regmap_read_poll_timeout(host->regmap, MESON_SDHC_ESTA, esta,
123 !(esta & MESON_SDHC_ESTA_11_13),
124 MESON_SDHC_WAIT_CMD_READY_SLEEP_US,
125 MESON_SDHC_WAIT_CMD_READY_TIMEOUT_US);
127 dev_warn(mmc_dev(mmc),
128 "Failed to poll for ESTA[13:11] while processing CMD%d\n",
130 meson_mx_sdhc_hw_reset(mmc);
134 static void meson_mx_sdhc_start_cmd(struct mmc_host *mmc,
135 struct mmc_command *cmd)
137 struct meson_mx_sdhc_host *host = mmc_priv(mmc);
138 bool manual_stop = false;
144 ictl = MESON_SDHC_ICTL_DATA_TIMEOUT | MESON_SDHC_ICTL_DATA_ERR_CRC |
145 MESON_SDHC_ICTL_RXFIFO_FULL | MESON_SDHC_ICTL_TXFIFO_EMPTY |
146 MESON_SDHC_ICTL_RESP_TIMEOUT | MESON_SDHC_ICTL_RESP_ERR_CRC;
148 send = FIELD_PREP(MESON_SDHC_SEND_CMD_INDEX, cmd->opcode);
151 send |= MESON_SDHC_SEND_CMD_HAS_DATA;
152 send |= FIELD_PREP(MESON_SDHC_SEND_TOTAL_PACK,
153 cmd->data->blocks - 1);
155 if (cmd->data->blksz < MESON_SDHC_MAX_BLK_SIZE)
156 pack_len = cmd->data->blksz;
160 if (cmd->data->flags & MMC_DATA_WRITE)
161 send |= MESON_SDHC_SEND_DATA_DIR;
164 * If command with no data, just wait response done
165 * interrupt(int[0]), and if command with data transfer, just
166 * wait dma done interrupt(int[11]), don't need care about
169 if (host->platform->hardware_flush_all_cmds ||
170 cmd->data->flags & MMC_DATA_WRITE)
171 /* hardware flush: */
172 ictl |= MESON_SDHC_ICTL_DMA_DONE;
174 /* software flush: */
175 ictl |= MESON_SDHC_ICTL_DATA_XFER_OK;
178 * Mimic the logic from the vendor driver where (only)
179 * SD_IO_RW_EXTENDED commands with more than one block set the
180 * MESON_SDHC_MISC_MANUAL_STOP bit. This fixes the firmware
181 * download in the brcmfmac driver for a BCM43362/1 card.
182 * Without this sdio_memcpy_toio() (with a size of 219557
183 * bytes) times out if MESON_SDHC_MISC_MANUAL_STOP is not set.
185 manual_stop = cmd->data->blocks > 1 &&
186 cmd->opcode == SD_IO_RW_EXTENDED;
190 ictl |= MESON_SDHC_ICTL_RESP_OK;
193 regmap_update_bits(host->regmap, MESON_SDHC_MISC,
194 MESON_SDHC_MISC_MANUAL_STOP,
195 manual_stop ? MESON_SDHC_MISC_MANUAL_STOP : 0);
197 if (cmd->opcode == MMC_STOP_TRANSMISSION)
198 send |= MESON_SDHC_SEND_DATA_STOP;
200 if (cmd->flags & MMC_RSP_PRESENT)
201 send |= MESON_SDHC_SEND_CMD_HAS_RESP;
203 if (cmd->flags & MMC_RSP_136) {
204 send |= MESON_SDHC_SEND_RESP_LEN;
205 send |= MESON_SDHC_SEND_RESP_NO_CRC;
208 if (!(cmd->flags & MMC_RSP_CRC))
209 send |= MESON_SDHC_SEND_RESP_NO_CRC;
211 if (cmd->flags & MMC_RSP_BUSY)
212 send |= MESON_SDHC_SEND_R1B;
214 /* enable the new IRQs and mask all pending ones */
215 regmap_write(host->regmap, MESON_SDHC_ICTL, ictl);
216 regmap_write(host->regmap, MESON_SDHC_ISTA, MESON_SDHC_ISTA_ALL_IRQS);
218 regmap_write(host->regmap, MESON_SDHC_ARGU, cmd->arg);
220 regmap_update_bits(host->regmap, MESON_SDHC_CTRL,
221 MESON_SDHC_CTRL_PACK_LEN,
222 FIELD_PREP(MESON_SDHC_CTRL_PACK_LEN, pack_len));
225 regmap_write(host->regmap, MESON_SDHC_ADDR,
226 sg_dma_address(cmd->data->sg));
228 meson_mx_sdhc_wait_cmd_ready(mmc);
231 host->platform->set_pdma(mmc);
233 if (host->platform->wait_before_send)
234 host->platform->wait_before_send(mmc);
236 regmap_write(host->regmap, MESON_SDHC_SEND, send);
239 static void meson_mx_sdhc_disable_clks(struct mmc_host *mmc)
241 struct meson_mx_sdhc_host *host = mmc_priv(mmc);
243 if (!host->bulk_clks_enabled)
246 clk_bulk_disable_unprepare(MESON_SDHC_NUM_BULK_CLKS, host->bulk_clks);
248 host->bulk_clks_enabled = false;
251 static int meson_mx_sdhc_enable_clks(struct mmc_host *mmc)
253 struct meson_mx_sdhc_host *host = mmc_priv(mmc);
256 if (host->bulk_clks_enabled)
259 ret = clk_bulk_prepare_enable(MESON_SDHC_NUM_BULK_CLKS,
264 host->bulk_clks_enabled = true;
269 static int meson_mx_sdhc_set_clk(struct mmc_host *mmc, struct mmc_ios *ios)
271 struct meson_mx_sdhc_host *host = mmc_priv(mmc);
275 meson_mx_sdhc_disable_clks(mmc);
278 ret = clk_set_rate(host->sd_clk, ios->clock);
280 dev_warn(mmc_dev(mmc),
281 "Failed to set MMC clock to %uHz: %d\n",
282 ios->clock, host->error);
286 ret = meson_mx_sdhc_enable_clks(mmc);
290 mmc->actual_clock = clk_get_rate(host->sd_clk);
293 * according to Amlogic the following latching points are
294 * selected with empirical values, there is no (known) formula
295 * to calculate these.
297 if (mmc->actual_clock > 100000000) {
299 } else if (mmc->actual_clock > 45000000) {
300 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
304 } else if (mmc->actual_clock >= 25000000) {
306 } else if (mmc->actual_clock > 5000000) {
308 } else if (mmc->actual_clock > 1000000) {
314 regmap_update_bits(host->regmap, MESON_SDHC_CLK2,
315 MESON_SDHC_CLK2_RX_CLK_PHASE,
316 FIELD_PREP(MESON_SDHC_CLK2_RX_CLK_PHASE,
319 mmc->actual_clock = 0;
325 static void meson_mx_sdhc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
327 struct meson_mx_sdhc_host *host = mmc_priv(mmc);
328 unsigned short vdd = ios->vdd;
330 switch (ios->power_mode) {
336 if (!IS_ERR(mmc->supply.vmmc)) {
337 host->error = mmc_regulator_set_ocr(mmc,
350 host->error = meson_mx_sdhc_set_clk(mmc, ios);
354 switch (ios->bus_width) {
355 case MMC_BUS_WIDTH_1:
356 regmap_update_bits(host->regmap, MESON_SDHC_CTRL,
357 MESON_SDHC_CTRL_DAT_TYPE,
358 FIELD_PREP(MESON_SDHC_CTRL_DAT_TYPE, 0));
361 case MMC_BUS_WIDTH_4:
362 regmap_update_bits(host->regmap, MESON_SDHC_CTRL,
363 MESON_SDHC_CTRL_DAT_TYPE,
364 FIELD_PREP(MESON_SDHC_CTRL_DAT_TYPE, 1));
367 case MMC_BUS_WIDTH_8:
368 regmap_update_bits(host->regmap, MESON_SDHC_CTRL,
369 MESON_SDHC_CTRL_DAT_TYPE,
370 FIELD_PREP(MESON_SDHC_CTRL_DAT_TYPE, 2));
374 dev_err(mmc_dev(mmc), "unsupported bus width: %d\n",
376 host->error = -EINVAL;
381 static int meson_mx_sdhc_map_dma(struct mmc_host *mmc, struct mmc_request *mrq)
383 struct mmc_data *data = mrq->data;
389 dma_len = dma_map_sg(mmc_dev(mmc), data->sg, data->sg_len,
390 mmc_get_dma_dir(data));
392 dev_err(mmc_dev(mmc), "dma_map_sg failed\n");
399 static void meson_mx_sdhc_request(struct mmc_host *mmc, struct mmc_request *mrq)
401 struct meson_mx_sdhc_host *host = mmc_priv(mmc);
402 struct mmc_command *cmd = mrq->cmd;
405 host->error = meson_mx_sdhc_map_dma(mmc, mrq);
408 cmd->error = host->error;
409 mmc_request_done(mmc, mrq);
415 meson_mx_sdhc_start_cmd(mmc, mrq->cmd);
418 static int meson_mx_sdhc_card_busy(struct mmc_host *mmc)
420 struct meson_mx_sdhc_host *host = mmc_priv(mmc);
423 regmap_read(host->regmap, MESON_SDHC_STAT, &stat);
424 return FIELD_GET(MESON_SDHC_STAT_DAT3_0, stat) == 0;
427 static bool meson_mx_sdhc_tuning_point_matches(struct mmc_host *mmc,
430 unsigned int i, num_matches = 0;
433 for (i = 0; i < MESON_SDHC_NUM_TUNING_TRIES; i++) {
434 ret = mmc_send_tuning(mmc, opcode, NULL);
439 return num_matches == MESON_SDHC_NUM_TUNING_TRIES;
442 static int meson_mx_sdhc_execute_tuning(struct mmc_host *mmc, u32 opcode)
444 struct meson_mx_sdhc_host *host = mmc_priv(mmc);
445 int div, start, len, best_start, best_len;
446 int curr_phase, old_phase, new_phase;
453 regmap_read(host->regmap, MESON_SDHC_CLK2, &val);
454 old_phase = FIELD_GET(MESON_SDHC_CLK2_RX_CLK_PHASE, val);
456 regmap_read(host->regmap, MESON_SDHC_CLKC, &val);
457 div = FIELD_GET(MESON_SDHC_CLKC_CLK_DIV, val);
459 for (curr_phase = 0; curr_phase <= div; curr_phase++) {
460 regmap_update_bits(host->regmap, MESON_SDHC_CLK2,
461 MESON_SDHC_CLK2_RX_CLK_PHASE,
462 FIELD_PREP(MESON_SDHC_CLK2_RX_CLK_PHASE,
465 if (meson_mx_sdhc_tuning_point_matches(mmc, opcode)) {
469 dev_dbg(mmc_dev(mmc),
470 "New RX phase window starts at %u\n",
476 if (len > best_len) {
480 dev_dbg(mmc_dev(mmc),
481 "New best RX phase window: %u - %u\n",
482 best_start, best_start + best_len);
485 /* reset the current window */
491 /* the last window is the best (or possibly only) window */
492 new_phase = start + (len / 2);
494 /* there was a better window than the last */
495 new_phase = best_start + (best_len / 2);
497 /* no window was found at all, reset to the original phase */
498 new_phase = old_phase;
500 regmap_update_bits(host->regmap, MESON_SDHC_CLK2,
501 MESON_SDHC_CLK2_RX_CLK_PHASE,
502 FIELD_PREP(MESON_SDHC_CLK2_RX_CLK_PHASE,
505 if (!len && !best_len)
508 dev_dbg(mmc_dev(mmc), "Tuned RX clock phase to %u\n", new_phase);
513 static const struct mmc_host_ops meson_mx_sdhc_ops = {
514 .hw_reset = meson_mx_sdhc_hw_reset,
515 .request = meson_mx_sdhc_request,
516 .set_ios = meson_mx_sdhc_set_ios,
517 .card_busy = meson_mx_sdhc_card_busy,
518 .execute_tuning = meson_mx_sdhc_execute_tuning,
519 .get_cd = mmc_gpio_get_cd,
520 .get_ro = mmc_gpio_get_ro,
523 static void meson_mx_sdhc_request_done(struct meson_mx_sdhc_host *host)
525 struct mmc_request *mrq = host->mrq;
526 struct mmc_host *mmc = host->mmc;
528 /* disable interrupts and mask all pending ones */
529 regmap_update_bits(host->regmap, MESON_SDHC_ICTL,
530 MESON_SDHC_ICTL_ALL_IRQS, 0);
531 regmap_update_bits(host->regmap, MESON_SDHC_ISTA,
532 MESON_SDHC_ISTA_ALL_IRQS, MESON_SDHC_ISTA_ALL_IRQS);
537 mmc_request_done(mmc, mrq);
540 static u32 meson_mx_sdhc_read_response(struct meson_mx_sdhc_host *host, u8 idx)
544 regmap_update_bits(host->regmap, MESON_SDHC_PDMA,
545 MESON_SDHC_PDMA_DMA_MODE, 0);
547 regmap_update_bits(host->regmap, MESON_SDHC_PDMA,
548 MESON_SDHC_PDMA_PIO_RDRESP,
549 FIELD_PREP(MESON_SDHC_PDMA_PIO_RDRESP, idx));
551 regmap_read(host->regmap, MESON_SDHC_ARGU, &val);
556 static irqreturn_t meson_mx_sdhc_irq(int irq, void *data)
558 struct meson_mx_sdhc_host *host = data;
559 struct mmc_command *cmd = host->cmd;
562 regmap_read(host->regmap, MESON_SDHC_ICTL, &ictl);
563 regmap_read(host->regmap, MESON_SDHC_ISTA, &ista);
568 if (ista & MESON_SDHC_ISTA_RXFIFO_FULL ||
569 ista & MESON_SDHC_ISTA_TXFIFO_EMPTY)
571 else if (ista & MESON_SDHC_ISTA_RESP_ERR_CRC)
572 cmd->error = -EILSEQ;
573 else if (ista & MESON_SDHC_ISTA_RESP_TIMEOUT)
574 cmd->error = -ETIMEDOUT;
577 if (ista & MESON_SDHC_ISTA_DATA_ERR_CRC)
578 cmd->data->error = -EILSEQ;
579 else if (ista & MESON_SDHC_ISTA_DATA_TIMEOUT)
580 cmd->data->error = -ETIMEDOUT;
583 if (cmd->error || (cmd->data && cmd->data->error))
584 dev_dbg(mmc_dev(host->mmc), "CMD%d error, ISTA: 0x%08x\n",
587 return IRQ_WAKE_THREAD;
590 static irqreturn_t meson_mx_sdhc_irq_thread(int irq, void *irq_data)
592 struct meson_mx_sdhc_host *host = irq_data;
593 struct mmc_command *cmd;
600 if (cmd->data && !cmd->data->error) {
601 if (!host->platform->hardware_flush_all_cmds &&
602 cmd->data->flags & MMC_DATA_READ) {
603 meson_mx_sdhc_wait_cmd_ready(host->mmc);
606 * If MESON_SDHC_PDMA_RXFIFO_MANUAL_FLUSH was
607 * previously 0x1 then it has to be set to 0x3. If it
608 * was 0x0 before then it has to be set to 0x2. Without
609 * this reading SD cards sometimes transfers garbage,
610 * which results in cards not being detected due to:
611 * unrecognised SCR structure version <random number>
613 val = FIELD_PREP(MESON_SDHC_PDMA_RXFIFO_MANUAL_FLUSH,
615 regmap_update_bits(host->regmap, MESON_SDHC_PDMA, val,
619 dma_unmap_sg(mmc_dev(host->mmc), cmd->data->sg,
620 cmd->data->sg_len, mmc_get_dma_dir(cmd->data));
622 cmd->data->bytes_xfered = cmd->data->blksz * cmd->data->blocks;
625 meson_mx_sdhc_wait_cmd_ready(host->mmc);
627 if (cmd->flags & MMC_RSP_136) {
628 cmd->resp[0] = meson_mx_sdhc_read_response(host, 4);
629 cmd->resp[1] = meson_mx_sdhc_read_response(host, 3);
630 cmd->resp[2] = meson_mx_sdhc_read_response(host, 2);
631 cmd->resp[3] = meson_mx_sdhc_read_response(host, 1);
633 cmd->resp[0] = meson_mx_sdhc_read_response(host, 0);
636 if (cmd->error == -EIO || cmd->error == -ETIMEDOUT)
637 meson_mx_sdhc_hw_reset(host->mmc);
640 * Clear the FIFOs after completing data transfers to prevent
641 * corrupting data on write access. It's not clear why this is
642 * needed (for reads and writes), but it mimics what the BSP
645 meson_mx_sdhc_clear_fifo(host->mmc);
647 meson_mx_sdhc_request_done(host);
652 static void meson_mx_sdhc_init_hw_meson8(struct mmc_host *mmc)
654 struct meson_mx_sdhc_host *host = mmc_priv(mmc);
656 regmap_write(host->regmap, MESON_SDHC_MISC,
657 FIELD_PREP(MESON_SDHC_MISC_TXSTART_THRES, 7) |
658 FIELD_PREP(MESON_SDHC_MISC_WCRC_ERR_PATT, 5) |
659 FIELD_PREP(MESON_SDHC_MISC_WCRC_OK_PATT, 2));
661 regmap_write(host->regmap, MESON_SDHC_ENHC,
662 FIELD_PREP(MESON_SDHC_ENHC_RXFIFO_TH, 63) |
663 MESON_SDHC_ENHC_MESON6_DMA_WR_RESP |
664 FIELD_PREP(MESON_SDHC_ENHC_MESON6_RX_TIMEOUT, 255) |
665 FIELD_PREP(MESON_SDHC_ENHC_SDIO_IRQ_PERIOD, 12));
668 static void meson_mx_sdhc_set_pdma_meson8(struct mmc_host *mmc)
670 struct meson_mx_sdhc_host *host = mmc_priv(mmc);
672 if (host->cmd->data->flags & MMC_DATA_WRITE)
673 regmap_update_bits(host->regmap, MESON_SDHC_PDMA,
674 MESON_SDHC_PDMA_DMA_MODE |
675 MESON_SDHC_PDMA_RD_BURST |
676 MESON_SDHC_PDMA_TXFIFO_FILL,
677 MESON_SDHC_PDMA_DMA_MODE |
678 FIELD_PREP(MESON_SDHC_PDMA_RD_BURST, 31) |
679 MESON_SDHC_PDMA_TXFIFO_FILL);
681 regmap_update_bits(host->regmap, MESON_SDHC_PDMA,
682 MESON_SDHC_PDMA_DMA_MODE |
683 MESON_SDHC_PDMA_RXFIFO_MANUAL_FLUSH,
684 MESON_SDHC_PDMA_DMA_MODE |
685 FIELD_PREP(MESON_SDHC_PDMA_RXFIFO_MANUAL_FLUSH,
688 if (host->cmd->data->flags & MMC_DATA_WRITE)
689 regmap_update_bits(host->regmap, MESON_SDHC_PDMA,
690 MESON_SDHC_PDMA_RD_BURST,
691 FIELD_PREP(MESON_SDHC_PDMA_RD_BURST, 15));
694 static void meson_mx_sdhc_wait_before_send_meson8(struct mmc_host *mmc)
696 struct meson_mx_sdhc_host *host = mmc_priv(mmc);
700 ret = regmap_read_poll_timeout(host->regmap, MESON_SDHC_ESTA, val,
702 MESON_SDHC_WAIT_BEFORE_SEND_SLEEP_US,
703 MESON_SDHC_WAIT_BEFORE_SEND_TIMEOUT_US);
705 dev_warn(mmc_dev(mmc),
706 "Failed to wait for ESTA to clear: 0x%08x\n", val);
708 if (host->cmd->data && host->cmd->data->flags & MMC_DATA_WRITE) {
709 ret = regmap_read_poll_timeout(host->regmap, MESON_SDHC_STAT,
710 val, val & MESON_SDHC_STAT_TXFIFO_CNT,
711 MESON_SDHC_WAIT_BEFORE_SEND_SLEEP_US,
712 MESON_SDHC_WAIT_BEFORE_SEND_TIMEOUT_US);
714 dev_warn(mmc_dev(mmc),
715 "Failed to wait for TX FIFO to fill\n");
719 static void meson_mx_sdhc_init_hw_meson8m2(struct mmc_host *mmc)
721 struct meson_mx_sdhc_host *host = mmc_priv(mmc);
723 regmap_write(host->regmap, MESON_SDHC_MISC,
724 FIELD_PREP(MESON_SDHC_MISC_TXSTART_THRES, 6) |
725 FIELD_PREP(MESON_SDHC_MISC_WCRC_ERR_PATT, 5) |
726 FIELD_PREP(MESON_SDHC_MISC_WCRC_OK_PATT, 2));
728 regmap_write(host->regmap, MESON_SDHC_ENHC,
729 FIELD_PREP(MESON_SDHC_ENHC_RXFIFO_TH, 64) |
730 FIELD_PREP(MESON_SDHC_ENHC_MESON8M2_DEBUG, 1) |
731 MESON_SDHC_ENHC_MESON8M2_WRRSP_MODE |
732 FIELD_PREP(MESON_SDHC_ENHC_SDIO_IRQ_PERIOD, 12));
735 static void meson_mx_sdhc_set_pdma_meson8m2(struct mmc_host *mmc)
737 struct meson_mx_sdhc_host *host = mmc_priv(mmc);
739 regmap_update_bits(host->regmap, MESON_SDHC_PDMA,
740 MESON_SDHC_PDMA_DMA_MODE, MESON_SDHC_PDMA_DMA_MODE);
743 static void meson_mx_sdhc_init_hw(struct mmc_host *mmc)
745 struct meson_mx_sdhc_host *host = mmc_priv(mmc);
747 meson_mx_sdhc_hw_reset(mmc);
749 regmap_write(host->regmap, MESON_SDHC_CTRL,
750 FIELD_PREP(MESON_SDHC_CTRL_RX_PERIOD, 0xf) |
751 FIELD_PREP(MESON_SDHC_CTRL_RX_TIMEOUT, 0x7f) |
752 FIELD_PREP(MESON_SDHC_CTRL_RX_ENDIAN, 0x7) |
753 FIELD_PREP(MESON_SDHC_CTRL_TX_ENDIAN, 0x7));
756 * start with a valid divider and enable the memory (un-setting
757 * MESON_SDHC_CLKC_MEM_PWR_OFF).
759 regmap_write(host->regmap, MESON_SDHC_CLKC, MESON_SDHC_CLKC_CLK_DIV);
761 regmap_write(host->regmap, MESON_SDHC_CLK2,
762 FIELD_PREP(MESON_SDHC_CLK2_SD_CLK_PHASE, 1));
764 regmap_write(host->regmap, MESON_SDHC_PDMA,
765 MESON_SDHC_PDMA_DMA_URGENT |
766 FIELD_PREP(MESON_SDHC_PDMA_WR_BURST, 7) |
767 FIELD_PREP(MESON_SDHC_PDMA_TXFIFO_TH, 49) |
768 FIELD_PREP(MESON_SDHC_PDMA_RD_BURST, 15) |
769 FIELD_PREP(MESON_SDHC_PDMA_RXFIFO_TH, 7));
771 /* some initialization bits depend on the SoC: */
772 host->platform->init_hw(mmc);
774 /* disable and mask all interrupts: */
775 regmap_write(host->regmap, MESON_SDHC_ICTL, 0);
776 regmap_write(host->regmap, MESON_SDHC_ISTA, MESON_SDHC_ISTA_ALL_IRQS);
779 static int meson_mx_sdhc_probe(struct platform_device *pdev)
781 struct device *dev = &pdev->dev;
782 struct meson_mx_sdhc_host *host;
783 struct mmc_host *mmc;
787 mmc = mmc_alloc_host(sizeof(*host), dev);
791 ret = devm_add_action_or_reset(dev, (void(*)(void *))mmc_free_host,
794 dev_err(dev, "Failed to register mmc_free_host action\n");
798 host = mmc_priv(mmc);
801 platform_set_drvdata(pdev, host);
803 host->platform = device_get_match_data(dev);
807 base = devm_platform_ioremap_resource(pdev, 0);
809 return PTR_ERR(base);
811 host->regmap = devm_regmap_init_mmio(dev, base,
812 &meson_mx_sdhc_regmap_config);
813 if (IS_ERR(host->regmap))
814 return PTR_ERR(host->regmap);
816 host->pclk = devm_clk_get(dev, "pclk");
817 if (IS_ERR(host->pclk))
818 return PTR_ERR(host->pclk);
820 /* accessing any register requires the module clock to be enabled: */
821 ret = clk_prepare_enable(host->pclk);
823 dev_err(dev, "Failed to enable 'pclk' clock\n");
827 meson_mx_sdhc_init_hw(mmc);
829 ret = meson_mx_sdhc_register_clkc(dev, base, host->bulk_clks);
831 goto err_disable_pclk;
833 host->sd_clk = host->bulk_clks[1].clk;
835 /* Get regulators and the supported OCR mask */
836 ret = mmc_regulator_get_supply(mmc);
838 goto err_disable_pclk;
840 mmc->max_req_size = SZ_128K;
841 mmc->max_seg_size = mmc->max_req_size;
842 mmc->max_blk_count = FIELD_GET(MESON_SDHC_SEND_TOTAL_PACK, ~0);
843 mmc->max_blk_size = MESON_SDHC_MAX_BLK_SIZE;
844 mmc->max_busy_timeout = 30 * MSEC_PER_SEC;
845 mmc->f_min = clk_round_rate(host->sd_clk, 1);
846 mmc->f_max = clk_round_rate(host->sd_clk, ULONG_MAX);
847 mmc->max_current_180 = 300;
848 mmc->max_current_330 = 300;
849 mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_HW_RESET;
850 mmc->ops = &meson_mx_sdhc_ops;
852 ret = mmc_of_parse(mmc);
854 goto err_disable_pclk;
856 irq = platform_get_irq(pdev, 0);
859 goto err_disable_pclk;
862 ret = devm_request_threaded_irq(dev, irq, meson_mx_sdhc_irq,
863 meson_mx_sdhc_irq_thread, IRQF_ONESHOT,
866 goto err_disable_pclk;
868 ret = mmc_add_host(mmc);
870 goto err_disable_pclk;
875 clk_disable_unprepare(host->pclk);
879 static int meson_mx_sdhc_remove(struct platform_device *pdev)
881 struct meson_mx_sdhc_host *host = platform_get_drvdata(pdev);
883 mmc_remove_host(host->mmc);
885 meson_mx_sdhc_disable_clks(host->mmc);
887 clk_disable_unprepare(host->pclk);
892 static const struct meson_mx_sdhc_data meson_mx_sdhc_data_meson8 = {
893 .init_hw = meson_mx_sdhc_init_hw_meson8,
894 .set_pdma = meson_mx_sdhc_set_pdma_meson8,
895 .wait_before_send = meson_mx_sdhc_wait_before_send_meson8,
896 .hardware_flush_all_cmds = false,
899 static const struct meson_mx_sdhc_data meson_mx_sdhc_data_meson8m2 = {
900 .init_hw = meson_mx_sdhc_init_hw_meson8m2,
901 .set_pdma = meson_mx_sdhc_set_pdma_meson8m2,
902 .hardware_flush_all_cmds = true,
905 static const struct of_device_id meson_mx_sdhc_of_match[] = {
907 .compatible = "amlogic,meson8-sdhc",
908 .data = &meson_mx_sdhc_data_meson8
911 .compatible = "amlogic,meson8b-sdhc",
912 .data = &meson_mx_sdhc_data_meson8
915 .compatible = "amlogic,meson8m2-sdhc",
916 .data = &meson_mx_sdhc_data_meson8m2
920 MODULE_DEVICE_TABLE(of, meson_mx_sdhc_of_match);
922 static struct platform_driver meson_mx_sdhc_driver = {
923 .probe = meson_mx_sdhc_probe,
924 .remove = meson_mx_sdhc_remove,
926 .name = "meson-mx-sdhc",
927 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
928 .of_match_table = of_match_ptr(meson_mx_sdhc_of_match),
932 module_platform_driver(meson_mx_sdhc_driver);
934 MODULE_DESCRIPTION("Meson6, Meson8, Meson8b and Meson8m2 SDHC Host Driver");
935 MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
936 MODULE_LICENSE("GPL v2");