2 * Amlogic SD/eMMC driver for the GX/S905 family SoCs
4 * Copyright (c) 2016 BayLibre, SAS.
5 * Author: Kevin Hilman <khilman@baylibre.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 * The full GNU General Public License is included in this distribution
19 * in the file called COPYING.
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/init.h>
24 #include <linux/delay.h>
25 #include <linux/device.h>
26 #include <linux/of_device.h>
27 #include <linux/platform_device.h>
28 #include <linux/ioport.h>
29 #include <linux/spinlock.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/mmc/host.h>
32 #include <linux/mmc/mmc.h>
33 #include <linux/mmc/sdio.h>
34 #include <linux/mmc/slot-gpio.h>
36 #include <linux/clk.h>
37 #include <linux/clk-provider.h>
38 #include <linux/regulator/consumer.h>
39 #include <linux/interrupt.h>
40 #include <linux/bitfield.h>
42 #define DRIVER_NAME "meson-gx-mmc"
44 #define SD_EMMC_CLOCK 0x0
45 #define CLK_DIV_MASK GENMASK(5, 0)
46 #define CLK_SRC_MASK GENMASK(7, 6)
47 #define CLK_CORE_PHASE_MASK GENMASK(9, 8)
48 #define CLK_TX_PHASE_MASK GENMASK(11, 10)
49 #define CLK_RX_PHASE_MASK GENMASK(13, 12)
50 #define CLK_TX_DELAY_MASK GENMASK(19, 16)
51 #define CLK_RX_DELAY_MASK GENMASK(23, 20)
52 #define CLK_DELAY_STEP_PS 200
53 #define CLK_PHASE_STEP 30
54 #define CLK_PHASE_POINT_NUM (360 / CLK_PHASE_STEP)
55 #define CLK_ALWAYS_ON BIT(24)
57 #define SD_EMMC_DELAY 0x4
58 #define SD_EMMC_ADJUST 0x8
59 #define SD_EMMC_CALOUT 0x10
60 #define SD_EMMC_START 0x40
61 #define START_DESC_INIT BIT(0)
62 #define START_DESC_BUSY BIT(1)
63 #define START_DESC_ADDR_MASK GENMASK(31, 2)
65 #define SD_EMMC_CFG 0x44
66 #define CFG_BUS_WIDTH_MASK GENMASK(1, 0)
67 #define CFG_BUS_WIDTH_1 0x0
68 #define CFG_BUS_WIDTH_4 0x1
69 #define CFG_BUS_WIDTH_8 0x2
70 #define CFG_DDR BIT(2)
71 #define CFG_BLK_LEN_MASK GENMASK(7, 4)
72 #define CFG_RESP_TIMEOUT_MASK GENMASK(11, 8)
73 #define CFG_RC_CC_MASK GENMASK(15, 12)
74 #define CFG_STOP_CLOCK BIT(22)
75 #define CFG_CLK_ALWAYS_ON BIT(18)
76 #define CFG_CHK_DS BIT(20)
77 #define CFG_AUTO_CLK BIT(23)
78 #define CFG_ERR_ABORT BIT(27)
80 #define SD_EMMC_STATUS 0x48
81 #define STATUS_BUSY BIT(31)
82 #define STATUS_DESC_BUSY BIT(30)
83 #define STATUS_DATI GENMASK(23, 16)
85 #define SD_EMMC_IRQ_EN 0x4c
86 #define IRQ_RXD_ERR_MASK GENMASK(7, 0)
87 #define IRQ_TXD_ERR BIT(8)
88 #define IRQ_DESC_ERR BIT(9)
89 #define IRQ_RESP_ERR BIT(10)
91 (IRQ_RXD_ERR_MASK | IRQ_TXD_ERR | IRQ_DESC_ERR | IRQ_RESP_ERR)
92 #define IRQ_RESP_TIMEOUT BIT(11)
93 #define IRQ_DESC_TIMEOUT BIT(12)
94 #define IRQ_TIMEOUTS \
95 (IRQ_RESP_TIMEOUT | IRQ_DESC_TIMEOUT)
96 #define IRQ_END_OF_CHAIN BIT(13)
97 #define IRQ_RESP_STATUS BIT(14)
98 #define IRQ_SDIO BIT(15)
100 (IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN | IRQ_RESP_STATUS |\
103 #define SD_EMMC_CMD_CFG 0x50
104 #define SD_EMMC_CMD_ARG 0x54
105 #define SD_EMMC_CMD_DAT 0x58
106 #define SD_EMMC_CMD_RSP 0x5c
107 #define SD_EMMC_CMD_RSP1 0x60
108 #define SD_EMMC_CMD_RSP2 0x64
109 #define SD_EMMC_CMD_RSP3 0x68
111 #define SD_EMMC_RXD 0x94
112 #define SD_EMMC_TXD 0x94
113 #define SD_EMMC_LAST_REG SD_EMMC_TXD
115 #define SD_EMMC_CFG_BLK_SIZE 512 /* internal buffer max: 512 bytes */
116 #define SD_EMMC_CFG_RESP_TIMEOUT 256 /* in clock cycles */
117 #define SD_EMMC_CMD_TIMEOUT 1024 /* in ms */
118 #define SD_EMMC_CMD_TIMEOUT_DATA 4096 /* in ms */
119 #define SD_EMMC_CFG_CMD_GAP 16 /* in clock cycles */
120 #define SD_EMMC_DESC_BUF_LEN PAGE_SIZE
122 #define SD_EMMC_PRE_REQ_DONE BIT(0)
123 #define SD_EMMC_DESC_CHAIN_MODE BIT(1)
125 #define MUX_CLK_NUM_PARENTS 2
127 struct sd_emmc_desc {
136 struct mmc_host *mmc;
137 struct mmc_command *cmd;
141 struct clk *core_clk;
145 unsigned long req_rate;
147 struct pinctrl *pinctrl;
148 struct pinctrl_state *pins_default;
149 struct pinctrl_state *pins_clk_gate;
151 unsigned int bounce_buf_size;
153 dma_addr_t bounce_dma_addr;
154 struct sd_emmc_desc *descs;
155 dma_addr_t descs_dma_addr;
160 #define CMD_CFG_LENGTH_MASK GENMASK(8, 0)
161 #define CMD_CFG_BLOCK_MODE BIT(9)
162 #define CMD_CFG_R1B BIT(10)
163 #define CMD_CFG_END_OF_CHAIN BIT(11)
164 #define CMD_CFG_TIMEOUT_MASK GENMASK(15, 12)
165 #define CMD_CFG_NO_RESP BIT(16)
166 #define CMD_CFG_NO_CMD BIT(17)
167 #define CMD_CFG_DATA_IO BIT(18)
168 #define CMD_CFG_DATA_WR BIT(19)
169 #define CMD_CFG_RESP_NOCRC BIT(20)
170 #define CMD_CFG_RESP_128 BIT(21)
171 #define CMD_CFG_RESP_NUM BIT(22)
172 #define CMD_CFG_DATA_NUM BIT(23)
173 #define CMD_CFG_CMD_INDEX_MASK GENMASK(29, 24)
174 #define CMD_CFG_ERROR BIT(30)
175 #define CMD_CFG_OWNER BIT(31)
177 #define CMD_DATA_MASK GENMASK(31, 2)
178 #define CMD_DATA_BIG_ENDIAN BIT(1)
179 #define CMD_DATA_SRAM BIT(0)
180 #define CMD_RESP_MASK GENMASK(31, 1)
181 #define CMD_RESP_SRAM BIT(0)
183 struct meson_mmc_phase {
186 unsigned long phase_mask;
187 unsigned long delay_mask;
188 unsigned int delay_step_ps;
191 #define to_meson_mmc_phase(_hw) container_of(_hw, struct meson_mmc_phase, hw)
193 static int meson_mmc_clk_get_phase(struct clk_hw *hw)
195 struct meson_mmc_phase *mmc = to_meson_mmc_phase(hw);
196 unsigned int phase_num = 1 << hweight_long(mmc->phase_mask);
197 unsigned long period_ps, p, d;
201 val = readl(mmc->reg);
202 p = (val & mmc->phase_mask) >> __ffs(mmc->phase_mask);
203 degrees = p * 360 / phase_num;
205 if (mmc->delay_mask) {
206 period_ps = DIV_ROUND_UP((unsigned long)NSEC_PER_SEC * 1000,
207 clk_get_rate(hw->clk));
208 d = (val & mmc->delay_mask) >> __ffs(mmc->delay_mask);
209 degrees += d * mmc->delay_step_ps * 360 / period_ps;
216 static void meson_mmc_apply_phase_delay(struct meson_mmc_phase *mmc,
222 val = readl(mmc->reg);
223 val &= ~mmc->phase_mask;
224 val |= phase << __ffs(mmc->phase_mask);
226 if (mmc->delay_mask) {
227 val &= ~mmc->delay_mask;
228 val |= delay << __ffs(mmc->delay_mask);
231 writel(val, mmc->reg);
234 static int meson_mmc_clk_set_phase(struct clk_hw *hw, int degrees)
236 struct meson_mmc_phase *mmc = to_meson_mmc_phase(hw);
237 unsigned int phase_num = 1 << hweight_long(mmc->phase_mask);
238 unsigned long period_ps, d = 0, r;
243 if (!mmc->delay_mask) {
244 p = DIV_ROUND_CLOSEST_ULL(p, 360 / phase_num);
246 period_ps = DIV_ROUND_UP((unsigned long)NSEC_PER_SEC * 1000,
247 clk_get_rate(hw->clk));
249 /* First compute the phase index (p), the remainder (r) is the
250 * part we'll try to acheive using the delays (d).
252 r = do_div(p, 360 / phase_num);
253 d = DIV_ROUND_CLOSEST(r * period_ps,
254 360 * mmc->delay_step_ps);
255 d = min(d, mmc->delay_mask >> __ffs(mmc->delay_mask));
258 meson_mmc_apply_phase_delay(mmc, p, d);
262 static const struct clk_ops meson_mmc_clk_phase_ops = {
263 .get_phase = meson_mmc_clk_get_phase,
264 .set_phase = meson_mmc_clk_set_phase,
267 static unsigned int meson_mmc_get_timeout_msecs(struct mmc_data *data)
269 unsigned int timeout = data->timeout_ns / NSEC_PER_MSEC;
272 return SD_EMMC_CMD_TIMEOUT_DATA;
274 timeout = roundup_pow_of_two(timeout);
276 return min(timeout, 32768U); /* max. 2^15 ms */
279 static struct mmc_command *meson_mmc_get_next_command(struct mmc_command *cmd)
281 if (cmd->opcode == MMC_SET_BLOCK_COUNT && !cmd->error)
282 return cmd->mrq->cmd;
283 else if (mmc_op_multi(cmd->opcode) &&
284 (!cmd->mrq->sbc || cmd->error || cmd->data->error))
285 return cmd->mrq->stop;
290 static void meson_mmc_get_transfer_mode(struct mmc_host *mmc,
291 struct mmc_request *mrq)
293 struct mmc_data *data = mrq->data;
294 struct scatterlist *sg;
296 bool use_desc_chain_mode = true;
299 * Broken SDIO with AP6255-based WiFi on Khadas VIM Pro has been
300 * reported. For some strange reason this occurs in descriptor
301 * chain mode only. So let's fall back to bounce buffer mode
302 * for command SD_IO_RW_EXTENDED.
304 if (mrq->cmd->opcode == SD_IO_RW_EXTENDED)
307 for_each_sg(data->sg, sg, data->sg_len, i)
308 /* check for 8 byte alignment */
309 if (sg->offset & 7) {
310 WARN_ONCE(1, "unaligned scatterlist buffer\n");
311 use_desc_chain_mode = false;
315 if (use_desc_chain_mode)
316 data->host_cookie |= SD_EMMC_DESC_CHAIN_MODE;
319 static inline bool meson_mmc_desc_chain_mode(const struct mmc_data *data)
321 return data->host_cookie & SD_EMMC_DESC_CHAIN_MODE;
324 static inline bool meson_mmc_bounce_buf_read(const struct mmc_data *data)
326 return data && data->flags & MMC_DATA_READ &&
327 !meson_mmc_desc_chain_mode(data);
330 static void meson_mmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
332 struct mmc_data *data = mrq->data;
337 meson_mmc_get_transfer_mode(mmc, mrq);
338 data->host_cookie |= SD_EMMC_PRE_REQ_DONE;
340 if (!meson_mmc_desc_chain_mode(data))
343 data->sg_count = dma_map_sg(mmc_dev(mmc), data->sg, data->sg_len,
344 mmc_get_dma_dir(data));
346 dev_err(mmc_dev(mmc), "dma_map_sg failed");
349 static void meson_mmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
352 struct mmc_data *data = mrq->data;
354 if (data && meson_mmc_desc_chain_mode(data) && data->sg_count)
355 dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len,
356 mmc_get_dma_dir(data));
359 static bool meson_mmc_timing_is_ddr(struct mmc_ios *ios)
361 if (ios->timing == MMC_TIMING_MMC_DDR52 ||
362 ios->timing == MMC_TIMING_UHS_DDR50 ||
363 ios->timing == MMC_TIMING_MMC_HS400)
370 * Gating the clock on this controller is tricky. It seems the mmc clock
371 * is also used by the controller. It may crash during some operation if the
372 * clock is stopped. The safest thing to do, whenever possible, is to keep
373 * clock running at stop it at the pad using the pinmux.
375 static void meson_mmc_clk_gate(struct meson_host *host)
379 if (host->pins_clk_gate) {
380 pinctrl_select_state(host->pinctrl, host->pins_clk_gate);
383 * If the pinmux is not provided - default to the classic and
386 cfg = readl(host->regs + SD_EMMC_CFG);
387 cfg |= CFG_STOP_CLOCK;
388 writel(cfg, host->regs + SD_EMMC_CFG);
392 static void meson_mmc_clk_ungate(struct meson_host *host)
396 if (host->pins_clk_gate)
397 pinctrl_select_state(host->pinctrl, host->pins_default);
399 /* Make sure the clock is not stopped in the controller */
400 cfg = readl(host->regs + SD_EMMC_CFG);
401 cfg &= ~CFG_STOP_CLOCK;
402 writel(cfg, host->regs + SD_EMMC_CFG);
405 static int meson_mmc_clk_set(struct meson_host *host, struct mmc_ios *ios)
407 struct mmc_host *mmc = host->mmc;
408 unsigned long rate = ios->clock;
412 /* DDR modes require higher module clock */
413 if (meson_mmc_timing_is_ddr(ios))
416 /* Same request - bail-out */
417 if (host->req_rate == rate)
421 meson_mmc_clk_gate(host);
425 mmc->actual_clock = 0;
426 /* return with clock being stopped */
430 /* Stop the clock during rate change to avoid glitches */
431 cfg = readl(host->regs + SD_EMMC_CFG);
432 cfg |= CFG_STOP_CLOCK;
433 writel(cfg, host->regs + SD_EMMC_CFG);
435 ret = clk_set_rate(host->mmc_clk, rate);
437 dev_err(host->dev, "Unable to set cfg_div_clk to %lu. ret=%d\n",
442 host->req_rate = rate;
443 mmc->actual_clock = clk_get_rate(host->mmc_clk);
445 /* We should report the real output frequency of the controller */
446 if (meson_mmc_timing_is_ddr(ios))
447 mmc->actual_clock >>= 1;
449 dev_dbg(host->dev, "clk rate: %u Hz\n", mmc->actual_clock);
450 if (ios->clock != mmc->actual_clock)
451 dev_dbg(host->dev, "requested rate was %u\n", ios->clock);
453 /* (re)start clock */
454 meson_mmc_clk_ungate(host);
460 * The SD/eMMC IP block has an internal mux and divider used for
461 * generating the MMC clock. Use the clock framework to create and
462 * manage these clocks.
464 static int meson_mmc_clk_init(struct meson_host *host)
466 struct clk_init_data init;
468 struct clk_divider *div;
469 struct meson_mmc_phase *core, *tx, *rx;
473 const char *mux_parent_names[MUX_CLK_NUM_PARENTS];
474 const char *clk_parent[1];
477 /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */
479 clk_reg |= CLK_ALWAYS_ON;
480 clk_reg |= CLK_DIV_MASK;
481 writel(clk_reg, host->regs + SD_EMMC_CLOCK);
483 /* get the mux parents */
484 for (i = 0; i < MUX_CLK_NUM_PARENTS; i++) {
488 snprintf(name, sizeof(name), "clkin%d", i);
489 clk = devm_clk_get(host->dev, name);
491 if (clk != ERR_PTR(-EPROBE_DEFER))
492 dev_err(host->dev, "Missing clock %s\n", name);
496 mux_parent_names[i] = __clk_get_name(clk);
500 mux = devm_kzalloc(host->dev, sizeof(*mux), GFP_KERNEL);
504 snprintf(clk_name, sizeof(clk_name), "%s#mux", dev_name(host->dev));
505 init.name = clk_name;
506 init.ops = &clk_mux_ops;
508 init.parent_names = mux_parent_names;
509 init.num_parents = MUX_CLK_NUM_PARENTS;
511 mux->reg = host->regs + SD_EMMC_CLOCK;
512 mux->shift = __ffs(CLK_SRC_MASK);
513 mux->mask = CLK_SRC_MASK >> mux->shift;
514 mux->hw.init = &init;
516 clk = devm_clk_register(host->dev, &mux->hw);
517 if (WARN_ON(IS_ERR(clk)))
520 /* create the divider */
521 div = devm_kzalloc(host->dev, sizeof(*div), GFP_KERNEL);
525 snprintf(clk_name, sizeof(clk_name), "%s#div", dev_name(host->dev));
526 init.name = clk_name;
527 init.ops = &clk_divider_ops;
528 init.flags = CLK_SET_RATE_PARENT;
529 clk_parent[0] = __clk_get_name(clk);
530 init.parent_names = clk_parent;
531 init.num_parents = 1;
533 div->reg = host->regs + SD_EMMC_CLOCK;
534 div->shift = __ffs(CLK_DIV_MASK);
535 div->width = __builtin_popcountl(CLK_DIV_MASK);
536 div->hw.init = &init;
537 div->flags = CLK_DIVIDER_ONE_BASED;
539 clk = devm_clk_register(host->dev, &div->hw);
540 if (WARN_ON(IS_ERR(clk)))
543 /* create the mmc core clock */
544 core = devm_kzalloc(host->dev, sizeof(*core), GFP_KERNEL);
548 snprintf(clk_name, sizeof(clk_name), "%s#core", dev_name(host->dev));
549 init.name = clk_name;
550 init.ops = &meson_mmc_clk_phase_ops;
551 init.flags = CLK_SET_RATE_PARENT;
552 clk_parent[0] = __clk_get_name(clk);
553 init.parent_names = clk_parent;
554 init.num_parents = 1;
556 core->reg = host->regs + SD_EMMC_CLOCK;
557 core->phase_mask = CLK_CORE_PHASE_MASK;
558 core->hw.init = &init;
560 host->mmc_clk = devm_clk_register(host->dev, &core->hw);
561 if (WARN_ON(PTR_ERR_OR_ZERO(host->mmc_clk)))
562 return PTR_ERR(host->mmc_clk);
564 /* create the mmc tx clock */
565 tx = devm_kzalloc(host->dev, sizeof(*tx), GFP_KERNEL);
569 snprintf(clk_name, sizeof(clk_name), "%s#tx", dev_name(host->dev));
570 init.name = clk_name;
571 init.ops = &meson_mmc_clk_phase_ops;
573 clk_parent[0] = __clk_get_name(host->mmc_clk);
574 init.parent_names = clk_parent;
575 init.num_parents = 1;
577 tx->reg = host->regs + SD_EMMC_CLOCK;
578 tx->phase_mask = CLK_TX_PHASE_MASK;
579 tx->delay_mask = CLK_TX_DELAY_MASK;
580 tx->delay_step_ps = CLK_DELAY_STEP_PS;
583 host->tx_clk = devm_clk_register(host->dev, &tx->hw);
584 if (WARN_ON(PTR_ERR_OR_ZERO(host->tx_clk)))
585 return PTR_ERR(host->tx_clk);
587 /* create the mmc rx clock */
588 rx = devm_kzalloc(host->dev, sizeof(*rx), GFP_KERNEL);
592 snprintf(clk_name, sizeof(clk_name), "%s#rx", dev_name(host->dev));
593 init.name = clk_name;
594 init.ops = &meson_mmc_clk_phase_ops;
596 clk_parent[0] = __clk_get_name(host->mmc_clk);
597 init.parent_names = clk_parent;
598 init.num_parents = 1;
600 rx->reg = host->regs + SD_EMMC_CLOCK;
601 rx->phase_mask = CLK_RX_PHASE_MASK;
602 rx->delay_mask = CLK_RX_DELAY_MASK;
603 rx->delay_step_ps = CLK_DELAY_STEP_PS;
606 host->rx_clk = devm_clk_register(host->dev, &rx->hw);
607 if (WARN_ON(PTR_ERR_OR_ZERO(host->rx_clk)))
608 return PTR_ERR(host->rx_clk);
610 /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */
611 host->mmc->f_min = clk_round_rate(host->mmc_clk, 400000);
612 ret = clk_set_rate(host->mmc_clk, host->mmc->f_min);
617 * Set phases : These values are mostly the datasheet recommended ones
618 * except for the Tx phase. Datasheet recommends 180 but some cards
619 * fail at initialisation with it. 270 works just fine, it fixes these
620 * initialisation issues and enable eMMC DDR52 mode.
622 clk_set_phase(host->mmc_clk, 180);
623 clk_set_phase(host->tx_clk, 270);
624 clk_set_phase(host->rx_clk, 0);
626 return clk_prepare_enable(host->mmc_clk);
629 static void meson_mmc_shift_map(unsigned long *map, unsigned long shift)
631 DECLARE_BITMAP(left, CLK_PHASE_POINT_NUM);
632 DECLARE_BITMAP(right, CLK_PHASE_POINT_NUM);
635 * shift the bitmap right and reintroduce the dropped bits on the left
638 bitmap_shift_right(right, map, shift, CLK_PHASE_POINT_NUM);
639 bitmap_shift_left(left, map, CLK_PHASE_POINT_NUM - shift,
640 CLK_PHASE_POINT_NUM);
641 bitmap_or(map, left, right, CLK_PHASE_POINT_NUM);
644 static void meson_mmc_find_next_region(unsigned long *map,
645 unsigned long *start,
648 *start = find_next_bit(map, CLK_PHASE_POINT_NUM, *start);
649 *stop = find_next_zero_bit(map, CLK_PHASE_POINT_NUM, *start);
652 static int meson_mmc_find_tuning_point(unsigned long *test)
654 unsigned long shift, stop, offset = 0, start = 0, size = 0;
656 /* Get the all good/all bad situation out the way */
657 if (bitmap_full(test, CLK_PHASE_POINT_NUM))
658 return 0; /* All points are good so point 0 will do */
659 else if (bitmap_empty(test, CLK_PHASE_POINT_NUM))
660 return -EIO; /* No successful tuning point */
663 * Now we know there is a least one region find. Make sure it does
664 * not wrap by the shifting the bitmap if necessary
666 shift = find_first_zero_bit(test, CLK_PHASE_POINT_NUM);
668 meson_mmc_shift_map(test, shift);
670 while (start < CLK_PHASE_POINT_NUM) {
671 meson_mmc_find_next_region(test, &start, &stop);
673 if ((stop - start) > size) {
681 /* Get the center point of the region */
682 offset += (size / 2);
684 /* Shift the result back */
685 offset = (offset + shift) % CLK_PHASE_POINT_NUM;
690 static int meson_mmc_clk_phase_tuning(struct mmc_host *mmc, u32 opcode,
694 DECLARE_BITMAP(test, CLK_PHASE_POINT_NUM);
696 dev_dbg(mmc_dev(mmc), "%s phase/delay tunning...\n",
697 __clk_get_name(clk));
698 bitmap_zero(test, CLK_PHASE_POINT_NUM);
700 /* Explore tuning points */
701 for (point = 0; point < CLK_PHASE_POINT_NUM; point++) {
702 clk_set_phase(clk, point * CLK_PHASE_STEP);
703 ret = mmc_send_tuning(mmc, opcode, NULL);
705 set_bit(point, test);
708 /* Find the optimal tuning point and apply it */
709 point = meson_mmc_find_tuning_point(test);
711 return point; /* tuning failed */
713 clk_set_phase(clk, point * CLK_PHASE_STEP);
714 dev_dbg(mmc_dev(mmc), "success with phase: %d\n",
719 static int meson_mmc_execute_tuning(struct mmc_host *mmc, u32 opcode)
721 struct meson_host *host = mmc_priv(mmc);
723 return meson_mmc_clk_phase_tuning(mmc, opcode, host->rx_clk);
726 static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
728 struct meson_host *host = mmc_priv(mmc);
733 * GPIO regulator, only controls switching between 1v8 and
734 * 3v3, doesn't support MMC_POWER_OFF, MMC_POWER_ON.
736 switch (ios->power_mode) {
738 if (!IS_ERR(mmc->supply.vmmc))
739 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
741 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
742 regulator_disable(mmc->supply.vqmmc);
743 host->vqmmc_enabled = false;
749 if (!IS_ERR(mmc->supply.vmmc))
750 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
753 clk_set_phase(host->rx_clk, 0);
758 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
759 int ret = regulator_enable(mmc->supply.vqmmc);
763 "failed to enable vqmmc regulator\n");
765 host->vqmmc_enabled = true;
772 switch (ios->bus_width) {
773 case MMC_BUS_WIDTH_1:
774 bus_width = CFG_BUS_WIDTH_1;
776 case MMC_BUS_WIDTH_4:
777 bus_width = CFG_BUS_WIDTH_4;
779 case MMC_BUS_WIDTH_8:
780 bus_width = CFG_BUS_WIDTH_8;
783 dev_err(host->dev, "Invalid ios->bus_width: %u. Setting to 4.\n",
785 bus_width = CFG_BUS_WIDTH_4;
788 val = readl(host->regs + SD_EMMC_CFG);
789 val &= ~CFG_BUS_WIDTH_MASK;
790 val |= FIELD_PREP(CFG_BUS_WIDTH_MASK, bus_width);
793 if (meson_mmc_timing_is_ddr(ios))
797 if (ios->timing == MMC_TIMING_MMC_HS400)
800 err = meson_mmc_clk_set(host, ios);
802 dev_err(host->dev, "Failed to set clock: %d\n,", err);
804 writel(val, host->regs + SD_EMMC_CFG);
805 dev_dbg(host->dev, "SD_EMMC_CFG: 0x%08x\n", val);
808 static void meson_mmc_request_done(struct mmc_host *mmc,
809 struct mmc_request *mrq)
811 struct meson_host *host = mmc_priv(mmc);
814 mmc_request_done(host->mmc, mrq);
817 static void meson_mmc_set_blksz(struct mmc_host *mmc, unsigned int blksz)
819 struct meson_host *host = mmc_priv(mmc);
822 cfg = readl(host->regs + SD_EMMC_CFG);
823 blksz_old = FIELD_GET(CFG_BLK_LEN_MASK, cfg);
825 if (!is_power_of_2(blksz))
826 dev_err(host->dev, "blksz %u is not a power of 2\n", blksz);
828 blksz = ilog2(blksz);
830 /* check if block-size matches, if not update */
831 if (blksz == blksz_old)
834 dev_dbg(host->dev, "%s: update blk_len %d -> %d\n", __func__,
837 cfg &= ~CFG_BLK_LEN_MASK;
838 cfg |= FIELD_PREP(CFG_BLK_LEN_MASK, blksz);
839 writel(cfg, host->regs + SD_EMMC_CFG);
842 static void meson_mmc_set_response_bits(struct mmc_command *cmd, u32 *cmd_cfg)
844 if (cmd->flags & MMC_RSP_PRESENT) {
845 if (cmd->flags & MMC_RSP_136)
846 *cmd_cfg |= CMD_CFG_RESP_128;
847 *cmd_cfg |= CMD_CFG_RESP_NUM;
849 if (!(cmd->flags & MMC_RSP_CRC))
850 *cmd_cfg |= CMD_CFG_RESP_NOCRC;
852 if (cmd->flags & MMC_RSP_BUSY)
853 *cmd_cfg |= CMD_CFG_R1B;
855 *cmd_cfg |= CMD_CFG_NO_RESP;
859 static void meson_mmc_desc_chain_transfer(struct mmc_host *mmc, u32 cmd_cfg)
861 struct meson_host *host = mmc_priv(mmc);
862 struct sd_emmc_desc *desc = host->descs;
863 struct mmc_data *data = host->cmd->data;
864 struct scatterlist *sg;
868 if (data->flags & MMC_DATA_WRITE)
869 cmd_cfg |= CMD_CFG_DATA_WR;
871 if (data->blocks > 1) {
872 cmd_cfg |= CMD_CFG_BLOCK_MODE;
873 meson_mmc_set_blksz(mmc, data->blksz);
876 for_each_sg(data->sg, sg, data->sg_count, i) {
877 unsigned int len = sg_dma_len(sg);
879 if (data->blocks > 1)
882 desc[i].cmd_cfg = cmd_cfg;
883 desc[i].cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, len);
885 desc[i].cmd_cfg |= CMD_CFG_NO_CMD;
886 desc[i].cmd_arg = host->cmd->arg;
887 desc[i].cmd_resp = 0;
888 desc[i].cmd_data = sg_dma_address(sg);
890 desc[data->sg_count - 1].cmd_cfg |= CMD_CFG_END_OF_CHAIN;
892 dma_wmb(); /* ensure descriptor is written before kicked */
893 start = host->descs_dma_addr | START_DESC_BUSY;
894 writel(start, host->regs + SD_EMMC_START);
897 static void meson_mmc_start_cmd(struct mmc_host *mmc, struct mmc_command *cmd)
899 struct meson_host *host = mmc_priv(mmc);
900 struct mmc_data *data = cmd->data;
901 u32 cmd_cfg = 0, cmd_data = 0;
902 unsigned int xfer_bytes = 0;
904 /* Setup descriptors */
909 cmd_cfg |= FIELD_PREP(CMD_CFG_CMD_INDEX_MASK, cmd->opcode);
910 cmd_cfg |= CMD_CFG_OWNER; /* owned by CPU */
911 cmd_cfg |= CMD_CFG_ERROR; /* stop in case of error */
913 meson_mmc_set_response_bits(cmd, &cmd_cfg);
917 data->bytes_xfered = 0;
918 cmd_cfg |= CMD_CFG_DATA_IO;
919 cmd_cfg |= FIELD_PREP(CMD_CFG_TIMEOUT_MASK,
920 ilog2(meson_mmc_get_timeout_msecs(data)));
922 if (meson_mmc_desc_chain_mode(data)) {
923 meson_mmc_desc_chain_transfer(mmc, cmd_cfg);
927 if (data->blocks > 1) {
928 cmd_cfg |= CMD_CFG_BLOCK_MODE;
929 cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK,
931 meson_mmc_set_blksz(mmc, data->blksz);
933 cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, data->blksz);
936 xfer_bytes = data->blksz * data->blocks;
937 if (data->flags & MMC_DATA_WRITE) {
938 cmd_cfg |= CMD_CFG_DATA_WR;
939 WARN_ON(xfer_bytes > host->bounce_buf_size);
940 sg_copy_to_buffer(data->sg, data->sg_len,
941 host->bounce_buf, xfer_bytes);
945 cmd_data = host->bounce_dma_addr & CMD_DATA_MASK;
947 cmd_cfg |= FIELD_PREP(CMD_CFG_TIMEOUT_MASK,
948 ilog2(SD_EMMC_CMD_TIMEOUT));
951 /* Last descriptor */
952 cmd_cfg |= CMD_CFG_END_OF_CHAIN;
953 writel(cmd_cfg, host->regs + SD_EMMC_CMD_CFG);
954 writel(cmd_data, host->regs + SD_EMMC_CMD_DAT);
955 writel(0, host->regs + SD_EMMC_CMD_RSP);
956 wmb(); /* ensure descriptor is written before kicked */
957 writel(cmd->arg, host->regs + SD_EMMC_CMD_ARG);
960 static void meson_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
962 struct meson_host *host = mmc_priv(mmc);
963 bool needs_pre_post_req = mrq->data &&
964 !(mrq->data->host_cookie & SD_EMMC_PRE_REQ_DONE);
966 if (needs_pre_post_req) {
967 meson_mmc_get_transfer_mode(mmc, mrq);
968 if (!meson_mmc_desc_chain_mode(mrq->data))
969 needs_pre_post_req = false;
972 if (needs_pre_post_req)
973 meson_mmc_pre_req(mmc, mrq);
976 writel(0, host->regs + SD_EMMC_START);
978 meson_mmc_start_cmd(mmc, mrq->sbc ?: mrq->cmd);
980 if (needs_pre_post_req)
981 meson_mmc_post_req(mmc, mrq, 0);
984 static void meson_mmc_read_resp(struct mmc_host *mmc, struct mmc_command *cmd)
986 struct meson_host *host = mmc_priv(mmc);
988 if (cmd->flags & MMC_RSP_136) {
989 cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP3);
990 cmd->resp[1] = readl(host->regs + SD_EMMC_CMD_RSP2);
991 cmd->resp[2] = readl(host->regs + SD_EMMC_CMD_RSP1);
992 cmd->resp[3] = readl(host->regs + SD_EMMC_CMD_RSP);
993 } else if (cmd->flags & MMC_RSP_PRESENT) {
994 cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP);
998 static irqreturn_t meson_mmc_irq(int irq, void *dev_id)
1000 struct meson_host *host = dev_id;
1001 struct mmc_command *cmd;
1002 struct mmc_data *data;
1003 u32 irq_en, status, raw_status;
1004 irqreturn_t ret = IRQ_NONE;
1006 irq_en = readl(host->regs + SD_EMMC_IRQ_EN);
1007 raw_status = readl(host->regs + SD_EMMC_STATUS);
1008 status = raw_status & irq_en;
1012 "Unexpected IRQ! irq_en 0x%08x - status 0x%08x\n",
1013 irq_en, raw_status);
1017 if (WARN_ON(!host) || WARN_ON(!host->cmd))
1020 spin_lock(&host->lock);
1025 if (status & IRQ_CRC_ERR) {
1026 dev_dbg(host->dev, "CRC Error - status 0x%08x\n", status);
1027 cmd->error = -EILSEQ;
1028 ret = IRQ_WAKE_THREAD;
1032 if (status & IRQ_TIMEOUTS) {
1033 dev_dbg(host->dev, "Timeout - status 0x%08x\n", status);
1034 cmd->error = -ETIMEDOUT;
1035 ret = IRQ_WAKE_THREAD;
1039 meson_mmc_read_resp(host->mmc, cmd);
1041 if (status & IRQ_SDIO) {
1042 dev_dbg(host->dev, "IRQ: SDIO TODO.\n");
1046 if (status & (IRQ_END_OF_CHAIN | IRQ_RESP_STATUS)) {
1047 if (data && !cmd->error)
1048 data->bytes_xfered = data->blksz * data->blocks;
1049 if (meson_mmc_bounce_buf_read(data) ||
1050 meson_mmc_get_next_command(cmd))
1051 ret = IRQ_WAKE_THREAD;
1057 /* ack all enabled interrupts */
1058 writel(irq_en, host->regs + SD_EMMC_STATUS);
1061 /* Stop desc in case of errors */
1062 u32 start = readl(host->regs + SD_EMMC_START);
1064 start &= ~START_DESC_BUSY;
1065 writel(start, host->regs + SD_EMMC_START);
1068 if (ret == IRQ_HANDLED)
1069 meson_mmc_request_done(host->mmc, cmd->mrq);
1071 spin_unlock(&host->lock);
1075 static int meson_mmc_wait_desc_stop(struct meson_host *host)
1081 * It may sometimes take a while for it to actually halt. Here, we
1082 * are giving it 5ms to comply
1084 * If we don't confirm the descriptor is stopped, it might raise new
1085 * IRQs after we have called mmc_request_done() which is bad.
1087 for (loop = 50; loop; loop--) {
1088 status = readl(host->regs + SD_EMMC_STATUS);
1089 if (status & (STATUS_BUSY | STATUS_DESC_BUSY))
1095 if (status & (STATUS_BUSY | STATUS_DESC_BUSY)) {
1096 dev_err(host->dev, "Timed out waiting for host to stop\n");
1103 static irqreturn_t meson_mmc_irq_thread(int irq, void *dev_id)
1105 struct meson_host *host = dev_id;
1106 struct mmc_command *next_cmd, *cmd = host->cmd;
1107 struct mmc_data *data;
1108 unsigned int xfer_bytes;
1114 meson_mmc_wait_desc_stop(host);
1115 meson_mmc_request_done(host->mmc, cmd->mrq);
1121 if (meson_mmc_bounce_buf_read(data)) {
1122 xfer_bytes = data->blksz * data->blocks;
1123 WARN_ON(xfer_bytes > host->bounce_buf_size);
1124 sg_copy_from_buffer(data->sg, data->sg_len,
1125 host->bounce_buf, xfer_bytes);
1128 next_cmd = meson_mmc_get_next_command(cmd);
1130 meson_mmc_start_cmd(host->mmc, next_cmd);
1132 meson_mmc_request_done(host->mmc, cmd->mrq);
1138 * NOTE: we only need this until the GPIO/pinctrl driver can handle
1139 * interrupts. For now, the MMC core will use this for polling.
1141 static int meson_mmc_get_cd(struct mmc_host *mmc)
1143 int status = mmc_gpio_get_cd(mmc);
1145 if (status == -ENOSYS)
1146 return 1; /* assume present */
1151 static void meson_mmc_cfg_init(struct meson_host *host)
1155 cfg |= FIELD_PREP(CFG_RESP_TIMEOUT_MASK,
1156 ilog2(SD_EMMC_CFG_RESP_TIMEOUT));
1157 cfg |= FIELD_PREP(CFG_RC_CC_MASK, ilog2(SD_EMMC_CFG_CMD_GAP));
1158 cfg |= FIELD_PREP(CFG_BLK_LEN_MASK, ilog2(SD_EMMC_CFG_BLK_SIZE));
1160 /* abort chain on R/W errors */
1161 cfg |= CFG_ERR_ABORT;
1163 writel(cfg, host->regs + SD_EMMC_CFG);
1166 static int meson_mmc_card_busy(struct mmc_host *mmc)
1168 struct meson_host *host = mmc_priv(mmc);
1171 regval = readl(host->regs + SD_EMMC_STATUS);
1173 /* We are only interrested in lines 0 to 3, so mask the other ones */
1174 return !(FIELD_GET(STATUS_DATI, regval) & 0xf);
1177 static int meson_mmc_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios)
1179 /* vqmmc regulator is available */
1180 if (!IS_ERR(mmc->supply.vqmmc)) {
1182 * The usual amlogic setup uses a GPIO to switch from one
1183 * regulator to the other. While the voltage ramp up is
1184 * pretty fast, care must be taken when switching from 3.3v
1185 * to 1.8v. Please make sure the regulator framework is aware
1186 * of your own regulator constraints
1188 return mmc_regulator_set_vqmmc(mmc, ios);
1191 /* no vqmmc regulator, assume fixed regulator at 3/3.3V */
1192 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1198 static const struct mmc_host_ops meson_mmc_ops = {
1199 .request = meson_mmc_request,
1200 .set_ios = meson_mmc_set_ios,
1201 .get_cd = meson_mmc_get_cd,
1202 .pre_req = meson_mmc_pre_req,
1203 .post_req = meson_mmc_post_req,
1204 .execute_tuning = meson_mmc_execute_tuning,
1205 .card_busy = meson_mmc_card_busy,
1206 .start_signal_voltage_switch = meson_mmc_voltage_switch,
1209 static int meson_mmc_probe(struct platform_device *pdev)
1211 struct resource *res;
1212 struct meson_host *host;
1213 struct mmc_host *mmc;
1216 mmc = mmc_alloc_host(sizeof(struct meson_host), &pdev->dev);
1219 host = mmc_priv(mmc);
1221 host->dev = &pdev->dev;
1222 dev_set_drvdata(&pdev->dev, host);
1224 spin_lock_init(&host->lock);
1226 /* Get regulators and the supported OCR mask */
1227 host->vqmmc_enabled = false;
1228 ret = mmc_regulator_get_supply(mmc);
1229 if (ret == -EPROBE_DEFER)
1232 ret = mmc_of_parse(mmc);
1234 if (ret != -EPROBE_DEFER)
1235 dev_warn(&pdev->dev, "error parsing DT: %d\n", ret);
1239 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1240 host->regs = devm_ioremap_resource(&pdev->dev, res);
1241 if (IS_ERR(host->regs)) {
1242 ret = PTR_ERR(host->regs);
1246 irq = platform_get_irq(pdev, 0);
1248 dev_err(&pdev->dev, "failed to get interrupt resource.\n");
1253 host->pinctrl = devm_pinctrl_get(&pdev->dev);
1254 if (IS_ERR(host->pinctrl)) {
1255 ret = PTR_ERR(host->pinctrl);
1259 host->pins_default = pinctrl_lookup_state(host->pinctrl,
1260 PINCTRL_STATE_DEFAULT);
1261 if (IS_ERR(host->pins_default)) {
1262 ret = PTR_ERR(host->pins_default);
1266 host->pins_clk_gate = pinctrl_lookup_state(host->pinctrl,
1268 if (IS_ERR(host->pins_clk_gate)) {
1269 dev_warn(&pdev->dev,
1270 "can't get clk-gate pinctrl, using clk_stop bit\n");
1271 host->pins_clk_gate = NULL;
1274 host->core_clk = devm_clk_get(&pdev->dev, "core");
1275 if (IS_ERR(host->core_clk)) {
1276 ret = PTR_ERR(host->core_clk);
1280 ret = clk_prepare_enable(host->core_clk);
1284 ret = meson_mmc_clk_init(host);
1288 /* set config to sane default */
1289 meson_mmc_cfg_init(host);
1291 /* Stop execution */
1292 writel(0, host->regs + SD_EMMC_START);
1294 /* clear, ack and enable interrupts */
1295 writel(0, host->regs + SD_EMMC_IRQ_EN);
1296 writel(IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN,
1297 host->regs + SD_EMMC_STATUS);
1298 writel(IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN,
1299 host->regs + SD_EMMC_IRQ_EN);
1301 ret = devm_request_threaded_irq(&pdev->dev, irq, meson_mmc_irq,
1302 meson_mmc_irq_thread, IRQF_SHARED,
1307 mmc->caps |= MMC_CAP_CMD23;
1308 mmc->max_blk_count = CMD_CFG_LENGTH_MASK;
1309 mmc->max_req_size = mmc->max_blk_count * mmc->max_blk_size;
1310 mmc->max_segs = SD_EMMC_DESC_BUF_LEN / sizeof(struct sd_emmc_desc);
1311 mmc->max_seg_size = mmc->max_req_size;
1313 /* data bounce buffer */
1314 host->bounce_buf_size = mmc->max_req_size;
1316 dma_alloc_coherent(host->dev, host->bounce_buf_size,
1317 &host->bounce_dma_addr, GFP_KERNEL);
1318 if (host->bounce_buf == NULL) {
1319 dev_err(host->dev, "Unable to map allocate DMA bounce buffer.\n");
1324 host->descs = dma_alloc_coherent(host->dev, SD_EMMC_DESC_BUF_LEN,
1325 &host->descs_dma_addr, GFP_KERNEL);
1327 dev_err(host->dev, "Allocating descriptor DMA buffer failed\n");
1329 goto err_bounce_buf;
1332 mmc->ops = &meson_mmc_ops;
1338 dma_free_coherent(host->dev, host->bounce_buf_size,
1339 host->bounce_buf, host->bounce_dma_addr);
1341 clk_disable_unprepare(host->mmc_clk);
1343 clk_disable_unprepare(host->core_clk);
1349 static int meson_mmc_remove(struct platform_device *pdev)
1351 struct meson_host *host = dev_get_drvdata(&pdev->dev);
1353 mmc_remove_host(host->mmc);
1355 /* disable interrupts */
1356 writel(0, host->regs + SD_EMMC_IRQ_EN);
1358 dma_free_coherent(host->dev, SD_EMMC_DESC_BUF_LEN,
1359 host->descs, host->descs_dma_addr);
1360 dma_free_coherent(host->dev, host->bounce_buf_size,
1361 host->bounce_buf, host->bounce_dma_addr);
1363 clk_disable_unprepare(host->mmc_clk);
1364 clk_disable_unprepare(host->core_clk);
1366 mmc_free_host(host->mmc);
1370 static const struct of_device_id meson_mmc_of_match[] = {
1371 { .compatible = "amlogic,meson-gx-mmc", },
1372 { .compatible = "amlogic,meson-gxbb-mmc", },
1373 { .compatible = "amlogic,meson-gxl-mmc", },
1374 { .compatible = "amlogic,meson-gxm-mmc", },
1377 MODULE_DEVICE_TABLE(of, meson_mmc_of_match);
1379 static struct platform_driver meson_mmc_driver = {
1380 .probe = meson_mmc_probe,
1381 .remove = meson_mmc_remove,
1383 .name = DRIVER_NAME,
1384 .of_match_table = of_match_ptr(meson_mmc_of_match),
1388 module_platform_driver(meson_mmc_driver);
1390 MODULE_DESCRIPTION("Amlogic S905*/GX* SD/eMMC driver");
1391 MODULE_AUTHOR("Kevin Hilman <khilman@baylibre.com>");
1392 MODULE_LICENSE("GPL v2");