drivers/mmc/host/dw_mmc.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Synopsys DesignWare Multimedia Card Interface driver
   4  *  (Based on NXP driver for lpc 31xx)
   5  *
   6  * Copyright (C) 2009 NXP Semiconductors
   7  * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
   8  */
   9
  10 #include <linux/blkdev.h>
  11 #include <linux/clk.h>
  12 #include <linux/debugfs.h>
  13 #include <linux/device.h>
  14 #include <linux/dma-mapping.h>
  15 #include <linux/err.h>
  16 #include <linux/init.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/iopoll.h>
  19 #include <linux/ioport.h>
  20 #include <linux/ktime.h>
  21 #include <linux/module.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/pm_runtime.h>
  24 #include <linux/prandom.h>
  25 #include <linux/seq_file.h>
  26 #include <linux/slab.h>
  27 #include <linux/stat.h>
  28 #include <linux/delay.h>
  29 #include <linux/irq.h>
  30 #include <linux/mmc/card.h>
  31 #include <linux/mmc/host.h>
  32 #include <linux/mmc/mmc.h>
  33 #include <linux/mmc/sd.h>
  34 #include <linux/mmc/sdio.h>
  35 #include <linux/bitops.h>
  36 #include <linux/regulator/consumer.h>
  37 #include <linux/of.h>
  38 #include <linux/mmc/slot-gpio.h>
  39
  40 #include "dw_mmc.h"
  41
  42 /* Common flag combinations */
  43 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
  44                                  SDMMC_INT_HTO | SDMMC_INT_SBE  | \
  45                                  SDMMC_INT_EBE | SDMMC_INT_HLE)
  46 #define DW_MCI_CMD_ERROR_FLAGS  (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
  47                                  SDMMC_INT_RESP_ERR | SDMMC_INT_HLE)
  48 #define DW_MCI_ERROR_FLAGS      (DW_MCI_DATA_ERROR_FLAGS | \
  49                                  DW_MCI_CMD_ERROR_FLAGS)
  50 #define DW_MCI_SEND_STATUS      1
  51 #define DW_MCI_RECV_STATUS      2
  52 #define DW_MCI_DMA_THRESHOLD    16
  53
  54 #define DW_MCI_FREQ_MAX 200000000       /* unit: HZ */
  55 #define DW_MCI_FREQ_MIN 100000          /* unit: HZ */
  56
  57 #define IDMAC_INT_CLR           (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
  58                                  SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
  59                                  SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
  60                                  SDMMC_IDMAC_INT_TI)
  61
  62 #define DESC_RING_BUF_SZ        PAGE_SIZE
  63
  64 struct idmac_desc_64addr {
  65         u32             des0;   /* Control Descriptor */
  66 #define IDMAC_OWN_CLR64(x) \
  67         !((x) & cpu_to_le32(IDMAC_DES0_OWN))
  68
  69         u32             des1;   /* Reserved */
  70
  71         u32             des2;   /*Buffer sizes */
  72 #define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \
  73         ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \
  74          ((cpu_to_le32(s)) & cpu_to_le32(0x1fff)))
  75
  76         u32             des3;   /* Reserved */
  77
  78         u32             des4;   /* Lower 32-bits of Buffer Address Pointer 1*/
  79         u32             des5;   /* Upper 32-bits of Buffer Address Pointer 1*/
  80
  81         u32             des6;   /* Lower 32-bits of Next Descriptor Address */
  82         u32             des7;   /* Upper 32-bits of Next Descriptor Address */
  83 };
  84
  85 struct idmac_desc {
  86         __le32          des0;   /* Control Descriptor */
  87 #define IDMAC_DES0_DIC  BIT(1)
  88 #define IDMAC_DES0_LD   BIT(2)
  89 #define IDMAC_DES0_FD   BIT(3)
  90 #define IDMAC_DES0_CH   BIT(4)
  91 #define IDMAC_DES0_ER   BIT(5)
  92 #define IDMAC_DES0_CES  BIT(30)
  93 #define IDMAC_DES0_OWN  BIT(31)
  94
  95         __le32          des1;   /* Buffer sizes */
  96 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
  97         ((d)->des1 = ((d)->des1 & cpu_to_le32(0x03ffe000)) | (cpu_to_le32((s) & 0x1fff)))
  98
  99         __le32          des2;   /* buffer 1 physical address */
 100
 101         __le32          des3;   /* buffer 2 physical address */
 102 };
 103
 104 /* Each descriptor can transfer up to 4KB of data in chained mode */
 105 #define DW_MCI_DESC_DATA_LENGTH 0x1000
 106
 107 #if defined(CONFIG_DEBUG_FS)
 108 static int dw_mci_req_show(struct seq_file *s, void *v)
 109 {
 110         struct dw_mci_slot *slot = s->private;
 111         struct mmc_request *mrq;
 112         struct mmc_command *cmd;
 113         struct mmc_command *stop;
 114         struct mmc_data *data;
 115
 116         /* Make sure we get a consistent snapshot */
 117         spin_lock_bh(&slot->host->lock);
 118         mrq = slot->mrq;
 119
 120         if (mrq) {
 121                 cmd = mrq->cmd;
 122                 data = mrq->data;
 123                 stop = mrq->stop;
 124
 125                 if (cmd)
 126                         seq_printf(s,
 127                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 128                                    cmd->opcode, cmd->arg, cmd->flags,
 129                                    cmd->resp[0], cmd->resp[1], cmd->resp[2],
 130                                    cmd->resp[2], cmd->error);
 131                 if (data)
 132                         seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
 133                                    data->bytes_xfered, data->blocks,
 134                                    data->blksz, data->flags, data->error);
 135                 if (stop)
 136                         seq_printf(s,
 137                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 138                                    stop->opcode, stop->arg, stop->flags,
 139                                    stop->resp[0], stop->resp[1], stop->resp[2],
 140                                    stop->resp[2], stop->error);
 141         }
 142
 143         spin_unlock_bh(&slot->host->lock);
 144
 145         return 0;
 146 }
 147 DEFINE_SHOW_ATTRIBUTE(dw_mci_req);
 148
 149 static int dw_mci_regs_show(struct seq_file *s, void *v)
 150 {
 151         struct dw_mci *host = s->private;
 152
 153         pm_runtime_get_sync(host->dev);
 154
 155         seq_printf(s, "STATUS:\t0x%08x\n", mci_readl(host, STATUS));
 156         seq_printf(s, "RINTSTS:\t0x%08x\n", mci_readl(host, RINTSTS));
 157         seq_printf(s, "CMD:\t0x%08x\n", mci_readl(host, CMD));
 158         seq_printf(s, "CTRL:\t0x%08x\n", mci_readl(host, CTRL));
 159         seq_printf(s, "INTMASK:\t0x%08x\n", mci_readl(host, INTMASK));
 160         seq_printf(s, "CLKENA:\t0x%08x\n", mci_readl(host, CLKENA));
 161
 162         pm_runtime_put_autosuspend(host->dev);
 163
 164         return 0;
 165 }
 166 DEFINE_SHOW_ATTRIBUTE(dw_mci_regs);
 167
 168 static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
 169 {
 170         struct mmc_host *mmc = slot->mmc;
 171         struct dw_mci *host = slot->host;
 172         struct dentry *root;
 173
 174         root = mmc->debugfs_root;
 175         if (!root)
 176                 return;
 177
 178         debugfs_create_file("regs", S_IRUSR, root, host, &dw_mci_regs_fops);
 179         debugfs_create_file("req", S_IRUSR, root, slot, &dw_mci_req_fops);
 180         debugfs_create_u32("state", S_IRUSR, root, &host->state);
 181         debugfs_create_xul("pending_events", S_IRUSR, root,
 182                            &host->pending_events);
 183         debugfs_create_xul("completed_events", S_IRUSR, root,
 184                            &host->completed_events);
 185 #ifdef CONFIG_FAULT_INJECTION
 186         fault_create_debugfs_attr("fail_data_crc", root, &host->fail_data_crc);
 187 #endif
 188 }
 189 #endif /* defined(CONFIG_DEBUG_FS) */
 190
 191 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
 192 {
 193         u32 ctrl;
 194
 195         ctrl = mci_readl(host, CTRL);
 196         ctrl |= reset;
 197         mci_writel(host, CTRL, ctrl);
 198
 199         /* wait till resets clear */
 200         if (readl_poll_timeout_atomic(host->regs + SDMMC_CTRL, ctrl,
 201                                       !(ctrl & reset),
 202                                       1, 500 * USEC_PER_MSEC)) {
 203                 dev_err(host->dev,
 204                         "Timeout resetting block (ctrl reset %#x)\n",
 205                         ctrl & reset);
 206                 return false;
 207         }
 208
 209         return true;
 210 }
 211
 212 static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags)
 213 {
 214         u32 status;
 215
 216         /*
 217          * Databook says that before issuing a new data transfer command
 218          * we need to check to see if the card is busy.  Data transfer commands
 219          * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that.
 220          *
 221          * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is
 222          * expected.
 223          */
 224         if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) &&
 225             !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) {
 226                 if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS,
 227                                               status,
 228                                               !(status & SDMMC_STATUS_BUSY),
 229                                               10, 500 * USEC_PER_MSEC))
 230                         dev_err(host->dev, "Busy; trying anyway\n");
 231         }
 232 }
 233
 234 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
 235 {
 236         struct dw_mci *host = slot->host;
 237         unsigned int cmd_status = 0;
 238
 239         mci_writel(host, CMDARG, arg);
 240         wmb(); /* drain writebuffer */
 241         dw_mci_wait_while_busy(host, cmd);
 242         mci_writel(host, CMD, SDMMC_CMD_START | cmd);
 243
 244         if (readl_poll_timeout_atomic(host->regs + SDMMC_CMD, cmd_status,
 245                                       !(cmd_status & SDMMC_CMD_START),
 246                                       1, 500 * USEC_PER_MSEC))
 247                 dev_err(&slot->mmc->class_dev,
 248                         "Timeout sending command (cmd %#x arg %#x status %#x)\n",
 249                         cmd, arg, cmd_status);
 250 }
 251
 252 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
 253 {
 254         struct dw_mci_slot *slot = mmc_priv(mmc);
 255         struct dw_mci *host = slot->host;
 256         u32 cmdr;
 257
 258         cmd->error = -EINPROGRESS;
 259         cmdr = cmd->opcode;
 260
 261         if (cmd->opcode == MMC_STOP_TRANSMISSION ||
 262             cmd->opcode == MMC_GO_IDLE_STATE ||
 263             cmd->opcode == MMC_GO_INACTIVE_STATE ||
 264             (cmd->opcode == SD_IO_RW_DIRECT &&
 265              ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT))
 266                 cmdr |= SDMMC_CMD_STOP;
 267         else if (cmd->opcode != MMC_SEND_STATUS && cmd->data)
 268                 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
 269
 270         if (cmd->opcode == SD_SWITCH_VOLTAGE) {
 271                 u32 clk_en_a;
 272
 273                 /* Special bit makes CMD11 not die */
 274                 cmdr |= SDMMC_CMD_VOLT_SWITCH;
 275
 276                 /* Change state to continue to handle CMD11 weirdness */
 277                 WARN_ON(slot->host->state != STATE_SENDING_CMD);
 278                 slot->host->state = STATE_SENDING_CMD11;
 279
 280                 /*
 281                  * We need to disable low power mode (automatic clock stop)
 282                  * while doing voltage switch so we don't confuse the card,
 283                  * since stopping the clock is a specific part of the UHS
 284                  * voltage change dance.
 285                  *
 286                  * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be
 287                  * unconditionally turned back on in dw_mci_setup_bus() if it's
 288                  * ever called with a non-zero clock.  That shouldn't happen
 289                  * until the voltage change is all done.
 290                  */
 291                 clk_en_a = mci_readl(host, CLKENA);
 292                 clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id);
 293                 mci_writel(host, CLKENA, clk_en_a);
 294                 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
 295                              SDMMC_CMD_PRV_DAT_WAIT, 0);
 296         }
 297
 298         if (cmd->flags & MMC_RSP_PRESENT) {
 299                 /* We expect a response, so set this bit */
 300                 cmdr |= SDMMC_CMD_RESP_EXP;
 301                 if (cmd->flags & MMC_RSP_136)
 302                         cmdr |= SDMMC_CMD_RESP_LONG;
 303         }
 304
 305         if (cmd->flags & MMC_RSP_CRC)
 306                 cmdr |= SDMMC_CMD_RESP_CRC;
 307
 308         if (cmd->data) {
 309                 cmdr |= SDMMC_CMD_DAT_EXP;
 310                 if (cmd->data->flags & MMC_DATA_WRITE)
 311                         cmdr |= SDMMC_CMD_DAT_WR;
 312         }
 313
 314         if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &slot->flags))
 315                 cmdr |= SDMMC_CMD_USE_HOLD_REG;
 316
 317         return cmdr;
 318 }
 319
 320 static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd)
 321 {
 322         struct mmc_command *stop;
 323         u32 cmdr;
 324
 325         if (!cmd->data)
 326                 return 0;
 327
 328         stop = &host->stop_abort;
 329         cmdr = cmd->opcode;
 330         memset(stop, 0, sizeof(struct mmc_command));
 331
 332         if (cmdr == MMC_READ_SINGLE_BLOCK ||
 333             cmdr == MMC_READ_MULTIPLE_BLOCK ||
 334             cmdr == MMC_WRITE_BLOCK ||
 335             cmdr == MMC_WRITE_MULTIPLE_BLOCK ||
 336             mmc_op_tuning(cmdr) ||
 337             cmdr == MMC_GEN_CMD) {
 338                 stop->opcode = MMC_STOP_TRANSMISSION;
 339                 stop->arg = 0;
 340                 stop->flags = MMC_RSP_R1B | MMC_CMD_AC;
 341         } else if (cmdr == SD_IO_RW_EXTENDED) {
 342                 stop->opcode = SD_IO_RW_DIRECT;
 343                 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
 344                              ((cmd->arg >> 28) & 0x7);
 345                 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC;
 346         } else {
 347                 return 0;
 348         }
 349
 350         cmdr = stop->opcode | SDMMC_CMD_STOP |
 351                 SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP;
 352
 353         if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &host->slot->flags))
 354                 cmdr |= SDMMC_CMD_USE_HOLD_REG;
 355
 356         return cmdr;
 357 }
 358
 359 static inline void dw_mci_set_cto(struct dw_mci *host)
 360 {
 361         unsigned int cto_clks;
 362         unsigned int cto_div;
 363         unsigned int cto_ms;
 364         unsigned long irqflags;
 365
 366         cto_clks = mci_readl(host, TMOUT) & 0xff;
 367         cto_div = (mci_readl(host, CLKDIV) & 0xff) * 2;
 368         if (cto_div == 0)
 369                 cto_div = 1;
 370
 371         cto_ms = DIV_ROUND_UP_ULL((u64)MSEC_PER_SEC * cto_clks * cto_div,
 372                                   host->bus_hz);
 373
 374         /* add a bit spare time */
 375         cto_ms += 10;
 376
 377         /*
 378          * The durations we're working with are fairly short so we have to be
 379          * extra careful about synchronization here.  Specifically in hardware a
 380          * command timeout is _at most_ 5.1 ms, so that means we expect an
 381          * interrupt (either command done or timeout) to come rather quickly
 382          * after the mci_writel.  ...but just in case we have a long interrupt
 383          * latency let's add a bit of paranoia.
 384          *
 385          * In general we'll assume that at least an interrupt will be asserted
 386          * in hardware by the time the cto_timer runs.  ...and if it hasn't
 387          * been asserted in hardware by that time then we'll assume it'll never
 388          * come.
 389          */
 390         spin_lock_irqsave(&host->irq_lock, irqflags);
 391         if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
 392                 mod_timer(&host->cto_timer,
 393                         jiffies + msecs_to_jiffies(cto_ms) + 1);
 394         spin_unlock_irqrestore(&host->irq_lock, irqflags);
 395 }
 396
 397 static void dw_mci_start_command(struct dw_mci *host,
 398                                  struct mmc_command *cmd, u32 cmd_flags)
 399 {
 400         host->cmd = cmd;
 401         dev_vdbg(host->dev,
 402                  "start command: ARGR=0x%08x CMDR=0x%08x\n",
 403                  cmd->arg, cmd_flags);
 404
 405         mci_writel(host, CMDARG, cmd->arg);
 406         wmb(); /* drain writebuffer */
 407         dw_mci_wait_while_busy(host, cmd_flags);
 408
 409         mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
 410
 411         /* response expected command only */
 412         if (cmd_flags & SDMMC_CMD_RESP_EXP)
 413                 dw_mci_set_cto(host);
 414 }
 415
 416 static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data)
 417 {
 418         struct mmc_command *stop = &host->stop_abort;
 419
 420         dw_mci_start_command(host, stop, host->stop_cmdr);
 421 }
 422
 423 /* DMA interface functions */
 424 static void dw_mci_stop_dma(struct dw_mci *host)
 425 {
 426         if (host->using_dma) {
 427                 host->dma_ops->stop(host);
 428                 host->dma_ops->cleanup(host);
 429         }
 430
 431         /* Data transfer was stopped by the interrupt handler */
 432         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 433 }
 434
 435 static void dw_mci_dma_cleanup(struct dw_mci *host)
 436 {
 437         struct mmc_data *data = host->data;
 438
 439         if (data && data->host_cookie == COOKIE_MAPPED) {
 440                 dma_unmap_sg(host->dev,
 441                              data->sg,
 442                              data->sg_len,
 443                              mmc_get_dma_dir(data));
 444                 data->host_cookie = COOKIE_UNMAPPED;
 445         }
 446 }
 447
 448 static void dw_mci_idmac_reset(struct dw_mci *host)
 449 {
 450         u32 bmod = mci_readl(host, BMOD);
 451         /* Software reset of DMA */
 452         bmod |= SDMMC_IDMAC_SWRESET;
 453         mci_writel(host, BMOD, bmod);
 454 }
 455
 456 static void dw_mci_idmac_stop_dma(struct dw_mci *host)
 457 {
 458         u32 temp;
 459
 460         /* Disable and reset the IDMAC interface */
 461         temp = mci_readl(host, CTRL);
 462         temp &= ~SDMMC_CTRL_USE_IDMAC;
 463         temp |= SDMMC_CTRL_DMA_RESET;
 464         mci_writel(host, CTRL, temp);
 465
 466         /* Stop the IDMAC running */
 467         temp = mci_readl(host, BMOD);
 468         temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
 469         temp |= SDMMC_IDMAC_SWRESET;
 470         mci_writel(host, BMOD, temp);
 471 }
 472
 473 static void dw_mci_dmac_complete_dma(void *arg)
 474 {
 475         struct dw_mci *host = arg;
 476         struct mmc_data *data = host->data;
 477
 478         dev_vdbg(host->dev, "DMA complete\n");
 479
 480         if ((host->use_dma == TRANS_MODE_EDMAC) &&
 481             data && (data->flags & MMC_DATA_READ))
 482                 /* Invalidate cache after read */
 483                 dma_sync_sg_for_cpu(mmc_dev(host->slot->mmc),
 484                                     data->sg,
 485                                     data->sg_len,
 486                                     DMA_FROM_DEVICE);
 487
 488         host->dma_ops->cleanup(host);
 489
 490         /*
 491          * If the card was removed, data will be NULL. No point in trying to
 492          * send the stop command or waiting for NBUSY in this case.
 493          */
 494         if (data) {
 495                 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 496                 tasklet_schedule(&host->tasklet);
 497         }
 498 }
 499
 500 static int dw_mci_idmac_init(struct dw_mci *host)
 501 {
 502         int i;
 503
 504         if (host->dma_64bit_address == 1) {
 505                 struct idmac_desc_64addr *p;
 506                 /* Number of descriptors in the ring buffer */
 507                 host->ring_size =
 508                         DESC_RING_BUF_SZ / sizeof(struct idmac_desc_64addr);
 509
 510                 /* Forward link the descriptor list */
 511                 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1;
 512                                                                 i++, p++) {
 513                         p->des6 = (host->sg_dma +
 514                                         (sizeof(struct idmac_desc_64addr) *
 515                                                         (i + 1))) & 0xffffffff;
 516
 517                         p->des7 = (u64)(host->sg_dma +
 518                                         (sizeof(struct idmac_desc_64addr) *
 519                                                         (i + 1))) >> 32;
 520                         /* Initialize reserved and buffer size fields to "0" */
 521                         p->des0 = 0;
 522                         p->des1 = 0;
 523                         p->des2 = 0;
 524                         p->des3 = 0;
 525                 }
 526
 527                 /* Set the last descriptor as the end-of-ring descriptor */
 528                 p->des6 = host->sg_dma & 0xffffffff;
 529                 p->des7 = (u64)host->sg_dma >> 32;
 530                 p->des0 = IDMAC_DES0_ER;
 531
 532         } else {
 533                 struct idmac_desc *p;
 534                 /* Number of descriptors in the ring buffer */
 535                 host->ring_size =
 536                         DESC_RING_BUF_SZ / sizeof(struct idmac_desc);
 537
 538                 /* Forward link the descriptor list */
 539                 for (i = 0, p = host->sg_cpu;
 540                      i < host->ring_size - 1;
 541                      i++, p++) {
 542                         p->des3 = cpu_to_le32(host->sg_dma +
 543                                         (sizeof(struct idmac_desc) * (i + 1)));
 544                         p->des0 = 0;
 545                         p->des1 = 0;
 546                 }
 547
 548                 /* Set the last descriptor as the end-of-ring descriptor */
 549                 p->des3 = cpu_to_le32(host->sg_dma);
 550                 p->des0 = cpu_to_le32(IDMAC_DES0_ER);
 551         }
 552
 553         dw_mci_idmac_reset(host);
 554
 555         if (host->dma_64bit_address == 1) {
 556                 /* Mask out interrupts - get Tx & Rx complete only */
 557                 mci_writel(host, IDSTS64, IDMAC_INT_CLR);
 558                 mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI |
 559                                 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
 560
 561                 /* Set the descriptor base address */
 562                 mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff);
 563                 mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32);
 564
 565         } else {
 566                 /* Mask out interrupts - get Tx & Rx complete only */
 567                 mci_writel(host, IDSTS, IDMAC_INT_CLR);
 568                 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI |
 569                                 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
 570
 571                 /* Set the descriptor base address */
 572                 mci_writel(host, DBADDR, host->sg_dma);
 573         }
 574
 575         return 0;
 576 }
 577
 578 static inline int dw_mci_prepare_desc64(struct dw_mci *host,
 579                                          struct mmc_data *data,
 580                                          unsigned int sg_len)
 581 {
 582         unsigned int desc_len;
 583         struct idmac_desc_64addr *desc_first, *desc_last, *desc;
 584         u32 val;
 585         int i;
 586
 587         desc_first = desc_last = desc = host->sg_cpu;
 588
 589         for (i = 0; i < sg_len; i++) {
 590                 unsigned int length = sg_dma_len(&data->sg[i]);
 591
 592                 u64 mem_addr = sg_dma_address(&data->sg[i]);
 593
 594                 for ( ; length ; desc++) {
 595                         desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
 596                                    length : DW_MCI_DESC_DATA_LENGTH;
 597
 598                         length -= desc_len;
 599
 600                         /*
 601                          * Wait for the former clear OWN bit operation
 602                          * of IDMAC to make sure that this descriptor
 603                          * isn't still owned by IDMAC as IDMAC's write
 604                          * ops and CPU's read ops are asynchronous.
 605                          */
 606                         if (readl_poll_timeout_atomic(&desc->des0, val,
 607                                                 !(val & IDMAC_DES0_OWN),
 608                                                 10, 100 * USEC_PER_MSEC))
 609                                 goto err_own_bit;
 610
 611                         /*
 612                          * Set the OWN bit and disable interrupts
 613                          * for this descriptor
 614                          */
 615                         desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC |
 616                                                 IDMAC_DES0_CH;
 617
 618                         /* Buffer length */
 619                         IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, desc_len);
 620
 621                         /* Physical address to DMA to/from */
 622                         desc->des4 = mem_addr & 0xffffffff;
 623                         desc->des5 = mem_addr >> 32;
 624
 625                         /* Update physical address for the next desc */
 626                         mem_addr += desc_len;
 627
 628                         /* Save pointer to the last descriptor */
 629                         desc_last = desc;
 630                 }
 631         }
 632
 633         /* Set first descriptor */
 634         desc_first->des0 |= IDMAC_DES0_FD;
 635
 636         /* Set last descriptor */
 637         desc_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
 638         desc_last->des0 |= IDMAC_DES0_LD;
 639
 640         return 0;
 641 err_own_bit:
 642         /* restore the descriptor chain as it's polluted */
 643         dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n");
 644         memset(host->sg_cpu, 0, DESC_RING_BUF_SZ);
 645         dw_mci_idmac_init(host);
 646         return -EINVAL;
 647 }
 648
 649
 650 static inline int dw_mci_prepare_desc32(struct dw_mci *host,
 651                                          struct mmc_data *data,
 652                                          unsigned int sg_len)
 653 {
 654         unsigned int desc_len;
 655         struct idmac_desc *desc_first, *desc_last, *desc;
 656         u32 val;
 657         int i;
 658
 659         desc_first = desc_last = desc = host->sg_cpu;
 660
 661         for (i = 0; i < sg_len; i++) {
 662                 unsigned int length = sg_dma_len(&data->sg[i]);
 663
 664                 u32 mem_addr = sg_dma_address(&data->sg[i]);
 665
 666                 for ( ; length ; desc++) {
 667                         desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
 668                                    length : DW_MCI_DESC_DATA_LENGTH;
 669
 670                         length -= desc_len;
 671
 672                         /*
 673                          * Wait for the former clear OWN bit operation
 674                          * of IDMAC to make sure that this descriptor
 675                          * isn't still owned by IDMAC as IDMAC's write
 676                          * ops and CPU's read ops are asynchronous.
 677                          */
 678                         if (readl_poll_timeout_atomic(&desc->des0, val,
 679                                                       IDMAC_OWN_CLR64(val),
 680                                                       10,
 681                                                       100 * USEC_PER_MSEC))
 682                                 goto err_own_bit;
 683
 684                         /*
 685                          * Set the OWN bit and disable interrupts
 686                          * for this descriptor
 687                          */
 688                         desc->des0 = cpu_to_le32(IDMAC_DES0_OWN |
 689                                                  IDMAC_DES0_DIC |
 690                                                  IDMAC_DES0_CH);
 691
 692                         /* Buffer length */
 693                         IDMAC_SET_BUFFER1_SIZE(desc, desc_len);
 694
 695                         /* Physical address to DMA to/from */
 696                         desc->des2 = cpu_to_le32(mem_addr);
 697
 698                         /* Update physical address for the next desc */
 699                         mem_addr += desc_len;
 700
 701                         /* Save pointer to the last descriptor */
 702                         desc_last = desc;
 703                 }
 704         }
 705
 706         /* Set first descriptor */
 707         desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD);
 708
 709         /* Set last descriptor */
 710         desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH |
 711                                        IDMAC_DES0_DIC));
 712         desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD);
 713
 714         return 0;
 715 err_own_bit:
 716         /* restore the descriptor chain as it's polluted */
 717         dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n");
 718         memset(host->sg_cpu, 0, DESC_RING_BUF_SZ);
 719         dw_mci_idmac_init(host);
 720         return -EINVAL;
 721 }
 722
 723 static int dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
 724 {
 725         u32 temp;
 726         int ret;
 727
 728         if (host->dma_64bit_address == 1)
 729                 ret = dw_mci_prepare_desc64(host, host->data, sg_len);
 730         else
 731                 ret = dw_mci_prepare_desc32(host, host->data, sg_len);
 732
 733         if (ret)
 734                 goto out;
 735
 736         /* drain writebuffer */
 737         wmb();
 738
 739         /* Make sure to reset DMA in case we did PIO before this */
 740         dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
 741         dw_mci_idmac_reset(host);
 742
 743         /* Select IDMAC interface */
 744         temp = mci_readl(host, CTRL);
 745         temp |= SDMMC_CTRL_USE_IDMAC;
 746         mci_writel(host, CTRL, temp);
 747
 748         /* drain writebuffer */
 749         wmb();
 750
 751         /* Enable the IDMAC */
 752         temp = mci_readl(host, BMOD);
 753         temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
 754         mci_writel(host, BMOD, temp);
 755
 756         /* Start it running */
 757         mci_writel(host, PLDMND, 1);
 758
 759 out:
 760         return ret;
 761 }
 762
 763 static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
 764         .init = dw_mci_idmac_init,
 765         .start = dw_mci_idmac_start_dma,
 766         .stop = dw_mci_idmac_stop_dma,
 767         .complete = dw_mci_dmac_complete_dma,
 768         .cleanup = dw_mci_dma_cleanup,
 769 };
 770
 771 static void dw_mci_edmac_stop_dma(struct dw_mci *host)
 772 {
 773         dmaengine_terminate_async(host->dms->ch);
 774 }
 775
 776 static int dw_mci_edmac_start_dma(struct dw_mci *host,
 777                                             unsigned int sg_len)
 778 {
 779         struct dma_slave_config cfg;
 780         struct dma_async_tx_descriptor *desc = NULL;
 781         struct scatterlist *sgl = host->data->sg;
 782         static const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
 783         u32 sg_elems = host->data->sg_len;
 784         u32 fifoth_val;
 785         u32 fifo_offset = host->fifo_reg - host->regs;
 786         int ret = 0;
 787
 788         /* Set external dma config: burst size, burst width */
 789         memset(&cfg, 0, sizeof(cfg));
 790         cfg.dst_addr = host->phy_regs + fifo_offset;
 791         cfg.src_addr = cfg.dst_addr;
 792         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 793         cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 794
 795         /* Match burst msize with external dma config */
 796         fifoth_val = mci_readl(host, FIFOTH);
 797         cfg.dst_maxburst = mszs[(fifoth_val >> 28) & 0x7];
 798         cfg.src_maxburst = cfg.dst_maxburst;
 799
 800         if (host->data->flags & MMC_DATA_WRITE)
 801                 cfg.direction = DMA_MEM_TO_DEV;
 802         else
 803                 cfg.direction = DMA_DEV_TO_MEM;
 804
 805         ret = dmaengine_slave_config(host->dms->ch, &cfg);
 806         if (ret) {
 807                 dev_err(host->dev, "Failed to config edmac.\n");
 808                 return -EBUSY;
 809         }
 810
 811         desc = dmaengine_prep_slave_sg(host->dms->ch, sgl,
 812                                        sg_len, cfg.direction,
 813                                        DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 814         if (!desc) {
 815                 dev_err(host->dev, "Can't prepare slave sg.\n");
 816                 return -EBUSY;
 817         }
 818
 819         /* Set dw_mci_dmac_complete_dma as callback */
 820         desc->callback = dw_mci_dmac_complete_dma;
 821         desc->callback_param = (void *)host;
 822         dmaengine_submit(desc);
 823
 824         /* Flush cache before write */
 825         if (host->data->flags & MMC_DATA_WRITE)
 826                 dma_sync_sg_for_device(mmc_dev(host->slot->mmc), sgl,
 827                                        sg_elems, DMA_TO_DEVICE);
 828
 829         dma_async_issue_pending(host->dms->ch);
 830
 831         return 0;
 832 }
 833
 834 static int dw_mci_edmac_init(struct dw_mci *host)
 835 {
 836         /* Request external dma channel */
 837         host->dms = kzalloc(sizeof(struct dw_mci_dma_slave), GFP_KERNEL);
 838         if (!host->dms)
 839                 return -ENOMEM;
 840
 841         host->dms->ch = dma_request_chan(host->dev, "rx-tx");
 842         if (IS_ERR(host->dms->ch)) {
 843                 int ret = PTR_ERR(host->dms->ch);
 844
 845                 dev_err(host->dev, "Failed to get external DMA channel.\n");
 846                 kfree(host->dms);
 847                 host->dms = NULL;
 848                 return ret;
 849         }
 850
 851         return 0;
 852 }
 853
 854 static void dw_mci_edmac_exit(struct dw_mci *host)
 855 {
 856         if (host->dms) {
 857                 if (host->dms->ch) {
 858                         dma_release_channel(host->dms->ch);
 859                         host->dms->ch = NULL;
 860                 }
 861                 kfree(host->dms);
 862                 host->dms = NULL;
 863         }
 864 }
 865
 866 static const struct dw_mci_dma_ops dw_mci_edmac_ops = {
 867         .init = dw_mci_edmac_init,
 868         .exit = dw_mci_edmac_exit,
 869         .start = dw_mci_edmac_start_dma,
 870         .stop = dw_mci_edmac_stop_dma,
 871         .complete = dw_mci_dmac_complete_dma,
 872         .cleanup = dw_mci_dma_cleanup,
 873 };
 874
 875 static int dw_mci_pre_dma_transfer(struct dw_mci *host,
 876                                    struct mmc_data *data,
 877                                    int cookie)
 878 {
 879         struct scatterlist *sg;
 880         unsigned int i, sg_len;
 881
 882         if (data->host_cookie == COOKIE_PRE_MAPPED)
 883                 return data->sg_len;
 884
 885         /*
 886          * We don't do DMA on "complex" transfers, i.e. with
 887          * non-word-aligned buffers or lengths. Also, we don't bother
 888          * with all the DMA setup overhead for short transfers.
 889          */
 890         if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
 891                 return -EINVAL;
 892
 893         if (data->blksz & 3)
 894                 return -EINVAL;
 895
 896         for_each_sg(data->sg, sg, data->sg_len, i) {
 897                 if (sg->offset & 3 || sg->length & 3)
 898                         return -EINVAL;
 899         }
 900
 901         sg_len = dma_map_sg(host->dev,
 902                             data->sg,
 903                             data->sg_len,
 904                             mmc_get_dma_dir(data));
 905         if (sg_len == 0)
 906                 return -EINVAL;
 907
 908         data->host_cookie = cookie;
 909
 910         return sg_len;
 911 }
 912
 913 static void dw_mci_pre_req(struct mmc_host *mmc,
 914                            struct mmc_request *mrq)
 915 {
 916         struct dw_mci_slot *slot = mmc_priv(mmc);
 917         struct mmc_data *data = mrq->data;
 918
 919         if (!slot->host->use_dma || !data)
 920                 return;
 921
 922         /* This data might be unmapped at this time */
 923         data->host_cookie = COOKIE_UNMAPPED;
 924
 925         if (dw_mci_pre_dma_transfer(slot->host, mrq->data,
 926                                 COOKIE_PRE_MAPPED) < 0)
 927                 data->host_cookie = COOKIE_UNMAPPED;
 928 }
 929
 930 static void dw_mci_post_req(struct mmc_host *mmc,
 931                             struct mmc_request *mrq,
 932                             int err)
 933 {
 934         struct dw_mci_slot *slot = mmc_priv(mmc);
 935         struct mmc_data *data = mrq->data;
 936
 937         if (!slot->host->use_dma || !data)
 938                 return;
 939
 940         if (data->host_cookie != COOKIE_UNMAPPED)
 941                 dma_unmap_sg(slot->host->dev,
 942                              data->sg,
 943                              data->sg_len,
 944                              mmc_get_dma_dir(data));
 945         data->host_cookie = COOKIE_UNMAPPED;
 946 }
 947
 948 static int dw_mci_get_cd(struct mmc_host *mmc)
 949 {
 950         int present;
 951         struct dw_mci_slot *slot = mmc_priv(mmc);
 952         struct dw_mci *host = slot->host;
 953         int gpio_cd = mmc_gpio_get_cd(mmc);
 954
 955         /* Use platform get_cd function, else try onboard card detect */
 956         if (((mmc->caps & MMC_CAP_NEEDS_POLL)
 957                                 || !mmc_card_is_removable(mmc))) {
 958                 present = 1;
 959
 960                 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
 961                         if (mmc->caps & MMC_CAP_NEEDS_POLL) {
 962                                 dev_info(&mmc->class_dev,
 963                                         "card is polling.\n");
 964                         } else {
 965                                 dev_info(&mmc->class_dev,
 966                                         "card is non-removable.\n");
 967                         }
 968                         set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
 969                 }
 970
 971                 return present;
 972         } else if (gpio_cd >= 0)
 973                 present = gpio_cd;
 974         else
 975                 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
 976                         == 0 ? 1 : 0;
 977
 978         spin_lock_bh(&host->lock);
 979         if (present && !test_and_set_bit(DW_MMC_CARD_PRESENT, &slot->flags))
 980                 dev_dbg(&mmc->class_dev, "card is present\n");
 981         else if (!present &&
 982                         !test_and_clear_bit(DW_MMC_CARD_PRESENT, &slot->flags))
 983                 dev_dbg(&mmc->class_dev, "card is not present\n");
 984         spin_unlock_bh(&host->lock);
 985
 986         return present;
 987 }
 988
 989 static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
 990 {
 991         unsigned int blksz = data->blksz;
 992         static const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
 993         u32 fifo_width = 1 << host->data_shift;
 994         u32 blksz_depth = blksz / fifo_width, fifoth_val;
 995         u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
 996         int idx = ARRAY_SIZE(mszs) - 1;
 997
 998         /* pio should ship this scenario */
 999         if (!host->use_dma)
1000                 return;
1001
1002         tx_wmark = (host->fifo_depth) / 2;
1003         tx_wmark_invers = host->fifo_depth - tx_wmark;
1004
1005         /*
1006          * MSIZE is '1',
1007          * if blksz is not a multiple of the FIFO width
1008          */
1009         if (blksz % fifo_width)
1010                 goto done;
1011
1012         do {
1013                 if (!((blksz_depth % mszs[idx]) ||
1014                      (tx_wmark_invers % mszs[idx]))) {
1015                         msize = idx;
1016                         rx_wmark = mszs[idx] - 1;
1017                         break;
1018                 }
1019         } while (--idx > 0);
1020         /*
1021          * If idx is '0', it won't be tried
1022          * Thus, initial values are uesed
1023          */
1024 done:
1025         fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
1026         mci_writel(host, FIFOTH, fifoth_val);
1027 }
1028
1029 static void dw_mci_ctrl_thld(struct dw_mci *host, struct mmc_data *data)
1030 {
1031         unsigned int blksz = data->blksz;
1032         u32 blksz_depth, fifo_depth;
1033         u16 thld_size;
1034         u8 enable;
1035
1036         /*
1037          * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is
1038          * in the FIFO region, so we really shouldn't access it).
1039          */
1040         if (host->verid < DW_MMC_240A ||
1041                 (host->verid < DW_MMC_280A && data->flags & MMC_DATA_WRITE))
1042                 return;
1043
1044         /*
1045          * Card write Threshold is introduced since 2.80a
1046          * It's used when HS400 mode is enabled.
1047          */
1048         if (data->flags & MMC_DATA_WRITE &&
1049                 host->timing != MMC_TIMING_MMC_HS400)
1050                 goto disable;
1051
1052         if (data->flags & MMC_DATA_WRITE)
1053                 enable = SDMMC_CARD_WR_THR_EN;
1054         else
1055                 enable = SDMMC_CARD_RD_THR_EN;
1056
1057         if (host->timing != MMC_TIMING_MMC_HS200 &&
1058             host->timing != MMC_TIMING_UHS_SDR104 &&
1059             host->timing != MMC_TIMING_MMC_HS400)
1060                 goto disable;
1061
1062         blksz_depth = blksz / (1 << host->data_shift);
1063         fifo_depth = host->fifo_depth;
1064
1065         if (blksz_depth > fifo_depth)
1066                 goto disable;
1067
1068         /*
1069          * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
1070          * If (blksz_depth) <  (fifo_depth >> 1), should be thld_size = blksz
1071          * Currently just choose blksz.
1072          */
1073         thld_size = blksz;
1074         mci_writel(host, CDTHRCTL, SDMMC_SET_THLD(thld_size, enable));
1075         return;
1076
1077 disable:
1078         mci_writel(host, CDTHRCTL, 0);
1079 }
1080
1081 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
1082 {
1083         unsigned long irqflags;
1084         int sg_len;
1085         u32 temp;
1086
1087         host->using_dma = 0;
1088
1089         /* If we don't have a channel, we can't do DMA */
1090         if (!host->use_dma)
1091                 return -ENODEV;
1092
1093         sg_len = dw_mci_pre_dma_transfer(host, data, COOKIE_MAPPED);
1094         if (sg_len < 0) {
1095                 host->dma_ops->stop(host);
1096                 return sg_len;
1097         }
1098
1099         host->using_dma = 1;
1100
1101         if (host->use_dma == TRANS_MODE_IDMAC)
1102                 dev_vdbg(host->dev,
1103                          "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
1104                          (unsigned long)host->sg_cpu,
1105                          (unsigned long)host->sg_dma,
1106                          sg_len);
1107
1108         /*
1109          * Decide the MSIZE and RX/TX Watermark.
1110          * If current block size is same with previous size,
1111          * no need to update fifoth.
1112          */
1113         if (host->prev_blksz != data->blksz)
1114                 dw_mci_adjust_fifoth(host, data);
1115
1116         /* Enable the DMA interface */
1117         temp = mci_readl(host, CTRL);
1118         temp |= SDMMC_CTRL_DMA_ENABLE;
1119         mci_writel(host, CTRL, temp);
1120
1121         /* Disable RX/TX IRQs, let DMA handle it */
1122         spin_lock_irqsave(&host->irq_lock, irqflags);
1123         temp = mci_readl(host, INTMASK);
1124         temp  &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
1125         mci_writel(host, INTMASK, temp);
1126         spin_unlock_irqrestore(&host->irq_lock, irqflags);
1127
1128         if (host->dma_ops->start(host, sg_len)) {
1129                 host->dma_ops->stop(host);
1130                 /* We can't do DMA, try PIO for this one */
1131                 dev_dbg(host->dev,
1132                         "%s: fall back to PIO mode for current transfer\n",
1133                         __func__);
1134                 return -ENODEV;
1135         }
1136
1137         return 0;
1138 }
1139
1140 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
1141 {
1142         unsigned long irqflags;
1143         int flags = SG_MITER_ATOMIC;
1144         u32 temp;
1145
1146         data->error = -EINPROGRESS;
1147
1148         WARN_ON(host->data);
1149         host->sg = NULL;
1150         host->data = data;
1151
1152         if (data->flags & MMC_DATA_READ)
1153                 host->dir_status = DW_MCI_RECV_STATUS;
1154         else
1155                 host->dir_status = DW_MCI_SEND_STATUS;
1156
1157         dw_mci_ctrl_thld(host, data);
1158
1159         if (dw_mci_submit_data_dma(host, data)) {
1160                 if (host->data->flags & MMC_DATA_READ)
1161                         flags |= SG_MITER_TO_SG;
1162                 else
1163                         flags |= SG_MITER_FROM_SG;
1164
1165                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
1166                 host->sg = data->sg;
1167                 host->part_buf_start = 0;
1168                 host->part_buf_count = 0;
1169
1170                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
1171
1172                 spin_lock_irqsave(&host->irq_lock, irqflags);
1173                 temp = mci_readl(host, INTMASK);
1174                 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
1175                 mci_writel(host, INTMASK, temp);
1176                 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1177
1178                 temp = mci_readl(host, CTRL);
1179                 temp &= ~SDMMC_CTRL_DMA_ENABLE;
1180                 mci_writel(host, CTRL, temp);
1181
1182                 /*
1183                  * Use the initial fifoth_val for PIO mode. If wm_algined
1184                  * is set, we set watermark same as data size.
1185                  * If next issued data may be transfered by DMA mode,
1186                  * prev_blksz should be invalidated.
1187                  */
1188                 if (host->wm_aligned)
1189                         dw_mci_adjust_fifoth(host, data);
1190                 else
1191                         mci_writel(host, FIFOTH, host->fifoth_val);
1192                 host->prev_blksz = 0;
1193         } else {
1194                 /*
1195                  * Keep the current block size.
1196                  * It will be used to decide whether to update
1197                  * fifoth register next time.
1198                  */
1199                 host->prev_blksz = data->blksz;
1200         }
1201 }
1202
1203 static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
1204 {
1205         struct dw_mci *host = slot->host;
1206         unsigned int clock = slot->clock;
1207         u32 div;
1208         u32 clk_en_a;
1209         u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT;
1210
1211         /* We must continue to set bit 28 in CMD until the change is complete */
1212         if (host->state == STATE_WAITING_CMD11_DONE)
1213                 sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH;
1214
1215         slot->mmc->actual_clock = 0;
1216
1217         if (!clock) {
1218                 mci_writel(host, CLKENA, 0);
1219                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1220         } else if (clock != host->current_speed || force_clkinit) {
1221                 div = host->bus_hz / clock;
1222                 if (host->bus_hz % clock && host->bus_hz > clock)
1223                         /*
1224                          * move the + 1 after the divide to prevent
1225                          * over-clocking the card.
1226                          */
1227                         div += 1;
1228
1229                 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
1230
1231                 if ((clock != slot->__clk_old &&
1232                         !test_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags)) ||
1233                         force_clkinit) {
1234                         /* Silent the verbose log if calling from PM context */
1235                         if (!force_clkinit)
1236                                 dev_info(&slot->mmc->class_dev,
1237                                          "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
1238                                          slot->id, host->bus_hz, clock,
1239                                          div ? ((host->bus_hz / div) >> 1) :
1240                                          host->bus_hz, div);
1241
1242                         /*
1243                          * If card is polling, display the message only
1244                          * one time at boot time.
1245                          */
1246                         if (slot->mmc->caps & MMC_CAP_NEEDS_POLL &&
1247                                         slot->mmc->f_min == clock)
1248                                 set_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags);
1249                 }
1250
1251                 /* disable clock */
1252                 mci_writel(host, CLKENA, 0);
1253                 mci_writel(host, CLKSRC, 0);
1254
1255                 /* inform CIU */
1256                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1257
1258                 /* set clock to desired speed */
1259                 mci_writel(host, CLKDIV, div);
1260
1261                 /* inform CIU */
1262                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1263
1264                 /* enable clock; only low power if no SDIO */
1265                 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
1266                 if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags))
1267                         clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
1268                 mci_writel(host, CLKENA, clk_en_a);
1269
1270                 /* inform CIU */
1271                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1272
1273                 /* keep the last clock value that was requested from core */
1274                 slot->__clk_old = clock;
1275                 slot->mmc->actual_clock = div ? ((host->bus_hz / div) >> 1) :
1276                                           host->bus_hz;
1277         }
1278
1279         host->current_speed = clock;
1280
1281         /* Set the current slot bus width */
1282         mci_writel(host, CTYPE, (slot->ctype << slot->id));
1283 }
1284
1285 static void dw_mci_set_data_timeout(struct dw_mci *host,
1286                                     unsigned int timeout_ns)
1287 {
1288         const struct dw_mci_drv_data *drv_data = host->drv_data;
1289         u32 clk_div, tmout;
1290         u64 tmp;
1291
1292         if (drv_data && drv_data->set_data_timeout)
1293                 return drv_data->set_data_timeout(host, timeout_ns);
1294
1295         clk_div = (mci_readl(host, CLKDIV) & 0xFF) * 2;
1296         if (clk_div == 0)
1297                 clk_div = 1;
1298
1299         tmp = DIV_ROUND_UP_ULL((u64)timeout_ns * host->bus_hz, NSEC_PER_SEC);
1300         tmp = DIV_ROUND_UP_ULL(tmp, clk_div);
1301
1302         /* TMOUT[7:0] (RESPONSE_TIMEOUT) */
1303         tmout = 0xFF; /* Set maximum */
1304
1305         /* TMOUT[31:8] (DATA_TIMEOUT) */
1306         if (!tmp || tmp > 0xFFFFFF)
1307                 tmout |= (0xFFFFFF << 8);
1308         else
1309                 tmout |= (tmp & 0xFFFFFF) << 8;
1310
1311         mci_writel(host, TMOUT, tmout);
1312         dev_dbg(host->dev, "timeout_ns: %u => TMOUT[31:8]: %#08x",
1313                 timeout_ns, tmout >> 8);
1314 }
1315
1316 static void __dw_mci_start_request(struct dw_mci *host,
1317                                    struct dw_mci_slot *slot,
1318                                    struct mmc_command *cmd)
1319 {
1320         struct mmc_request *mrq;
1321         struct mmc_data *data;
1322         u32 cmdflags;
1323
1324         mrq = slot->mrq;
1325
1326         host->mrq = mrq;
1327
1328         host->pending_events = 0;
1329         host->completed_events = 0;
1330         host->cmd_status = 0;
1331         host->data_status = 0;
1332         host->dir_status = 0;
1333
1334         data = cmd->data;
1335         if (data) {
1336                 dw_mci_set_data_timeout(host, data->timeout_ns);
1337                 mci_writel(host, BYTCNT, data->blksz*data->blocks);
1338                 mci_writel(host, BLKSIZ, data->blksz);
1339         }
1340
1341         cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
1342
1343         /* this is the first command, send the initialization clock */
1344         if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
1345                 cmdflags |= SDMMC_CMD_INIT;
1346
1347         if (data) {
1348                 dw_mci_submit_data(host, data);
1349                 wmb(); /* drain writebuffer */
1350         }
1351
1352         dw_mci_start_command(host, cmd, cmdflags);
1353
1354         if (cmd->opcode == SD_SWITCH_VOLTAGE) {
1355                 unsigned long irqflags;
1356
1357                 /*
1358                  * Databook says to fail after 2ms w/ no response, but evidence
1359                  * shows that sometimes the cmd11 interrupt takes over 130ms.
1360                  * We'll set to 500ms, plus an extra jiffy just in case jiffies
1361                  * is just about to roll over.
1362                  *
1363                  * We do this whole thing under spinlock and only if the
1364                  * command hasn't already completed (indicating the irq
1365                  * already ran so we don't want the timeout).
1366                  */
1367                 spin_lock_irqsave(&host->irq_lock, irqflags);
1368                 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
1369                         mod_timer(&host->cmd11_timer,
1370                                 jiffies + msecs_to_jiffies(500) + 1);
1371                 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1372         }
1373
1374         host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd);
1375 }
1376
1377 static void dw_mci_start_request(struct dw_mci *host,
1378                                  struct dw_mci_slot *slot)
1379 {
1380         struct mmc_request *mrq = slot->mrq;
1381         struct mmc_command *cmd;
1382
1383         cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
1384         __dw_mci_start_request(host, slot, cmd);
1385 }
1386
1387 /* must be called with host->lock held */
1388 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
1389                                  struct mmc_request *mrq)
1390 {
1391         dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1392                  host->state);
1393
1394         slot->mrq = mrq;
1395
1396         if (host->state == STATE_WAITING_CMD11_DONE) {
1397                 dev_warn(&slot->mmc->class_dev,
1398                          "Voltage change didn't complete\n");
1399                 /*
1400                  * this case isn't expected to happen, so we can
1401                  * either crash here or just try to continue on
1402                  * in the closest possible state
1403                  */
1404                 host->state = STATE_IDLE;
1405         }
1406
1407         if (host->state == STATE_IDLE) {
1408                 host->state = STATE_SENDING_CMD;
1409                 dw_mci_start_request(host, slot);
1410         } else {
1411                 list_add_tail(&slot->queue_node, &host->queue);
1412         }
1413 }
1414
1415 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1416 {
1417         struct dw_mci_slot *slot = mmc_priv(mmc);
1418         struct dw_mci *host = slot->host;
1419
1420         WARN_ON(slot->mrq);
1421
1422         /*
1423          * The check for card presence and queueing of the request must be
1424          * atomic, otherwise the card could be removed in between and the
1425          * request wouldn't fail until another card was inserted.
1426          */
1427
1428         if (!dw_mci_get_cd(mmc)) {
1429                 mrq->cmd->error = -ENOMEDIUM;
1430                 mmc_request_done(mmc, mrq);
1431                 return;
1432         }
1433
1434         spin_lock_bh(&host->lock);
1435
1436         dw_mci_queue_request(host, slot, mrq);
1437
1438         spin_unlock_bh(&host->lock);
1439 }
1440
1441 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1442 {
1443         struct dw_mci_slot *slot = mmc_priv(mmc);
1444         const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
1445         u32 regs;
1446         int ret;
1447
1448         switch (ios->bus_width) {
1449         case MMC_BUS_WIDTH_4:
1450                 slot->ctype = SDMMC_CTYPE_4BIT;
1451                 break;
1452         case MMC_BUS_WIDTH_8:
1453                 slot->ctype = SDMMC_CTYPE_8BIT;
1454                 break;
1455         default:
1456                 /* set default 1 bit mode */
1457                 slot->ctype = SDMMC_CTYPE_1BIT;
1458         }
1459
1460         regs = mci_readl(slot->host, UHS_REG);
1461
1462         /* DDR mode set */
1463         if (ios->timing == MMC_TIMING_MMC_DDR52 ||
1464             ios->timing == MMC_TIMING_UHS_DDR50 ||
1465             ios->timing == MMC_TIMING_MMC_HS400)
1466                 regs |= ((0x1 << slot->id) << 16);
1467         else
1468                 regs &= ~((0x1 << slot->id) << 16);
1469
1470         mci_writel(slot->host, UHS_REG, regs);
1471         slot->host->timing = ios->timing;
1472
1473         /*
1474          * Use mirror of ios->clock to prevent race with mmc
1475          * core ios update when finding the minimum.
1476          */
1477         slot->clock = ios->clock;
1478
1479         if (drv_data && drv_data->set_ios)
1480                 drv_data->set_ios(slot->host, ios);
1481
1482         switch (ios->power_mode) {
1483         case MMC_POWER_UP:
1484                 if (!IS_ERR(mmc->supply.vmmc)) {
1485                         ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1486                                         ios->vdd);
1487                         if (ret) {
1488                                 dev_err(slot->host->dev,
1489                                         "failed to enable vmmc regulator\n");
1490                                 /*return, if failed turn on vmmc*/
1491                                 return;
1492                         }
1493                 }
1494                 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
1495                 regs = mci_readl(slot->host, PWREN);
1496                 regs |= (1 << slot->id);
1497                 mci_writel(slot->host, PWREN, regs);
1498                 break;
1499         case MMC_POWER_ON:
1500                 if (!slot->host->vqmmc_enabled) {
1501                         if (!IS_ERR(mmc->supply.vqmmc)) {
1502                                 ret = regulator_enable(mmc->supply.vqmmc);
1503                                 if (ret < 0)
1504                                         dev_err(slot->host->dev,
1505                                                 "failed to enable vqmmc\n");
1506                                 else
1507                                         slot->host->vqmmc_enabled = true;
1508
1509                         } else {
1510                                 /* Keep track so we don't reset again */
1511                                 slot->host->vqmmc_enabled = true;
1512                         }
1513
1514                         /* Reset our state machine after powering on */
1515                         dw_mci_ctrl_reset(slot->host,
1516                                           SDMMC_CTRL_ALL_RESET_FLAGS);
1517                 }
1518
1519                 /* Adjust clock / bus width after power is up */
1520                 dw_mci_setup_bus(slot, false);
1521
1522                 break;
1523         case MMC_POWER_OFF:
1524                 /* Turn clock off before power goes down */
1525                 dw_mci_setup_bus(slot, false);
1526
1527                 if (!IS_ERR(mmc->supply.vmmc))
1528                         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1529
1530                 if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled)
1531                         regulator_disable(mmc->supply.vqmmc);
1532                 slot->host->vqmmc_enabled = false;
1533
1534                 regs = mci_readl(slot->host, PWREN);
1535                 regs &= ~(1 << slot->id);
1536                 mci_writel(slot->host, PWREN, regs);
1537                 break;
1538         default:
1539                 break;
1540         }
1541
1542         if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0)
1543                 slot->host->state = STATE_IDLE;
1544 }
1545
1546 static int dw_mci_card_busy(struct mmc_host *mmc)
1547 {
1548         struct dw_mci_slot *slot = mmc_priv(mmc);
1549         u32 status;
1550
1551         /*
1552          * Check the busy bit which is low when DAT[3:0]
1553          * (the data lines) are 0000
1554          */
1555         status = mci_readl(slot->host, STATUS);
1556
1557         return !!(status & SDMMC_STATUS_BUSY);
1558 }
1559
1560 static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1561 {
1562         struct dw_mci_slot *slot = mmc_priv(mmc);
1563         struct dw_mci *host = slot->host;
1564         const struct dw_mci_drv_data *drv_data = host->drv_data;
1565         u32 uhs;
1566         u32 v18 = SDMMC_UHS_18V << slot->id;
1567         int ret;
1568
1569         if (drv_data && drv_data->switch_voltage)
1570                 return drv_data->switch_voltage(mmc, ios);
1571
1572         /*
1573          * Program the voltage.  Note that some instances of dw_mmc may use
1574          * the UHS_REG for this.  For other instances (like exynos) the UHS_REG
1575          * does no harm but you need to set the regulator directly.  Try both.
1576          */
1577         uhs = mci_readl(host, UHS_REG);
1578         if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1579                 uhs &= ~v18;
1580         else
1581                 uhs |= v18;
1582
1583         if (!IS_ERR(mmc->supply.vqmmc)) {
1584                 ret = mmc_regulator_set_vqmmc(mmc, ios);
1585                 if (ret < 0) {
1586                         dev_dbg(&mmc->class_dev,
1587                                          "Regulator set error %d - %s V\n",
1588                                          ret, uhs & v18 ? "1.8" : "3.3");
1589                         return ret;
1590                 }
1591         }
1592         mci_writel(host, UHS_REG, uhs);
1593
1594         return 0;
1595 }
1596
1597 static int dw_mci_get_ro(struct mmc_host *mmc)
1598 {
1599         int read_only;
1600         struct dw_mci_slot *slot = mmc_priv(mmc);
1601         int gpio_ro = mmc_gpio_get_ro(mmc);
1602
1603         /* Use platform get_ro function, else try on board write protect */
1604         if (gpio_ro >= 0)
1605                 read_only = gpio_ro;
1606         else
1607                 read_only =
1608                         mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
1609
1610         dev_dbg(&mmc->class_dev, "card is %s\n",
1611                 read_only ? "read-only" : "read-write");
1612
1613         return read_only;
1614 }
1615
1616 static void dw_mci_hw_reset(struct mmc_host *mmc)
1617 {
1618         struct dw_mci_slot *slot = mmc_priv(mmc);
1619         struct dw_mci *host = slot->host;
1620         int reset;
1621
1622         if (host->use_dma == TRANS_MODE_IDMAC)
1623                 dw_mci_idmac_reset(host);
1624
1625         if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET |
1626                                      SDMMC_CTRL_FIFO_RESET))
1627                 return;
1628
1629         /*
1630          * According to eMMC spec, card reset procedure:
1631          * tRstW >= 1us:   RST_n pulse width
1632          * tRSCA >= 200us: RST_n to Command time
1633          * tRSTH >= 1us:   RST_n high period
1634          */
1635         reset = mci_readl(host, RST_N);
1636         reset &= ~(SDMMC_RST_HWACTIVE << slot->id);
1637         mci_writel(host, RST_N, reset);
1638         usleep_range(1, 2);
1639         reset |= SDMMC_RST_HWACTIVE << slot->id;
1640         mci_writel(host, RST_N, reset);
1641         usleep_range(200, 300);
1642 }
1643
1644 static void dw_mci_prepare_sdio_irq(struct dw_mci_slot *slot, bool prepare)
1645 {
1646         struct dw_mci *host = slot->host;
1647         const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
1648         u32 clk_en_a_old;
1649         u32 clk_en_a;
1650
1651         /*
1652          * Low power mode will stop the card clock when idle.  According to the
1653          * description of the CLKENA register we should disable low power mode
1654          * for SDIO cards if we need SDIO interrupts to work.
1655          */
1656
1657         clk_en_a_old = mci_readl(host, CLKENA);
1658         if (prepare) {
1659                 set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1660                 clk_en_a = clk_en_a_old & ~clken_low_pwr;
1661         } else {
1662                 clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1663                 clk_en_a = clk_en_a_old | clken_low_pwr;
1664         }
1665
1666         if (clk_en_a != clk_en_a_old) {
1667                 mci_writel(host, CLKENA, clk_en_a);
1668                 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT,
1669                              0);
1670         }
1671 }
1672
1673 static void __dw_mci_enable_sdio_irq(struct dw_mci_slot *slot, int enb)
1674 {
1675         struct dw_mci *host = slot->host;
1676         unsigned long irqflags;
1677         u32 int_mask;
1678
1679         spin_lock_irqsave(&host->irq_lock, irqflags);
1680
1681         /* Enable/disable Slot Specific SDIO interrupt */
1682         int_mask = mci_readl(host, INTMASK);
1683         if (enb)
1684                 int_mask |= SDMMC_INT_SDIO(slot->sdio_id);
1685         else
1686                 int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id);
1687         mci_writel(host, INTMASK, int_mask);
1688
1689         spin_unlock_irqrestore(&host->irq_lock, irqflags);
1690 }
1691
1692 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
1693 {
1694         struct dw_mci_slot *slot = mmc_priv(mmc);
1695         struct dw_mci *host = slot->host;
1696
1697         dw_mci_prepare_sdio_irq(slot, enb);
1698         __dw_mci_enable_sdio_irq(slot, enb);
1699
1700         /* Avoid runtime suspending the device when SDIO IRQ is enabled */
1701         if (enb)
1702                 pm_runtime_get_noresume(host->dev);
1703         else
1704                 pm_runtime_put_noidle(host->dev);
1705 }
1706
1707 static void dw_mci_ack_sdio_irq(struct mmc_host *mmc)
1708 {
1709         struct dw_mci_slot *slot = mmc_priv(mmc);
1710
1711         __dw_mci_enable_sdio_irq(slot, 1);
1712 }
1713
1714 static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1715 {
1716         struct dw_mci_slot *slot = mmc_priv(mmc);
1717         struct dw_mci *host = slot->host;
1718         const struct dw_mci_drv_data *drv_data = host->drv_data;
1719         int err = -EINVAL;
1720
1721         if (drv_data && drv_data->execute_tuning)
1722                 err = drv_data->execute_tuning(slot, opcode);
1723         return err;
1724 }
1725
1726 static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc,
1727                                        struct mmc_ios *ios)
1728 {
1729         struct dw_mci_slot *slot = mmc_priv(mmc);
1730         struct dw_mci *host = slot->host;
1731         const struct dw_mci_drv_data *drv_data = host->drv_data;
1732
1733         if (drv_data && drv_data->prepare_hs400_tuning)
1734                 return drv_data->prepare_hs400_tuning(host, ios);
1735
1736         return 0;
1737 }
1738
1739 static bool dw_mci_reset(struct dw_mci *host)
1740 {
1741         u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET;
1742         bool ret = false;
1743         u32 status = 0;
1744
1745         /*
1746          * Resetting generates a block interrupt, hence setting
1747          * the scatter-gather pointer to NULL.
1748          */
1749         if (host->sg) {
1750                 sg_miter_stop(&host->sg_miter);
1751                 host->sg = NULL;
1752         }
1753
1754         if (host->use_dma)
1755                 flags |= SDMMC_CTRL_DMA_RESET;
1756
1757         if (dw_mci_ctrl_reset(host, flags)) {
1758                 /*
1759                  * In all cases we clear the RAWINTS
1760                  * register to clear any interrupts.
1761                  */
1762                 mci_writel(host, RINTSTS, 0xFFFFFFFF);
1763
1764                 if (!host->use_dma) {
1765                         ret = true;
1766                         goto ciu_out;
1767                 }
1768
1769                 /* Wait for dma_req to be cleared */
1770                 if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS,
1771                                               status,
1772                                               !(status & SDMMC_STATUS_DMA_REQ),
1773                                               1, 500 * USEC_PER_MSEC)) {
1774                         dev_err(host->dev,
1775                                 "%s: Timeout waiting for dma_req to be cleared\n",
1776                                 __func__);
1777                         goto ciu_out;
1778                 }
1779
1780                 /* when using DMA next we reset the fifo again */
1781                 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET))
1782                         goto ciu_out;
1783         } else {
1784                 /* if the controller reset bit did clear, then set clock regs */
1785                 if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) {
1786                         dev_err(host->dev,
1787                                 "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n",
1788                                 __func__);
1789                         goto ciu_out;
1790                 }
1791         }
1792
1793         if (host->use_dma == TRANS_MODE_IDMAC)
1794                 /* It is also required that we reinit idmac */
1795                 dw_mci_idmac_init(host);
1796
1797         ret = true;
1798
1799 ciu_out:
1800         /* After a CTRL reset we need to have CIU set clock registers  */
1801         mci_send_cmd(host->slot, SDMMC_CMD_UPD_CLK, 0);
1802
1803         return ret;
1804 }
1805
1806 static const struct mmc_host_ops dw_mci_ops = {
1807         .request                = dw_mci_request,
1808         .pre_req                = dw_mci_pre_req,
1809         .post_req               = dw_mci_post_req,
1810         .set_ios                = dw_mci_set_ios,
1811         .get_ro                 = dw_mci_get_ro,
1812         .get_cd                 = dw_mci_get_cd,
1813         .card_hw_reset          = dw_mci_hw_reset,
1814         .enable_sdio_irq        = dw_mci_enable_sdio_irq,
1815         .ack_sdio_irq           = dw_mci_ack_sdio_irq,
1816         .execute_tuning         = dw_mci_execute_tuning,
1817         .card_busy              = dw_mci_card_busy,
1818         .start_signal_voltage_switch = dw_mci_switch_voltage,
1819         .prepare_hs400_tuning   = dw_mci_prepare_hs400_tuning,
1820 };
1821
1822 #ifdef CONFIG_FAULT_INJECTION
1823 static enum hrtimer_restart dw_mci_fault_timer(struct hrtimer *t)
1824 {
1825         struct dw_mci *host = container_of(t, struct dw_mci, fault_timer);
1826         unsigned long flags;
1827
1828         spin_lock_irqsave(&host->irq_lock, flags);
1829
1830         /*
1831          * Only inject an error if we haven't already got an error or data over
1832          * interrupt.
1833          */
1834         if (!host->data_status) {
1835                 host->data_status = SDMMC_INT_DCRC;
1836                 set_bit(EVENT_DATA_ERROR, &host->pending_events);
1837                 tasklet_schedule(&host->tasklet);
1838         }
1839
1840         spin_unlock_irqrestore(&host->irq_lock, flags);
1841
1842         return HRTIMER_NORESTART;
1843 }
1844
1845 static void dw_mci_start_fault_timer(struct dw_mci *host)
1846 {
1847         struct mmc_data *data = host->data;
1848
1849         if (!data || data->blocks <= 1)
1850                 return;
1851
1852         if (!should_fail(&host->fail_data_crc, 1))
1853                 return;
1854
1855         /*
1856          * Try to inject the error at random points during the data transfer.
1857          */
1858         hrtimer_start(&host->fault_timer,
1859                       ms_to_ktime(get_random_u32_below(25)),
1860                       HRTIMER_MODE_REL);
1861 }
1862
1863 static void dw_mci_stop_fault_timer(struct dw_mci *host)
1864 {
1865         hrtimer_cancel(&host->fault_timer);
1866 }
1867
1868 static void dw_mci_init_fault(struct dw_mci *host)
1869 {
1870         host->fail_data_crc = (struct fault_attr) FAULT_ATTR_INITIALIZER;
1871
1872         hrtimer_init(&host->fault_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1873         host->fault_timer.function = dw_mci_fault_timer;
1874 }
1875 #else
1876 static void dw_mci_init_fault(struct dw_mci *host)
1877 {
1878 }
1879
1880 static void dw_mci_start_fault_timer(struct dw_mci *host)
1881 {
1882 }
1883
1884 static void dw_mci_stop_fault_timer(struct dw_mci *host)
1885 {
1886 }
1887 #endif
1888
1889 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
1890         __releases(&host->lock)
1891         __acquires(&host->lock)
1892 {
1893         struct dw_mci_slot *slot;
1894         struct mmc_host *prev_mmc = host->slot->mmc;
1895
1896         WARN_ON(host->cmd || host->data);
1897
1898         host->slot->mrq = NULL;
1899         host->mrq = NULL;
1900         if (!list_empty(&host->queue)) {
1901                 slot = list_entry(host->queue.next,
1902                                   struct dw_mci_slot, queue_node);
1903                 list_del(&slot->queue_node);
1904                 dev_vdbg(host->dev, "list not empty: %s is next\n",
1905                          mmc_hostname(slot->mmc));
1906                 host->state = STATE_SENDING_CMD;
1907                 dw_mci_start_request(host, slot);
1908         } else {
1909                 dev_vdbg(host->dev, "list empty\n");
1910
1911                 if (host->state == STATE_SENDING_CMD11)
1912                         host->state = STATE_WAITING_CMD11_DONE;
1913                 else
1914                         host->state = STATE_IDLE;
1915         }
1916
1917         spin_unlock(&host->lock);
1918         mmc_request_done(prev_mmc, mrq);
1919         spin_lock(&host->lock);
1920 }
1921
1922 static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
1923 {
1924         u32 status = host->cmd_status;
1925
1926         host->cmd_status = 0;
1927
1928         /* Read the response from the card (up to 16 bytes) */
1929         if (cmd->flags & MMC_RSP_PRESENT) {
1930                 if (cmd->flags & MMC_RSP_136) {
1931                         cmd->resp[3] = mci_readl(host, RESP0);
1932                         cmd->resp[2] = mci_readl(host, RESP1);
1933                         cmd->resp[1] = mci_readl(host, RESP2);
1934                         cmd->resp[0] = mci_readl(host, RESP3);
1935                 } else {
1936                         cmd->resp[0] = mci_readl(host, RESP0);
1937                         cmd->resp[1] = 0;
1938                         cmd->resp[2] = 0;
1939                         cmd->resp[3] = 0;
1940                 }
1941         }
1942
1943         if (status & SDMMC_INT_RTO)
1944                 cmd->error = -ETIMEDOUT;
1945         else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
1946                 cmd->error = -EILSEQ;
1947         else if (status & SDMMC_INT_RESP_ERR)
1948                 cmd->error = -EIO;
1949         else
1950                 cmd->error = 0;
1951
1952         return cmd->error;
1953 }
1954
1955 static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data)
1956 {
1957         u32 status = host->data_status;
1958
1959         if (status & DW_MCI_DATA_ERROR_FLAGS) {
1960                 if (status & SDMMC_INT_DRTO) {
1961                         data->error = -ETIMEDOUT;
1962                 } else if (status & SDMMC_INT_DCRC) {
1963                         data->error = -EILSEQ;
1964                 } else if (status & SDMMC_INT_EBE) {
1965                         if (host->dir_status ==
1966                                 DW_MCI_SEND_STATUS) {
1967                                 /*
1968                                  * No data CRC status was returned.
1969                                  * The number of bytes transferred
1970                                  * will be exaggerated in PIO mode.
1971                                  */
1972                                 data->bytes_xfered = 0;
1973                                 data->error = -ETIMEDOUT;
1974                         } else if (host->dir_status ==
1975                                         DW_MCI_RECV_STATUS) {
1976                                 data->error = -EILSEQ;
1977                         }
1978                 } else {
1979                         /* SDMMC_INT_SBE is included */
1980                         data->error = -EILSEQ;
1981                 }
1982
1983                 dev_dbg(host->dev, "data error, status 0x%08x\n", status);
1984
1985                 /*
1986                  * After an error, there may be data lingering
1987                  * in the FIFO
1988                  */
1989                 dw_mci_reset(host);
1990         } else {
1991                 data->bytes_xfered = data->blocks * data->blksz;
1992                 data->error = 0;
1993         }
1994
1995         return data->error;
1996 }
1997
1998 static void dw_mci_set_drto(struct dw_mci *host)
1999 {
2000         const struct dw_mci_drv_data *drv_data = host->drv_data;
2001         unsigned int drto_clks;
2002         unsigned int drto_div;
2003         unsigned int drto_ms;
2004         unsigned long irqflags;
2005
2006         if (drv_data && drv_data->get_drto_clks)
2007                 drto_clks = drv_data->get_drto_clks(host);
2008         else
2009                 drto_clks = mci_readl(host, TMOUT) >> 8;
2010         drto_div = (mci_readl(host, CLKDIV) & 0xff) * 2;
2011         if (drto_div == 0)
2012                 drto_div = 1;
2013
2014         drto_ms = DIV_ROUND_UP_ULL((u64)MSEC_PER_SEC * drto_clks * drto_div,
2015                                    host->bus_hz);
2016
2017         dev_dbg(host->dev, "drto_ms: %u\n", drto_ms);
2018
2019         /* add a bit spare time */
2020         drto_ms += 10;
2021
2022         spin_lock_irqsave(&host->irq_lock, irqflags);
2023         if (!test_bit(EVENT_DATA_COMPLETE, &host->pending_events))
2024                 mod_timer(&host->dto_timer,
2025                           jiffies + msecs_to_jiffies(drto_ms));
2026         spin_unlock_irqrestore(&host->irq_lock, irqflags);
2027 }
2028
2029 static bool dw_mci_clear_pending_cmd_complete(struct dw_mci *host)
2030 {
2031         if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
2032                 return false;
2033
2034         /*
2035          * Really be certain that the timer has stopped.  This is a bit of
2036          * paranoia and could only really happen if we had really bad
2037          * interrupt latency and the interrupt routine and timeout were
2038          * running concurrently so that the del_timer() in the interrupt
2039          * handler couldn't run.
2040          */
2041         WARN_ON(del_timer_sync(&host->cto_timer));
2042         clear_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2043
2044         return true;
2045 }
2046
2047 static bool dw_mci_clear_pending_data_complete(struct dw_mci *host)
2048 {
2049         if (!test_bit(EVENT_DATA_COMPLETE, &host->pending_events))
2050                 return false;
2051
2052         /* Extra paranoia just like dw_mci_clear_pending_cmd_complete() */
2053         WARN_ON(del_timer_sync(&host->dto_timer));
2054         clear_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2055
2056         return true;
2057 }
2058
2059 static void dw_mci_tasklet_func(struct tasklet_struct *t)
2060 {
2061         struct dw_mci *host = from_tasklet(host, t, tasklet);
2062         struct mmc_data *data;
2063         struct mmc_command *cmd;
2064         struct mmc_request *mrq;
2065         enum dw_mci_state state;
2066         enum dw_mci_state prev_state;
2067         unsigned int err;
2068
2069         spin_lock(&host->lock);
2070
2071         state = host->state;
2072         data = host->data;
2073         mrq = host->mrq;
2074
2075         do {
2076                 prev_state = state;
2077
2078                 switch (state) {
2079                 case STATE_IDLE:
2080                 case STATE_WAITING_CMD11_DONE:
2081                         break;
2082
2083                 case STATE_SENDING_CMD11:
2084                 case STATE_SENDING_CMD:
2085                         if (!dw_mci_clear_pending_cmd_complete(host))
2086                                 break;
2087
2088                         cmd = host->cmd;
2089                         host->cmd = NULL;
2090                         set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
2091                         err = dw_mci_command_complete(host, cmd);
2092                         if (cmd == mrq->sbc && !err) {
2093                                 __dw_mci_start_request(host, host->slot,
2094                                                        mrq->cmd);
2095                                 goto unlock;
2096                         }
2097
2098                         if (cmd->data && err) {
2099                                 /*
2100                                  * During UHS tuning sequence, sending the stop
2101                                  * command after the response CRC error would
2102                                  * throw the system into a confused state
2103                                  * causing all future tuning phases to report
2104                                  * failure.
2105                                  *
2106                                  * In such case controller will move into a data
2107                                  * transfer state after a response error or
2108                                  * response CRC error. Let's let that finish
2109                                  * before trying to send a stop, so we'll go to
2110                                  * STATE_SENDING_DATA.
2111                                  *
2112                                  * Although letting the data transfer take place
2113                                  * will waste a bit of time (we already know
2114                                  * the command was bad), it can't cause any
2115                                  * errors since it's possible it would have
2116                                  * taken place anyway if this tasklet got
2117                                  * delayed. Allowing the transfer to take place
2118                                  * avoids races and keeps things simple.
2119                                  */
2120                                 if (err != -ETIMEDOUT &&
2121                                     host->dir_status == DW_MCI_RECV_STATUS) {
2122                                         state = STATE_SENDING_DATA;
2123                                         continue;
2124                                 }
2125
2126                                 send_stop_abort(host, data);
2127                                 dw_mci_stop_dma(host);
2128                                 state = STATE_SENDING_STOP;
2129                                 break;
2130                         }
2131
2132                         if (!cmd->data || err) {
2133                                 dw_mci_request_end(host, mrq);
2134                                 goto unlock;
2135                         }
2136
2137                         prev_state = state = STATE_SENDING_DATA;
2138                         fallthrough;
2139
2140                 case STATE_SENDING_DATA:
2141                         /*
2142                          * We could get a data error and never a transfer
2143                          * complete so we'd better check for it here.
2144                          *
2145                          * Note that we don't really care if we also got a
2146                          * transfer complete; stopping the DMA and sending an
2147                          * abort won't hurt.
2148                          */
2149                         if (test_and_clear_bit(EVENT_DATA_ERROR,
2150                                                &host->pending_events)) {
2151                                 if (!(host->data_status & (SDMMC_INT_DRTO |
2152                                                            SDMMC_INT_EBE)))
2153                                         send_stop_abort(host, data);
2154                                 dw_mci_stop_dma(host);
2155                                 state = STATE_DATA_ERROR;
2156                                 break;
2157                         }
2158
2159                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
2160                                                 &host->pending_events)) {
2161                                 /*
2162                                  * If all data-related interrupts don't come
2163                                  * within the given time in reading data state.
2164                                  */
2165                                 if (host->dir_status == DW_MCI_RECV_STATUS)
2166                                         dw_mci_set_drto(host);
2167                                 break;
2168                         }
2169
2170                         set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
2171
2172                         /*
2173                          * Handle an EVENT_DATA_ERROR that might have shown up
2174                          * before the transfer completed.  This might not have
2175                          * been caught by the check above because the interrupt
2176                          * could have gone off between the previous check and
2177                          * the check for transfer complete.
2178                          *
2179                          * Technically this ought not be needed assuming we
2180                          * get a DATA_COMPLETE eventually (we'll notice the
2181                          * error and end the request), but it shouldn't hurt.
2182                          *
2183                          * This has the advantage of sending the stop command.
2184                          */
2185                         if (test_and_clear_bit(EVENT_DATA_ERROR,
2186                                                &host->pending_events)) {
2187                                 if (!(host->data_status & (SDMMC_INT_DRTO |
2188                                                            SDMMC_INT_EBE)))
2189                                         send_stop_abort(host, data);
2190                                 dw_mci_stop_dma(host);
2191                                 state = STATE_DATA_ERROR;
2192                                 break;
2193                         }
2194                         prev_state = state = STATE_DATA_BUSY;
2195
2196                         fallthrough;
2197
2198                 case STATE_DATA_BUSY:
2199                         if (!dw_mci_clear_pending_data_complete(host)) {
2200                                 /*
2201                                  * If data error interrupt comes but data over
2202                                  * interrupt doesn't come within the given time.
2203                                  * in reading data state.
2204                                  */
2205                                 if (host->dir_status == DW_MCI_RECV_STATUS)
2206                                         dw_mci_set_drto(host);
2207                                 break;
2208                         }
2209
2210                         dw_mci_stop_fault_timer(host);
2211                         host->data = NULL;
2212                         set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
2213                         err = dw_mci_data_complete(host, data);
2214
2215                         if (!err) {
2216                                 if (!data->stop || mrq->sbc) {
2217                                         if (mrq->sbc && data->stop)
2218                                                 data->stop->error = 0;
2219                                         dw_mci_request_end(host, mrq);
2220                                         goto unlock;
2221                                 }
2222
2223                                 /* stop command for open-ended transfer*/
2224                                 if (data->stop)
2225                                         send_stop_abort(host, data);
2226                         } else {
2227                                 /*
2228                                  * If we don't have a command complete now we'll
2229                                  * never get one since we just reset everything;
2230                                  * better end the request.
2231                                  *
2232                                  * If we do have a command complete we'll fall
2233                                  * through to the SENDING_STOP command and
2234                                  * everything will be peachy keen.
2235                                  */
2236                                 if (!test_bit(EVENT_CMD_COMPLETE,
2237                                               &host->pending_events)) {
2238                                         host->cmd = NULL;
2239                                         dw_mci_request_end(host, mrq);
2240                                         goto unlock;
2241                                 }
2242                         }
2243
2244                         /*
2245                          * If err has non-zero,
2246                          * stop-abort command has been already issued.
2247                          */
2248                         prev_state = state = STATE_SENDING_STOP;
2249
2250                         fallthrough;
2251
2252                 case STATE_SENDING_STOP:
2253                         if (!dw_mci_clear_pending_cmd_complete(host))
2254                                 break;
2255
2256                         /* CMD error in data command */
2257                         if (mrq->cmd->error && mrq->data)
2258                                 dw_mci_reset(host);
2259
2260                         dw_mci_stop_fault_timer(host);
2261                         host->cmd = NULL;
2262                         host->data = NULL;
2263
2264                         if (!mrq->sbc && mrq->stop)
2265                                 dw_mci_command_complete(host, mrq->stop);
2266                         else
2267                                 host->cmd_status = 0;
2268
2269                         dw_mci_request_end(host, mrq);
2270                         goto unlock;
2271
2272                 case STATE_DATA_ERROR:
2273                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
2274                                                 &host->pending_events))
2275                                 break;
2276
2277                         state = STATE_DATA_BUSY;
2278                         break;
2279                 }
2280         } while (state != prev_state);
2281
2282         host->state = state;
2283 unlock:
2284         spin_unlock(&host->lock);
2285
2286 }
2287
2288 /* push final bytes to part_buf, only use during push */
2289 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
2290 {
2291         memcpy((void *)&host->part_buf, buf, cnt);
2292         host->part_buf_count = cnt;
2293 }
2294
2295 /* append bytes to part_buf, only use during push */
2296 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
2297 {
2298         cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
2299         memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
2300         host->part_buf_count += cnt;
2301         return cnt;
2302 }
2303
2304 /* pull first bytes from part_buf, only use during pull */
2305 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
2306 {
2307         cnt = min_t(int, cnt, host->part_buf_count);
2308         if (cnt) {
2309                 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
2310                        cnt);
2311                 host->part_buf_count -= cnt;
2312                 host->part_buf_start += cnt;
2313         }
2314         return cnt;
2315 }
2316
2317 /* pull final bytes from the part_buf, assuming it's just been filled */
2318 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
2319 {
2320         memcpy(buf, &host->part_buf, cnt);
2321         host->part_buf_start = cnt;
2322         host->part_buf_count = (1 << host->data_shift) - cnt;
2323 }
2324
2325 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
2326 {
2327         struct mmc_data *data = host->data;
2328         int init_cnt = cnt;
2329
2330         /* try and push anything in the part_buf */
2331         if (unlikely(host->part_buf_count)) {
2332                 int len = dw_mci_push_part_bytes(host, buf, cnt);
2333
2334                 buf += len;
2335                 cnt -= len;
2336                 if (host->part_buf_count == 2) {
2337                         mci_fifo_writew(host->fifo_reg, host->part_buf16);
2338                         host->part_buf_count = 0;
2339                 }
2340         }
2341 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2342         if (unlikely((unsigned long)buf & 0x1)) {
2343                 while (cnt >= 2) {
2344                         u16 aligned_buf[64];
2345                         int len = min(cnt & -2, (int)sizeof(aligned_buf));
2346                         int items = len >> 1;
2347                         int i;
2348                         /* memcpy from input buffer into aligned buffer */
2349                         memcpy(aligned_buf, buf, len);
2350                         buf += len;
2351                         cnt -= len;
2352                         /* push data from aligned buffer into fifo */
2353                         for (i = 0; i < items; ++i)
2354                                 mci_fifo_writew(host->fifo_reg, aligned_buf[i]);
2355                 }
2356         } else
2357 #endif
2358         {
2359                 u16 *pdata = buf;
2360
2361                 for (; cnt >= 2; cnt -= 2)
2362                         mci_fifo_writew(host->fifo_reg, *pdata++);
2363                 buf = pdata;
2364         }
2365         /* put anything remaining in the part_buf */
2366         if (cnt) {
2367                 dw_mci_set_part_bytes(host, buf, cnt);
2368                  /* Push data if we have reached the expected data length */
2369                 if ((data->bytes_xfered + init_cnt) ==
2370                     (data->blksz * data->blocks))
2371                         mci_fifo_writew(host->fifo_reg, host->part_buf16);
2372         }
2373 }
2374
2375 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
2376 {
2377 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2378         if (unlikely((unsigned long)buf & 0x1)) {
2379                 while (cnt >= 2) {
2380                         /* pull data from fifo into aligned buffer */
2381                         u16 aligned_buf[64];
2382                         int len = min(cnt & -2, (int)sizeof(aligned_buf));
2383                         int items = len >> 1;
2384                         int i;
2385
2386                         for (i = 0; i < items; ++i)
2387                                 aligned_buf[i] = mci_fifo_readw(host->fifo_reg);
2388                         /* memcpy from aligned buffer into output buffer */
2389                         memcpy(buf, aligned_buf, len);
2390                         buf += len;
2391                         cnt -= len;
2392                 }
2393         } else
2394 #endif
2395         {
2396                 u16 *pdata = buf;
2397
2398                 for (; cnt >= 2; cnt -= 2)
2399                         *pdata++ = mci_fifo_readw(host->fifo_reg);
2400                 buf = pdata;
2401         }
2402         if (cnt) {
2403                 host->part_buf16 = mci_fifo_readw(host->fifo_reg);
2404                 dw_mci_pull_final_bytes(host, buf, cnt);
2405         }
2406 }
2407
2408 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
2409 {
2410         struct mmc_data *data = host->data;
2411         int init_cnt = cnt;
2412
2413         /* try and push anything in the part_buf */
2414         if (unlikely(host->part_buf_count)) {
2415                 int len = dw_mci_push_part_bytes(host, buf, cnt);
2416
2417                 buf += len;
2418                 cnt -= len;
2419                 if (host->part_buf_count == 4) {
2420                         mci_fifo_writel(host->fifo_reg, host->part_buf32);
2421                         host->part_buf_count = 0;
2422                 }
2423         }
2424 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2425         if (unlikely((unsigned long)buf & 0x3)) {
2426                 while (cnt >= 4) {
2427                         u32 aligned_buf[32];
2428                         int len = min(cnt & -4, (int)sizeof(aligned_buf));
2429                         int items = len >> 2;
2430                         int i;
2431                         /* memcpy from input buffer into aligned buffer */
2432                         memcpy(aligned_buf, buf, len);
2433                         buf += len;
2434                         cnt -= len;
2435                         /* push data from aligned buffer into fifo */
2436                         for (i = 0; i < items; ++i)
2437                                 mci_fifo_writel(host->fifo_reg, aligned_buf[i]);
2438                 }
2439         } else
2440 #endif
2441         {
2442                 u32 *pdata = buf;
2443
2444                 for (; cnt >= 4; cnt -= 4)
2445                         mci_fifo_writel(host->fifo_reg, *pdata++);
2446                 buf = pdata;
2447         }
2448         /* put anything remaining in the part_buf */
2449         if (cnt) {
2450                 dw_mci_set_part_bytes(host, buf, cnt);
2451                  /* Push data if we have reached the expected data length */
2452                 if ((data->bytes_xfered + init_cnt) ==
2453                     (data->blksz * data->blocks))
2454                         mci_fifo_writel(host->fifo_reg, host->part_buf32);
2455         }
2456 }
2457
2458 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
2459 {
2460 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2461         if (unlikely((unsigned long)buf & 0x3)) {
2462                 while (cnt >= 4) {
2463                         /* pull data from fifo into aligned buffer */
2464                         u32 aligned_buf[32];
2465                         int len = min(cnt & -4, (int)sizeof(aligned_buf));
2466                         int items = len >> 2;
2467                         int i;
2468
2469                         for (i = 0; i < items; ++i)
2470                                 aligned_buf[i] = mci_fifo_readl(host->fifo_reg);
2471                         /* memcpy from aligned buffer into output buffer */
2472                         memcpy(buf, aligned_buf, len);
2473                         buf += len;
2474                         cnt -= len;
2475                 }
2476         } else
2477 #endif
2478         {
2479                 u32 *pdata = buf;
2480
2481                 for (; cnt >= 4; cnt -= 4)
2482                         *pdata++ = mci_fifo_readl(host->fifo_reg);
2483                 buf = pdata;
2484         }
2485         if (cnt) {
2486                 host->part_buf32 = mci_fifo_readl(host->fifo_reg);
2487                 dw_mci_pull_final_bytes(host, buf, cnt);
2488         }
2489 }
2490
2491 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
2492 {
2493         struct mmc_data *data = host->data;
2494         int init_cnt = cnt;
2495
2496         /* try and push anything in the part_buf */
2497         if (unlikely(host->part_buf_count)) {
2498                 int len = dw_mci_push_part_bytes(host, buf, cnt);
2499
2500                 buf += len;
2501                 cnt -= len;
2502
2503                 if (host->part_buf_count == 8) {
2504                         mci_fifo_writeq(host->fifo_reg, host->part_buf);
2505                         host->part_buf_count = 0;
2506                 }
2507         }
2508 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2509         if (unlikely((unsigned long)buf & 0x7)) {
2510                 while (cnt >= 8) {
2511                         u64 aligned_buf[16];
2512                         int len = min(cnt & -8, (int)sizeof(aligned_buf));
2513                         int items = len >> 3;
2514                         int i;
2515                         /* memcpy from input buffer into aligned buffer */
2516                         memcpy(aligned_buf, buf, len);
2517                         buf += len;
2518                         cnt -= len;
2519                         /* push data from aligned buffer into fifo */
2520                         for (i = 0; i < items; ++i)
2521                                 mci_fifo_writeq(host->fifo_reg, aligned_buf[i]);
2522                 }
2523         } else
2524 #endif
2525         {
2526                 u64 *pdata = buf;
2527
2528                 for (; cnt >= 8; cnt -= 8)
2529                         mci_fifo_writeq(host->fifo_reg, *pdata++);
2530                 buf = pdata;
2531         }
2532         /* put anything remaining in the part_buf */
2533         if (cnt) {
2534                 dw_mci_set_part_bytes(host, buf, cnt);
2535                 /* Push data if we have reached the expected data length */
2536                 if ((data->bytes_xfered + init_cnt) ==
2537                     (data->blksz * data->blocks))
2538                         mci_fifo_writeq(host->fifo_reg, host->part_buf);
2539         }
2540 }
2541
2542 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
2543 {
2544 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2545         if (unlikely((unsigned long)buf & 0x7)) {
2546                 while (cnt >= 8) {
2547                         /* pull data from fifo into aligned buffer */
2548                         u64 aligned_buf[16];
2549                         int len = min(cnt & -8, (int)sizeof(aligned_buf));
2550                         int items = len >> 3;
2551                         int i;
2552
2553                         for (i = 0; i < items; ++i)
2554                                 aligned_buf[i] = mci_fifo_readq(host->fifo_reg);
2555
2556                         /* memcpy from aligned buffer into output buffer */
2557                         memcpy(buf, aligned_buf, len);
2558                         buf += len;
2559                         cnt -= len;
2560                 }
2561         } else
2562 #endif
2563         {
2564                 u64 *pdata = buf;
2565
2566                 for (; cnt >= 8; cnt -= 8)
2567                         *pdata++ = mci_fifo_readq(host->fifo_reg);
2568                 buf = pdata;
2569         }
2570         if (cnt) {
2571                 host->part_buf = mci_fifo_readq(host->fifo_reg);
2572                 dw_mci_pull_final_bytes(host, buf, cnt);
2573         }
2574 }
2575
2576 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
2577 {
2578         int len;
2579
2580         /* get remaining partial bytes */
2581         len = dw_mci_pull_part_bytes(host, buf, cnt);
2582         if (unlikely(len == cnt))
2583                 return;
2584         buf += len;
2585         cnt -= len;
2586
2587         /* get the rest of the data */
2588         host->pull_data(host, buf, cnt);
2589 }
2590
2591 static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
2592 {
2593         struct sg_mapping_iter *sg_miter = &host->sg_miter;
2594         void *buf;
2595         unsigned int offset;
2596         struct mmc_data *data = host->data;
2597         int shift = host->data_shift;
2598         u32 status;
2599         unsigned int len;
2600         unsigned int remain, fcnt;
2601
2602         do {
2603                 if (!sg_miter_next(sg_miter))
2604                         goto done;
2605
2606                 host->sg = sg_miter->piter.sg;
2607                 buf = sg_miter->addr;
2608                 remain = sg_miter->length;
2609                 offset = 0;
2610
2611                 do {
2612                         fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
2613                                         << shift) + host->part_buf_count;
2614                         len = min(remain, fcnt);
2615                         if (!len)
2616                                 break;
2617                         dw_mci_pull_data(host, (void *)(buf + offset), len);
2618                         data->bytes_xfered += len;
2619                         offset += len;
2620                         remain -= len;
2621                 } while (remain);
2622
2623                 sg_miter->consumed = offset;
2624                 status = mci_readl(host, MINTSTS);
2625                 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2626         /* if the RXDR is ready read again */
2627         } while ((status & SDMMC_INT_RXDR) ||
2628                  (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
2629
2630         if (!remain) {
2631                 if (!sg_miter_next(sg_miter))
2632                         goto done;
2633                 sg_miter->consumed = 0;
2634         }
2635         sg_miter_stop(sg_miter);
2636         return;
2637
2638 done:
2639         sg_miter_stop(sg_miter);
2640         host->sg = NULL;
2641         smp_wmb(); /* drain writebuffer */
2642         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2643 }
2644
2645 static void dw_mci_write_data_pio(struct dw_mci *host)
2646 {
2647         struct sg_mapping_iter *sg_miter = &host->sg_miter;
2648         void *buf;
2649         unsigned int offset;
2650         struct mmc_data *data = host->data;
2651         int shift = host->data_shift;
2652         u32 status;
2653         unsigned int len;
2654         unsigned int fifo_depth = host->fifo_depth;
2655         unsigned int remain, fcnt;
2656
2657         do {
2658                 if (!sg_miter_next(sg_miter))
2659                         goto done;
2660
2661                 host->sg = sg_miter->piter.sg;
2662                 buf = sg_miter->addr;
2663                 remain = sg_miter->length;
2664                 offset = 0;
2665
2666                 do {
2667                         fcnt = ((fifo_depth -
2668                                  SDMMC_GET_FCNT(mci_readl(host, STATUS)))
2669                                         << shift) - host->part_buf_count;
2670                         len = min(remain, fcnt);
2671                         if (!len)
2672                                 break;
2673                         host->push_data(host, (void *)(buf + offset), len);
2674                         data->bytes_xfered += len;
2675                         offset += len;
2676                         remain -= len;
2677                 } while (remain);
2678
2679                 sg_miter->consumed = offset;
2680                 status = mci_readl(host, MINTSTS);
2681                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2682         } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
2683
2684         if (!remain) {
2685                 if (!sg_miter_next(sg_miter))
2686                         goto done;
2687                 sg_miter->consumed = 0;
2688         }
2689         sg_miter_stop(sg_miter);
2690         return;
2691
2692 done:
2693         sg_miter_stop(sg_miter);
2694         host->sg = NULL;
2695         smp_wmb(); /* drain writebuffer */
2696         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2697 }
2698
2699 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
2700 {
2701         del_timer(&host->cto_timer);
2702
2703         if (!host->cmd_status)
2704                 host->cmd_status = status;
2705
2706         smp_wmb(); /* drain writebuffer */
2707
2708         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2709         tasklet_schedule(&host->tasklet);
2710
2711         dw_mci_start_fault_timer(host);
2712 }
2713
2714 static void dw_mci_handle_cd(struct dw_mci *host)
2715 {
2716         struct dw_mci_slot *slot = host->slot;
2717
2718         mmc_detect_change(slot->mmc,
2719                 msecs_to_jiffies(host->pdata->detect_delay_ms));
2720 }
2721
2722 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
2723 {
2724         struct dw_mci *host = dev_id;
2725         u32 pending;
2726         struct dw_mci_slot *slot = host->slot;
2727
2728         pending = mci_readl(host, MINTSTS); /* read-only mask reg */
2729
2730         if (pending) {
2731                 /* Check volt switch first, since it can look like an error */
2732                 if ((host->state == STATE_SENDING_CMD11) &&
2733                     (pending & SDMMC_INT_VOLT_SWITCH)) {
2734                         mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH);
2735                         pending &= ~SDMMC_INT_VOLT_SWITCH;
2736
2737                         /*
2738                          * Hold the lock; we know cmd11_timer can't be kicked
2739                          * off after the lock is released, so safe to delete.
2740                          */
2741                         spin_lock(&host->irq_lock);
2742                         dw_mci_cmd_interrupt(host, pending);
2743                         spin_unlock(&host->irq_lock);
2744
2745                         del_timer(&host->cmd11_timer);
2746                 }
2747
2748                 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
2749                         spin_lock(&host->irq_lock);
2750
2751                         del_timer(&host->cto_timer);
2752                         mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
2753                         host->cmd_status = pending;
2754                         smp_wmb(); /* drain writebuffer */
2755                         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2756
2757                         spin_unlock(&host->irq_lock);
2758                 }
2759
2760                 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
2761                         spin_lock(&host->irq_lock);
2762
2763                         if (host->quirks & DW_MMC_QUIRK_EXTENDED_TMOUT)
2764                                 del_timer(&host->dto_timer);
2765
2766                         /* if there is an error report DATA_ERROR */
2767                         mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
2768                         host->data_status = pending;
2769                         smp_wmb(); /* drain writebuffer */
2770                         set_bit(EVENT_DATA_ERROR, &host->pending_events);
2771
2772                         if (host->quirks & DW_MMC_QUIRK_EXTENDED_TMOUT)
2773                                 /* In case of error, we cannot expect a DTO */
2774                                 set_bit(EVENT_DATA_COMPLETE,
2775                                         &host->pending_events);
2776
2777                         tasklet_schedule(&host->tasklet);
2778
2779                         spin_unlock(&host->irq_lock);
2780                 }
2781
2782                 if (pending & SDMMC_INT_DATA_OVER) {
2783                         spin_lock(&host->irq_lock);
2784
2785                         del_timer(&host->dto_timer);
2786
2787                         mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
2788                         if (!host->data_status)
2789                                 host->data_status = pending;
2790                         smp_wmb(); /* drain writebuffer */
2791                         if (host->dir_status == DW_MCI_RECV_STATUS) {
2792                                 if (host->sg != NULL)
2793                                         dw_mci_read_data_pio(host, true);
2794                         }
2795                         set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2796                         tasklet_schedule(&host->tasklet);
2797
2798                         spin_unlock(&host->irq_lock);
2799                 }
2800
2801                 if (pending & SDMMC_INT_RXDR) {
2802                         mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2803                         if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
2804                                 dw_mci_read_data_pio(host, false);
2805                 }
2806
2807                 if (pending & SDMMC_INT_TXDR) {
2808                         mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2809                         if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
2810                                 dw_mci_write_data_pio(host);
2811                 }
2812
2813                 if (pending & SDMMC_INT_CMD_DONE) {
2814                         spin_lock(&host->irq_lock);
2815
2816                         mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
2817                         dw_mci_cmd_interrupt(host, pending);
2818
2819                         spin_unlock(&host->irq_lock);
2820                 }
2821
2822                 if (pending & SDMMC_INT_CD) {
2823                         mci_writel(host, RINTSTS, SDMMC_INT_CD);
2824                         dw_mci_handle_cd(host);
2825                 }
2826
2827                 if (pending & SDMMC_INT_SDIO(slot->sdio_id)) {
2828                         mci_writel(host, RINTSTS,
2829                                    SDMMC_INT_SDIO(slot->sdio_id));
2830                         __dw_mci_enable_sdio_irq(slot, 0);
2831                         sdio_signal_irq(slot->mmc);
2832                 }
2833
2834         }
2835
2836         if (host->use_dma != TRANS_MODE_IDMAC)
2837                 return IRQ_HANDLED;
2838
2839         /* Handle IDMA interrupts */
2840         if (host->dma_64bit_address == 1) {
2841                 pending = mci_readl(host, IDSTS64);
2842                 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2843                         mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI |
2844                                                         SDMMC_IDMAC_INT_RI);
2845                         mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI);
2846                         if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
2847                                 host->dma_ops->complete((void *)host);
2848                 }
2849         } else {
2850                 pending = mci_readl(host, IDSTS);
2851                 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2852                         mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI |
2853                                                         SDMMC_IDMAC_INT_RI);
2854                         mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
2855                         if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
2856                                 host->dma_ops->complete((void *)host);
2857                 }
2858         }
2859
2860         return IRQ_HANDLED;
2861 }
2862
2863 static int dw_mci_init_slot_caps(struct dw_mci_slot *slot)
2864 {
2865         struct dw_mci *host = slot->host;
2866         const struct dw_mci_drv_data *drv_data = host->drv_data;
2867         struct mmc_host *mmc = slot->mmc;
2868         int ctrl_id;
2869
2870         if (host->pdata->caps)
2871                 mmc->caps = host->pdata->caps;
2872
2873         if (host->pdata->pm_caps)
2874                 mmc->pm_caps = host->pdata->pm_caps;
2875
2876         if (drv_data)
2877                 mmc->caps |= drv_data->common_caps;
2878
2879         if (host->dev->of_node) {
2880                 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
2881                 if (ctrl_id < 0)
2882                         ctrl_id = 0;
2883         } else {
2884                 ctrl_id = to_platform_device(host->dev)->id;
2885         }
2886
2887         if (drv_data && drv_data->caps) {
2888                 if (ctrl_id >= drv_data->num_caps) {
2889                         dev_err(host->dev, "invalid controller id %d\n",
2890                                 ctrl_id);
2891                         return -EINVAL;
2892                 }
2893                 mmc->caps |= drv_data->caps[ctrl_id];
2894         }
2895
2896         if (host->pdata->caps2)
2897                 mmc->caps2 = host->pdata->caps2;
2898
2899         /* if host has set a minimum_freq, we should respect it */
2900         if (host->minimum_speed)
2901                 mmc->f_min = host->minimum_speed;
2902         else
2903                 mmc->f_min = DW_MCI_FREQ_MIN;
2904
2905         if (!mmc->f_max)
2906                 mmc->f_max = DW_MCI_FREQ_MAX;
2907
2908         /* Process SDIO IRQs through the sdio_irq_work. */
2909         if (mmc->caps & MMC_CAP_SDIO_IRQ)
2910                 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
2911
2912         return 0;
2913 }
2914
2915 static int dw_mci_init_slot(struct dw_mci *host)
2916 {
2917         struct mmc_host *mmc;
2918         struct dw_mci_slot *slot;
2919         int ret;
2920
2921         mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
2922         if (!mmc)
2923                 return -ENOMEM;
2924
2925         slot = mmc_priv(mmc);
2926         slot->id = 0;
2927         slot->sdio_id = host->sdio_id0 + slot->id;
2928         slot->mmc = mmc;
2929         slot->host = host;
2930         host->slot = slot;
2931
2932         mmc->ops = &dw_mci_ops;
2933
2934         /*if there are external regulators, get them*/
2935         ret = mmc_regulator_get_supply(mmc);
2936         if (ret)
2937                 goto err_host_allocated;
2938
2939         if (!mmc->ocr_avail)
2940                 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
2941
2942         ret = mmc_of_parse(mmc);
2943         if (ret)
2944                 goto err_host_allocated;
2945
2946         ret = dw_mci_init_slot_caps(slot);
2947         if (ret)
2948                 goto err_host_allocated;
2949
2950         /* Useful defaults if platform data is unset. */
2951         if (host->use_dma == TRANS_MODE_IDMAC) {
2952                 mmc->max_segs = host->ring_size;
2953                 mmc->max_blk_size = 65535;
2954                 mmc->max_seg_size = 0x1000;
2955                 mmc->max_req_size = mmc->max_seg_size * host->ring_size;
2956                 mmc->max_blk_count = mmc->max_req_size / 512;
2957         } else if (host->use_dma == TRANS_MODE_EDMAC) {
2958                 mmc->max_segs = 64;
2959                 mmc->max_blk_size = 65535;
2960                 mmc->max_blk_count = 65535;
2961                 mmc->max_req_size =
2962                                 mmc->max_blk_size * mmc->max_blk_count;
2963                 mmc->max_seg_size = mmc->max_req_size;
2964         } else {
2965                 /* TRANS_MODE_PIO */
2966                 mmc->max_segs = 64;
2967                 mmc->max_blk_size = 65535; /* BLKSIZ is 16 bits */
2968                 mmc->max_blk_count = 512;
2969                 mmc->max_req_size = mmc->max_blk_size *
2970                                     mmc->max_blk_count;
2971                 mmc->max_seg_size = mmc->max_req_size;
2972         }
2973
2974         dw_mci_get_cd(mmc);
2975
2976         ret = mmc_add_host(mmc);
2977         if (ret)
2978                 goto err_host_allocated;
2979
2980 #if defined(CONFIG_DEBUG_FS)
2981         dw_mci_init_debugfs(slot);
2982 #endif
2983
2984         return 0;
2985
2986 err_host_allocated:
2987         mmc_free_host(mmc);
2988         return ret;
2989 }
2990
2991 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot)
2992 {
2993         /* Debugfs stuff is cleaned up by mmc core */
2994         mmc_remove_host(slot->mmc);
2995         slot->host->slot = NULL;
2996         mmc_free_host(slot->mmc);
2997 }
2998
2999 static void dw_mci_init_dma(struct dw_mci *host)
3000 {
3001         int addr_config;
3002         struct device *dev = host->dev;
3003
3004         /*
3005         * Check tansfer mode from HCON[17:16]
3006         * Clear the ambiguous description of dw_mmc databook:
3007         * 2b'00: No DMA Interface -> Actually means using Internal DMA block
3008         * 2b'01: DesignWare DMA Interface -> Synopsys DW-DMA block
3009         * 2b'10: Generic DMA Interface -> non-Synopsys generic DMA block
3010         * 2b'11: Non DW DMA Interface -> pio only
3011         * Compared to DesignWare DMA Interface, Generic DMA Interface has a
3012         * simpler request/acknowledge handshake mechanism and both of them
3013         * are regarded as external dma master for dw_mmc.
3014         */
3015         host->use_dma = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON));
3016         if (host->use_dma == DMA_INTERFACE_IDMA) {
3017                 host->use_dma = TRANS_MODE_IDMAC;
3018         } else if (host->use_dma == DMA_INTERFACE_DWDMA ||
3019                    host->use_dma == DMA_INTERFACE_GDMA) {
3020                 host->use_dma = TRANS_MODE_EDMAC;
3021         } else {
3022                 goto no_dma;
3023         }
3024
3025         /* Determine which DMA interface to use */
3026         if (host->use_dma == TRANS_MODE_IDMAC) {
3027                 /*
3028                 * Check ADDR_CONFIG bit in HCON to find
3029                 * IDMAC address bus width
3030                 */
3031                 addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON));
3032
3033                 if (addr_config == 1) {
3034                         /* host supports IDMAC in 64-bit address mode */
3035                         host->dma_64bit_address = 1;
3036                         dev_info(host->dev,
3037                                  "IDMAC supports 64-bit address mode.\n");
3038                         if (!dma_set_mask(host->dev, DMA_BIT_MASK(64)))
3039                                 dma_set_coherent_mask(host->dev,
3040                                                       DMA_BIT_MASK(64));
3041                 } else {
3042                         /* host supports IDMAC in 32-bit address mode */
3043                         host->dma_64bit_address = 0;
3044                         dev_info(host->dev,
3045                                  "IDMAC supports 32-bit address mode.\n");
3046                 }
3047
3048                 /* Alloc memory for sg translation */
3049                 host->sg_cpu = dmam_alloc_coherent(host->dev,
3050                                                    DESC_RING_BUF_SZ,
3051                                                    &host->sg_dma, GFP_KERNEL);
3052                 if (!host->sg_cpu) {
3053                         dev_err(host->dev,
3054                                 "%s: could not alloc DMA memory\n",
3055                                 __func__);
3056                         goto no_dma;
3057                 }
3058
3059                 host->dma_ops = &dw_mci_idmac_ops;
3060                 dev_info(host->dev, "Using internal DMA controller.\n");
3061         } else {
3062                 /* TRANS_MODE_EDMAC: check dma bindings again */
3063                 if ((device_property_string_array_count(dev, "dma-names") < 0) ||
3064                     !device_property_present(dev, "dmas")) {
3065                         goto no_dma;
3066                 }
3067                 host->dma_ops = &dw_mci_edmac_ops;
3068                 dev_info(host->dev, "Using external DMA controller.\n");
3069         }
3070
3071         if (host->dma_ops->init && host->dma_ops->start &&
3072             host->dma_ops->stop && host->dma_ops->cleanup) {
3073                 if (host->dma_ops->init(host)) {
3074                         dev_err(host->dev, "%s: Unable to initialize DMA Controller.\n",
3075                                 __func__);
3076                         goto no_dma;
3077                 }
3078         } else {
3079                 dev_err(host->dev, "DMA initialization not found.\n");
3080                 goto no_dma;
3081         }
3082
3083         return;
3084
3085 no_dma:
3086         dev_info(host->dev, "Using PIO mode.\n");
3087         host->use_dma = TRANS_MODE_PIO;
3088 }
3089
3090 static void dw_mci_cmd11_timer(struct timer_list *t)
3091 {
3092         struct dw_mci *host = from_timer(host, t, cmd11_timer);
3093
3094         if (host->state != STATE_SENDING_CMD11) {
3095                 dev_warn(host->dev, "Unexpected CMD11 timeout\n");
3096                 return;
3097         }
3098
3099         host->cmd_status = SDMMC_INT_RTO;
3100         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
3101         tasklet_schedule(&host->tasklet);
3102 }
3103
3104 static void dw_mci_cto_timer(struct timer_list *t)
3105 {
3106         struct dw_mci *host = from_timer(host, t, cto_timer);
3107         unsigned long irqflags;
3108         u32 pending;
3109
3110         spin_lock_irqsave(&host->irq_lock, irqflags);
3111
3112         /*
3113          * If somehow we have very bad interrupt latency it's remotely possible
3114          * that the timer could fire while the interrupt is still pending or
3115          * while the interrupt is midway through running.  Let's be paranoid
3116          * and detect those two cases.  Note that this is paranoia is somewhat
3117          * justified because in this function we don't actually cancel the
3118          * pending command in the controller--we just assume it will never come.
3119          */
3120         pending = mci_readl(host, MINTSTS); /* read-only mask reg */
3121         if (pending & (DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_CMD_DONE)) {
3122                 /* The interrupt should fire; no need to act but we can warn */
3123                 dev_warn(host->dev, "Unexpected interrupt latency\n");
3124                 goto exit;
3125         }
3126         if (test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) {
3127                 /* Presumably interrupt handler couldn't delete the timer */
3128                 dev_warn(host->dev, "CTO timeout when already completed\n");
3129                 goto exit;
3130         }
3131
3132         /*
3133          * Continued paranoia to make sure we're in the state we expect.
3134          * This paranoia isn't really justified but it seems good to be safe.
3135          */
3136         switch (host->state) {
3137         case STATE_SENDING_CMD11:
3138         case STATE_SENDING_CMD:
3139         case STATE_SENDING_STOP:
3140                 /*
3141                  * If CMD_DONE interrupt does NOT come in sending command
3142                  * state, we should notify the driver to terminate current
3143                  * transfer and report a command timeout to the core.
3144                  */
3145                 host->cmd_status = SDMMC_INT_RTO;
3146                 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
3147                 tasklet_schedule(&host->tasklet);
3148                 break;
3149         default:
3150                 dev_warn(host->dev, "Unexpected command timeout, state %d\n",
3151                          host->state);
3152                 break;
3153         }
3154
3155 exit:
3156         spin_unlock_irqrestore(&host->irq_lock, irqflags);
3157 }
3158
3159 static void dw_mci_dto_timer(struct timer_list *t)
3160 {
3161         struct dw_mci *host = from_timer(host, t, dto_timer);
3162         unsigned long irqflags;
3163         u32 pending;
3164
3165         spin_lock_irqsave(&host->irq_lock, irqflags);
3166
3167         /*
3168          * The DTO timer is much longer than the CTO timer, so it's even less
3169          * likely that we'll these cases, but it pays to be paranoid.
3170          */
3171         pending = mci_readl(host, MINTSTS); /* read-only mask reg */
3172         if (pending & SDMMC_INT_DATA_OVER) {
3173                 /* The interrupt should fire; no need to act but we can warn */
3174                 dev_warn(host->dev, "Unexpected data interrupt latency\n");
3175                 goto exit;
3176         }
3177         if (test_bit(EVENT_DATA_COMPLETE, &host->pending_events)) {
3178                 /* Presumably interrupt handler couldn't delete the timer */
3179                 dev_warn(host->dev, "DTO timeout when already completed\n");
3180                 goto exit;
3181         }
3182
3183         /*
3184          * Continued paranoia to make sure we're in the state we expect.
3185          * This paranoia isn't really justified but it seems good to be safe.
3186          */
3187         switch (host->state) {
3188         case STATE_SENDING_DATA:
3189         case STATE_DATA_BUSY:
3190                 /*
3191                  * If DTO interrupt does NOT come in sending data state,
3192                  * we should notify the driver to terminate current transfer
3193                  * and report a data timeout to the core.
3194                  */
3195                 host->data_status = SDMMC_INT_DRTO;
3196                 set_bit(EVENT_DATA_ERROR, &host->pending_events);
3197                 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
3198                 tasklet_schedule(&host->tasklet);
3199                 break;
3200         default:
3201                 dev_warn(host->dev, "Unexpected data timeout, state %d\n",
3202                          host->state);
3203                 break;
3204         }
3205
3206 exit:
3207         spin_unlock_irqrestore(&host->irq_lock, irqflags);
3208 }
3209
3210 #ifdef CONFIG_OF
3211 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
3212 {
3213         struct dw_mci_board *pdata;
3214         struct device *dev = host->dev;
3215         const struct dw_mci_drv_data *drv_data = host->drv_data;
3216         int ret;
3217         u32 clock_frequency;
3218
3219         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
3220         if (!pdata)
3221                 return ERR_PTR(-ENOMEM);
3222
3223         /* find reset controller when exist */
3224         pdata->rstc = devm_reset_control_get_optional_exclusive(dev, "reset");
3225         if (IS_ERR(pdata->rstc))
3226                 return ERR_CAST(pdata->rstc);
3227
3228         if (device_property_read_u32(dev, "fifo-depth", &pdata->fifo_depth))
3229                 dev_info(dev,
3230                          "fifo-depth property not found, using value of FIFOTH register as default\n");
3231
3232         device_property_read_u32(dev, "card-detect-delay",
3233                                  &pdata->detect_delay_ms);
3234
3235         device_property_read_u32(dev, "data-addr", &host->data_addr_override);
3236
3237         if (device_property_present(dev, "fifo-watermark-aligned"))
3238                 host->wm_aligned = true;
3239
3240         if (!device_property_read_u32(dev, "clock-frequency", &clock_frequency))
3241                 pdata->bus_hz = clock_frequency;
3242
3243         if (drv_data && drv_data->parse_dt) {
3244                 ret = drv_data->parse_dt(host);
3245                 if (ret)
3246                         return ERR_PTR(ret);
3247         }
3248
3249         return pdata;
3250 }
3251
3252 #else /* CONFIG_OF */
3253 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
3254 {
3255         return ERR_PTR(-EINVAL);
3256 }
3257 #endif /* CONFIG_OF */
3258
3259 static void dw_mci_enable_cd(struct dw_mci *host)
3260 {
3261         unsigned long irqflags;
3262         u32 temp;
3263
3264         /*
3265          * No need for CD if all slots have a non-error GPIO
3266          * as well as broken card detection is found.
3267          */
3268         if (host->slot->mmc->caps & MMC_CAP_NEEDS_POLL)
3269                 return;
3270
3271         if (mmc_gpio_get_cd(host->slot->mmc) < 0) {
3272                 spin_lock_irqsave(&host->irq_lock, irqflags);
3273                 temp = mci_readl(host, INTMASK);
3274                 temp  |= SDMMC_INT_CD;
3275                 mci_writel(host, INTMASK, temp);
3276                 spin_unlock_irqrestore(&host->irq_lock, irqflags);
3277         }
3278 }
3279
3280 int dw_mci_probe(struct dw_mci *host)
3281 {
3282         const struct dw_mci_drv_data *drv_data = host->drv_data;
3283         int width, i, ret = 0;
3284         u32 fifo_size;
3285
3286         if (!host->pdata) {
3287                 host->pdata = dw_mci_parse_dt(host);
3288                 if (IS_ERR(host->pdata))
3289                         return dev_err_probe(host->dev, PTR_ERR(host->pdata),
3290                                              "platform data not available\n");
3291         }
3292
3293         host->biu_clk = devm_clk_get(host->dev, "biu");
3294         if (IS_ERR(host->biu_clk)) {
3295                 dev_dbg(host->dev, "biu clock not available\n");
3296         } else {
3297                 ret = clk_prepare_enable(host->biu_clk);
3298                 if (ret) {
3299                         dev_err(host->dev, "failed to enable biu clock\n");
3300                         return ret;
3301                 }
3302         }
3303
3304         host->ciu_clk = devm_clk_get(host->dev, "ciu");
3305         if (IS_ERR(host->ciu_clk)) {
3306                 dev_dbg(host->dev, "ciu clock not available\n");
3307                 host->bus_hz = host->pdata->bus_hz;
3308         } else {
3309                 ret = clk_prepare_enable(host->ciu_clk);
3310                 if (ret) {
3311                         dev_err(host->dev, "failed to enable ciu clock\n");
3312                         goto err_clk_biu;
3313                 }
3314
3315                 if (host->pdata->bus_hz) {
3316                         ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz);
3317                         if (ret)
3318                                 dev_warn(host->dev,
3319                                          "Unable to set bus rate to %uHz\n",
3320                                          host->pdata->bus_hz);
3321                 }
3322                 host->bus_hz = clk_get_rate(host->ciu_clk);
3323         }
3324
3325         if (!host->bus_hz) {
3326                 dev_err(host->dev,
3327                         "Platform data must supply bus speed\n");
3328                 ret = -ENODEV;
3329                 goto err_clk_ciu;
3330         }
3331
3332         if (host->pdata->rstc) {
3333                 reset_control_assert(host->pdata->rstc);
3334                 usleep_range(10, 50);
3335                 reset_control_deassert(host->pdata->rstc);
3336         }
3337
3338         if (drv_data && drv_data->init) {
3339                 ret = drv_data->init(host);
3340                 if (ret) {
3341                         dev_err(host->dev,
3342                                 "implementation specific init failed\n");
3343                         goto err_clk_ciu;
3344                 }
3345         }
3346
3347         timer_setup(&host->cmd11_timer, dw_mci_cmd11_timer, 0);
3348         timer_setup(&host->cto_timer, dw_mci_cto_timer, 0);
3349         timer_setup(&host->dto_timer, dw_mci_dto_timer, 0);
3350
3351         spin_lock_init(&host->lock);
3352         spin_lock_init(&host->irq_lock);
3353         INIT_LIST_HEAD(&host->queue);
3354
3355         dw_mci_init_fault(host);
3356
3357         /*
3358          * Get the host data width - this assumes that HCON has been set with
3359          * the correct values.
3360          */
3361         i = SDMMC_GET_HDATA_WIDTH(mci_readl(host, HCON));
3362         if (!i) {
3363                 host->push_data = dw_mci_push_data16;
3364                 host->pull_data = dw_mci_pull_data16;
3365                 width = 16;
3366                 host->data_shift = 1;
3367         } else if (i == 2) {
3368                 host->push_data = dw_mci_push_data64;
3369                 host->pull_data = dw_mci_pull_data64;
3370                 width = 64;
3371                 host->data_shift = 3;
3372         } else {
3373                 /* Check for a reserved value, and warn if it is */
3374                 WARN((i != 1),
3375                      "HCON reports a reserved host data width!\n"
3376                      "Defaulting to 32-bit access.\n");
3377                 host->push_data = dw_mci_push_data32;
3378                 host->pull_data = dw_mci_pull_data32;
3379                 width = 32;
3380                 host->data_shift = 2;
3381         }
3382
3383         /* Reset all blocks */
3384         if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
3385                 ret = -ENODEV;
3386                 goto err_clk_ciu;
3387         }
3388
3389         host->dma_ops = host->pdata->dma_ops;
3390         dw_mci_init_dma(host);
3391
3392         /* Clear the interrupts for the host controller */
3393         mci_writel(host, RINTSTS, 0xFFFFFFFF);
3394         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3395
3396         /* Put in max timeout */
3397         mci_writel(host, TMOUT, 0xFFFFFFFF);
3398
3399         /*
3400          * FIFO threshold settings  RxMark  = fifo_size / 2 - 1,
3401          *                          Tx Mark = fifo_size / 2 DMA Size = 8
3402          */
3403         if (!host->pdata->fifo_depth) {
3404                 /*
3405                  * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
3406                  * have been overwritten by the bootloader, just like we're
3407                  * about to do, so if you know the value for your hardware, you
3408                  * should put it in the platform data.
3409                  */
3410                 fifo_size = mci_readl(host, FIFOTH);
3411                 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
3412         } else {
3413                 fifo_size = host->pdata->fifo_depth;
3414         }
3415         host->fifo_depth = fifo_size;
3416         host->fifoth_val =
3417                 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2);
3418         mci_writel(host, FIFOTH, host->fifoth_val);
3419
3420         /* disable clock to CIU */
3421         mci_writel(host, CLKENA, 0);
3422         mci_writel(host, CLKSRC, 0);
3423
3424         /*
3425          * In 2.40a spec, Data offset is changed.
3426          * Need to check the version-id and set data-offset for DATA register.
3427          */
3428         host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
3429         dev_info(host->dev, "Version ID is %04x\n", host->verid);
3430
3431         if (host->data_addr_override)
3432                 host->fifo_reg = host->regs + host->data_addr_override;
3433         else if (host->verid < DW_MMC_240A)
3434                 host->fifo_reg = host->regs + DATA_OFFSET;
3435         else
3436                 host->fifo_reg = host->regs + DATA_240A_OFFSET;
3437
3438         tasklet_setup(&host->tasklet, dw_mci_tasklet_func);
3439         ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
3440                                host->irq_flags, "dw-mci", host);
3441         if (ret)
3442                 goto err_dmaunmap;
3443
3444         /*
3445          * Enable interrupts for command done, data over, data empty,
3446          * receive ready and error such as transmit, receive timeout, crc error
3447          */
3448         mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3449                    SDMMC_INT_TXDR | SDMMC_INT_RXDR |
3450                    DW_MCI_ERROR_FLAGS);
3451         /* Enable mci interrupt */
3452         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3453
3454         dev_info(host->dev,
3455                  "DW MMC controller at irq %d,%d bit host data width,%u deep fifo\n",
3456                  host->irq, width, fifo_size);
3457
3458         /* We need at least one slot to succeed */
3459         ret = dw_mci_init_slot(host);
3460         if (ret) {
3461                 dev_dbg(host->dev, "slot %d init failed\n", i);
3462                 goto err_dmaunmap;
3463         }
3464
3465         /* Now that slots are all setup, we can enable card detect */
3466         dw_mci_enable_cd(host);
3467
3468         return 0;
3469
3470 err_dmaunmap:
3471         if (host->use_dma && host->dma_ops->exit)
3472                 host->dma_ops->exit(host);
3473
3474         reset_control_assert(host->pdata->rstc);
3475
3476 err_clk_ciu:
3477         clk_disable_unprepare(host->ciu_clk);
3478
3479 err_clk_biu:
3480         clk_disable_unprepare(host->biu_clk);
3481
3482         return ret;
3483 }
3484 EXPORT_SYMBOL(dw_mci_probe);
3485
3486 void dw_mci_remove(struct dw_mci *host)
3487 {
3488         dev_dbg(host->dev, "remove slot\n");
3489         if (host->slot)
3490                 dw_mci_cleanup_slot(host->slot);
3491
3492         mci_writel(host, RINTSTS, 0xFFFFFFFF);
3493         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3494
3495         /* disable clock to CIU */
3496         mci_writel(host, CLKENA, 0);
3497         mci_writel(host, CLKSRC, 0);
3498
3499         if (host->use_dma && host->dma_ops->exit)
3500                 host->dma_ops->exit(host);
3501
3502         reset_control_assert(host->pdata->rstc);
3503
3504         clk_disable_unprepare(host->ciu_clk);
3505         clk_disable_unprepare(host->biu_clk);
3506 }
3507 EXPORT_SYMBOL(dw_mci_remove);
3508
3509
3510
3511 #ifdef CONFIG_PM
3512 int dw_mci_runtime_suspend(struct device *dev)
3513 {
3514         struct dw_mci *host = dev_get_drvdata(dev);
3515
3516         if (host->use_dma && host->dma_ops->exit)
3517                 host->dma_ops->exit(host);
3518
3519         clk_disable_unprepare(host->ciu_clk);
3520
3521         if (host->slot &&
3522             (mmc_can_gpio_cd(host->slot->mmc) ||
3523              !mmc_card_is_removable(host->slot->mmc)))
3524                 clk_disable_unprepare(host->biu_clk);
3525
3526         return 0;
3527 }
3528 EXPORT_SYMBOL(dw_mci_runtime_suspend);
3529
3530 int dw_mci_runtime_resume(struct device *dev)
3531 {
3532         int ret = 0;
3533         struct dw_mci *host = dev_get_drvdata(dev);
3534
3535         if (host->slot &&
3536             (mmc_can_gpio_cd(host->slot->mmc) ||
3537              !mmc_card_is_removable(host->slot->mmc))) {
3538                 ret = clk_prepare_enable(host->biu_clk);
3539                 if (ret)
3540                         return ret;
3541         }
3542
3543         ret = clk_prepare_enable(host->ciu_clk);
3544         if (ret)
3545                 goto err;
3546
3547         if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
3548                 clk_disable_unprepare(host->ciu_clk);
3549                 ret = -ENODEV;
3550                 goto err;
3551         }
3552
3553         if (host->use_dma && host->dma_ops->init)
3554                 host->dma_ops->init(host);
3555
3556         /*
3557          * Restore the initial value at FIFOTH register
3558          * And Invalidate the prev_blksz with zero
3559          */
3560         mci_writel(host, FIFOTH, host->fifoth_val);
3561         host->prev_blksz = 0;
3562
3563         /* Put in max timeout */
3564         mci_writel(host, TMOUT, 0xFFFFFFFF);
3565
3566         mci_writel(host, RINTSTS, 0xFFFFFFFF);
3567         mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3568                    SDMMC_INT_TXDR | SDMMC_INT_RXDR |
3569                    DW_MCI_ERROR_FLAGS);
3570         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3571
3572
3573         if (host->slot && host->slot->mmc->pm_flags & MMC_PM_KEEP_POWER)
3574                 dw_mci_set_ios(host->slot->mmc, &host->slot->mmc->ios);
3575
3576         /* Force setup bus to guarantee available clock output */
3577         dw_mci_setup_bus(host->slot, true);
3578
3579         /* Re-enable SDIO interrupts. */
3580         if (sdio_irq_claimed(host->slot->mmc))
3581                 __dw_mci_enable_sdio_irq(host->slot, 1);
3582
3583         /* Now that slots are all setup, we can enable card detect */
3584         dw_mci_enable_cd(host);
3585
3586         return 0;
3587
3588 err:
3589         if (host->slot &&
3590             (mmc_can_gpio_cd(host->slot->mmc) ||
3591              !mmc_card_is_removable(host->slot->mmc)))
3592                 clk_disable_unprepare(host->biu_clk);
3593
3594         return ret;
3595 }
3596 EXPORT_SYMBOL(dw_mci_runtime_resume);
3597 #endif /* CONFIG_PM */
3598
3599 static int __init dw_mci_init(void)
3600 {
3601         pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
3602         return 0;
3603 }
3604
3605 static void __exit dw_mci_exit(void)
3606 {
3607 }
3608
3609 module_init(dw_mci_init);
3610 module_exit(dw_mci_exit);
3611
3612 MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
3613 MODULE_AUTHOR("NXP Semiconductor VietNam");
3614 MODULE_AUTHOR("Imagination Technologies Ltd");
3615 MODULE_LICENSE("GPL v2");