drivers/mmc/host/dw_mmc.c

   1 /*
   2  * Synopsys DesignWare Multimedia Card Interface driver
   3  *  (Based on NXP driver for lpc 31xx)
   4  *
   5  * Copyright (C) 2009 NXP Semiconductors
   6  * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #include <linux/blkdev.h>
  15 #include <linux/clk.h>
  16 #include <linux/debugfs.h>
  17 #include <linux/device.h>
  18 #include <linux/dma-mapping.h>
  19 #include <linux/err.h>
  20 #include <linux/init.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/ioport.h>
  23 #include <linux/module.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/seq_file.h>
  26 #include <linux/slab.h>
  27 #include <linux/stat.h>
  28 #include <linux/delay.h>
  29 #include <linux/irq.h>
  30 #include <linux/mmc/card.h>
  31 #include <linux/mmc/host.h>
  32 #include <linux/mmc/mmc.h>
  33 #include <linux/mmc/sd.h>
  34 #include <linux/mmc/sdio.h>
  35 #include <linux/mmc/dw_mmc.h>
  36 #include <linux/bitops.h>
  37 #include <linux/regulator/consumer.h>
  38 #include <linux/of.h>
  39 #include <linux/of_gpio.h>
  40 #include <linux/mmc/slot-gpio.h>
  41
  42 #include "dw_mmc.h"
  43
  44 /* Common flag combinations */
  45 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
  46                                  SDMMC_INT_HTO | SDMMC_INT_SBE  | \
  47                                  SDMMC_INT_EBE | SDMMC_INT_HLE)
  48 #define DW_MCI_CMD_ERROR_FLAGS  (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
  49                                  SDMMC_INT_RESP_ERR | SDMMC_INT_HLE)
  50 #define DW_MCI_ERROR_FLAGS      (DW_MCI_DATA_ERROR_FLAGS | \
  51                                  DW_MCI_CMD_ERROR_FLAGS)
  52 #define DW_MCI_SEND_STATUS      1
  53 #define DW_MCI_RECV_STATUS      2
  54 #define DW_MCI_DMA_THRESHOLD    16
  55
  56 #define DW_MCI_FREQ_MAX 200000000       /* unit: HZ */
  57 #define DW_MCI_FREQ_MIN 400000          /* unit: HZ */
  58
  59 #define IDMAC_INT_CLR           (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
  60                                  SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
  61                                  SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
  62                                  SDMMC_IDMAC_INT_TI)
  63
  64 #define DESC_RING_BUF_SZ        PAGE_SIZE
  65
  66 struct idmac_desc_64addr {
  67         u32             des0;   /* Control Descriptor */
  68
  69         u32             des1;   /* Reserved */
  70
  71         u32             des2;   /*Buffer sizes */
  72 #define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \
  73         ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \
  74          ((cpu_to_le32(s)) & cpu_to_le32(0x1fff)))
  75
  76         u32             des3;   /* Reserved */
  77
  78         u32             des4;   /* Lower 32-bits of Buffer Address Pointer 1*/
  79         u32             des5;   /* Upper 32-bits of Buffer Address Pointer 1*/
  80
  81         u32             des6;   /* Lower 32-bits of Next Descriptor Address */
  82         u32             des7;   /* Upper 32-bits of Next Descriptor Address */
  83 };
  84
  85 struct idmac_desc {
  86         __le32          des0;   /* Control Descriptor */
  87 #define IDMAC_DES0_DIC  BIT(1)
  88 #define IDMAC_DES0_LD   BIT(2)
  89 #define IDMAC_DES0_FD   BIT(3)
  90 #define IDMAC_DES0_CH   BIT(4)
  91 #define IDMAC_DES0_ER   BIT(5)
  92 #define IDMAC_DES0_CES  BIT(30)
  93 #define IDMAC_DES0_OWN  BIT(31)
  94
  95         __le32          des1;   /* Buffer sizes */
  96 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
  97         ((d)->des1 = ((d)->des1 & cpu_to_le32(0x03ffe000)) | (cpu_to_le32((s) & 0x1fff)))
  98
  99         __le32          des2;   /* buffer 1 physical address */
 100
 101         __le32          des3;   /* buffer 2 physical address */
 102 };
 103
 104 /* Each descriptor can transfer up to 4KB of data in chained mode */
 105 #define DW_MCI_DESC_DATA_LENGTH 0x1000
 106
 107 static bool dw_mci_reset(struct dw_mci *host);
 108 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
 109 static int dw_mci_card_busy(struct mmc_host *mmc);
 110 static int dw_mci_get_cd(struct mmc_host *mmc);
 111
 112 #if defined(CONFIG_DEBUG_FS)
 113 static int dw_mci_req_show(struct seq_file *s, void *v)
 114 {
 115         struct dw_mci_slot *slot = s->private;
 116         struct mmc_request *mrq;
 117         struct mmc_command *cmd;
 118         struct mmc_command *stop;
 119         struct mmc_data *data;
 120
 121         /* Make sure we get a consistent snapshot */
 122         spin_lock_bh(&slot->host->lock);
 123         mrq = slot->mrq;
 124
 125         if (mrq) {
 126                 cmd = mrq->cmd;
 127                 data = mrq->data;
 128                 stop = mrq->stop;
 129
 130                 if (cmd)
 131                         seq_printf(s,
 132                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 133                                    cmd->opcode, cmd->arg, cmd->flags,
 134                                    cmd->resp[0], cmd->resp[1], cmd->resp[2],
 135                                    cmd->resp[2], cmd->error);
 136                 if (data)
 137                         seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
 138                                    data->bytes_xfered, data->blocks,
 139                                    data->blksz, data->flags, data->error);
 140                 if (stop)
 141                         seq_printf(s,
 142                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 143                                    stop->opcode, stop->arg, stop->flags,
 144                                    stop->resp[0], stop->resp[1], stop->resp[2],
 145                                    stop->resp[2], stop->error);
 146         }
 147
 148         spin_unlock_bh(&slot->host->lock);
 149
 150         return 0;
 151 }
 152
 153 static int dw_mci_req_open(struct inode *inode, struct file *file)
 154 {
 155         return single_open(file, dw_mci_req_show, inode->i_private);
 156 }
 157
 158 static const struct file_operations dw_mci_req_fops = {
 159         .owner          = THIS_MODULE,
 160         .open           = dw_mci_req_open,
 161         .read           = seq_read,
 162         .llseek         = seq_lseek,
 163         .release        = single_release,
 164 };
 165
 166 static int dw_mci_regs_show(struct seq_file *s, void *v)
 167 {
 168         seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS);
 169         seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS);
 170         seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD);
 171         seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL);
 172         seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK);
 173         seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA);
 174
 175         return 0;
 176 }
 177
 178 static int dw_mci_regs_open(struct inode *inode, struct file *file)
 179 {
 180         return single_open(file, dw_mci_regs_show, inode->i_private);
 181 }
 182
 183 static const struct file_operations dw_mci_regs_fops = {
 184         .owner          = THIS_MODULE,
 185         .open           = dw_mci_regs_open,
 186         .read           = seq_read,
 187         .llseek         = seq_lseek,
 188         .release        = single_release,
 189 };
 190
 191 static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
 192 {
 193         struct mmc_host *mmc = slot->mmc;
 194         struct dw_mci *host = slot->host;
 195         struct dentry *root;
 196         struct dentry *node;
 197
 198         root = mmc->debugfs_root;
 199         if (!root)
 200                 return;
 201
 202         node = debugfs_create_file("regs", S_IRUSR, root, host,
 203                                    &dw_mci_regs_fops);
 204         if (!node)
 205                 goto err;
 206
 207         node = debugfs_create_file("req", S_IRUSR, root, slot,
 208                                    &dw_mci_req_fops);
 209         if (!node)
 210                 goto err;
 211
 212         node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
 213         if (!node)
 214                 goto err;
 215
 216         node = debugfs_create_x32("pending_events", S_IRUSR, root,
 217                                   (u32 *)&host->pending_events);
 218         if (!node)
 219                 goto err;
 220
 221         node = debugfs_create_x32("completed_events", S_IRUSR, root,
 222                                   (u32 *)&host->completed_events);
 223         if (!node)
 224                 goto err;
 225
 226         return;
 227
 228 err:
 229         dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
 230 }
 231 #endif /* defined(CONFIG_DEBUG_FS) */
 232
 233 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg);
 234
 235 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
 236 {
 237         struct mmc_data *data;
 238         struct dw_mci_slot *slot = mmc_priv(mmc);
 239         struct dw_mci *host = slot->host;
 240         u32 cmdr;
 241
 242         cmd->error = -EINPROGRESS;
 243         cmdr = cmd->opcode;
 244
 245         if (cmd->opcode == MMC_STOP_TRANSMISSION ||
 246             cmd->opcode == MMC_GO_IDLE_STATE ||
 247             cmd->opcode == MMC_GO_INACTIVE_STATE ||
 248             (cmd->opcode == SD_IO_RW_DIRECT &&
 249              ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT))
 250                 cmdr |= SDMMC_CMD_STOP;
 251         else if (cmd->opcode != MMC_SEND_STATUS && cmd->data)
 252                 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
 253
 254         if (cmd->opcode == SD_SWITCH_VOLTAGE) {
 255                 u32 clk_en_a;
 256
 257                 /* Special bit makes CMD11 not die */
 258                 cmdr |= SDMMC_CMD_VOLT_SWITCH;
 259
 260                 /* Change state to continue to handle CMD11 weirdness */
 261                 WARN_ON(slot->host->state != STATE_SENDING_CMD);
 262                 slot->host->state = STATE_SENDING_CMD11;
 263
 264                 /*
 265                  * We need to disable low power mode (automatic clock stop)
 266                  * while doing voltage switch so we don't confuse the card,
 267                  * since stopping the clock is a specific part of the UHS
 268                  * voltage change dance.
 269                  *
 270                  * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be
 271                  * unconditionally turned back on in dw_mci_setup_bus() if it's
 272                  * ever called with a non-zero clock.  That shouldn't happen
 273                  * until the voltage change is all done.
 274                  */
 275                 clk_en_a = mci_readl(host, CLKENA);
 276                 clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id);
 277                 mci_writel(host, CLKENA, clk_en_a);
 278                 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
 279                              SDMMC_CMD_PRV_DAT_WAIT, 0);
 280         }
 281
 282         if (cmd->flags & MMC_RSP_PRESENT) {
 283                 /* We expect a response, so set this bit */
 284                 cmdr |= SDMMC_CMD_RESP_EXP;
 285                 if (cmd->flags & MMC_RSP_136)
 286                         cmdr |= SDMMC_CMD_RESP_LONG;
 287         }
 288
 289         if (cmd->flags & MMC_RSP_CRC)
 290                 cmdr |= SDMMC_CMD_RESP_CRC;
 291
 292         data = cmd->data;
 293         if (data) {
 294                 cmdr |= SDMMC_CMD_DAT_EXP;
 295                 if (data->flags & MMC_DATA_WRITE)
 296                         cmdr |= SDMMC_CMD_DAT_WR;
 297         }
 298
 299         if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &slot->flags))
 300                 cmdr |= SDMMC_CMD_USE_HOLD_REG;
 301
 302         return cmdr;
 303 }
 304
 305 static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd)
 306 {
 307         struct mmc_command *stop;
 308         u32 cmdr;
 309
 310         if (!cmd->data)
 311                 return 0;
 312
 313         stop = &host->stop_abort;
 314         cmdr = cmd->opcode;
 315         memset(stop, 0, sizeof(struct mmc_command));
 316
 317         if (cmdr == MMC_READ_SINGLE_BLOCK ||
 318             cmdr == MMC_READ_MULTIPLE_BLOCK ||
 319             cmdr == MMC_WRITE_BLOCK ||
 320             cmdr == MMC_WRITE_MULTIPLE_BLOCK ||
 321             cmdr == MMC_SEND_TUNING_BLOCK ||
 322             cmdr == MMC_SEND_TUNING_BLOCK_HS200) {
 323                 stop->opcode = MMC_STOP_TRANSMISSION;
 324                 stop->arg = 0;
 325                 stop->flags = MMC_RSP_R1B | MMC_CMD_AC;
 326         } else if (cmdr == SD_IO_RW_EXTENDED) {
 327                 stop->opcode = SD_IO_RW_DIRECT;
 328                 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
 329                              ((cmd->arg >> 28) & 0x7);
 330                 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC;
 331         } else {
 332                 return 0;
 333         }
 334
 335         cmdr = stop->opcode | SDMMC_CMD_STOP |
 336                 SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP;
 337
 338         return cmdr;
 339 }
 340
 341 static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags)
 342 {
 343         unsigned long timeout = jiffies + msecs_to_jiffies(500);
 344
 345         /*
 346          * Databook says that before issuing a new data transfer command
 347          * we need to check to see if the card is busy.  Data transfer commands
 348          * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that.
 349          *
 350          * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is
 351          * expected.
 352          */
 353         if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) &&
 354             !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) {
 355                 while (mci_readl(host, STATUS) & SDMMC_STATUS_BUSY) {
 356                         if (time_after(jiffies, timeout)) {
 357                                 /* Command will fail; we'll pass error then */
 358                                 dev_err(host->dev, "Busy; trying anyway\n");
 359                                 break;
 360                         }
 361                         udelay(10);
 362                 }
 363         }
 364 }
 365
 366 static void dw_mci_start_command(struct dw_mci *host,
 367                                  struct mmc_command *cmd, u32 cmd_flags)
 368 {
 369         host->cmd = cmd;
 370         dev_vdbg(host->dev,
 371                  "start command: ARGR=0x%08x CMDR=0x%08x\n",
 372                  cmd->arg, cmd_flags);
 373
 374         mci_writel(host, CMDARG, cmd->arg);
 375         wmb(); /* drain writebuffer */
 376         dw_mci_wait_while_busy(host, cmd_flags);
 377
 378         mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
 379 }
 380
 381 static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data)
 382 {
 383         struct mmc_command *stop = &host->stop_abort;
 384
 385         dw_mci_start_command(host, stop, host->stop_cmdr);
 386 }
 387
 388 /* DMA interface functions */
 389 static void dw_mci_stop_dma(struct dw_mci *host)
 390 {
 391         if (host->using_dma) {
 392                 host->dma_ops->stop(host);
 393                 host->dma_ops->cleanup(host);
 394         }
 395
 396         /* Data transfer was stopped by the interrupt handler */
 397         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 398 }
 399
 400 static int dw_mci_get_dma_dir(struct mmc_data *data)
 401 {
 402         if (data->flags & MMC_DATA_WRITE)
 403                 return DMA_TO_DEVICE;
 404         else
 405                 return DMA_FROM_DEVICE;
 406 }
 407
 408 static void dw_mci_dma_cleanup(struct dw_mci *host)
 409 {
 410         struct mmc_data *data = host->data;
 411
 412         if (data)
 413                 if (!data->host_cookie)
 414                         dma_unmap_sg(host->dev,
 415                                      data->sg,
 416                                      data->sg_len,
 417                                      dw_mci_get_dma_dir(data));
 418 }
 419
 420 static void dw_mci_idmac_reset(struct dw_mci *host)
 421 {
 422         u32 bmod = mci_readl(host, BMOD);
 423         /* Software reset of DMA */
 424         bmod |= SDMMC_IDMAC_SWRESET;
 425         mci_writel(host, BMOD, bmod);
 426 }
 427
 428 static void dw_mci_idmac_stop_dma(struct dw_mci *host)
 429 {
 430         u32 temp;
 431
 432         /* Disable and reset the IDMAC interface */
 433         temp = mci_readl(host, CTRL);
 434         temp &= ~SDMMC_CTRL_USE_IDMAC;
 435         temp |= SDMMC_CTRL_DMA_RESET;
 436         mci_writel(host, CTRL, temp);
 437
 438         /* Stop the IDMAC running */
 439         temp = mci_readl(host, BMOD);
 440         temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
 441         temp |= SDMMC_IDMAC_SWRESET;
 442         mci_writel(host, BMOD, temp);
 443 }
 444
 445 static void dw_mci_dmac_complete_dma(void *arg)
 446 {
 447         struct dw_mci *host = arg;
 448         struct mmc_data *data = host->data;
 449
 450         dev_vdbg(host->dev, "DMA complete\n");
 451
 452         if ((host->use_dma == TRANS_MODE_EDMAC) &&
 453             data && (data->flags & MMC_DATA_READ))
 454                 /* Invalidate cache after read */
 455                 dma_sync_sg_for_cpu(mmc_dev(host->cur_slot->mmc),
 456                                     data->sg,
 457                                     data->sg_len,
 458                                     DMA_FROM_DEVICE);
 459
 460         host->dma_ops->cleanup(host);
 461
 462         /*
 463          * If the card was removed, data will be NULL. No point in trying to
 464          * send the stop command or waiting for NBUSY in this case.
 465          */
 466         if (data) {
 467                 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 468                 tasklet_schedule(&host->tasklet);
 469         }
 470 }
 471
 472 static int dw_mci_idmac_init(struct dw_mci *host)
 473 {
 474         int i;
 475
 476         if (host->dma_64bit_address == 1) {
 477                 struct idmac_desc_64addr *p;
 478                 /* Number of descriptors in the ring buffer */
 479                 host->ring_size =
 480                         DESC_RING_BUF_SZ / sizeof(struct idmac_desc_64addr);
 481
 482                 /* Forward link the descriptor list */
 483                 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1;
 484                                                                 i++, p++) {
 485                         p->des6 = (host->sg_dma +
 486                                         (sizeof(struct idmac_desc_64addr) *
 487                                                         (i + 1))) & 0xffffffff;
 488
 489                         p->des7 = (u64)(host->sg_dma +
 490                                         (sizeof(struct idmac_desc_64addr) *
 491                                                         (i + 1))) >> 32;
 492                         /* Initialize reserved and buffer size fields to "0" */
 493                         p->des0 = 0;
 494                         p->des1 = 0;
 495                         p->des2 = 0;
 496                         p->des3 = 0;
 497                 }
 498
 499                 /* Set the last descriptor as the end-of-ring descriptor */
 500                 p->des6 = host->sg_dma & 0xffffffff;
 501                 p->des7 = (u64)host->sg_dma >> 32;
 502                 p->des0 = IDMAC_DES0_ER;
 503
 504         } else {
 505                 struct idmac_desc *p;
 506                 /* Number of descriptors in the ring buffer */
 507                 host->ring_size =
 508                         DESC_RING_BUF_SZ / sizeof(struct idmac_desc);
 509
 510                 /* Forward link the descriptor list */
 511                 for (i = 0, p = host->sg_cpu;
 512                      i < host->ring_size - 1;
 513                      i++, p++) {
 514                         p->des3 = cpu_to_le32(host->sg_dma +
 515                                         (sizeof(struct idmac_desc) * (i + 1)));
 516                         p->des0 = 0;
 517                         p->des1 = 0;
 518                 }
 519
 520                 /* Set the last descriptor as the end-of-ring descriptor */
 521                 p->des3 = cpu_to_le32(host->sg_dma);
 522                 p->des0 = cpu_to_le32(IDMAC_DES0_ER);
 523         }
 524
 525         dw_mci_idmac_reset(host);
 526
 527         if (host->dma_64bit_address == 1) {
 528                 /* Mask out interrupts - get Tx & Rx complete only */
 529                 mci_writel(host, IDSTS64, IDMAC_INT_CLR);
 530                 mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI |
 531                                 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
 532
 533                 /* Set the descriptor base address */
 534                 mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff);
 535                 mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32);
 536
 537         } else {
 538                 /* Mask out interrupts - get Tx & Rx complete only */
 539                 mci_writel(host, IDSTS, IDMAC_INT_CLR);
 540                 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI |
 541                                 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
 542
 543                 /* Set the descriptor base address */
 544                 mci_writel(host, DBADDR, host->sg_dma);
 545         }
 546
 547         return 0;
 548 }
 549
 550 static inline int dw_mci_prepare_desc64(struct dw_mci *host,
 551                                          struct mmc_data *data,
 552                                          unsigned int sg_len)
 553 {
 554         unsigned int desc_len;
 555         struct idmac_desc_64addr *desc_first, *desc_last, *desc;
 556         unsigned long timeout;
 557         int i;
 558
 559         desc_first = desc_last = desc = host->sg_cpu;
 560
 561         for (i = 0; i < sg_len; i++) {
 562                 unsigned int length = sg_dma_len(&data->sg[i]);
 563
 564                 u64 mem_addr = sg_dma_address(&data->sg[i]);
 565
 566                 for ( ; length ; desc++) {
 567                         desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
 568                                    length : DW_MCI_DESC_DATA_LENGTH;
 569
 570                         length -= desc_len;
 571
 572                         /*
 573                          * Wait for the former clear OWN bit operation
 574                          * of IDMAC to make sure that this descriptor
 575                          * isn't still owned by IDMAC as IDMAC's write
 576                          * ops and CPU's read ops are asynchronous.
 577                          */
 578                         timeout = jiffies + msecs_to_jiffies(100);
 579                         while (readl(&desc->des0) & IDMAC_DES0_OWN) {
 580                                 if (time_after(jiffies, timeout))
 581                                         goto err_own_bit;
 582                                 udelay(10);
 583                         }
 584
 585                         /*
 586                          * Set the OWN bit and disable interrupts
 587                          * for this descriptor
 588                          */
 589                         desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC |
 590                                                 IDMAC_DES0_CH;
 591
 592                         /* Buffer length */
 593                         IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, desc_len);
 594
 595                         /* Physical address to DMA to/from */
 596                         desc->des4 = mem_addr & 0xffffffff;
 597                         desc->des5 = mem_addr >> 32;
 598
 599                         /* Update physical address for the next desc */
 600                         mem_addr += desc_len;
 601
 602                         /* Save pointer to the last descriptor */
 603                         desc_last = desc;
 604                 }
 605         }
 606
 607         /* Set first descriptor */
 608         desc_first->des0 |= IDMAC_DES0_FD;
 609
 610         /* Set last descriptor */
 611         desc_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
 612         desc_last->des0 |= IDMAC_DES0_LD;
 613
 614         return 0;
 615 err_own_bit:
 616         /* restore the descriptor chain as it's polluted */
 617         dev_dbg(host->dev, "desciptor is still owned by IDMAC.\n");
 618         memset(host->sg_cpu, 0, DESC_RING_BUF_SZ);
 619         dw_mci_idmac_init(host);
 620         return -EINVAL;
 621 }
 622
 623
 624 static inline int dw_mci_prepare_desc32(struct dw_mci *host,
 625                                          struct mmc_data *data,
 626                                          unsigned int sg_len)
 627 {
 628         unsigned int desc_len;
 629         struct idmac_desc *desc_first, *desc_last, *desc;
 630         unsigned long timeout;
 631         int i;
 632
 633         desc_first = desc_last = desc = host->sg_cpu;
 634
 635         for (i = 0; i < sg_len; i++) {
 636                 unsigned int length = sg_dma_len(&data->sg[i]);
 637
 638                 u32 mem_addr = sg_dma_address(&data->sg[i]);
 639
 640                 for ( ; length ; desc++) {
 641                         desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
 642                                    length : DW_MCI_DESC_DATA_LENGTH;
 643
 644                         length -= desc_len;
 645
 646                         /*
 647                          * Wait for the former clear OWN bit operation
 648                          * of IDMAC to make sure that this descriptor
 649                          * isn't still owned by IDMAC as IDMAC's write
 650                          * ops and CPU's read ops are asynchronous.
 651                          */
 652                         timeout = jiffies + msecs_to_jiffies(100);
 653                         while (readl(&desc->des0) &
 654                                cpu_to_le32(IDMAC_DES0_OWN)) {
 655                                 if (time_after(jiffies, timeout))
 656                                         goto err_own_bit;
 657                                 udelay(10);
 658                         }
 659
 660                         /*
 661                          * Set the OWN bit and disable interrupts
 662                          * for this descriptor
 663                          */
 664                         desc->des0 = cpu_to_le32(IDMAC_DES0_OWN |
 665                                                  IDMAC_DES0_DIC |
 666                                                  IDMAC_DES0_CH);
 667
 668                         /* Buffer length */
 669                         IDMAC_SET_BUFFER1_SIZE(desc, desc_len);
 670
 671                         /* Physical address to DMA to/from */
 672                         desc->des2 = cpu_to_le32(mem_addr);
 673
 674                         /* Update physical address for the next desc */
 675                         mem_addr += desc_len;
 676
 677                         /* Save pointer to the last descriptor */
 678                         desc_last = desc;
 679                 }
 680         }
 681
 682         /* Set first descriptor */
 683         desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD);
 684
 685         /* Set last descriptor */
 686         desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH |
 687                                        IDMAC_DES0_DIC));
 688         desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD);
 689
 690         return 0;
 691 err_own_bit:
 692         /* restore the descriptor chain as it's polluted */
 693         dev_dbg(host->dev, "desciptor is still owned by IDMAC.\n");
 694         memset(host->sg_cpu, 0, DESC_RING_BUF_SZ);
 695         dw_mci_idmac_init(host);
 696         return -EINVAL;
 697 }
 698
 699 static int dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
 700 {
 701         u32 temp;
 702         int ret;
 703
 704         if (host->dma_64bit_address == 1)
 705                 ret = dw_mci_prepare_desc64(host, host->data, sg_len);
 706         else
 707                 ret = dw_mci_prepare_desc32(host, host->data, sg_len);
 708
 709         if (ret)
 710                 goto out;
 711
 712         /* drain writebuffer */
 713         wmb();
 714
 715         /* Make sure to reset DMA in case we did PIO before this */
 716         dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
 717         dw_mci_idmac_reset(host);
 718
 719         /* Select IDMAC interface */
 720         temp = mci_readl(host, CTRL);
 721         temp |= SDMMC_CTRL_USE_IDMAC;
 722         mci_writel(host, CTRL, temp);
 723
 724         /* drain writebuffer */
 725         wmb();
 726
 727         /* Enable the IDMAC */
 728         temp = mci_readl(host, BMOD);
 729         temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
 730         mci_writel(host, BMOD, temp);
 731
 732         /* Start it running */
 733         mci_writel(host, PLDMND, 1);
 734
 735 out:
 736         return ret;
 737 }
 738
 739 static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
 740         .init = dw_mci_idmac_init,
 741         .start = dw_mci_idmac_start_dma,
 742         .stop = dw_mci_idmac_stop_dma,
 743         .complete = dw_mci_dmac_complete_dma,
 744         .cleanup = dw_mci_dma_cleanup,
 745 };
 746
 747 static void dw_mci_edmac_stop_dma(struct dw_mci *host)
 748 {
 749         dmaengine_terminate_async(host->dms->ch);
 750 }
 751
 752 static int dw_mci_edmac_start_dma(struct dw_mci *host,
 753                                             unsigned int sg_len)
 754 {
 755         struct dma_slave_config cfg;
 756         struct dma_async_tx_descriptor *desc = NULL;
 757         struct scatterlist *sgl = host->data->sg;
 758         const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
 759         u32 sg_elems = host->data->sg_len;
 760         u32 fifoth_val;
 761         u32 fifo_offset = host->fifo_reg - host->regs;
 762         int ret = 0;
 763
 764         /* Set external dma config: burst size, burst width */
 765         memset(&cfg, 0, sizeof(cfg));
 766         cfg.dst_addr = host->phy_regs + fifo_offset;
 767         cfg.src_addr = cfg.dst_addr;
 768         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 769         cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 770
 771         /* Match burst msize with external dma config */
 772         fifoth_val = mci_readl(host, FIFOTH);
 773         cfg.dst_maxburst = mszs[(fifoth_val >> 28) & 0x7];
 774         cfg.src_maxburst = cfg.dst_maxburst;
 775
 776         if (host->data->flags & MMC_DATA_WRITE)
 777                 cfg.direction = DMA_MEM_TO_DEV;
 778         else
 779                 cfg.direction = DMA_DEV_TO_MEM;
 780
 781         ret = dmaengine_slave_config(host->dms->ch, &cfg);
 782         if (ret) {
 783                 dev_err(host->dev, "Failed to config edmac.\n");
 784                 return -EBUSY;
 785         }
 786
 787         desc = dmaengine_prep_slave_sg(host->dms->ch, sgl,
 788                                        sg_len, cfg.direction,
 789                                        DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 790         if (!desc) {
 791                 dev_err(host->dev, "Can't prepare slave sg.\n");
 792                 return -EBUSY;
 793         }
 794
 795         /* Set dw_mci_dmac_complete_dma as callback */
 796         desc->callback = dw_mci_dmac_complete_dma;
 797         desc->callback_param = (void *)host;
 798         dmaengine_submit(desc);
 799
 800         /* Flush cache before write */
 801         if (host->data->flags & MMC_DATA_WRITE)
 802                 dma_sync_sg_for_device(mmc_dev(host->cur_slot->mmc), sgl,
 803                                        sg_elems, DMA_TO_DEVICE);
 804
 805         dma_async_issue_pending(host->dms->ch);
 806
 807         return 0;
 808 }
 809
 810 static int dw_mci_edmac_init(struct dw_mci *host)
 811 {
 812         /* Request external dma channel */
 813         host->dms = kzalloc(sizeof(struct dw_mci_dma_slave), GFP_KERNEL);
 814         if (!host->dms)
 815                 return -ENOMEM;
 816
 817         host->dms->ch = dma_request_slave_channel(host->dev, "rx-tx");
 818         if (!host->dms->ch) {
 819                 dev_err(host->dev, "Failed to get external DMA channel.\n");
 820                 kfree(host->dms);
 821                 host->dms = NULL;
 822                 return -ENXIO;
 823         }
 824
 825         return 0;
 826 }
 827
 828 static void dw_mci_edmac_exit(struct dw_mci *host)
 829 {
 830         if (host->dms) {
 831                 if (host->dms->ch) {
 832                         dma_release_channel(host->dms->ch);
 833                         host->dms->ch = NULL;
 834                 }
 835                 kfree(host->dms);
 836                 host->dms = NULL;
 837         }
 838 }
 839
 840 static const struct dw_mci_dma_ops dw_mci_edmac_ops = {
 841         .init = dw_mci_edmac_init,
 842         .exit = dw_mci_edmac_exit,
 843         .start = dw_mci_edmac_start_dma,
 844         .stop = dw_mci_edmac_stop_dma,
 845         .complete = dw_mci_dmac_complete_dma,
 846         .cleanup = dw_mci_dma_cleanup,
 847 };
 848
 849 static int dw_mci_pre_dma_transfer(struct dw_mci *host,
 850                                    struct mmc_data *data,
 851                                    bool next)
 852 {
 853         struct scatterlist *sg;
 854         unsigned int i, sg_len;
 855
 856         if (!next && data->host_cookie)
 857                 return data->host_cookie;
 858
 859         /*
 860          * We don't do DMA on "complex" transfers, i.e. with
 861          * non-word-aligned buffers or lengths. Also, we don't bother
 862          * with all the DMA setup overhead for short transfers.
 863          */
 864         if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
 865                 return -EINVAL;
 866
 867         if (data->blksz & 3)
 868                 return -EINVAL;
 869
 870         for_each_sg(data->sg, sg, data->sg_len, i) {
 871                 if (sg->offset & 3 || sg->length & 3)
 872                         return -EINVAL;
 873         }
 874
 875         sg_len = dma_map_sg(host->dev,
 876                             data->sg,
 877                             data->sg_len,
 878                             dw_mci_get_dma_dir(data));
 879         if (sg_len == 0)
 880                 return -EINVAL;
 881
 882         if (next)
 883                 data->host_cookie = sg_len;
 884
 885         return sg_len;
 886 }
 887
 888 static void dw_mci_pre_req(struct mmc_host *mmc,
 889                            struct mmc_request *mrq,
 890                            bool is_first_req)
 891 {
 892         struct dw_mci_slot *slot = mmc_priv(mmc);
 893         struct mmc_data *data = mrq->data;
 894
 895         if (!slot->host->use_dma || !data)
 896                 return;
 897
 898         if (data->host_cookie) {
 899                 data->host_cookie = 0;
 900                 return;
 901         }
 902
 903         if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0)
 904                 data->host_cookie = 0;
 905 }
 906
 907 static void dw_mci_post_req(struct mmc_host *mmc,
 908                             struct mmc_request *mrq,
 909                             int err)
 910 {
 911         struct dw_mci_slot *slot = mmc_priv(mmc);
 912         struct mmc_data *data = mrq->data;
 913
 914         if (!slot->host->use_dma || !data)
 915                 return;
 916
 917         if (data->host_cookie)
 918                 dma_unmap_sg(slot->host->dev,
 919                              data->sg,
 920                              data->sg_len,
 921                              dw_mci_get_dma_dir(data));
 922         data->host_cookie = 0;
 923 }
 924
 925 static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
 926 {
 927         unsigned int blksz = data->blksz;
 928         const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
 929         u32 fifo_width = 1 << host->data_shift;
 930         u32 blksz_depth = blksz / fifo_width, fifoth_val;
 931         u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
 932         int idx = ARRAY_SIZE(mszs) - 1;
 933
 934         /* pio should ship this scenario */
 935         if (!host->use_dma)
 936                 return;
 937
 938         tx_wmark = (host->fifo_depth) / 2;
 939         tx_wmark_invers = host->fifo_depth - tx_wmark;
 940
 941         /*
 942          * MSIZE is '1',
 943          * if blksz is not a multiple of the FIFO width
 944          */
 945         if (blksz % fifo_width)
 946                 goto done;
 947
 948         do {
 949                 if (!((blksz_depth % mszs[idx]) ||
 950                      (tx_wmark_invers % mszs[idx]))) {
 951                         msize = idx;
 952                         rx_wmark = mszs[idx] - 1;
 953                         break;
 954                 }
 955         } while (--idx > 0);
 956         /*
 957          * If idx is '0', it won't be tried
 958          * Thus, initial values are uesed
 959          */
 960 done:
 961         fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
 962         mci_writel(host, FIFOTH, fifoth_val);
 963 }
 964
 965 static void dw_mci_ctrl_thld(struct dw_mci *host, struct mmc_data *data)
 966 {
 967         unsigned int blksz = data->blksz;
 968         u32 blksz_depth, fifo_depth;
 969         u16 thld_size;
 970         u8 enable;
 971
 972         /*
 973          * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is
 974          * in the FIFO region, so we really shouldn't access it).
 975          */
 976         if (host->verid < DW_MMC_240A ||
 977                 (host->verid < DW_MMC_280A && data->flags & MMC_DATA_WRITE))
 978                 return;
 979
 980         /*
 981          * Card write Threshold is introduced since 2.80a
 982          * It's used when HS400 mode is enabled.
 983          */
 984         if (data->flags & MMC_DATA_WRITE &&
 985                 host->timing != MMC_TIMING_MMC_HS400)
 986                 goto disable;
 987
 988         if (data->flags & MMC_DATA_WRITE)
 989                 enable = SDMMC_CARD_WR_THR_EN;
 990         else
 991                 enable = SDMMC_CARD_RD_THR_EN;
 992
 993         if (host->timing != MMC_TIMING_MMC_HS200 &&
 994             host->timing != MMC_TIMING_UHS_SDR104 &&
 995             host->timing != MMC_TIMING_MMC_HS400)
 996                 goto disable;
 997
 998         blksz_depth = blksz / (1 << host->data_shift);
 999         fifo_depth = host->fifo_depth;
1000
1001         if (blksz_depth > fifo_depth)
1002                 goto disable;
1003
1004         /*
1005          * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
1006          * If (blksz_depth) <  (fifo_depth >> 1), should be thld_size = blksz
1007          * Currently just choose blksz.
1008          */
1009         thld_size = blksz;
1010         mci_writel(host, CDTHRCTL, SDMMC_SET_THLD(thld_size, enable));
1011         return;
1012
1013 disable:
1014         mci_writel(host, CDTHRCTL, 0);
1015 }
1016
1017 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
1018 {
1019         unsigned long irqflags;
1020         int sg_len;
1021         u32 temp;
1022
1023         host->using_dma = 0;
1024
1025         /* If we don't have a channel, we can't do DMA */
1026         if (!host->use_dma)
1027                 return -ENODEV;
1028
1029         sg_len = dw_mci_pre_dma_transfer(host, data, 0);
1030         if (sg_len < 0) {
1031                 host->dma_ops->stop(host);
1032                 return sg_len;
1033         }
1034
1035         host->using_dma = 1;
1036
1037         if (host->use_dma == TRANS_MODE_IDMAC)
1038                 dev_vdbg(host->dev,
1039                          "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
1040                          (unsigned long)host->sg_cpu,
1041                          (unsigned long)host->sg_dma,
1042                          sg_len);
1043
1044         /*
1045          * Decide the MSIZE and RX/TX Watermark.
1046          * If current block size is same with previous size,
1047          * no need to update fifoth.
1048          */
1049         if (host->prev_blksz != data->blksz)
1050                 dw_mci_adjust_fifoth(host, data);
1051
1052         /* Enable the DMA interface */
1053         temp = mci_readl(host, CTRL);
1054         temp |= SDMMC_CTRL_DMA_ENABLE;
1055         mci_writel(host, CTRL, temp);
1056
1057         /* Disable RX/TX IRQs, let DMA handle it */
1058         spin_lock_irqsave(&host->irq_lock, irqflags);
1059         temp = mci_readl(host, INTMASK);
1060         temp  &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
1061         mci_writel(host, INTMASK, temp);
1062         spin_unlock_irqrestore(&host->irq_lock, irqflags);
1063
1064         if (host->dma_ops->start(host, sg_len)) {
1065                 host->dma_ops->stop(host);
1066                 /* We can't do DMA, try PIO for this one */
1067                 dev_dbg(host->dev,
1068                         "%s: fall back to PIO mode for current transfer\n",
1069                         __func__);
1070                 return -ENODEV;
1071         }
1072
1073         return 0;
1074 }
1075
1076 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
1077 {
1078         unsigned long irqflags;
1079         int flags = SG_MITER_ATOMIC;
1080         u32 temp;
1081
1082         data->error = -EINPROGRESS;
1083
1084         WARN_ON(host->data);
1085         host->sg = NULL;
1086         host->data = data;
1087
1088         if (data->flags & MMC_DATA_READ)
1089                 host->dir_status = DW_MCI_RECV_STATUS;
1090         else
1091                 host->dir_status = DW_MCI_SEND_STATUS;
1092
1093         dw_mci_ctrl_thld(host, data);
1094
1095         if (dw_mci_submit_data_dma(host, data)) {
1096                 if (host->data->flags & MMC_DATA_READ)
1097                         flags |= SG_MITER_TO_SG;
1098                 else
1099                         flags |= SG_MITER_FROM_SG;
1100
1101                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
1102                 host->sg = data->sg;
1103                 host->part_buf_start = 0;
1104                 host->part_buf_count = 0;
1105
1106                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
1107
1108                 spin_lock_irqsave(&host->irq_lock, irqflags);
1109                 temp = mci_readl(host, INTMASK);
1110                 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
1111                 mci_writel(host, INTMASK, temp);
1112                 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1113
1114                 temp = mci_readl(host, CTRL);
1115                 temp &= ~SDMMC_CTRL_DMA_ENABLE;
1116                 mci_writel(host, CTRL, temp);
1117
1118                 /*
1119                  * Use the initial fifoth_val for PIO mode.
1120                  * If next issued data may be transfered by DMA mode,
1121                  * prev_blksz should be invalidated.
1122                  */
1123                 mci_writel(host, FIFOTH, host->fifoth_val);
1124                 host->prev_blksz = 0;
1125         } else {
1126                 /*
1127                  * Keep the current block size.
1128                  * It will be used to decide whether to update
1129                  * fifoth register next time.
1130                  */
1131                 host->prev_blksz = data->blksz;
1132         }
1133 }
1134
1135 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
1136 {
1137         struct dw_mci *host = slot->host;
1138         unsigned long timeout = jiffies + msecs_to_jiffies(500);
1139         unsigned int cmd_status = 0;
1140
1141         mci_writel(host, CMDARG, arg);
1142         wmb(); /* drain writebuffer */
1143         dw_mci_wait_while_busy(host, cmd);
1144         mci_writel(host, CMD, SDMMC_CMD_START | cmd);
1145
1146         while (time_before(jiffies, timeout)) {
1147                 cmd_status = mci_readl(host, CMD);
1148                 if (!(cmd_status & SDMMC_CMD_START))
1149                         return;
1150         }
1151         dev_err(&slot->mmc->class_dev,
1152                 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
1153                 cmd, arg, cmd_status);
1154 }
1155
1156 static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
1157 {
1158         struct dw_mci *host = slot->host;
1159         unsigned int clock = slot->clock;
1160         u32 div;
1161         u32 clk_en_a;
1162         u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT;
1163
1164         /* We must continue to set bit 28 in CMD until the change is complete */
1165         if (host->state == STATE_WAITING_CMD11_DONE)
1166                 sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH;
1167
1168         slot->mmc->actual_clock = 0;
1169
1170         if (!clock) {
1171                 mci_writel(host, CLKENA, 0);
1172                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1173         } else if (clock != host->current_speed || force_clkinit) {
1174                 div = host->bus_hz / clock;
1175                 if (host->bus_hz % clock && host->bus_hz > clock)
1176                         /*
1177                          * move the + 1 after the divide to prevent
1178                          * over-clocking the card.
1179                          */
1180                         div += 1;
1181
1182                 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
1183
1184                 if (clock != slot->__clk_old || force_clkinit)
1185                         dev_info(&slot->mmc->class_dev,
1186                                  "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
1187                                  slot->id, host->bus_hz, clock,
1188                                  div ? ((host->bus_hz / div) >> 1) :
1189                                  host->bus_hz, div);
1190
1191                 /* disable clock */
1192                 mci_writel(host, CLKENA, 0);
1193                 mci_writel(host, CLKSRC, 0);
1194
1195                 /* inform CIU */
1196                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1197
1198                 /* set clock to desired speed */
1199                 mci_writel(host, CLKDIV, div);
1200
1201                 /* inform CIU */
1202                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1203
1204                 /* enable clock; only low power if no SDIO */
1205                 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
1206                 if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags))
1207                         clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
1208                 mci_writel(host, CLKENA, clk_en_a);
1209
1210                 /* inform CIU */
1211                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1212
1213                 /* keep the last clock value that was requested from core */
1214                 slot->__clk_old = clock;
1215                 slot->mmc->actual_clock = div ? ((host->bus_hz / div) >> 1) :
1216                                           host->bus_hz;
1217         }
1218
1219         host->current_speed = clock;
1220
1221         /* Set the current slot bus width */
1222         mci_writel(host, CTYPE, (slot->ctype << slot->id));
1223 }
1224
1225 static void __dw_mci_start_request(struct dw_mci *host,
1226                                    struct dw_mci_slot *slot,
1227                                    struct mmc_command *cmd)
1228 {
1229         struct mmc_request *mrq;
1230         struct mmc_data *data;
1231         u32 cmdflags;
1232
1233         mrq = slot->mrq;
1234
1235         host->cur_slot = slot;
1236         host->mrq = mrq;
1237
1238         host->pending_events = 0;
1239         host->completed_events = 0;
1240         host->cmd_status = 0;
1241         host->data_status = 0;
1242         host->dir_status = 0;
1243
1244         data = cmd->data;
1245         if (data) {
1246                 mci_writel(host, TMOUT, 0xFFFFFFFF);
1247                 mci_writel(host, BYTCNT, data->blksz*data->blocks);
1248                 mci_writel(host, BLKSIZ, data->blksz);
1249         }
1250
1251         cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
1252
1253         /* this is the first command, send the initialization clock */
1254         if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
1255                 cmdflags |= SDMMC_CMD_INIT;
1256
1257         if (data) {
1258                 dw_mci_submit_data(host, data);
1259                 wmb(); /* drain writebuffer */
1260         }
1261
1262         dw_mci_start_command(host, cmd, cmdflags);
1263
1264         if (cmd->opcode == SD_SWITCH_VOLTAGE) {
1265                 unsigned long irqflags;
1266
1267                 /*
1268                  * Databook says to fail after 2ms w/ no response, but evidence
1269                  * shows that sometimes the cmd11 interrupt takes over 130ms.
1270                  * We'll set to 500ms, plus an extra jiffy just in case jiffies
1271                  * is just about to roll over.
1272                  *
1273                  * We do this whole thing under spinlock and only if the
1274                  * command hasn't already completed (indicating the the irq
1275                  * already ran so we don't want the timeout).
1276                  */
1277                 spin_lock_irqsave(&host->irq_lock, irqflags);
1278                 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
1279                         mod_timer(&host->cmd11_timer,
1280                                 jiffies + msecs_to_jiffies(500) + 1);
1281                 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1282         }
1283
1284         host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd);
1285 }
1286
1287 static void dw_mci_start_request(struct dw_mci *host,
1288                                  struct dw_mci_slot *slot)
1289 {
1290         struct mmc_request *mrq = slot->mrq;
1291         struct mmc_command *cmd;
1292
1293         cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
1294         __dw_mci_start_request(host, slot, cmd);
1295 }
1296
1297 /* must be called with host->lock held */
1298 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
1299                                  struct mmc_request *mrq)
1300 {
1301         dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1302                  host->state);
1303
1304         slot->mrq = mrq;
1305
1306         if (host->state == STATE_WAITING_CMD11_DONE) {
1307                 dev_warn(&slot->mmc->class_dev,
1308                          "Voltage change didn't complete\n");
1309                 /*
1310                  * this case isn't expected to happen, so we can
1311                  * either crash here or just try to continue on
1312                  * in the closest possible state
1313                  */
1314                 host->state = STATE_IDLE;
1315         }
1316
1317         if (host->state == STATE_IDLE) {
1318                 host->state = STATE_SENDING_CMD;
1319                 dw_mci_start_request(host, slot);
1320         } else {
1321                 list_add_tail(&slot->queue_node, &host->queue);
1322         }
1323 }
1324
1325 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1326 {
1327         struct dw_mci_slot *slot = mmc_priv(mmc);
1328         struct dw_mci *host = slot->host;
1329
1330         WARN_ON(slot->mrq);
1331
1332         /*
1333          * The check for card presence and queueing of the request must be
1334          * atomic, otherwise the card could be removed in between and the
1335          * request wouldn't fail until another card was inserted.
1336          */
1337
1338         if (!dw_mci_get_cd(mmc)) {
1339                 mrq->cmd->error = -ENOMEDIUM;
1340                 mmc_request_done(mmc, mrq);
1341                 return;
1342         }
1343
1344         spin_lock_bh(&host->lock);
1345
1346         dw_mci_queue_request(host, slot, mrq);
1347
1348         spin_unlock_bh(&host->lock);
1349 }
1350
1351 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1352 {
1353         struct dw_mci_slot *slot = mmc_priv(mmc);
1354         const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
1355         u32 regs;
1356         int ret;
1357
1358         switch (ios->bus_width) {
1359         case MMC_BUS_WIDTH_4:
1360                 slot->ctype = SDMMC_CTYPE_4BIT;
1361                 break;
1362         case MMC_BUS_WIDTH_8:
1363                 slot->ctype = SDMMC_CTYPE_8BIT;
1364                 break;
1365         default:
1366                 /* set default 1 bit mode */
1367                 slot->ctype = SDMMC_CTYPE_1BIT;
1368         }
1369
1370         regs = mci_readl(slot->host, UHS_REG);
1371
1372         /* DDR mode set */
1373         if (ios->timing == MMC_TIMING_MMC_DDR52 ||
1374             ios->timing == MMC_TIMING_UHS_DDR50 ||
1375             ios->timing == MMC_TIMING_MMC_HS400)
1376                 regs |= ((0x1 << slot->id) << 16);
1377         else
1378                 regs &= ~((0x1 << slot->id) << 16);
1379
1380         mci_writel(slot->host, UHS_REG, regs);
1381         slot->host->timing = ios->timing;
1382
1383         /*
1384          * Use mirror of ios->clock to prevent race with mmc
1385          * core ios update when finding the minimum.
1386          */
1387         slot->clock = ios->clock;
1388
1389         if (drv_data && drv_data->set_ios)
1390                 drv_data->set_ios(slot->host, ios);
1391
1392         switch (ios->power_mode) {
1393         case MMC_POWER_UP:
1394                 if (!IS_ERR(mmc->supply.vmmc)) {
1395                         ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1396                                         ios->vdd);
1397                         if (ret) {
1398                                 dev_err(slot->host->dev,
1399                                         "failed to enable vmmc regulator\n");
1400                                 /*return, if failed turn on vmmc*/
1401                                 return;
1402                         }
1403                 }
1404                 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
1405                 regs = mci_readl(slot->host, PWREN);
1406                 regs |= (1 << slot->id);
1407                 mci_writel(slot->host, PWREN, regs);
1408                 break;
1409         case MMC_POWER_ON:
1410                 if (!slot->host->vqmmc_enabled) {
1411                         if (!IS_ERR(mmc->supply.vqmmc)) {
1412                                 ret = regulator_enable(mmc->supply.vqmmc);
1413                                 if (ret < 0)
1414                                         dev_err(slot->host->dev,
1415                                                 "failed to enable vqmmc\n");
1416                                 else
1417                                         slot->host->vqmmc_enabled = true;
1418
1419                         } else {
1420                                 /* Keep track so we don't reset again */
1421                                 slot->host->vqmmc_enabled = true;
1422                         }
1423
1424                         /* Reset our state machine after powering on */
1425                         dw_mci_ctrl_reset(slot->host,
1426                                           SDMMC_CTRL_ALL_RESET_FLAGS);
1427                 }
1428
1429                 /* Adjust clock / bus width after power is up */
1430                 dw_mci_setup_bus(slot, false);
1431
1432                 break;
1433         case MMC_POWER_OFF:
1434                 /* Turn clock off before power goes down */
1435                 dw_mci_setup_bus(slot, false);
1436
1437                 if (!IS_ERR(mmc->supply.vmmc))
1438                         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1439
1440                 if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled)
1441                         regulator_disable(mmc->supply.vqmmc);
1442                 slot->host->vqmmc_enabled = false;
1443
1444                 regs = mci_readl(slot->host, PWREN);
1445                 regs &= ~(1 << slot->id);
1446                 mci_writel(slot->host, PWREN, regs);
1447                 break;
1448         default:
1449                 break;
1450         }
1451
1452         if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0)
1453                 slot->host->state = STATE_IDLE;
1454 }
1455
1456 static int dw_mci_card_busy(struct mmc_host *mmc)
1457 {
1458         struct dw_mci_slot *slot = mmc_priv(mmc);
1459         u32 status;
1460
1461         /*
1462          * Check the busy bit which is low when DAT[3:0]
1463          * (the data lines) are 0000
1464          */
1465         status = mci_readl(slot->host, STATUS);
1466
1467         return !!(status & SDMMC_STATUS_BUSY);
1468 }
1469
1470 static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1471 {
1472         struct dw_mci_slot *slot = mmc_priv(mmc);
1473         struct dw_mci *host = slot->host;
1474         const struct dw_mci_drv_data *drv_data = host->drv_data;
1475         u32 uhs;
1476         u32 v18 = SDMMC_UHS_18V << slot->id;
1477         int ret;
1478
1479         if (drv_data && drv_data->switch_voltage)
1480                 return drv_data->switch_voltage(mmc, ios);
1481
1482         /*
1483          * Program the voltage.  Note that some instances of dw_mmc may use
1484          * the UHS_REG for this.  For other instances (like exynos) the UHS_REG
1485          * does no harm but you need to set the regulator directly.  Try both.
1486          */
1487         uhs = mci_readl(host, UHS_REG);
1488         if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1489                 uhs &= ~v18;
1490         else
1491                 uhs |= v18;
1492
1493         if (!IS_ERR(mmc->supply.vqmmc)) {
1494                 ret = mmc_regulator_set_vqmmc(mmc, ios);
1495
1496                 if (ret) {
1497                         dev_dbg(&mmc->class_dev,
1498                                          "Regulator set error %d - %s V\n",
1499                                          ret, uhs & v18 ? "1.8" : "3.3");
1500                         return ret;
1501                 }
1502         }
1503         mci_writel(host, UHS_REG, uhs);
1504
1505         return 0;
1506 }
1507
1508 static int dw_mci_get_ro(struct mmc_host *mmc)
1509 {
1510         int read_only;
1511         struct dw_mci_slot *slot = mmc_priv(mmc);
1512         int gpio_ro = mmc_gpio_get_ro(mmc);
1513
1514         /* Use platform get_ro function, else try on board write protect */
1515         if (gpio_ro >= 0)
1516                 read_only = gpio_ro;
1517         else
1518                 read_only =
1519                         mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
1520
1521         dev_dbg(&mmc->class_dev, "card is %s\n",
1522                 read_only ? "read-only" : "read-write");
1523
1524         return read_only;
1525 }
1526
1527 static int dw_mci_get_cd(struct mmc_host *mmc)
1528 {
1529         int present;
1530         struct dw_mci_slot *slot = mmc_priv(mmc);
1531         struct dw_mci *host = slot->host;
1532         int gpio_cd = mmc_gpio_get_cd(mmc);
1533
1534         /* Use platform get_cd function, else try onboard card detect */
1535         if ((mmc->caps & MMC_CAP_NEEDS_POLL) || !mmc_card_is_removable(mmc))
1536                 present = 1;
1537         else if (gpio_cd >= 0)
1538                 present = gpio_cd;
1539         else
1540                 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
1541                         == 0 ? 1 : 0;
1542
1543         spin_lock_bh(&host->lock);
1544         if (present) {
1545                 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1546                 dev_dbg(&mmc->class_dev, "card is present\n");
1547         } else {
1548                 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1549                 dev_dbg(&mmc->class_dev, "card is not present\n");
1550         }
1551         spin_unlock_bh(&host->lock);
1552
1553         return present;
1554 }
1555
1556 static void dw_mci_hw_reset(struct mmc_host *mmc)
1557 {
1558         struct dw_mci_slot *slot = mmc_priv(mmc);
1559         struct dw_mci *host = slot->host;
1560         int reset;
1561
1562         if (host->use_dma == TRANS_MODE_IDMAC)
1563                 dw_mci_idmac_reset(host);
1564
1565         if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET |
1566                                      SDMMC_CTRL_FIFO_RESET))
1567                 return;
1568
1569         /*
1570          * According to eMMC spec, card reset procedure:
1571          * tRstW >= 1us:   RST_n pulse width
1572          * tRSCA >= 200us: RST_n to Command time
1573          * tRSTH >= 1us:   RST_n high period
1574          */
1575         reset = mci_readl(host, RST_N);
1576         reset &= ~(SDMMC_RST_HWACTIVE << slot->id);
1577         mci_writel(host, RST_N, reset);
1578         usleep_range(1, 2);
1579         reset |= SDMMC_RST_HWACTIVE << slot->id;
1580         mci_writel(host, RST_N, reset);
1581         usleep_range(200, 300);
1582 }
1583
1584 static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card)
1585 {
1586         struct dw_mci_slot *slot = mmc_priv(mmc);
1587         struct dw_mci *host = slot->host;
1588
1589         /*
1590          * Low power mode will stop the card clock when idle.  According to the
1591          * description of the CLKENA register we should disable low power mode
1592          * for SDIO cards if we need SDIO interrupts to work.
1593          */
1594         if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1595                 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
1596                 u32 clk_en_a_old;
1597                 u32 clk_en_a;
1598
1599                 clk_en_a_old = mci_readl(host, CLKENA);
1600
1601                 if (card->type == MMC_TYPE_SDIO ||
1602                     card->type == MMC_TYPE_SD_COMBO) {
1603                         set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1604                         clk_en_a = clk_en_a_old & ~clken_low_pwr;
1605                 } else {
1606                         clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1607                         clk_en_a = clk_en_a_old | clken_low_pwr;
1608                 }
1609
1610                 if (clk_en_a != clk_en_a_old) {
1611                         mci_writel(host, CLKENA, clk_en_a);
1612                         mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
1613                                      SDMMC_CMD_PRV_DAT_WAIT, 0);
1614                 }
1615         }
1616 }
1617
1618 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
1619 {
1620         struct dw_mci_slot *slot = mmc_priv(mmc);
1621         struct dw_mci *host = slot->host;
1622         unsigned long irqflags;
1623         u32 int_mask;
1624
1625         spin_lock_irqsave(&host->irq_lock, irqflags);
1626
1627         /* Enable/disable Slot Specific SDIO interrupt */
1628         int_mask = mci_readl(host, INTMASK);
1629         if (enb)
1630                 int_mask |= SDMMC_INT_SDIO(slot->sdio_id);
1631         else
1632                 int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id);
1633         mci_writel(host, INTMASK, int_mask);
1634
1635         spin_unlock_irqrestore(&host->irq_lock, irqflags);
1636 }
1637
1638 static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1639 {
1640         struct dw_mci_slot *slot = mmc_priv(mmc);
1641         struct dw_mci *host = slot->host;
1642         const struct dw_mci_drv_data *drv_data = host->drv_data;
1643         int err = -EINVAL;
1644
1645         if (drv_data && drv_data->execute_tuning)
1646                 err = drv_data->execute_tuning(slot, opcode);
1647         return err;
1648 }
1649
1650 static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc,
1651                                        struct mmc_ios *ios)
1652 {
1653         struct dw_mci_slot *slot = mmc_priv(mmc);
1654         struct dw_mci *host = slot->host;
1655         const struct dw_mci_drv_data *drv_data = host->drv_data;
1656
1657         if (drv_data && drv_data->prepare_hs400_tuning)
1658                 return drv_data->prepare_hs400_tuning(host, ios);
1659
1660         return 0;
1661 }
1662
1663 static const struct mmc_host_ops dw_mci_ops = {
1664         .request                = dw_mci_request,
1665         .pre_req                = dw_mci_pre_req,
1666         .post_req               = dw_mci_post_req,
1667         .set_ios                = dw_mci_set_ios,
1668         .get_ro                 = dw_mci_get_ro,
1669         .get_cd                 = dw_mci_get_cd,
1670         .hw_reset               = dw_mci_hw_reset,
1671         .enable_sdio_irq        = dw_mci_enable_sdio_irq,
1672         .execute_tuning         = dw_mci_execute_tuning,
1673         .card_busy              = dw_mci_card_busy,
1674         .start_signal_voltage_switch = dw_mci_switch_voltage,
1675         .init_card              = dw_mci_init_card,
1676         .prepare_hs400_tuning   = dw_mci_prepare_hs400_tuning,
1677 };
1678
1679 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
1680         __releases(&host->lock)
1681         __acquires(&host->lock)
1682 {
1683         struct dw_mci_slot *slot;
1684         struct mmc_host *prev_mmc = host->cur_slot->mmc;
1685
1686         WARN_ON(host->cmd || host->data);
1687
1688         host->cur_slot->mrq = NULL;
1689         host->mrq = NULL;
1690         if (!list_empty(&host->queue)) {
1691                 slot = list_entry(host->queue.next,
1692                                   struct dw_mci_slot, queue_node);
1693                 list_del(&slot->queue_node);
1694                 dev_vdbg(host->dev, "list not empty: %s is next\n",
1695                          mmc_hostname(slot->mmc));
1696                 host->state = STATE_SENDING_CMD;
1697                 dw_mci_start_request(host, slot);
1698         } else {
1699                 dev_vdbg(host->dev, "list empty\n");
1700
1701                 if (host->state == STATE_SENDING_CMD11)
1702                         host->state = STATE_WAITING_CMD11_DONE;
1703                 else
1704                         host->state = STATE_IDLE;
1705         }
1706
1707         spin_unlock(&host->lock);
1708         mmc_request_done(prev_mmc, mrq);
1709         spin_lock(&host->lock);
1710 }
1711
1712 static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
1713 {
1714         u32 status = host->cmd_status;
1715
1716         host->cmd_status = 0;
1717
1718         /* Read the response from the card (up to 16 bytes) */
1719         if (cmd->flags & MMC_RSP_PRESENT) {
1720                 if (cmd->flags & MMC_RSP_136) {
1721                         cmd->resp[3] = mci_readl(host, RESP0);
1722                         cmd->resp[2] = mci_readl(host, RESP1);
1723                         cmd->resp[1] = mci_readl(host, RESP2);
1724                         cmd->resp[0] = mci_readl(host, RESP3);
1725                 } else {
1726                         cmd->resp[0] = mci_readl(host, RESP0);
1727                         cmd->resp[1] = 0;
1728                         cmd->resp[2] = 0;
1729                         cmd->resp[3] = 0;
1730                 }
1731         }
1732
1733         if (status & SDMMC_INT_RTO)
1734                 cmd->error = -ETIMEDOUT;
1735         else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
1736                 cmd->error = -EILSEQ;
1737         else if (status & SDMMC_INT_RESP_ERR)
1738                 cmd->error = -EIO;
1739         else
1740                 cmd->error = 0;
1741
1742         return cmd->error;
1743 }
1744
1745 static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data)
1746 {
1747         u32 status = host->data_status;
1748
1749         if (status & DW_MCI_DATA_ERROR_FLAGS) {
1750                 if (status & SDMMC_INT_DRTO) {
1751                         data->error = -ETIMEDOUT;
1752                 } else if (status & SDMMC_INT_DCRC) {
1753                         data->error = -EILSEQ;
1754                 } else if (status & SDMMC_INT_EBE) {
1755                         if (host->dir_status ==
1756                                 DW_MCI_SEND_STATUS) {
1757                                 /*
1758                                  * No data CRC status was returned.
1759                                  * The number of bytes transferred
1760                                  * will be exaggerated in PIO mode.
1761                                  */
1762                                 data->bytes_xfered = 0;
1763                                 data->error = -ETIMEDOUT;
1764                         } else if (host->dir_status ==
1765                                         DW_MCI_RECV_STATUS) {
1766                                 data->error = -EILSEQ;
1767                         }
1768                 } else {
1769                         /* SDMMC_INT_SBE is included */
1770                         data->error = -EILSEQ;
1771                 }
1772
1773                 dev_dbg(host->dev, "data error, status 0x%08x\n", status);
1774
1775                 /*
1776                  * After an error, there may be data lingering
1777                  * in the FIFO
1778                  */
1779                 dw_mci_reset(host);
1780         } else {
1781                 data->bytes_xfered = data->blocks * data->blksz;
1782                 data->error = 0;
1783         }
1784
1785         return data->error;
1786 }
1787
1788 static void dw_mci_set_drto(struct dw_mci *host)
1789 {
1790         unsigned int drto_clks;
1791         unsigned int drto_ms;
1792
1793         drto_clks = mci_readl(host, TMOUT) >> 8;
1794         drto_ms = DIV_ROUND_UP(drto_clks, host->bus_hz / 1000);
1795
1796         /* add a bit spare time */
1797         drto_ms += 10;
1798
1799         mod_timer(&host->dto_timer, jiffies + msecs_to_jiffies(drto_ms));
1800 }
1801
1802 static void dw_mci_tasklet_func(unsigned long priv)
1803 {
1804         struct dw_mci *host = (struct dw_mci *)priv;
1805         struct mmc_data *data;
1806         struct mmc_command *cmd;
1807         struct mmc_request *mrq;
1808         enum dw_mci_state state;
1809         enum dw_mci_state prev_state;
1810         unsigned int err;
1811
1812         spin_lock(&host->lock);
1813
1814         state = host->state;
1815         data = host->data;
1816         mrq = host->mrq;
1817
1818         do {
1819                 prev_state = state;
1820
1821                 switch (state) {
1822                 case STATE_IDLE:
1823                 case STATE_WAITING_CMD11_DONE:
1824                         break;
1825
1826                 case STATE_SENDING_CMD11:
1827                 case STATE_SENDING_CMD:
1828                         if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1829                                                 &host->pending_events))
1830                                 break;
1831
1832                         cmd = host->cmd;
1833                         host->cmd = NULL;
1834                         set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
1835                         err = dw_mci_command_complete(host, cmd);
1836                         if (cmd == mrq->sbc && !err) {
1837                                 prev_state = state = STATE_SENDING_CMD;
1838                                 __dw_mci_start_request(host, host->cur_slot,
1839                                                        mrq->cmd);
1840                                 goto unlock;
1841                         }
1842
1843                         if (cmd->data && err) {
1844                                 /*
1845                                  * During UHS tuning sequence, sending the stop
1846                                  * command after the response CRC error would
1847                                  * throw the system into a confused state
1848                                  * causing all future tuning phases to report
1849                                  * failure.
1850                                  *
1851                                  * In such case controller will move into a data
1852                                  * transfer state after a response error or
1853                                  * response CRC error. Let's let that finish
1854                                  * before trying to send a stop, so we'll go to
1855                                  * STATE_SENDING_DATA.
1856                                  *
1857                                  * Although letting the data transfer take place
1858                                  * will waste a bit of time (we already know
1859                                  * the command was bad), it can't cause any
1860                                  * errors since it's possible it would have
1861                                  * taken place anyway if this tasklet got
1862                                  * delayed. Allowing the transfer to take place
1863                                  * avoids races and keeps things simple.
1864                                  */
1865                                 if (err != -ETIMEDOUT) {
1866                                         state = STATE_SENDING_DATA;
1867                                         continue;
1868                                 }
1869
1870                                 send_stop_abort(host, data);
1871                                 dw_mci_stop_dma(host);
1872                                 state = STATE_SENDING_STOP;
1873                                 break;
1874                         }
1875
1876                         if (!cmd->data || err) {
1877                                 dw_mci_request_end(host, mrq);
1878                                 goto unlock;
1879                         }
1880
1881                         prev_state = state = STATE_SENDING_DATA;
1882                         /* fall through */
1883
1884                 case STATE_SENDING_DATA:
1885                         /*
1886                          * We could get a data error and never a transfer
1887                          * complete so we'd better check for it here.
1888                          *
1889                          * Note that we don't really care if we also got a
1890                          * transfer complete; stopping the DMA and sending an
1891                          * abort won't hurt.
1892                          */
1893                         if (test_and_clear_bit(EVENT_DATA_ERROR,
1894                                                &host->pending_events)) {
1895                                 if (!(host->data_status & (SDMMC_INT_DRTO |
1896                                                            SDMMC_INT_EBE)))
1897                                         send_stop_abort(host, data);
1898                                 dw_mci_stop_dma(host);
1899                                 state = STATE_DATA_ERROR;
1900                                 break;
1901                         }
1902
1903                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1904                                                 &host->pending_events)) {
1905                                 /*
1906                                  * If all data-related interrupts don't come
1907                                  * within the given time in reading data state.
1908                                  */
1909                                 if (host->dir_status == DW_MCI_RECV_STATUS)
1910                                         dw_mci_set_drto(host);
1911                                 break;
1912                         }
1913
1914                         set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
1915
1916                         /*
1917                          * Handle an EVENT_DATA_ERROR that might have shown up
1918                          * before the transfer completed.  This might not have
1919                          * been caught by the check above because the interrupt
1920                          * could have gone off between the previous check and
1921                          * the check for transfer complete.
1922                          *
1923                          * Technically this ought not be needed assuming we
1924                          * get a DATA_COMPLETE eventually (we'll notice the
1925                          * error and end the request), but it shouldn't hurt.
1926                          *
1927                          * This has the advantage of sending the stop command.
1928                          */
1929                         if (test_and_clear_bit(EVENT_DATA_ERROR,
1930                                                &host->pending_events)) {
1931                                 if (!(host->data_status & (SDMMC_INT_DRTO |
1932                                                            SDMMC_INT_EBE)))
1933                                         send_stop_abort(host, data);
1934                                 dw_mci_stop_dma(host);
1935                                 state = STATE_DATA_ERROR;
1936                                 break;
1937                         }
1938                         prev_state = state = STATE_DATA_BUSY;
1939
1940                         /* fall through */
1941
1942                 case STATE_DATA_BUSY:
1943                         if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
1944                                                 &host->pending_events)) {
1945                                 /*
1946                                  * If data error interrupt comes but data over
1947                                  * interrupt doesn't come within the given time.
1948                                  * in reading data state.
1949                                  */
1950                                 if (host->dir_status == DW_MCI_RECV_STATUS)
1951                                         dw_mci_set_drto(host);
1952                                 break;
1953                         }
1954
1955                         host->data = NULL;
1956                         set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
1957                         err = dw_mci_data_complete(host, data);
1958
1959                         if (!err) {
1960                                 if (!data->stop || mrq->sbc) {
1961                                         if (mrq->sbc && data->stop)
1962                                                 data->stop->error = 0;
1963                                         dw_mci_request_end(host, mrq);
1964                                         goto unlock;
1965                                 }
1966
1967                                 /* stop command for open-ended transfer*/
1968                                 if (data->stop)
1969                                         send_stop_abort(host, data);
1970                         } else {
1971                                 /*
1972                                  * If we don't have a command complete now we'll
1973                                  * never get one since we just reset everything;
1974                                  * better end the request.
1975                                  *
1976                                  * If we do have a command complete we'll fall
1977                                  * through to the SENDING_STOP command and
1978                                  * everything will be peachy keen.
1979                                  */
1980                                 if (!test_bit(EVENT_CMD_COMPLETE,
1981                                               &host->pending_events)) {
1982                                         host->cmd = NULL;
1983                                         dw_mci_request_end(host, mrq);
1984                                         goto unlock;
1985                                 }
1986                         }
1987
1988                         /*
1989                          * If err has non-zero,
1990                          * stop-abort command has been already issued.
1991                          */
1992                         prev_state = state = STATE_SENDING_STOP;
1993
1994                         /* fall through */
1995
1996                 case STATE_SENDING_STOP:
1997                         if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1998                                                 &host->pending_events))
1999                                 break;
2000
2001                         /* CMD error in data command */
2002                         if (mrq->cmd->error && mrq->data)
2003                                 dw_mci_reset(host);
2004
2005                         host->cmd = NULL;
2006                         host->data = NULL;
2007
2008                         if (!mrq->sbc && mrq->stop)
2009                                 dw_mci_command_complete(host, mrq->stop);
2010                         else
2011                                 host->cmd_status = 0;
2012
2013                         dw_mci_request_end(host, mrq);
2014                         goto unlock;
2015
2016                 case STATE_DATA_ERROR:
2017                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
2018                                                 &host->pending_events))
2019                                 break;
2020
2021                         state = STATE_DATA_BUSY;
2022                         break;
2023                 }
2024         } while (state != prev_state);
2025
2026         host->state = state;
2027 unlock:
2028         spin_unlock(&host->lock);
2029
2030 }
2031
2032 /* push final bytes to part_buf, only use during push */
2033 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
2034 {
2035         memcpy((void *)&host->part_buf, buf, cnt);
2036         host->part_buf_count = cnt;
2037 }
2038
2039 /* append bytes to part_buf, only use during push */
2040 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
2041 {
2042         cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
2043         memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
2044         host->part_buf_count += cnt;
2045         return cnt;
2046 }
2047
2048 /* pull first bytes from part_buf, only use during pull */
2049 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
2050 {
2051         cnt = min_t(int, cnt, host->part_buf_count);
2052         if (cnt) {
2053                 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
2054                        cnt);
2055                 host->part_buf_count -= cnt;
2056                 host->part_buf_start += cnt;
2057         }
2058         return cnt;
2059 }
2060
2061 /* pull final bytes from the part_buf, assuming it's just been filled */
2062 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
2063 {
2064         memcpy(buf, &host->part_buf, cnt);
2065         host->part_buf_start = cnt;
2066         host->part_buf_count = (1 << host->data_shift) - cnt;
2067 }
2068
2069 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
2070 {
2071         struct mmc_data *data = host->data;
2072         int init_cnt = cnt;
2073
2074         /* try and push anything in the part_buf */
2075         if (unlikely(host->part_buf_count)) {
2076                 int len = dw_mci_push_part_bytes(host, buf, cnt);
2077
2078                 buf += len;
2079                 cnt -= len;
2080                 if (host->part_buf_count == 2) {
2081                         mci_fifo_writew(host->fifo_reg, host->part_buf16);
2082                         host->part_buf_count = 0;
2083                 }
2084         }
2085 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2086         if (unlikely((unsigned long)buf & 0x1)) {
2087                 while (cnt >= 2) {
2088                         u16 aligned_buf[64];
2089                         int len = min(cnt & -2, (int)sizeof(aligned_buf));
2090                         int items = len >> 1;
2091                         int i;
2092                         /* memcpy from input buffer into aligned buffer */
2093                         memcpy(aligned_buf, buf, len);
2094                         buf += len;
2095                         cnt -= len;
2096                         /* push data from aligned buffer into fifo */
2097                         for (i = 0; i < items; ++i)
2098                                 mci_fifo_writew(host->fifo_reg, aligned_buf[i]);
2099                 }
2100         } else
2101 #endif
2102         {
2103                 u16 *pdata = buf;
2104
2105                 for (; cnt >= 2; cnt -= 2)
2106                         mci_fifo_writew(host->fifo_reg, *pdata++);
2107                 buf = pdata;
2108         }
2109         /* put anything remaining in the part_buf */
2110         if (cnt) {
2111                 dw_mci_set_part_bytes(host, buf, cnt);
2112                  /* Push data if we have reached the expected data length */
2113                 if ((data->bytes_xfered + init_cnt) ==
2114                     (data->blksz * data->blocks))
2115                         mci_fifo_writew(host->fifo_reg, host->part_buf16);
2116         }
2117 }
2118
2119 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
2120 {
2121 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2122         if (unlikely((unsigned long)buf & 0x1)) {
2123                 while (cnt >= 2) {
2124                         /* pull data from fifo into aligned buffer */
2125                         u16 aligned_buf[64];
2126                         int len = min(cnt & -2, (int)sizeof(aligned_buf));
2127                         int items = len >> 1;
2128                         int i;
2129
2130                         for (i = 0; i < items; ++i)
2131                                 aligned_buf[i] = mci_fifo_readw(host->fifo_reg);
2132                         /* memcpy from aligned buffer into output buffer */
2133                         memcpy(buf, aligned_buf, len);
2134                         buf += len;
2135                         cnt -= len;
2136                 }
2137         } else
2138 #endif
2139         {
2140                 u16 *pdata = buf;
2141
2142                 for (; cnt >= 2; cnt -= 2)
2143                         *pdata++ = mci_fifo_readw(host->fifo_reg);
2144                 buf = pdata;
2145         }
2146         if (cnt) {
2147                 host->part_buf16 = mci_fifo_readw(host->fifo_reg);
2148                 dw_mci_pull_final_bytes(host, buf, cnt);
2149         }
2150 }
2151
2152 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
2153 {
2154         struct mmc_data *data = host->data;
2155         int init_cnt = cnt;
2156
2157         /* try and push anything in the part_buf */
2158         if (unlikely(host->part_buf_count)) {
2159                 int len = dw_mci_push_part_bytes(host, buf, cnt);
2160
2161                 buf += len;
2162                 cnt -= len;
2163                 if (host->part_buf_count == 4) {
2164                         mci_fifo_writel(host->fifo_reg, host->part_buf32);
2165                         host->part_buf_count = 0;
2166                 }
2167         }
2168 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2169         if (unlikely((unsigned long)buf & 0x3)) {
2170                 while (cnt >= 4) {
2171                         u32 aligned_buf[32];
2172                         int len = min(cnt & -4, (int)sizeof(aligned_buf));
2173                         int items = len >> 2;
2174                         int i;
2175                         /* memcpy from input buffer into aligned buffer */
2176                         memcpy(aligned_buf, buf, len);
2177                         buf += len;
2178                         cnt -= len;
2179                         /* push data from aligned buffer into fifo */
2180                         for (i = 0; i < items; ++i)
2181                                 mci_fifo_writel(host->fifo_reg, aligned_buf[i]);
2182                 }
2183         } else
2184 #endif
2185         {
2186                 u32 *pdata = buf;
2187
2188                 for (; cnt >= 4; cnt -= 4)
2189                         mci_fifo_writel(host->fifo_reg, *pdata++);
2190                 buf = pdata;
2191         }
2192         /* put anything remaining in the part_buf */
2193         if (cnt) {
2194                 dw_mci_set_part_bytes(host, buf, cnt);
2195                  /* Push data if we have reached the expected data length */
2196                 if ((data->bytes_xfered + init_cnt) ==
2197                     (data->blksz * data->blocks))
2198                         mci_fifo_writel(host->fifo_reg, host->part_buf32);
2199         }
2200 }
2201
2202 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
2203 {
2204 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2205         if (unlikely((unsigned long)buf & 0x3)) {
2206                 while (cnt >= 4) {
2207                         /* pull data from fifo into aligned buffer */
2208                         u32 aligned_buf[32];
2209                         int len = min(cnt & -4, (int)sizeof(aligned_buf));
2210                         int items = len >> 2;
2211                         int i;
2212
2213                         for (i = 0; i < items; ++i)
2214                                 aligned_buf[i] = mci_fifo_readl(host->fifo_reg);
2215                         /* memcpy from aligned buffer into output buffer */
2216                         memcpy(buf, aligned_buf, len);
2217                         buf += len;
2218                         cnt -= len;
2219                 }
2220         } else
2221 #endif
2222         {
2223                 u32 *pdata = buf;
2224
2225                 for (; cnt >= 4; cnt -= 4)
2226                         *pdata++ = mci_fifo_readl(host->fifo_reg);
2227                 buf = pdata;
2228         }
2229         if (cnt) {
2230                 host->part_buf32 = mci_fifo_readl(host->fifo_reg);
2231                 dw_mci_pull_final_bytes(host, buf, cnt);
2232         }
2233 }
2234
2235 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
2236 {
2237         struct mmc_data *data = host->data;
2238         int init_cnt = cnt;
2239
2240         /* try and push anything in the part_buf */
2241         if (unlikely(host->part_buf_count)) {
2242                 int len = dw_mci_push_part_bytes(host, buf, cnt);
2243
2244                 buf += len;
2245                 cnt -= len;
2246
2247                 if (host->part_buf_count == 8) {
2248                         mci_fifo_writeq(host->fifo_reg, host->part_buf);
2249                         host->part_buf_count = 0;
2250                 }
2251         }
2252 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2253         if (unlikely((unsigned long)buf & 0x7)) {
2254                 while (cnt >= 8) {
2255                         u64 aligned_buf[16];
2256                         int len = min(cnt & -8, (int)sizeof(aligned_buf));
2257                         int items = len >> 3;
2258                         int i;
2259                         /* memcpy from input buffer into aligned buffer */
2260                         memcpy(aligned_buf, buf, len);
2261                         buf += len;
2262                         cnt -= len;
2263                         /* push data from aligned buffer into fifo */
2264                         for (i = 0; i < items; ++i)
2265                                 mci_fifo_writeq(host->fifo_reg, aligned_buf[i]);
2266                 }
2267         } else
2268 #endif
2269         {
2270                 u64 *pdata = buf;
2271
2272                 for (; cnt >= 8; cnt -= 8)
2273                         mci_fifo_writeq(host->fifo_reg, *pdata++);
2274                 buf = pdata;
2275         }
2276         /* put anything remaining in the part_buf */
2277         if (cnt) {
2278                 dw_mci_set_part_bytes(host, buf, cnt);
2279                 /* Push data if we have reached the expected data length */
2280                 if ((data->bytes_xfered + init_cnt) ==
2281                     (data->blksz * data->blocks))
2282                         mci_fifo_writeq(host->fifo_reg, host->part_buf);
2283         }
2284 }
2285
2286 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
2287 {
2288 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2289         if (unlikely((unsigned long)buf & 0x7)) {
2290                 while (cnt >= 8) {
2291                         /* pull data from fifo into aligned buffer */
2292                         u64 aligned_buf[16];
2293                         int len = min(cnt & -8, (int)sizeof(aligned_buf));
2294                         int items = len >> 3;
2295                         int i;
2296
2297                         for (i = 0; i < items; ++i)
2298                                 aligned_buf[i] = mci_fifo_readq(host->fifo_reg);
2299
2300                         /* memcpy from aligned buffer into output buffer */
2301                         memcpy(buf, aligned_buf, len);
2302                         buf += len;
2303                         cnt -= len;
2304                 }
2305         } else
2306 #endif
2307         {
2308                 u64 *pdata = buf;
2309
2310                 for (; cnt >= 8; cnt -= 8)
2311                         *pdata++ = mci_fifo_readq(host->fifo_reg);
2312                 buf = pdata;
2313         }
2314         if (cnt) {
2315                 host->part_buf = mci_fifo_readq(host->fifo_reg);
2316                 dw_mci_pull_final_bytes(host, buf, cnt);
2317         }
2318 }
2319
2320 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
2321 {
2322         int len;
2323
2324         /* get remaining partial bytes */
2325         len = dw_mci_pull_part_bytes(host, buf, cnt);
2326         if (unlikely(len == cnt))
2327                 return;
2328         buf += len;
2329         cnt -= len;
2330
2331         /* get the rest of the data */
2332         host->pull_data(host, buf, cnt);
2333 }
2334
2335 static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
2336 {
2337         struct sg_mapping_iter *sg_miter = &host->sg_miter;
2338         void *buf;
2339         unsigned int offset;
2340         struct mmc_data *data = host->data;
2341         int shift = host->data_shift;
2342         u32 status;
2343         unsigned int len;
2344         unsigned int remain, fcnt;
2345
2346         do {
2347                 if (!sg_miter_next(sg_miter))
2348                         goto done;
2349
2350                 host->sg = sg_miter->piter.sg;
2351                 buf = sg_miter->addr;
2352                 remain = sg_miter->length;
2353                 offset = 0;
2354
2355                 do {
2356                         fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
2357                                         << shift) + host->part_buf_count;
2358                         len = min(remain, fcnt);
2359                         if (!len)
2360                                 break;
2361                         dw_mci_pull_data(host, (void *)(buf + offset), len);
2362                         data->bytes_xfered += len;
2363                         offset += len;
2364                         remain -= len;
2365                 } while (remain);
2366
2367                 sg_miter->consumed = offset;
2368                 status = mci_readl(host, MINTSTS);
2369                 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2370         /* if the RXDR is ready read again */
2371         } while ((status & SDMMC_INT_RXDR) ||
2372                  (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
2373
2374         if (!remain) {
2375                 if (!sg_miter_next(sg_miter))
2376                         goto done;
2377                 sg_miter->consumed = 0;
2378         }
2379         sg_miter_stop(sg_miter);
2380         return;
2381
2382 done:
2383         sg_miter_stop(sg_miter);
2384         host->sg = NULL;
2385         smp_wmb(); /* drain writebuffer */
2386         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2387 }
2388
2389 static void dw_mci_write_data_pio(struct dw_mci *host)
2390 {
2391         struct sg_mapping_iter *sg_miter = &host->sg_miter;
2392         void *buf;
2393         unsigned int offset;
2394         struct mmc_data *data = host->data;
2395         int shift = host->data_shift;
2396         u32 status;
2397         unsigned int len;
2398         unsigned int fifo_depth = host->fifo_depth;
2399         unsigned int remain, fcnt;
2400
2401         do {
2402                 if (!sg_miter_next(sg_miter))
2403                         goto done;
2404
2405                 host->sg = sg_miter->piter.sg;
2406                 buf = sg_miter->addr;
2407                 remain = sg_miter->length;
2408                 offset = 0;
2409
2410                 do {
2411                         fcnt = ((fifo_depth -
2412                                  SDMMC_GET_FCNT(mci_readl(host, STATUS)))
2413                                         << shift) - host->part_buf_count;
2414                         len = min(remain, fcnt);
2415                         if (!len)
2416                                 break;
2417                         host->push_data(host, (void *)(buf + offset), len);
2418                         data->bytes_xfered += len;
2419                         offset += len;
2420                         remain -= len;
2421                 } while (remain);
2422
2423                 sg_miter->consumed = offset;
2424                 status = mci_readl(host, MINTSTS);
2425                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2426         } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
2427
2428         if (!remain) {
2429                 if (!sg_miter_next(sg_miter))
2430                         goto done;
2431                 sg_miter->consumed = 0;
2432         }
2433         sg_miter_stop(sg_miter);
2434         return;
2435
2436 done:
2437         sg_miter_stop(sg_miter);
2438         host->sg = NULL;
2439         smp_wmb(); /* drain writebuffer */
2440         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2441 }
2442
2443 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
2444 {
2445         if (!host->cmd_status)
2446                 host->cmd_status = status;
2447
2448         smp_wmb(); /* drain writebuffer */
2449
2450         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2451         tasklet_schedule(&host->tasklet);
2452 }
2453
2454 static void dw_mci_handle_cd(struct dw_mci *host)
2455 {
2456         int i;
2457
2458         for (i = 0; i < host->num_slots; i++) {
2459                 struct dw_mci_slot *slot = host->slot[i];
2460
2461                 if (!slot)
2462                         continue;
2463
2464                 if (slot->mmc->ops->card_event)
2465                         slot->mmc->ops->card_event(slot->mmc);
2466                 mmc_detect_change(slot->mmc,
2467                         msecs_to_jiffies(host->pdata->detect_delay_ms));
2468         }
2469 }
2470
2471 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
2472 {
2473         struct dw_mci *host = dev_id;
2474         u32 pending;
2475         int i;
2476
2477         pending = mci_readl(host, MINTSTS); /* read-only mask reg */
2478
2479         if (pending) {
2480                 /* Check volt switch first, since it can look like an error */
2481                 if ((host->state == STATE_SENDING_CMD11) &&
2482                     (pending & SDMMC_INT_VOLT_SWITCH)) {
2483                         unsigned long irqflags;
2484
2485                         mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH);
2486                         pending &= ~SDMMC_INT_VOLT_SWITCH;
2487
2488                         /*
2489                          * Hold the lock; we know cmd11_timer can't be kicked
2490                          * off after the lock is released, so safe to delete.
2491                          */
2492                         spin_lock_irqsave(&host->irq_lock, irqflags);
2493                         dw_mci_cmd_interrupt(host, pending);
2494                         spin_unlock_irqrestore(&host->irq_lock, irqflags);
2495
2496                         del_timer(&host->cmd11_timer);
2497                 }
2498
2499                 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
2500                         mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
2501                         host->cmd_status = pending;
2502                         smp_wmb(); /* drain writebuffer */
2503                         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2504                 }
2505
2506                 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
2507                         /* if there is an error report DATA_ERROR */
2508                         mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
2509                         host->data_status = pending;
2510                         smp_wmb(); /* drain writebuffer */
2511                         set_bit(EVENT_DATA_ERROR, &host->pending_events);
2512                         tasklet_schedule(&host->tasklet);
2513                 }
2514
2515                 if (pending & SDMMC_INT_DATA_OVER) {
2516                         del_timer(&host->dto_timer);
2517
2518                         mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
2519                         if (!host->data_status)
2520                                 host->data_status = pending;
2521                         smp_wmb(); /* drain writebuffer */
2522                         if (host->dir_status == DW_MCI_RECV_STATUS) {
2523                                 if (host->sg != NULL)
2524                                         dw_mci_read_data_pio(host, true);
2525                         }
2526                         set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2527                         tasklet_schedule(&host->tasklet);
2528                 }
2529
2530                 if (pending & SDMMC_INT_RXDR) {
2531                         mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2532                         if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
2533                                 dw_mci_read_data_pio(host, false);
2534                 }
2535
2536                 if (pending & SDMMC_INT_TXDR) {
2537                         mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2538                         if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
2539                                 dw_mci_write_data_pio(host);
2540                 }
2541
2542                 if (pending & SDMMC_INT_CMD_DONE) {
2543                         mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
2544                         dw_mci_cmd_interrupt(host, pending);
2545                 }
2546
2547                 if (pending & SDMMC_INT_CD) {
2548                         mci_writel(host, RINTSTS, SDMMC_INT_CD);
2549                         dw_mci_handle_cd(host);
2550                 }
2551
2552                 /* Handle SDIO Interrupts */
2553                 for (i = 0; i < host->num_slots; i++) {
2554                         struct dw_mci_slot *slot = host->slot[i];
2555
2556                         if (!slot)
2557                                 continue;
2558
2559                         if (pending & SDMMC_INT_SDIO(slot->sdio_id)) {
2560                                 mci_writel(host, RINTSTS,
2561                                            SDMMC_INT_SDIO(slot->sdio_id));
2562                                 mmc_signal_sdio_irq(slot->mmc);
2563                         }
2564                 }
2565
2566         }
2567
2568         if (host->use_dma != TRANS_MODE_IDMAC)
2569                 return IRQ_HANDLED;
2570
2571         /* Handle IDMA interrupts */
2572         if (host->dma_64bit_address == 1) {
2573                 pending = mci_readl(host, IDSTS64);
2574                 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2575                         mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI |
2576                                                         SDMMC_IDMAC_INT_RI);
2577                         mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI);
2578                         if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
2579                                 host->dma_ops->complete((void *)host);
2580                 }
2581         } else {
2582                 pending = mci_readl(host, IDSTS);
2583                 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2584                         mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI |
2585                                                         SDMMC_IDMAC_INT_RI);
2586                         mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
2587                         if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
2588                                 host->dma_ops->complete((void *)host);
2589                 }
2590         }
2591
2592         return IRQ_HANDLED;
2593 }
2594
2595 static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
2596 {
2597         struct mmc_host *mmc;
2598         struct dw_mci_slot *slot;
2599         const struct dw_mci_drv_data *drv_data = host->drv_data;
2600         int ctrl_id, ret;
2601         u32 freq[2];
2602
2603         mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
2604         if (!mmc)
2605                 return -ENOMEM;
2606
2607         slot = mmc_priv(mmc);
2608         slot->id = id;
2609         slot->sdio_id = host->sdio_id0 + id;
2610         slot->mmc = mmc;
2611         slot->host = host;
2612         host->slot[id] = slot;
2613
2614         mmc->ops = &dw_mci_ops;
2615         if (device_property_read_u32_array(host->dev, "clock-freq-min-max",
2616                                            freq, 2)) {
2617                 mmc->f_min = DW_MCI_FREQ_MIN;
2618                 mmc->f_max = DW_MCI_FREQ_MAX;
2619         } else {
2620                 mmc->f_min = freq[0];
2621                 mmc->f_max = freq[1];
2622         }
2623
2624         /*if there are external regulators, get them*/
2625         ret = mmc_regulator_get_supply(mmc);
2626         if (ret == -EPROBE_DEFER)
2627                 goto err_host_allocated;
2628
2629         if (!mmc->ocr_avail)
2630                 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
2631
2632         if (host->pdata->caps)
2633                 mmc->caps = host->pdata->caps;
2634
2635         /*
2636          * Support MMC_CAP_ERASE by default.
2637          * It needs to use trim/discard/erase commands.
2638          */
2639         mmc->caps |= MMC_CAP_ERASE;
2640
2641         if (host->pdata->pm_caps)
2642                 mmc->pm_caps = host->pdata->pm_caps;
2643
2644         if (host->dev->of_node) {
2645                 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
2646                 if (ctrl_id < 0)
2647                         ctrl_id = 0;
2648         } else {
2649                 ctrl_id = to_platform_device(host->dev)->id;
2650         }
2651         if (drv_data && drv_data->caps)
2652                 mmc->caps |= drv_data->caps[ctrl_id];
2653
2654         if (host->pdata->caps2)
2655                 mmc->caps2 = host->pdata->caps2;
2656
2657         ret = mmc_of_parse(mmc);
2658         if (ret)
2659                 goto err_host_allocated;
2660
2661         /* Useful defaults if platform data is unset. */
2662         if (host->use_dma == TRANS_MODE_IDMAC) {
2663                 mmc->max_segs = host->ring_size;
2664                 mmc->max_blk_size = 65535;
2665                 mmc->max_seg_size = 0x1000;
2666                 mmc->max_req_size = mmc->max_seg_size * host->ring_size;
2667                 mmc->max_blk_count = mmc->max_req_size / 512;
2668         } else if (host->use_dma == TRANS_MODE_EDMAC) {
2669                 mmc->max_segs = 64;
2670                 mmc->max_blk_size = 65535;
2671                 mmc->max_blk_count = 65535;
2672                 mmc->max_req_size =
2673                                 mmc->max_blk_size * mmc->max_blk_count;
2674                 mmc->max_seg_size = mmc->max_req_size;
2675         } else {
2676                 /* TRANS_MODE_PIO */
2677                 mmc->max_segs = 64;
2678                 mmc->max_blk_size = 65535; /* BLKSIZ is 16 bits */
2679                 mmc->max_blk_count = 512;
2680                 mmc->max_req_size = mmc->max_blk_size *
2681                                     mmc->max_blk_count;
2682                 mmc->max_seg_size = mmc->max_req_size;
2683         }
2684
2685         dw_mci_get_cd(mmc);
2686
2687         ret = mmc_add_host(mmc);
2688         if (ret)
2689                 goto err_host_allocated;
2690
2691 #if defined(CONFIG_DEBUG_FS)
2692         dw_mci_init_debugfs(slot);
2693 #endif
2694
2695         return 0;
2696
2697 err_host_allocated:
2698         mmc_free_host(mmc);
2699         return ret;
2700 }
2701
2702 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
2703 {
2704         /* Debugfs stuff is cleaned up by mmc core */
2705         mmc_remove_host(slot->mmc);
2706         slot->host->slot[id] = NULL;
2707         mmc_free_host(slot->mmc);
2708 }
2709
2710 static void dw_mci_init_dma(struct dw_mci *host)
2711 {
2712         int addr_config;
2713         struct device *dev = host->dev;
2714
2715         /*
2716         * Check tansfer mode from HCON[17:16]
2717         * Clear the ambiguous description of dw_mmc databook:
2718         * 2b'00: No DMA Interface -> Actually means using Internal DMA block
2719         * 2b'01: DesignWare DMA Interface -> Synopsys DW-DMA block
2720         * 2b'10: Generic DMA Interface -> non-Synopsys generic DMA block
2721         * 2b'11: Non DW DMA Interface -> pio only
2722         * Compared to DesignWare DMA Interface, Generic DMA Interface has a
2723         * simpler request/acknowledge handshake mechanism and both of them
2724         * are regarded as external dma master for dw_mmc.
2725         */
2726         host->use_dma = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON));
2727         if (host->use_dma == DMA_INTERFACE_IDMA) {
2728                 host->use_dma = TRANS_MODE_IDMAC;
2729         } else if (host->use_dma == DMA_INTERFACE_DWDMA ||
2730                    host->use_dma == DMA_INTERFACE_GDMA) {
2731                 host->use_dma = TRANS_MODE_EDMAC;
2732         } else {
2733                 goto no_dma;
2734         }
2735
2736         /* Determine which DMA interface to use */
2737         if (host->use_dma == TRANS_MODE_IDMAC) {
2738                 /*
2739                 * Check ADDR_CONFIG bit in HCON to find
2740                 * IDMAC address bus width
2741                 */
2742                 addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON));
2743
2744                 if (addr_config == 1) {
2745                         /* host supports IDMAC in 64-bit address mode */
2746                         host->dma_64bit_address = 1;
2747                         dev_info(host->dev,
2748                                  "IDMAC supports 64-bit address mode.\n");
2749                         if (!dma_set_mask(host->dev, DMA_BIT_MASK(64)))
2750                                 dma_set_coherent_mask(host->dev,
2751                                                       DMA_BIT_MASK(64));
2752                 } else {
2753                         /* host supports IDMAC in 32-bit address mode */
2754                         host->dma_64bit_address = 0;
2755                         dev_info(host->dev,
2756                                  "IDMAC supports 32-bit address mode.\n");
2757                 }
2758
2759                 /* Alloc memory for sg translation */
2760                 host->sg_cpu = dmam_alloc_coherent(host->dev,
2761                                                    DESC_RING_BUF_SZ,
2762                                                    &host->sg_dma, GFP_KERNEL);
2763                 if (!host->sg_cpu) {
2764                         dev_err(host->dev,
2765                                 "%s: could not alloc DMA memory\n",
2766                                 __func__);
2767                         goto no_dma;
2768                 }
2769
2770                 host->dma_ops = &dw_mci_idmac_ops;
2771                 dev_info(host->dev, "Using internal DMA controller.\n");
2772         } else {
2773                 /* TRANS_MODE_EDMAC: check dma bindings again */
2774                 if ((device_property_read_string_array(dev, "dma-names",
2775                                                        NULL, 0) < 0) ||
2776                     !device_property_present(dev, "dmas")) {
2777                         goto no_dma;
2778                 }
2779                 host->dma_ops = &dw_mci_edmac_ops;
2780                 dev_info(host->dev, "Using external DMA controller.\n");
2781         }
2782
2783         if (host->dma_ops->init && host->dma_ops->start &&
2784             host->dma_ops->stop && host->dma_ops->cleanup) {
2785                 if (host->dma_ops->init(host)) {
2786                         dev_err(host->dev, "%s: Unable to initialize DMA Controller.\n",
2787                                 __func__);
2788                         goto no_dma;
2789                 }
2790         } else {
2791                 dev_err(host->dev, "DMA initialization not found.\n");
2792                 goto no_dma;
2793         }
2794
2795         return;
2796
2797 no_dma:
2798         dev_info(host->dev, "Using PIO mode.\n");
2799         host->use_dma = TRANS_MODE_PIO;
2800 }
2801
2802 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
2803 {
2804         unsigned long timeout = jiffies + msecs_to_jiffies(500);
2805         u32 ctrl;
2806
2807         ctrl = mci_readl(host, CTRL);
2808         ctrl |= reset;
2809         mci_writel(host, CTRL, ctrl);
2810
2811         /* wait till resets clear */
2812         do {
2813                 ctrl = mci_readl(host, CTRL);
2814                 if (!(ctrl & reset))
2815                         return true;
2816         } while (time_before(jiffies, timeout));
2817
2818         dev_err(host->dev,
2819                 "Timeout resetting block (ctrl reset %#x)\n",
2820                 ctrl & reset);
2821
2822         return false;
2823 }
2824
2825 static bool dw_mci_reset(struct dw_mci *host)
2826 {
2827         u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET;
2828         bool ret = false;
2829
2830         /*
2831          * Reseting generates a block interrupt, hence setting
2832          * the scatter-gather pointer to NULL.
2833          */
2834         if (host->sg) {
2835                 sg_miter_stop(&host->sg_miter);
2836                 host->sg = NULL;
2837         }
2838
2839         if (host->use_dma)
2840                 flags |= SDMMC_CTRL_DMA_RESET;
2841
2842         if (dw_mci_ctrl_reset(host, flags)) {
2843                 /*
2844                  * In all cases we clear the RAWINTS register to clear any
2845                  * interrupts.
2846                  */
2847                 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2848
2849                 /* if using dma we wait for dma_req to clear */
2850                 if (host->use_dma) {
2851                         unsigned long timeout = jiffies + msecs_to_jiffies(500);
2852                         u32 status;
2853
2854                         do {
2855                                 status = mci_readl(host, STATUS);
2856                                 if (!(status & SDMMC_STATUS_DMA_REQ))
2857                                         break;
2858                                 cpu_relax();
2859                         } while (time_before(jiffies, timeout));
2860
2861                         if (status & SDMMC_STATUS_DMA_REQ) {
2862                                 dev_err(host->dev,
2863                                         "%s: Timeout waiting for dma_req to clear during reset\n",
2864                                         __func__);
2865                                 goto ciu_out;
2866                         }
2867
2868                         /* when using DMA next we reset the fifo again */
2869                         if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET))
2870                                 goto ciu_out;
2871                 }
2872         } else {
2873                 /* if the controller reset bit did clear, then set clock regs */
2874                 if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) {
2875                         dev_err(host->dev,
2876                                 "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n",
2877                                 __func__);
2878                         goto ciu_out;
2879                 }
2880         }
2881
2882         if (host->use_dma == TRANS_MODE_IDMAC)
2883                 /* It is also required that we reinit idmac */
2884                 dw_mci_idmac_init(host);
2885
2886         ret = true;
2887
2888 ciu_out:
2889         /* After a CTRL reset we need to have CIU set clock registers  */
2890         mci_send_cmd(host->cur_slot, SDMMC_CMD_UPD_CLK, 0);
2891
2892         return ret;
2893 }
2894
2895 static void dw_mci_cmd11_timer(unsigned long arg)
2896 {
2897         struct dw_mci *host = (struct dw_mci *)arg;
2898
2899         if (host->state != STATE_SENDING_CMD11) {
2900                 dev_warn(host->dev, "Unexpected CMD11 timeout\n");
2901                 return;
2902         }
2903
2904         host->cmd_status = SDMMC_INT_RTO;
2905         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2906         tasklet_schedule(&host->tasklet);
2907 }
2908
2909 static void dw_mci_dto_timer(unsigned long arg)
2910 {
2911         struct dw_mci *host = (struct dw_mci *)arg;
2912
2913         switch (host->state) {
2914         case STATE_SENDING_DATA:
2915         case STATE_DATA_BUSY:
2916                 /*
2917                  * If DTO interrupt does NOT come in sending data state,
2918                  * we should notify the driver to terminate current transfer
2919                  * and report a data timeout to the core.
2920                  */
2921                 host->data_status = SDMMC_INT_DRTO;
2922                 set_bit(EVENT_DATA_ERROR, &host->pending_events);
2923                 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2924                 tasklet_schedule(&host->tasklet);
2925                 break;
2926         default:
2927                 break;
2928         }
2929 }
2930
2931 #ifdef CONFIG_OF
2932 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2933 {
2934         struct dw_mci_board *pdata;
2935         struct device *dev = host->dev;
2936         const struct dw_mci_drv_data *drv_data = host->drv_data;
2937         int ret;
2938         u32 clock_frequency;
2939
2940         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2941         if (!pdata)
2942                 return ERR_PTR(-ENOMEM);
2943
2944         /* find reset controller when exist */
2945         pdata->rstc = devm_reset_control_get_optional(dev, "reset");
2946         if (IS_ERR(pdata->rstc)) {
2947                 if (PTR_ERR(pdata->rstc) == -EPROBE_DEFER)
2948                         return ERR_PTR(-EPROBE_DEFER);
2949         }
2950
2951         /* find out number of slots supported */
2952         device_property_read_u32(dev, "num-slots", &pdata->num_slots);
2953
2954         if (device_property_read_u32(dev, "fifo-depth", &pdata->fifo_depth))
2955                 dev_info(dev,
2956                          "fifo-depth property not found, using value of FIFOTH register as default\n");
2957
2958         device_property_read_u32(dev, "card-detect-delay",
2959                                  &pdata->detect_delay_ms);
2960
2961         if (!device_property_read_u32(dev, "clock-frequency", &clock_frequency))
2962                 pdata->bus_hz = clock_frequency;
2963
2964         if (drv_data && drv_data->parse_dt) {
2965                 ret = drv_data->parse_dt(host);
2966                 if (ret)
2967                         return ERR_PTR(ret);
2968         }
2969
2970         return pdata;
2971 }
2972
2973 #else /* CONFIG_OF */
2974 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2975 {
2976         return ERR_PTR(-EINVAL);
2977 }
2978 #endif /* CONFIG_OF */
2979
2980 static void dw_mci_enable_cd(struct dw_mci *host)
2981 {
2982         unsigned long irqflags;
2983         u32 temp;
2984         int i;
2985         struct dw_mci_slot *slot;
2986
2987         /*
2988          * No need for CD if all slots have a non-error GPIO
2989          * as well as broken card detection is found.
2990          */
2991         for (i = 0; i < host->num_slots; i++) {
2992                 slot = host->slot[i];
2993                 if (slot->mmc->caps & MMC_CAP_NEEDS_POLL)
2994                         return;
2995
2996                 if (mmc_gpio_get_cd(slot->mmc) < 0)
2997                         break;
2998         }
2999         if (i == host->num_slots)
3000                 return;
3001
3002         spin_lock_irqsave(&host->irq_lock, irqflags);
3003         temp = mci_readl(host, INTMASK);
3004         temp  |= SDMMC_INT_CD;
3005         mci_writel(host, INTMASK, temp);
3006         spin_unlock_irqrestore(&host->irq_lock, irqflags);
3007 }
3008
3009 int dw_mci_probe(struct dw_mci *host)
3010 {
3011         const struct dw_mci_drv_data *drv_data = host->drv_data;
3012         int width, i, ret = 0;
3013         u32 fifo_size;
3014         int init_slots = 0;
3015
3016         if (!host->pdata) {
3017                 host->pdata = dw_mci_parse_dt(host);
3018                 if (PTR_ERR(host->pdata) == -EPROBE_DEFER) {
3019                         return -EPROBE_DEFER;
3020                 } else if (IS_ERR(host->pdata)) {
3021                         dev_err(host->dev, "platform data not available\n");
3022                         return -EINVAL;
3023                 }
3024         }
3025
3026         host->biu_clk = devm_clk_get(host->dev, "biu");
3027         if (IS_ERR(host->biu_clk)) {
3028                 dev_dbg(host->dev, "biu clock not available\n");
3029         } else {
3030                 ret = clk_prepare_enable(host->biu_clk);
3031                 if (ret) {
3032                         dev_err(host->dev, "failed to enable biu clock\n");
3033                         return ret;
3034                 }
3035         }
3036
3037         host->ciu_clk = devm_clk_get(host->dev, "ciu");
3038         if (IS_ERR(host->ciu_clk)) {
3039                 dev_dbg(host->dev, "ciu clock not available\n");
3040                 host->bus_hz = host->pdata->bus_hz;
3041         } else {
3042                 ret = clk_prepare_enable(host->ciu_clk);
3043                 if (ret) {
3044                         dev_err(host->dev, "failed to enable ciu clock\n");
3045                         goto err_clk_biu;
3046                 }
3047
3048                 if (host->pdata->bus_hz) {
3049                         ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz);
3050                         if (ret)
3051                                 dev_warn(host->dev,
3052                                          "Unable to set bus rate to %uHz\n",
3053                                          host->pdata->bus_hz);
3054                 }
3055                 host->bus_hz = clk_get_rate(host->ciu_clk);
3056         }
3057
3058         if (!host->bus_hz) {
3059                 dev_err(host->dev,
3060                         "Platform data must supply bus speed\n");
3061                 ret = -ENODEV;
3062                 goto err_clk_ciu;
3063         }
3064
3065         if (drv_data && drv_data->init) {
3066                 ret = drv_data->init(host);
3067                 if (ret) {
3068                         dev_err(host->dev,
3069                                 "implementation specific init failed\n");
3070                         goto err_clk_ciu;
3071                 }
3072         }
3073
3074         if (!IS_ERR(host->pdata->rstc)) {
3075                 reset_control_assert(host->pdata->rstc);
3076                 usleep_range(10, 50);
3077                 reset_control_deassert(host->pdata->rstc);
3078         }
3079
3080         setup_timer(&host->cmd11_timer,
3081                     dw_mci_cmd11_timer, (unsigned long)host);
3082
3083         setup_timer(&host->dto_timer,
3084                     dw_mci_dto_timer, (unsigned long)host);
3085
3086         spin_lock_init(&host->lock);
3087         spin_lock_init(&host->irq_lock);
3088         INIT_LIST_HEAD(&host->queue);
3089
3090         /*
3091          * Get the host data width - this assumes that HCON has been set with
3092          * the correct values.
3093          */
3094         i = SDMMC_GET_HDATA_WIDTH(mci_readl(host, HCON));
3095         if (!i) {
3096                 host->push_data = dw_mci_push_data16;
3097                 host->pull_data = dw_mci_pull_data16;
3098                 width = 16;
3099                 host->data_shift = 1;
3100         } else if (i == 2) {
3101                 host->push_data = dw_mci_push_data64;
3102                 host->pull_data = dw_mci_pull_data64;
3103                 width = 64;
3104                 host->data_shift = 3;
3105         } else {
3106                 /* Check for a reserved value, and warn if it is */
3107                 WARN((i != 1),
3108                      "HCON reports a reserved host data width!\n"
3109                      "Defaulting to 32-bit access.\n");
3110                 host->push_data = dw_mci_push_data32;
3111                 host->pull_data = dw_mci_pull_data32;
3112                 width = 32;
3113                 host->data_shift = 2;
3114         }
3115
3116         /* Reset all blocks */
3117         if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
3118                 ret = -ENODEV;
3119                 goto err_clk_ciu;
3120         }
3121
3122         host->dma_ops = host->pdata->dma_ops;
3123         dw_mci_init_dma(host);
3124
3125         /* Clear the interrupts for the host controller */
3126         mci_writel(host, RINTSTS, 0xFFFFFFFF);
3127         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3128
3129         /* Put in max timeout */
3130         mci_writel(host, TMOUT, 0xFFFFFFFF);
3131
3132         /*
3133          * FIFO threshold settings  RxMark  = fifo_size / 2 - 1,
3134          *                          Tx Mark = fifo_size / 2 DMA Size = 8
3135          */
3136         if (!host->pdata->fifo_depth) {
3137                 /*
3138                  * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
3139                  * have been overwritten by the bootloader, just like we're
3140                  * about to do, so if you know the value for your hardware, you
3141                  * should put it in the platform data.
3142                  */
3143                 fifo_size = mci_readl(host, FIFOTH);
3144                 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
3145         } else {
3146                 fifo_size = host->pdata->fifo_depth;
3147         }
3148         host->fifo_depth = fifo_size;
3149         host->fifoth_val =
3150                 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2);
3151         mci_writel(host, FIFOTH, host->fifoth_val);
3152
3153         /* disable clock to CIU */
3154         mci_writel(host, CLKENA, 0);
3155         mci_writel(host, CLKSRC, 0);
3156
3157         /*
3158          * In 2.40a spec, Data offset is changed.
3159          * Need to check the version-id and set data-offset for DATA register.
3160          */
3161         host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
3162         dev_info(host->dev, "Version ID is %04x\n", host->verid);
3163
3164         if (host->verid < DW_MMC_240A)
3165                 host->fifo_reg = host->regs + DATA_OFFSET;
3166         else
3167                 host->fifo_reg = host->regs + DATA_240A_OFFSET;
3168
3169         tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
3170         ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
3171                                host->irq_flags, "dw-mci", host);
3172         if (ret)
3173                 goto err_dmaunmap;
3174
3175         if (host->pdata->num_slots)
3176                 host->num_slots = host->pdata->num_slots;
3177         else
3178                 host->num_slots = 1;
3179
3180         if (host->num_slots < 1 ||
3181             host->num_slots > SDMMC_GET_SLOT_NUM(mci_readl(host, HCON))) {
3182                 dev_err(host->dev,
3183                         "Platform data must supply correct num_slots.\n");
3184                 ret = -ENODEV;
3185                 goto err_clk_ciu;
3186         }
3187
3188         /*
3189          * Enable interrupts for command done, data over, data empty,
3190          * receive ready and error such as transmit, receive timeout, crc error
3191          */
3192         mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3193                    SDMMC_INT_TXDR | SDMMC_INT_RXDR |
3194                    DW_MCI_ERROR_FLAGS);
3195         /* Enable mci interrupt */
3196         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3197
3198         dev_info(host->dev,
3199                  "DW MMC controller at irq %d,%d bit host data width,%u deep fifo\n",
3200                  host->irq, width, fifo_size);
3201
3202         /* We need at least one slot to succeed */
3203         for (i = 0; i < host->num_slots; i++) {
3204                 ret = dw_mci_init_slot(host, i);
3205                 if (ret)
3206                         dev_dbg(host->dev, "slot %d init failed\n", i);
3207                 else
3208                         init_slots++;
3209         }
3210
3211         if (init_slots) {
3212                 dev_info(host->dev, "%d slots initialized\n", init_slots);
3213         } else {
3214                 dev_dbg(host->dev,
3215                         "attempted to initialize %d slots, but failed on all\n",
3216                         host->num_slots);
3217                 goto err_dmaunmap;
3218         }
3219
3220         /* Now that slots are all setup, we can enable card detect */
3221         dw_mci_enable_cd(host);
3222
3223         return 0;
3224
3225 err_dmaunmap:
3226         if (host->use_dma && host->dma_ops->exit)
3227                 host->dma_ops->exit(host);
3228
3229         if (!IS_ERR(host->pdata->rstc))
3230                 reset_control_assert(host->pdata->rstc);
3231
3232 err_clk_ciu:
3233         clk_disable_unprepare(host->ciu_clk);
3234
3235 err_clk_biu:
3236         clk_disable_unprepare(host->biu_clk);
3237
3238         return ret;
3239 }
3240 EXPORT_SYMBOL(dw_mci_probe);
3241
3242 void dw_mci_remove(struct dw_mci *host)
3243 {
3244         int i;
3245
3246         for (i = 0; i < host->num_slots; i++) {
3247                 dev_dbg(host->dev, "remove slot %d\n", i);
3248                 if (host->slot[i])
3249                         dw_mci_cleanup_slot(host->slot[i], i);
3250         }
3251
3252         mci_writel(host, RINTSTS, 0xFFFFFFFF);
3253         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3254
3255         /* disable clock to CIU */
3256         mci_writel(host, CLKENA, 0);
3257         mci_writel(host, CLKSRC, 0);
3258
3259         if (host->use_dma && host->dma_ops->exit)
3260                 host->dma_ops->exit(host);
3261
3262         if (!IS_ERR(host->pdata->rstc))
3263                 reset_control_assert(host->pdata->rstc);
3264
3265         clk_disable_unprepare(host->ciu_clk);
3266         clk_disable_unprepare(host->biu_clk);
3267 }
3268 EXPORT_SYMBOL(dw_mci_remove);
3269
3270
3271
3272 #ifdef CONFIG_PM_SLEEP
3273 /*
3274  * TODO: we should probably disable the clock to the card in the suspend path.
3275  */
3276 int dw_mci_suspend(struct dw_mci *host)
3277 {
3278         if (host->use_dma && host->dma_ops->exit)
3279                 host->dma_ops->exit(host);
3280
3281         return 0;
3282 }
3283 EXPORT_SYMBOL(dw_mci_suspend);
3284
3285 int dw_mci_resume(struct dw_mci *host)
3286 {
3287         int i, ret;
3288
3289         if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
3290                 ret = -ENODEV;
3291                 return ret;
3292         }
3293
3294         if (host->use_dma && host->dma_ops->init)
3295                 host->dma_ops->init(host);
3296
3297         /*
3298          * Restore the initial value at FIFOTH register
3299          * And Invalidate the prev_blksz with zero
3300          */
3301         mci_writel(host, FIFOTH, host->fifoth_val);
3302         host->prev_blksz = 0;
3303
3304         /* Put in max timeout */
3305         mci_writel(host, TMOUT, 0xFFFFFFFF);
3306
3307         mci_writel(host, RINTSTS, 0xFFFFFFFF);
3308         mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3309                    SDMMC_INT_TXDR | SDMMC_INT_RXDR |
3310                    DW_MCI_ERROR_FLAGS);
3311         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3312
3313         for (i = 0; i < host->num_slots; i++) {
3314                 struct dw_mci_slot *slot = host->slot[i];
3315
3316                 if (!slot)
3317                         continue;
3318                 if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) {
3319                         dw_mci_set_ios(slot->mmc, &slot->mmc->ios);
3320                         dw_mci_setup_bus(slot, true);
3321                 }
3322         }
3323
3324         /* Now that slots are all setup, we can enable card detect */
3325         dw_mci_enable_cd(host);
3326
3327         return 0;
3328 }
3329 EXPORT_SYMBOL(dw_mci_resume);
3330 #endif /* CONFIG_PM_SLEEP */
3331
3332 static int __init dw_mci_init(void)
3333 {
3334         pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
3335         return 0;
3336 }
3337
3338 static void __exit dw_mci_exit(void)
3339 {
3340 }
3341
3342 module_init(dw_mci_init);
3343 module_exit(dw_mci_exit);
3344
3345 MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
3346 MODULE_AUTHOR("NXP Semiconductor VietNam");
3347 MODULE_AUTHOR("Imagination Technologies Ltd");
3348 MODULE_LICENSE("GPL v2");