2 * Synopsys DesignWare Multimedia Card Interface driver
3 * (Based on NXP driver for lpc 31xx)
5 * Copyright (C) 2009 NXP Semiconductors
6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/blkdev.h>
15 #include <linux/clk.h>
16 #include <linux/debugfs.h>
17 #include <linux/device.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/err.h>
20 #include <linux/init.h>
21 #include <linux/interrupt.h>
22 #include <linux/ioport.h>
23 #include <linux/module.h>
24 #include <linux/platform_device.h>
25 #include <linux/seq_file.h>
26 #include <linux/slab.h>
27 #include <linux/stat.h>
28 #include <linux/delay.h>
29 #include <linux/irq.h>
30 #include <linux/mmc/card.h>
31 #include <linux/mmc/host.h>
32 #include <linux/mmc/mmc.h>
33 #include <linux/mmc/sd.h>
34 #include <linux/mmc/sdio.h>
35 #include <linux/mmc/dw_mmc.h>
36 #include <linux/bitops.h>
37 #include <linux/regulator/consumer.h>
39 #include <linux/of_gpio.h>
40 #include <linux/mmc/slot-gpio.h>
44 /* Common flag combinations */
45 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
46 SDMMC_INT_HTO | SDMMC_INT_SBE | \
47 SDMMC_INT_EBE | SDMMC_INT_HLE)
48 #define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
49 SDMMC_INT_RESP_ERR | SDMMC_INT_HLE)
50 #define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \
51 DW_MCI_CMD_ERROR_FLAGS)
52 #define DW_MCI_SEND_STATUS 1
53 #define DW_MCI_RECV_STATUS 2
54 #define DW_MCI_DMA_THRESHOLD 16
56 #define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */
57 #define DW_MCI_FREQ_MIN 400000 /* unit: HZ */
59 #define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
60 SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
61 SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
64 #define DESC_RING_BUF_SZ PAGE_SIZE
66 struct idmac_desc_64addr {
67 u32 des0; /* Control Descriptor */
69 u32 des1; /* Reserved */
71 u32 des2; /*Buffer sizes */
72 #define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \
73 ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \
74 ((cpu_to_le32(s)) & cpu_to_le32(0x1fff)))
76 u32 des3; /* Reserved */
78 u32 des4; /* Lower 32-bits of Buffer Address Pointer 1*/
79 u32 des5; /* Upper 32-bits of Buffer Address Pointer 1*/
81 u32 des6; /* Lower 32-bits of Next Descriptor Address */
82 u32 des7; /* Upper 32-bits of Next Descriptor Address */
86 __le32 des0; /* Control Descriptor */
87 #define IDMAC_DES0_DIC BIT(1)
88 #define IDMAC_DES0_LD BIT(2)
89 #define IDMAC_DES0_FD BIT(3)
90 #define IDMAC_DES0_CH BIT(4)
91 #define IDMAC_DES0_ER BIT(5)
92 #define IDMAC_DES0_CES BIT(30)
93 #define IDMAC_DES0_OWN BIT(31)
95 __le32 des1; /* Buffer sizes */
96 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
97 ((d)->des1 = ((d)->des1 & cpu_to_le32(0x03ffe000)) | (cpu_to_le32((s) & 0x1fff)))
99 __le32 des2; /* buffer 1 physical address */
101 __le32 des3; /* buffer 2 physical address */
104 /* Each descriptor can transfer up to 4KB of data in chained mode */
105 #define DW_MCI_DESC_DATA_LENGTH 0x1000
107 static bool dw_mci_reset(struct dw_mci *host);
108 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
109 static int dw_mci_card_busy(struct mmc_host *mmc);
110 static int dw_mci_get_cd(struct mmc_host *mmc);
112 #if defined(CONFIG_DEBUG_FS)
113 static int dw_mci_req_show(struct seq_file *s, void *v)
115 struct dw_mci_slot *slot = s->private;
116 struct mmc_request *mrq;
117 struct mmc_command *cmd;
118 struct mmc_command *stop;
119 struct mmc_data *data;
121 /* Make sure we get a consistent snapshot */
122 spin_lock_bh(&slot->host->lock);
132 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
133 cmd->opcode, cmd->arg, cmd->flags,
134 cmd->resp[0], cmd->resp[1], cmd->resp[2],
135 cmd->resp[2], cmd->error);
137 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
138 data->bytes_xfered, data->blocks,
139 data->blksz, data->flags, data->error);
142 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
143 stop->opcode, stop->arg, stop->flags,
144 stop->resp[0], stop->resp[1], stop->resp[2],
145 stop->resp[2], stop->error);
148 spin_unlock_bh(&slot->host->lock);
153 static int dw_mci_req_open(struct inode *inode, struct file *file)
155 return single_open(file, dw_mci_req_show, inode->i_private);
158 static const struct file_operations dw_mci_req_fops = {
159 .owner = THIS_MODULE,
160 .open = dw_mci_req_open,
163 .release = single_release,
166 static int dw_mci_regs_show(struct seq_file *s, void *v)
168 seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS);
169 seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS);
170 seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD);
171 seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL);
172 seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK);
173 seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA);
178 static int dw_mci_regs_open(struct inode *inode, struct file *file)
180 return single_open(file, dw_mci_regs_show, inode->i_private);
183 static const struct file_operations dw_mci_regs_fops = {
184 .owner = THIS_MODULE,
185 .open = dw_mci_regs_open,
188 .release = single_release,
191 static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
193 struct mmc_host *mmc = slot->mmc;
194 struct dw_mci *host = slot->host;
198 root = mmc->debugfs_root;
202 node = debugfs_create_file("regs", S_IRUSR, root, host,
207 node = debugfs_create_file("req", S_IRUSR, root, slot,
212 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
216 node = debugfs_create_x32("pending_events", S_IRUSR, root,
217 (u32 *)&host->pending_events);
221 node = debugfs_create_x32("completed_events", S_IRUSR, root,
222 (u32 *)&host->completed_events);
229 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
231 #endif /* defined(CONFIG_DEBUG_FS) */
233 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg);
235 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
237 struct mmc_data *data;
238 struct dw_mci_slot *slot = mmc_priv(mmc);
239 struct dw_mci *host = slot->host;
242 cmd->error = -EINPROGRESS;
245 if (cmd->opcode == MMC_STOP_TRANSMISSION ||
246 cmd->opcode == MMC_GO_IDLE_STATE ||
247 cmd->opcode == MMC_GO_INACTIVE_STATE ||
248 (cmd->opcode == SD_IO_RW_DIRECT &&
249 ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT))
250 cmdr |= SDMMC_CMD_STOP;
251 else if (cmd->opcode != MMC_SEND_STATUS && cmd->data)
252 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
254 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
257 /* Special bit makes CMD11 not die */
258 cmdr |= SDMMC_CMD_VOLT_SWITCH;
260 /* Change state to continue to handle CMD11 weirdness */
261 WARN_ON(slot->host->state != STATE_SENDING_CMD);
262 slot->host->state = STATE_SENDING_CMD11;
265 * We need to disable low power mode (automatic clock stop)
266 * while doing voltage switch so we don't confuse the card,
267 * since stopping the clock is a specific part of the UHS
268 * voltage change dance.
270 * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be
271 * unconditionally turned back on in dw_mci_setup_bus() if it's
272 * ever called with a non-zero clock. That shouldn't happen
273 * until the voltage change is all done.
275 clk_en_a = mci_readl(host, CLKENA);
276 clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id);
277 mci_writel(host, CLKENA, clk_en_a);
278 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
279 SDMMC_CMD_PRV_DAT_WAIT, 0);
282 if (cmd->flags & MMC_RSP_PRESENT) {
283 /* We expect a response, so set this bit */
284 cmdr |= SDMMC_CMD_RESP_EXP;
285 if (cmd->flags & MMC_RSP_136)
286 cmdr |= SDMMC_CMD_RESP_LONG;
289 if (cmd->flags & MMC_RSP_CRC)
290 cmdr |= SDMMC_CMD_RESP_CRC;
294 cmdr |= SDMMC_CMD_DAT_EXP;
295 if (data->flags & MMC_DATA_WRITE)
296 cmdr |= SDMMC_CMD_DAT_WR;
299 if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &slot->flags))
300 cmdr |= SDMMC_CMD_USE_HOLD_REG;
305 static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd)
307 struct mmc_command *stop;
313 stop = &host->stop_abort;
315 memset(stop, 0, sizeof(struct mmc_command));
317 if (cmdr == MMC_READ_SINGLE_BLOCK ||
318 cmdr == MMC_READ_MULTIPLE_BLOCK ||
319 cmdr == MMC_WRITE_BLOCK ||
320 cmdr == MMC_WRITE_MULTIPLE_BLOCK ||
321 cmdr == MMC_SEND_TUNING_BLOCK ||
322 cmdr == MMC_SEND_TUNING_BLOCK_HS200) {
323 stop->opcode = MMC_STOP_TRANSMISSION;
325 stop->flags = MMC_RSP_R1B | MMC_CMD_AC;
326 } else if (cmdr == SD_IO_RW_EXTENDED) {
327 stop->opcode = SD_IO_RW_DIRECT;
328 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
329 ((cmd->arg >> 28) & 0x7);
330 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC;
335 cmdr = stop->opcode | SDMMC_CMD_STOP |
336 SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP;
341 static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags)
343 unsigned long timeout = jiffies + msecs_to_jiffies(500);
346 * Databook says that before issuing a new data transfer command
347 * we need to check to see if the card is busy. Data transfer commands
348 * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that.
350 * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is
353 if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) &&
354 !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) {
355 while (mci_readl(host, STATUS) & SDMMC_STATUS_BUSY) {
356 if (time_after(jiffies, timeout)) {
357 /* Command will fail; we'll pass error then */
358 dev_err(host->dev, "Busy; trying anyway\n");
366 static void dw_mci_start_command(struct dw_mci *host,
367 struct mmc_command *cmd, u32 cmd_flags)
371 "start command: ARGR=0x%08x CMDR=0x%08x\n",
372 cmd->arg, cmd_flags);
374 mci_writel(host, CMDARG, cmd->arg);
375 wmb(); /* drain writebuffer */
376 dw_mci_wait_while_busy(host, cmd_flags);
378 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
381 static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data)
383 struct mmc_command *stop = &host->stop_abort;
385 dw_mci_start_command(host, stop, host->stop_cmdr);
388 /* DMA interface functions */
389 static void dw_mci_stop_dma(struct dw_mci *host)
391 if (host->using_dma) {
392 host->dma_ops->stop(host);
393 host->dma_ops->cleanup(host);
396 /* Data transfer was stopped by the interrupt handler */
397 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
400 static int dw_mci_get_dma_dir(struct mmc_data *data)
402 if (data->flags & MMC_DATA_WRITE)
403 return DMA_TO_DEVICE;
405 return DMA_FROM_DEVICE;
408 static void dw_mci_dma_cleanup(struct dw_mci *host)
410 struct mmc_data *data = host->data;
413 if (!data->host_cookie)
414 dma_unmap_sg(host->dev,
417 dw_mci_get_dma_dir(data));
420 static void dw_mci_idmac_reset(struct dw_mci *host)
422 u32 bmod = mci_readl(host, BMOD);
423 /* Software reset of DMA */
424 bmod |= SDMMC_IDMAC_SWRESET;
425 mci_writel(host, BMOD, bmod);
428 static void dw_mci_idmac_stop_dma(struct dw_mci *host)
432 /* Disable and reset the IDMAC interface */
433 temp = mci_readl(host, CTRL);
434 temp &= ~SDMMC_CTRL_USE_IDMAC;
435 temp |= SDMMC_CTRL_DMA_RESET;
436 mci_writel(host, CTRL, temp);
438 /* Stop the IDMAC running */
439 temp = mci_readl(host, BMOD);
440 temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
441 temp |= SDMMC_IDMAC_SWRESET;
442 mci_writel(host, BMOD, temp);
445 static void dw_mci_dmac_complete_dma(void *arg)
447 struct dw_mci *host = arg;
448 struct mmc_data *data = host->data;
450 dev_vdbg(host->dev, "DMA complete\n");
452 if ((host->use_dma == TRANS_MODE_EDMAC) &&
453 data && (data->flags & MMC_DATA_READ))
454 /* Invalidate cache after read */
455 dma_sync_sg_for_cpu(mmc_dev(host->cur_slot->mmc),
460 host->dma_ops->cleanup(host);
463 * If the card was removed, data will be NULL. No point in trying to
464 * send the stop command or waiting for NBUSY in this case.
467 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
468 tasklet_schedule(&host->tasklet);
472 static int dw_mci_idmac_init(struct dw_mci *host)
476 if (host->dma_64bit_address == 1) {
477 struct idmac_desc_64addr *p;
478 /* Number of descriptors in the ring buffer */
480 DESC_RING_BUF_SZ / sizeof(struct idmac_desc_64addr);
482 /* Forward link the descriptor list */
483 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1;
485 p->des6 = (host->sg_dma +
486 (sizeof(struct idmac_desc_64addr) *
487 (i + 1))) & 0xffffffff;
489 p->des7 = (u64)(host->sg_dma +
490 (sizeof(struct idmac_desc_64addr) *
492 /* Initialize reserved and buffer size fields to "0" */
499 /* Set the last descriptor as the end-of-ring descriptor */
500 p->des6 = host->sg_dma & 0xffffffff;
501 p->des7 = (u64)host->sg_dma >> 32;
502 p->des0 = IDMAC_DES0_ER;
505 struct idmac_desc *p;
506 /* Number of descriptors in the ring buffer */
508 DESC_RING_BUF_SZ / sizeof(struct idmac_desc);
510 /* Forward link the descriptor list */
511 for (i = 0, p = host->sg_cpu;
512 i < host->ring_size - 1;
514 p->des3 = cpu_to_le32(host->sg_dma +
515 (sizeof(struct idmac_desc) * (i + 1)));
520 /* Set the last descriptor as the end-of-ring descriptor */
521 p->des3 = cpu_to_le32(host->sg_dma);
522 p->des0 = cpu_to_le32(IDMAC_DES0_ER);
525 dw_mci_idmac_reset(host);
527 if (host->dma_64bit_address == 1) {
528 /* Mask out interrupts - get Tx & Rx complete only */
529 mci_writel(host, IDSTS64, IDMAC_INT_CLR);
530 mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI |
531 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
533 /* Set the descriptor base address */
534 mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff);
535 mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32);
538 /* Mask out interrupts - get Tx & Rx complete only */
539 mci_writel(host, IDSTS, IDMAC_INT_CLR);
540 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI |
541 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
543 /* Set the descriptor base address */
544 mci_writel(host, DBADDR, host->sg_dma);
550 static inline int dw_mci_prepare_desc64(struct dw_mci *host,
551 struct mmc_data *data,
554 unsigned int desc_len;
555 struct idmac_desc_64addr *desc_first, *desc_last, *desc;
556 unsigned long timeout;
559 desc_first = desc_last = desc = host->sg_cpu;
561 for (i = 0; i < sg_len; i++) {
562 unsigned int length = sg_dma_len(&data->sg[i]);
564 u64 mem_addr = sg_dma_address(&data->sg[i]);
566 for ( ; length ; desc++) {
567 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
568 length : DW_MCI_DESC_DATA_LENGTH;
573 * Wait for the former clear OWN bit operation
574 * of IDMAC to make sure that this descriptor
575 * isn't still owned by IDMAC as IDMAC's write
576 * ops and CPU's read ops are asynchronous.
578 timeout = jiffies + msecs_to_jiffies(100);
579 while (readl(&desc->des0) & IDMAC_DES0_OWN) {
580 if (time_after(jiffies, timeout))
586 * Set the OWN bit and disable interrupts
587 * for this descriptor
589 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC |
593 IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, desc_len);
595 /* Physical address to DMA to/from */
596 desc->des4 = mem_addr & 0xffffffff;
597 desc->des5 = mem_addr >> 32;
599 /* Update physical address for the next desc */
600 mem_addr += desc_len;
602 /* Save pointer to the last descriptor */
607 /* Set first descriptor */
608 desc_first->des0 |= IDMAC_DES0_FD;
610 /* Set last descriptor */
611 desc_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
612 desc_last->des0 |= IDMAC_DES0_LD;
616 /* restore the descriptor chain as it's polluted */
617 dev_dbg(host->dev, "desciptor is still owned by IDMAC.\n");
618 memset(host->sg_cpu, 0, DESC_RING_BUF_SZ);
619 dw_mci_idmac_init(host);
624 static inline int dw_mci_prepare_desc32(struct dw_mci *host,
625 struct mmc_data *data,
628 unsigned int desc_len;
629 struct idmac_desc *desc_first, *desc_last, *desc;
630 unsigned long timeout;
633 desc_first = desc_last = desc = host->sg_cpu;
635 for (i = 0; i < sg_len; i++) {
636 unsigned int length = sg_dma_len(&data->sg[i]);
638 u32 mem_addr = sg_dma_address(&data->sg[i]);
640 for ( ; length ; desc++) {
641 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
642 length : DW_MCI_DESC_DATA_LENGTH;
647 * Wait for the former clear OWN bit operation
648 * of IDMAC to make sure that this descriptor
649 * isn't still owned by IDMAC as IDMAC's write
650 * ops and CPU's read ops are asynchronous.
652 timeout = jiffies + msecs_to_jiffies(100);
653 while (readl(&desc->des0) &
654 cpu_to_le32(IDMAC_DES0_OWN)) {
655 if (time_after(jiffies, timeout))
661 * Set the OWN bit and disable interrupts
662 * for this descriptor
664 desc->des0 = cpu_to_le32(IDMAC_DES0_OWN |
669 IDMAC_SET_BUFFER1_SIZE(desc, desc_len);
671 /* Physical address to DMA to/from */
672 desc->des2 = cpu_to_le32(mem_addr);
674 /* Update physical address for the next desc */
675 mem_addr += desc_len;
677 /* Save pointer to the last descriptor */
682 /* Set first descriptor */
683 desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD);
685 /* Set last descriptor */
686 desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH |
688 desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD);
692 /* restore the descriptor chain as it's polluted */
693 dev_dbg(host->dev, "desciptor is still owned by IDMAC.\n");
694 memset(host->sg_cpu, 0, DESC_RING_BUF_SZ);
695 dw_mci_idmac_init(host);
699 static int dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
704 if (host->dma_64bit_address == 1)
705 ret = dw_mci_prepare_desc64(host, host->data, sg_len);
707 ret = dw_mci_prepare_desc32(host, host->data, sg_len);
712 /* drain writebuffer */
715 /* Make sure to reset DMA in case we did PIO before this */
716 dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
717 dw_mci_idmac_reset(host);
719 /* Select IDMAC interface */
720 temp = mci_readl(host, CTRL);
721 temp |= SDMMC_CTRL_USE_IDMAC;
722 mci_writel(host, CTRL, temp);
724 /* drain writebuffer */
727 /* Enable the IDMAC */
728 temp = mci_readl(host, BMOD);
729 temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
730 mci_writel(host, BMOD, temp);
732 /* Start it running */
733 mci_writel(host, PLDMND, 1);
739 static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
740 .init = dw_mci_idmac_init,
741 .start = dw_mci_idmac_start_dma,
742 .stop = dw_mci_idmac_stop_dma,
743 .complete = dw_mci_dmac_complete_dma,
744 .cleanup = dw_mci_dma_cleanup,
747 static void dw_mci_edmac_stop_dma(struct dw_mci *host)
749 dmaengine_terminate_async(host->dms->ch);
752 static int dw_mci_edmac_start_dma(struct dw_mci *host,
755 struct dma_slave_config cfg;
756 struct dma_async_tx_descriptor *desc = NULL;
757 struct scatterlist *sgl = host->data->sg;
758 const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
759 u32 sg_elems = host->data->sg_len;
761 u32 fifo_offset = host->fifo_reg - host->regs;
764 /* Set external dma config: burst size, burst width */
765 memset(&cfg, 0, sizeof(cfg));
766 cfg.dst_addr = host->phy_regs + fifo_offset;
767 cfg.src_addr = cfg.dst_addr;
768 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
769 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
771 /* Match burst msize with external dma config */
772 fifoth_val = mci_readl(host, FIFOTH);
773 cfg.dst_maxburst = mszs[(fifoth_val >> 28) & 0x7];
774 cfg.src_maxburst = cfg.dst_maxburst;
776 if (host->data->flags & MMC_DATA_WRITE)
777 cfg.direction = DMA_MEM_TO_DEV;
779 cfg.direction = DMA_DEV_TO_MEM;
781 ret = dmaengine_slave_config(host->dms->ch, &cfg);
783 dev_err(host->dev, "Failed to config edmac.\n");
787 desc = dmaengine_prep_slave_sg(host->dms->ch, sgl,
788 sg_len, cfg.direction,
789 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
791 dev_err(host->dev, "Can't prepare slave sg.\n");
795 /* Set dw_mci_dmac_complete_dma as callback */
796 desc->callback = dw_mci_dmac_complete_dma;
797 desc->callback_param = (void *)host;
798 dmaengine_submit(desc);
800 /* Flush cache before write */
801 if (host->data->flags & MMC_DATA_WRITE)
802 dma_sync_sg_for_device(mmc_dev(host->cur_slot->mmc), sgl,
803 sg_elems, DMA_TO_DEVICE);
805 dma_async_issue_pending(host->dms->ch);
810 static int dw_mci_edmac_init(struct dw_mci *host)
812 /* Request external dma channel */
813 host->dms = kzalloc(sizeof(struct dw_mci_dma_slave), GFP_KERNEL);
817 host->dms->ch = dma_request_slave_channel(host->dev, "rx-tx");
818 if (!host->dms->ch) {
819 dev_err(host->dev, "Failed to get external DMA channel.\n");
828 static void dw_mci_edmac_exit(struct dw_mci *host)
832 dma_release_channel(host->dms->ch);
833 host->dms->ch = NULL;
840 static const struct dw_mci_dma_ops dw_mci_edmac_ops = {
841 .init = dw_mci_edmac_init,
842 .exit = dw_mci_edmac_exit,
843 .start = dw_mci_edmac_start_dma,
844 .stop = dw_mci_edmac_stop_dma,
845 .complete = dw_mci_dmac_complete_dma,
846 .cleanup = dw_mci_dma_cleanup,
849 static int dw_mci_pre_dma_transfer(struct dw_mci *host,
850 struct mmc_data *data,
853 struct scatterlist *sg;
854 unsigned int i, sg_len;
856 if (!next && data->host_cookie)
857 return data->host_cookie;
860 * We don't do DMA on "complex" transfers, i.e. with
861 * non-word-aligned buffers or lengths. Also, we don't bother
862 * with all the DMA setup overhead for short transfers.
864 if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
870 for_each_sg(data->sg, sg, data->sg_len, i) {
871 if (sg->offset & 3 || sg->length & 3)
875 sg_len = dma_map_sg(host->dev,
878 dw_mci_get_dma_dir(data));
883 data->host_cookie = sg_len;
888 static void dw_mci_pre_req(struct mmc_host *mmc,
889 struct mmc_request *mrq,
892 struct dw_mci_slot *slot = mmc_priv(mmc);
893 struct mmc_data *data = mrq->data;
895 if (!slot->host->use_dma || !data)
898 if (data->host_cookie) {
899 data->host_cookie = 0;
903 if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0)
904 data->host_cookie = 0;
907 static void dw_mci_post_req(struct mmc_host *mmc,
908 struct mmc_request *mrq,
911 struct dw_mci_slot *slot = mmc_priv(mmc);
912 struct mmc_data *data = mrq->data;
914 if (!slot->host->use_dma || !data)
917 if (data->host_cookie)
918 dma_unmap_sg(slot->host->dev,
921 dw_mci_get_dma_dir(data));
922 data->host_cookie = 0;
925 static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
927 unsigned int blksz = data->blksz;
928 const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
929 u32 fifo_width = 1 << host->data_shift;
930 u32 blksz_depth = blksz / fifo_width, fifoth_val;
931 u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
932 int idx = ARRAY_SIZE(mszs) - 1;
934 /* pio should ship this scenario */
938 tx_wmark = (host->fifo_depth) / 2;
939 tx_wmark_invers = host->fifo_depth - tx_wmark;
943 * if blksz is not a multiple of the FIFO width
945 if (blksz % fifo_width)
949 if (!((blksz_depth % mszs[idx]) ||
950 (tx_wmark_invers % mszs[idx]))) {
952 rx_wmark = mszs[idx] - 1;
957 * If idx is '0', it won't be tried
958 * Thus, initial values are uesed
961 fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
962 mci_writel(host, FIFOTH, fifoth_val);
965 static void dw_mci_ctrl_thld(struct dw_mci *host, struct mmc_data *data)
967 unsigned int blksz = data->blksz;
968 u32 blksz_depth, fifo_depth;
973 * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is
974 * in the FIFO region, so we really shouldn't access it).
976 if (host->verid < DW_MMC_240A ||
977 (host->verid < DW_MMC_280A && data->flags & MMC_DATA_WRITE))
981 * Card write Threshold is introduced since 2.80a
982 * It's used when HS400 mode is enabled.
984 if (data->flags & MMC_DATA_WRITE &&
985 host->timing != MMC_TIMING_MMC_HS400)
988 if (data->flags & MMC_DATA_WRITE)
989 enable = SDMMC_CARD_WR_THR_EN;
991 enable = SDMMC_CARD_RD_THR_EN;
993 if (host->timing != MMC_TIMING_MMC_HS200 &&
994 host->timing != MMC_TIMING_UHS_SDR104 &&
995 host->timing != MMC_TIMING_MMC_HS400)
998 blksz_depth = blksz / (1 << host->data_shift);
999 fifo_depth = host->fifo_depth;
1001 if (blksz_depth > fifo_depth)
1005 * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
1006 * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz
1007 * Currently just choose blksz.
1010 mci_writel(host, CDTHRCTL, SDMMC_SET_THLD(thld_size, enable));
1014 mci_writel(host, CDTHRCTL, 0);
1017 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
1019 unsigned long irqflags;
1023 host->using_dma = 0;
1025 /* If we don't have a channel, we can't do DMA */
1029 sg_len = dw_mci_pre_dma_transfer(host, data, 0);
1031 host->dma_ops->stop(host);
1035 host->using_dma = 1;
1037 if (host->use_dma == TRANS_MODE_IDMAC)
1039 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
1040 (unsigned long)host->sg_cpu,
1041 (unsigned long)host->sg_dma,
1045 * Decide the MSIZE and RX/TX Watermark.
1046 * If current block size is same with previous size,
1047 * no need to update fifoth.
1049 if (host->prev_blksz != data->blksz)
1050 dw_mci_adjust_fifoth(host, data);
1052 /* Enable the DMA interface */
1053 temp = mci_readl(host, CTRL);
1054 temp |= SDMMC_CTRL_DMA_ENABLE;
1055 mci_writel(host, CTRL, temp);
1057 /* Disable RX/TX IRQs, let DMA handle it */
1058 spin_lock_irqsave(&host->irq_lock, irqflags);
1059 temp = mci_readl(host, INTMASK);
1060 temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
1061 mci_writel(host, INTMASK, temp);
1062 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1064 if (host->dma_ops->start(host, sg_len)) {
1065 host->dma_ops->stop(host);
1066 /* We can't do DMA, try PIO for this one */
1068 "%s: fall back to PIO mode for current transfer\n",
1076 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
1078 unsigned long irqflags;
1079 int flags = SG_MITER_ATOMIC;
1082 data->error = -EINPROGRESS;
1084 WARN_ON(host->data);
1088 if (data->flags & MMC_DATA_READ)
1089 host->dir_status = DW_MCI_RECV_STATUS;
1091 host->dir_status = DW_MCI_SEND_STATUS;
1093 dw_mci_ctrl_thld(host, data);
1095 if (dw_mci_submit_data_dma(host, data)) {
1096 if (host->data->flags & MMC_DATA_READ)
1097 flags |= SG_MITER_TO_SG;
1099 flags |= SG_MITER_FROM_SG;
1101 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
1102 host->sg = data->sg;
1103 host->part_buf_start = 0;
1104 host->part_buf_count = 0;
1106 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
1108 spin_lock_irqsave(&host->irq_lock, irqflags);
1109 temp = mci_readl(host, INTMASK);
1110 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
1111 mci_writel(host, INTMASK, temp);
1112 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1114 temp = mci_readl(host, CTRL);
1115 temp &= ~SDMMC_CTRL_DMA_ENABLE;
1116 mci_writel(host, CTRL, temp);
1119 * Use the initial fifoth_val for PIO mode.
1120 * If next issued data may be transfered by DMA mode,
1121 * prev_blksz should be invalidated.
1123 mci_writel(host, FIFOTH, host->fifoth_val);
1124 host->prev_blksz = 0;
1127 * Keep the current block size.
1128 * It will be used to decide whether to update
1129 * fifoth register next time.
1131 host->prev_blksz = data->blksz;
1135 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
1137 struct dw_mci *host = slot->host;
1138 unsigned long timeout = jiffies + msecs_to_jiffies(500);
1139 unsigned int cmd_status = 0;
1141 mci_writel(host, CMDARG, arg);
1142 wmb(); /* drain writebuffer */
1143 dw_mci_wait_while_busy(host, cmd);
1144 mci_writel(host, CMD, SDMMC_CMD_START | cmd);
1146 while (time_before(jiffies, timeout)) {
1147 cmd_status = mci_readl(host, CMD);
1148 if (!(cmd_status & SDMMC_CMD_START))
1151 dev_err(&slot->mmc->class_dev,
1152 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
1153 cmd, arg, cmd_status);
1156 static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
1158 struct dw_mci *host = slot->host;
1159 unsigned int clock = slot->clock;
1162 u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT;
1164 /* We must continue to set bit 28 in CMD until the change is complete */
1165 if (host->state == STATE_WAITING_CMD11_DONE)
1166 sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH;
1168 slot->mmc->actual_clock = 0;
1171 mci_writel(host, CLKENA, 0);
1172 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1173 } else if (clock != host->current_speed || force_clkinit) {
1174 div = host->bus_hz / clock;
1175 if (host->bus_hz % clock && host->bus_hz > clock)
1177 * move the + 1 after the divide to prevent
1178 * over-clocking the card.
1182 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
1184 if (clock != slot->__clk_old || force_clkinit)
1185 dev_info(&slot->mmc->class_dev,
1186 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
1187 slot->id, host->bus_hz, clock,
1188 div ? ((host->bus_hz / div) >> 1) :
1192 mci_writel(host, CLKENA, 0);
1193 mci_writel(host, CLKSRC, 0);
1196 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1198 /* set clock to desired speed */
1199 mci_writel(host, CLKDIV, div);
1202 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1204 /* enable clock; only low power if no SDIO */
1205 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
1206 if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags))
1207 clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
1208 mci_writel(host, CLKENA, clk_en_a);
1211 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1213 /* keep the last clock value that was requested from core */
1214 slot->__clk_old = clock;
1215 slot->mmc->actual_clock = div ? ((host->bus_hz / div) >> 1) :
1219 host->current_speed = clock;
1221 /* Set the current slot bus width */
1222 mci_writel(host, CTYPE, (slot->ctype << slot->id));
1225 static void __dw_mci_start_request(struct dw_mci *host,
1226 struct dw_mci_slot *slot,
1227 struct mmc_command *cmd)
1229 struct mmc_request *mrq;
1230 struct mmc_data *data;
1235 host->cur_slot = slot;
1238 host->pending_events = 0;
1239 host->completed_events = 0;
1240 host->cmd_status = 0;
1241 host->data_status = 0;
1242 host->dir_status = 0;
1246 mci_writel(host, TMOUT, 0xFFFFFFFF);
1247 mci_writel(host, BYTCNT, data->blksz*data->blocks);
1248 mci_writel(host, BLKSIZ, data->blksz);
1251 cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
1253 /* this is the first command, send the initialization clock */
1254 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
1255 cmdflags |= SDMMC_CMD_INIT;
1258 dw_mci_submit_data(host, data);
1259 wmb(); /* drain writebuffer */
1262 dw_mci_start_command(host, cmd, cmdflags);
1264 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
1265 unsigned long irqflags;
1268 * Databook says to fail after 2ms w/ no response, but evidence
1269 * shows that sometimes the cmd11 interrupt takes over 130ms.
1270 * We'll set to 500ms, plus an extra jiffy just in case jiffies
1271 * is just about to roll over.
1273 * We do this whole thing under spinlock and only if the
1274 * command hasn't already completed (indicating the the irq
1275 * already ran so we don't want the timeout).
1277 spin_lock_irqsave(&host->irq_lock, irqflags);
1278 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
1279 mod_timer(&host->cmd11_timer,
1280 jiffies + msecs_to_jiffies(500) + 1);
1281 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1284 host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd);
1287 static void dw_mci_start_request(struct dw_mci *host,
1288 struct dw_mci_slot *slot)
1290 struct mmc_request *mrq = slot->mrq;
1291 struct mmc_command *cmd;
1293 cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
1294 __dw_mci_start_request(host, slot, cmd);
1297 /* must be called with host->lock held */
1298 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
1299 struct mmc_request *mrq)
1301 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1306 if (host->state == STATE_WAITING_CMD11_DONE) {
1307 dev_warn(&slot->mmc->class_dev,
1308 "Voltage change didn't complete\n");
1310 * this case isn't expected to happen, so we can
1311 * either crash here or just try to continue on
1312 * in the closest possible state
1314 host->state = STATE_IDLE;
1317 if (host->state == STATE_IDLE) {
1318 host->state = STATE_SENDING_CMD;
1319 dw_mci_start_request(host, slot);
1321 list_add_tail(&slot->queue_node, &host->queue);
1325 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1327 struct dw_mci_slot *slot = mmc_priv(mmc);
1328 struct dw_mci *host = slot->host;
1333 * The check for card presence and queueing of the request must be
1334 * atomic, otherwise the card could be removed in between and the
1335 * request wouldn't fail until another card was inserted.
1338 if (!dw_mci_get_cd(mmc)) {
1339 mrq->cmd->error = -ENOMEDIUM;
1340 mmc_request_done(mmc, mrq);
1344 spin_lock_bh(&host->lock);
1346 dw_mci_queue_request(host, slot, mrq);
1348 spin_unlock_bh(&host->lock);
1351 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1353 struct dw_mci_slot *slot = mmc_priv(mmc);
1354 const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
1358 switch (ios->bus_width) {
1359 case MMC_BUS_WIDTH_4:
1360 slot->ctype = SDMMC_CTYPE_4BIT;
1362 case MMC_BUS_WIDTH_8:
1363 slot->ctype = SDMMC_CTYPE_8BIT;
1366 /* set default 1 bit mode */
1367 slot->ctype = SDMMC_CTYPE_1BIT;
1370 regs = mci_readl(slot->host, UHS_REG);
1373 if (ios->timing == MMC_TIMING_MMC_DDR52 ||
1374 ios->timing == MMC_TIMING_UHS_DDR50 ||
1375 ios->timing == MMC_TIMING_MMC_HS400)
1376 regs |= ((0x1 << slot->id) << 16);
1378 regs &= ~((0x1 << slot->id) << 16);
1380 mci_writel(slot->host, UHS_REG, regs);
1381 slot->host->timing = ios->timing;
1384 * Use mirror of ios->clock to prevent race with mmc
1385 * core ios update when finding the minimum.
1387 slot->clock = ios->clock;
1389 if (drv_data && drv_data->set_ios)
1390 drv_data->set_ios(slot->host, ios);
1392 switch (ios->power_mode) {
1394 if (!IS_ERR(mmc->supply.vmmc)) {
1395 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1398 dev_err(slot->host->dev,
1399 "failed to enable vmmc regulator\n");
1400 /*return, if failed turn on vmmc*/
1404 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
1405 regs = mci_readl(slot->host, PWREN);
1406 regs |= (1 << slot->id);
1407 mci_writel(slot->host, PWREN, regs);
1410 if (!slot->host->vqmmc_enabled) {
1411 if (!IS_ERR(mmc->supply.vqmmc)) {
1412 ret = regulator_enable(mmc->supply.vqmmc);
1414 dev_err(slot->host->dev,
1415 "failed to enable vqmmc\n");
1417 slot->host->vqmmc_enabled = true;
1420 /* Keep track so we don't reset again */
1421 slot->host->vqmmc_enabled = true;
1424 /* Reset our state machine after powering on */
1425 dw_mci_ctrl_reset(slot->host,
1426 SDMMC_CTRL_ALL_RESET_FLAGS);
1429 /* Adjust clock / bus width after power is up */
1430 dw_mci_setup_bus(slot, false);
1434 /* Turn clock off before power goes down */
1435 dw_mci_setup_bus(slot, false);
1437 if (!IS_ERR(mmc->supply.vmmc))
1438 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1440 if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled)
1441 regulator_disable(mmc->supply.vqmmc);
1442 slot->host->vqmmc_enabled = false;
1444 regs = mci_readl(slot->host, PWREN);
1445 regs &= ~(1 << slot->id);
1446 mci_writel(slot->host, PWREN, regs);
1452 if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0)
1453 slot->host->state = STATE_IDLE;
1456 static int dw_mci_card_busy(struct mmc_host *mmc)
1458 struct dw_mci_slot *slot = mmc_priv(mmc);
1462 * Check the busy bit which is low when DAT[3:0]
1463 * (the data lines) are 0000
1465 status = mci_readl(slot->host, STATUS);
1467 return !!(status & SDMMC_STATUS_BUSY);
1470 static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1472 struct dw_mci_slot *slot = mmc_priv(mmc);
1473 struct dw_mci *host = slot->host;
1474 const struct dw_mci_drv_data *drv_data = host->drv_data;
1476 u32 v18 = SDMMC_UHS_18V << slot->id;
1479 if (drv_data && drv_data->switch_voltage)
1480 return drv_data->switch_voltage(mmc, ios);
1483 * Program the voltage. Note that some instances of dw_mmc may use
1484 * the UHS_REG for this. For other instances (like exynos) the UHS_REG
1485 * does no harm but you need to set the regulator directly. Try both.
1487 uhs = mci_readl(host, UHS_REG);
1488 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1493 if (!IS_ERR(mmc->supply.vqmmc)) {
1494 ret = mmc_regulator_set_vqmmc(mmc, ios);
1497 dev_dbg(&mmc->class_dev,
1498 "Regulator set error %d - %s V\n",
1499 ret, uhs & v18 ? "1.8" : "3.3");
1503 mci_writel(host, UHS_REG, uhs);
1508 static int dw_mci_get_ro(struct mmc_host *mmc)
1511 struct dw_mci_slot *slot = mmc_priv(mmc);
1512 int gpio_ro = mmc_gpio_get_ro(mmc);
1514 /* Use platform get_ro function, else try on board write protect */
1516 read_only = gpio_ro;
1519 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
1521 dev_dbg(&mmc->class_dev, "card is %s\n",
1522 read_only ? "read-only" : "read-write");
1527 static int dw_mci_get_cd(struct mmc_host *mmc)
1530 struct dw_mci_slot *slot = mmc_priv(mmc);
1531 struct dw_mci *host = slot->host;
1532 int gpio_cd = mmc_gpio_get_cd(mmc);
1534 /* Use platform get_cd function, else try onboard card detect */
1535 if ((mmc->caps & MMC_CAP_NEEDS_POLL) || !mmc_card_is_removable(mmc))
1537 else if (gpio_cd >= 0)
1540 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
1543 spin_lock_bh(&host->lock);
1545 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1546 dev_dbg(&mmc->class_dev, "card is present\n");
1548 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1549 dev_dbg(&mmc->class_dev, "card is not present\n");
1551 spin_unlock_bh(&host->lock);
1556 static void dw_mci_hw_reset(struct mmc_host *mmc)
1558 struct dw_mci_slot *slot = mmc_priv(mmc);
1559 struct dw_mci *host = slot->host;
1562 if (host->use_dma == TRANS_MODE_IDMAC)
1563 dw_mci_idmac_reset(host);
1565 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET |
1566 SDMMC_CTRL_FIFO_RESET))
1570 * According to eMMC spec, card reset procedure:
1571 * tRstW >= 1us: RST_n pulse width
1572 * tRSCA >= 200us: RST_n to Command time
1573 * tRSTH >= 1us: RST_n high period
1575 reset = mci_readl(host, RST_N);
1576 reset &= ~(SDMMC_RST_HWACTIVE << slot->id);
1577 mci_writel(host, RST_N, reset);
1579 reset |= SDMMC_RST_HWACTIVE << slot->id;
1580 mci_writel(host, RST_N, reset);
1581 usleep_range(200, 300);
1584 static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card)
1586 struct dw_mci_slot *slot = mmc_priv(mmc);
1587 struct dw_mci *host = slot->host;
1590 * Low power mode will stop the card clock when idle. According to the
1591 * description of the CLKENA register we should disable low power mode
1592 * for SDIO cards if we need SDIO interrupts to work.
1594 if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1595 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
1599 clk_en_a_old = mci_readl(host, CLKENA);
1601 if (card->type == MMC_TYPE_SDIO ||
1602 card->type == MMC_TYPE_SD_COMBO) {
1603 set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1604 clk_en_a = clk_en_a_old & ~clken_low_pwr;
1606 clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1607 clk_en_a = clk_en_a_old | clken_low_pwr;
1610 if (clk_en_a != clk_en_a_old) {
1611 mci_writel(host, CLKENA, clk_en_a);
1612 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
1613 SDMMC_CMD_PRV_DAT_WAIT, 0);
1618 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
1620 struct dw_mci_slot *slot = mmc_priv(mmc);
1621 struct dw_mci *host = slot->host;
1622 unsigned long irqflags;
1625 spin_lock_irqsave(&host->irq_lock, irqflags);
1627 /* Enable/disable Slot Specific SDIO interrupt */
1628 int_mask = mci_readl(host, INTMASK);
1630 int_mask |= SDMMC_INT_SDIO(slot->sdio_id);
1632 int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id);
1633 mci_writel(host, INTMASK, int_mask);
1635 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1638 static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1640 struct dw_mci_slot *slot = mmc_priv(mmc);
1641 struct dw_mci *host = slot->host;
1642 const struct dw_mci_drv_data *drv_data = host->drv_data;
1645 if (drv_data && drv_data->execute_tuning)
1646 err = drv_data->execute_tuning(slot, opcode);
1650 static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc,
1651 struct mmc_ios *ios)
1653 struct dw_mci_slot *slot = mmc_priv(mmc);
1654 struct dw_mci *host = slot->host;
1655 const struct dw_mci_drv_data *drv_data = host->drv_data;
1657 if (drv_data && drv_data->prepare_hs400_tuning)
1658 return drv_data->prepare_hs400_tuning(host, ios);
1663 static const struct mmc_host_ops dw_mci_ops = {
1664 .request = dw_mci_request,
1665 .pre_req = dw_mci_pre_req,
1666 .post_req = dw_mci_post_req,
1667 .set_ios = dw_mci_set_ios,
1668 .get_ro = dw_mci_get_ro,
1669 .get_cd = dw_mci_get_cd,
1670 .hw_reset = dw_mci_hw_reset,
1671 .enable_sdio_irq = dw_mci_enable_sdio_irq,
1672 .execute_tuning = dw_mci_execute_tuning,
1673 .card_busy = dw_mci_card_busy,
1674 .start_signal_voltage_switch = dw_mci_switch_voltage,
1675 .init_card = dw_mci_init_card,
1676 .prepare_hs400_tuning = dw_mci_prepare_hs400_tuning,
1679 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
1680 __releases(&host->lock)
1681 __acquires(&host->lock)
1683 struct dw_mci_slot *slot;
1684 struct mmc_host *prev_mmc = host->cur_slot->mmc;
1686 WARN_ON(host->cmd || host->data);
1688 host->cur_slot->mrq = NULL;
1690 if (!list_empty(&host->queue)) {
1691 slot = list_entry(host->queue.next,
1692 struct dw_mci_slot, queue_node);
1693 list_del(&slot->queue_node);
1694 dev_vdbg(host->dev, "list not empty: %s is next\n",
1695 mmc_hostname(slot->mmc));
1696 host->state = STATE_SENDING_CMD;
1697 dw_mci_start_request(host, slot);
1699 dev_vdbg(host->dev, "list empty\n");
1701 if (host->state == STATE_SENDING_CMD11)
1702 host->state = STATE_WAITING_CMD11_DONE;
1704 host->state = STATE_IDLE;
1707 spin_unlock(&host->lock);
1708 mmc_request_done(prev_mmc, mrq);
1709 spin_lock(&host->lock);
1712 static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
1714 u32 status = host->cmd_status;
1716 host->cmd_status = 0;
1718 /* Read the response from the card (up to 16 bytes) */
1719 if (cmd->flags & MMC_RSP_PRESENT) {
1720 if (cmd->flags & MMC_RSP_136) {
1721 cmd->resp[3] = mci_readl(host, RESP0);
1722 cmd->resp[2] = mci_readl(host, RESP1);
1723 cmd->resp[1] = mci_readl(host, RESP2);
1724 cmd->resp[0] = mci_readl(host, RESP3);
1726 cmd->resp[0] = mci_readl(host, RESP0);
1733 if (status & SDMMC_INT_RTO)
1734 cmd->error = -ETIMEDOUT;
1735 else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
1736 cmd->error = -EILSEQ;
1737 else if (status & SDMMC_INT_RESP_ERR)
1745 static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data)
1747 u32 status = host->data_status;
1749 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1750 if (status & SDMMC_INT_DRTO) {
1751 data->error = -ETIMEDOUT;
1752 } else if (status & SDMMC_INT_DCRC) {
1753 data->error = -EILSEQ;
1754 } else if (status & SDMMC_INT_EBE) {
1755 if (host->dir_status ==
1756 DW_MCI_SEND_STATUS) {
1758 * No data CRC status was returned.
1759 * The number of bytes transferred
1760 * will be exaggerated in PIO mode.
1762 data->bytes_xfered = 0;
1763 data->error = -ETIMEDOUT;
1764 } else if (host->dir_status ==
1765 DW_MCI_RECV_STATUS) {
1766 data->error = -EILSEQ;
1769 /* SDMMC_INT_SBE is included */
1770 data->error = -EILSEQ;
1773 dev_dbg(host->dev, "data error, status 0x%08x\n", status);
1776 * After an error, there may be data lingering
1781 data->bytes_xfered = data->blocks * data->blksz;
1788 static void dw_mci_set_drto(struct dw_mci *host)
1790 unsigned int drto_clks;
1791 unsigned int drto_ms;
1793 drto_clks = mci_readl(host, TMOUT) >> 8;
1794 drto_ms = DIV_ROUND_UP(drto_clks, host->bus_hz / 1000);
1796 /* add a bit spare time */
1799 mod_timer(&host->dto_timer, jiffies + msecs_to_jiffies(drto_ms));
1802 static void dw_mci_tasklet_func(unsigned long priv)
1804 struct dw_mci *host = (struct dw_mci *)priv;
1805 struct mmc_data *data;
1806 struct mmc_command *cmd;
1807 struct mmc_request *mrq;
1808 enum dw_mci_state state;
1809 enum dw_mci_state prev_state;
1812 spin_lock(&host->lock);
1814 state = host->state;
1823 case STATE_WAITING_CMD11_DONE:
1826 case STATE_SENDING_CMD11:
1827 case STATE_SENDING_CMD:
1828 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1829 &host->pending_events))
1834 set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
1835 err = dw_mci_command_complete(host, cmd);
1836 if (cmd == mrq->sbc && !err) {
1837 prev_state = state = STATE_SENDING_CMD;
1838 __dw_mci_start_request(host, host->cur_slot,
1843 if (cmd->data && err) {
1845 * During UHS tuning sequence, sending the stop
1846 * command after the response CRC error would
1847 * throw the system into a confused state
1848 * causing all future tuning phases to report
1851 * In such case controller will move into a data
1852 * transfer state after a response error or
1853 * response CRC error. Let's let that finish
1854 * before trying to send a stop, so we'll go to
1855 * STATE_SENDING_DATA.
1857 * Although letting the data transfer take place
1858 * will waste a bit of time (we already know
1859 * the command was bad), it can't cause any
1860 * errors since it's possible it would have
1861 * taken place anyway if this tasklet got
1862 * delayed. Allowing the transfer to take place
1863 * avoids races and keeps things simple.
1865 if (err != -ETIMEDOUT &&
1866 host->dir_status == DW_MCI_RECV_STATUS) {
1867 state = STATE_SENDING_DATA;
1871 send_stop_abort(host, data);
1872 dw_mci_stop_dma(host);
1873 state = STATE_SENDING_STOP;
1877 if (!cmd->data || err) {
1878 dw_mci_request_end(host, mrq);
1882 prev_state = state = STATE_SENDING_DATA;
1885 case STATE_SENDING_DATA:
1887 * We could get a data error and never a transfer
1888 * complete so we'd better check for it here.
1890 * Note that we don't really care if we also got a
1891 * transfer complete; stopping the DMA and sending an
1894 if (test_and_clear_bit(EVENT_DATA_ERROR,
1895 &host->pending_events)) {
1896 if (!(host->data_status & (SDMMC_INT_DRTO |
1898 send_stop_abort(host, data);
1899 dw_mci_stop_dma(host);
1900 state = STATE_DATA_ERROR;
1904 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1905 &host->pending_events)) {
1907 * If all data-related interrupts don't come
1908 * within the given time in reading data state.
1910 if (host->dir_status == DW_MCI_RECV_STATUS)
1911 dw_mci_set_drto(host);
1915 set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
1918 * Handle an EVENT_DATA_ERROR that might have shown up
1919 * before the transfer completed. This might not have
1920 * been caught by the check above because the interrupt
1921 * could have gone off between the previous check and
1922 * the check for transfer complete.
1924 * Technically this ought not be needed assuming we
1925 * get a DATA_COMPLETE eventually (we'll notice the
1926 * error and end the request), but it shouldn't hurt.
1928 * This has the advantage of sending the stop command.
1930 if (test_and_clear_bit(EVENT_DATA_ERROR,
1931 &host->pending_events)) {
1932 if (!(host->data_status & (SDMMC_INT_DRTO |
1934 send_stop_abort(host, data);
1935 dw_mci_stop_dma(host);
1936 state = STATE_DATA_ERROR;
1939 prev_state = state = STATE_DATA_BUSY;
1943 case STATE_DATA_BUSY:
1944 if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
1945 &host->pending_events)) {
1947 * If data error interrupt comes but data over
1948 * interrupt doesn't come within the given time.
1949 * in reading data state.
1951 if (host->dir_status == DW_MCI_RECV_STATUS)
1952 dw_mci_set_drto(host);
1957 set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
1958 err = dw_mci_data_complete(host, data);
1961 if (!data->stop || mrq->sbc) {
1962 if (mrq->sbc && data->stop)
1963 data->stop->error = 0;
1964 dw_mci_request_end(host, mrq);
1968 /* stop command for open-ended transfer*/
1970 send_stop_abort(host, data);
1973 * If we don't have a command complete now we'll
1974 * never get one since we just reset everything;
1975 * better end the request.
1977 * If we do have a command complete we'll fall
1978 * through to the SENDING_STOP command and
1979 * everything will be peachy keen.
1981 if (!test_bit(EVENT_CMD_COMPLETE,
1982 &host->pending_events)) {
1984 dw_mci_request_end(host, mrq);
1990 * If err has non-zero,
1991 * stop-abort command has been already issued.
1993 prev_state = state = STATE_SENDING_STOP;
1997 case STATE_SENDING_STOP:
1998 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1999 &host->pending_events))
2002 /* CMD error in data command */
2003 if (mrq->cmd->error && mrq->data)
2009 if (!mrq->sbc && mrq->stop)
2010 dw_mci_command_complete(host, mrq->stop);
2012 host->cmd_status = 0;
2014 dw_mci_request_end(host, mrq);
2017 case STATE_DATA_ERROR:
2018 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
2019 &host->pending_events))
2022 state = STATE_DATA_BUSY;
2025 } while (state != prev_state);
2027 host->state = state;
2029 spin_unlock(&host->lock);
2033 /* push final bytes to part_buf, only use during push */
2034 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
2036 memcpy((void *)&host->part_buf, buf, cnt);
2037 host->part_buf_count = cnt;
2040 /* append bytes to part_buf, only use during push */
2041 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
2043 cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
2044 memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
2045 host->part_buf_count += cnt;
2049 /* pull first bytes from part_buf, only use during pull */
2050 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
2052 cnt = min_t(int, cnt, host->part_buf_count);
2054 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
2056 host->part_buf_count -= cnt;
2057 host->part_buf_start += cnt;
2062 /* pull final bytes from the part_buf, assuming it's just been filled */
2063 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
2065 memcpy(buf, &host->part_buf, cnt);
2066 host->part_buf_start = cnt;
2067 host->part_buf_count = (1 << host->data_shift) - cnt;
2070 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
2072 struct mmc_data *data = host->data;
2075 /* try and push anything in the part_buf */
2076 if (unlikely(host->part_buf_count)) {
2077 int len = dw_mci_push_part_bytes(host, buf, cnt);
2081 if (host->part_buf_count == 2) {
2082 mci_fifo_writew(host->fifo_reg, host->part_buf16);
2083 host->part_buf_count = 0;
2086 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2087 if (unlikely((unsigned long)buf & 0x1)) {
2089 u16 aligned_buf[64];
2090 int len = min(cnt & -2, (int)sizeof(aligned_buf));
2091 int items = len >> 1;
2093 /* memcpy from input buffer into aligned buffer */
2094 memcpy(aligned_buf, buf, len);
2097 /* push data from aligned buffer into fifo */
2098 for (i = 0; i < items; ++i)
2099 mci_fifo_writew(host->fifo_reg, aligned_buf[i]);
2106 for (; cnt >= 2; cnt -= 2)
2107 mci_fifo_writew(host->fifo_reg, *pdata++);
2110 /* put anything remaining in the part_buf */
2112 dw_mci_set_part_bytes(host, buf, cnt);
2113 /* Push data if we have reached the expected data length */
2114 if ((data->bytes_xfered + init_cnt) ==
2115 (data->blksz * data->blocks))
2116 mci_fifo_writew(host->fifo_reg, host->part_buf16);
2120 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
2122 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2123 if (unlikely((unsigned long)buf & 0x1)) {
2125 /* pull data from fifo into aligned buffer */
2126 u16 aligned_buf[64];
2127 int len = min(cnt & -2, (int)sizeof(aligned_buf));
2128 int items = len >> 1;
2131 for (i = 0; i < items; ++i)
2132 aligned_buf[i] = mci_fifo_readw(host->fifo_reg);
2133 /* memcpy from aligned buffer into output buffer */
2134 memcpy(buf, aligned_buf, len);
2143 for (; cnt >= 2; cnt -= 2)
2144 *pdata++ = mci_fifo_readw(host->fifo_reg);
2148 host->part_buf16 = mci_fifo_readw(host->fifo_reg);
2149 dw_mci_pull_final_bytes(host, buf, cnt);
2153 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
2155 struct mmc_data *data = host->data;
2158 /* try and push anything in the part_buf */
2159 if (unlikely(host->part_buf_count)) {
2160 int len = dw_mci_push_part_bytes(host, buf, cnt);
2164 if (host->part_buf_count == 4) {
2165 mci_fifo_writel(host->fifo_reg, host->part_buf32);
2166 host->part_buf_count = 0;
2169 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2170 if (unlikely((unsigned long)buf & 0x3)) {
2172 u32 aligned_buf[32];
2173 int len = min(cnt & -4, (int)sizeof(aligned_buf));
2174 int items = len >> 2;
2176 /* memcpy from input buffer into aligned buffer */
2177 memcpy(aligned_buf, buf, len);
2180 /* push data from aligned buffer into fifo */
2181 for (i = 0; i < items; ++i)
2182 mci_fifo_writel(host->fifo_reg, aligned_buf[i]);
2189 for (; cnt >= 4; cnt -= 4)
2190 mci_fifo_writel(host->fifo_reg, *pdata++);
2193 /* put anything remaining in the part_buf */
2195 dw_mci_set_part_bytes(host, buf, cnt);
2196 /* Push data if we have reached the expected data length */
2197 if ((data->bytes_xfered + init_cnt) ==
2198 (data->blksz * data->blocks))
2199 mci_fifo_writel(host->fifo_reg, host->part_buf32);
2203 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
2205 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2206 if (unlikely((unsigned long)buf & 0x3)) {
2208 /* pull data from fifo into aligned buffer */
2209 u32 aligned_buf[32];
2210 int len = min(cnt & -4, (int)sizeof(aligned_buf));
2211 int items = len >> 2;
2214 for (i = 0; i < items; ++i)
2215 aligned_buf[i] = mci_fifo_readl(host->fifo_reg);
2216 /* memcpy from aligned buffer into output buffer */
2217 memcpy(buf, aligned_buf, len);
2226 for (; cnt >= 4; cnt -= 4)
2227 *pdata++ = mci_fifo_readl(host->fifo_reg);
2231 host->part_buf32 = mci_fifo_readl(host->fifo_reg);
2232 dw_mci_pull_final_bytes(host, buf, cnt);
2236 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
2238 struct mmc_data *data = host->data;
2241 /* try and push anything in the part_buf */
2242 if (unlikely(host->part_buf_count)) {
2243 int len = dw_mci_push_part_bytes(host, buf, cnt);
2248 if (host->part_buf_count == 8) {
2249 mci_fifo_writeq(host->fifo_reg, host->part_buf);
2250 host->part_buf_count = 0;
2253 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2254 if (unlikely((unsigned long)buf & 0x7)) {
2256 u64 aligned_buf[16];
2257 int len = min(cnt & -8, (int)sizeof(aligned_buf));
2258 int items = len >> 3;
2260 /* memcpy from input buffer into aligned buffer */
2261 memcpy(aligned_buf, buf, len);
2264 /* push data from aligned buffer into fifo */
2265 for (i = 0; i < items; ++i)
2266 mci_fifo_writeq(host->fifo_reg, aligned_buf[i]);
2273 for (; cnt >= 8; cnt -= 8)
2274 mci_fifo_writeq(host->fifo_reg, *pdata++);
2277 /* put anything remaining in the part_buf */
2279 dw_mci_set_part_bytes(host, buf, cnt);
2280 /* Push data if we have reached the expected data length */
2281 if ((data->bytes_xfered + init_cnt) ==
2282 (data->blksz * data->blocks))
2283 mci_fifo_writeq(host->fifo_reg, host->part_buf);
2287 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
2289 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2290 if (unlikely((unsigned long)buf & 0x7)) {
2292 /* pull data from fifo into aligned buffer */
2293 u64 aligned_buf[16];
2294 int len = min(cnt & -8, (int)sizeof(aligned_buf));
2295 int items = len >> 3;
2298 for (i = 0; i < items; ++i)
2299 aligned_buf[i] = mci_fifo_readq(host->fifo_reg);
2301 /* memcpy from aligned buffer into output buffer */
2302 memcpy(buf, aligned_buf, len);
2311 for (; cnt >= 8; cnt -= 8)
2312 *pdata++ = mci_fifo_readq(host->fifo_reg);
2316 host->part_buf = mci_fifo_readq(host->fifo_reg);
2317 dw_mci_pull_final_bytes(host, buf, cnt);
2321 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
2325 /* get remaining partial bytes */
2326 len = dw_mci_pull_part_bytes(host, buf, cnt);
2327 if (unlikely(len == cnt))
2332 /* get the rest of the data */
2333 host->pull_data(host, buf, cnt);
2336 static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
2338 struct sg_mapping_iter *sg_miter = &host->sg_miter;
2340 unsigned int offset;
2341 struct mmc_data *data = host->data;
2342 int shift = host->data_shift;
2345 unsigned int remain, fcnt;
2348 if (!sg_miter_next(sg_miter))
2351 host->sg = sg_miter->piter.sg;
2352 buf = sg_miter->addr;
2353 remain = sg_miter->length;
2357 fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
2358 << shift) + host->part_buf_count;
2359 len = min(remain, fcnt);
2362 dw_mci_pull_data(host, (void *)(buf + offset), len);
2363 data->bytes_xfered += len;
2368 sg_miter->consumed = offset;
2369 status = mci_readl(host, MINTSTS);
2370 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2371 /* if the RXDR is ready read again */
2372 } while ((status & SDMMC_INT_RXDR) ||
2373 (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
2376 if (!sg_miter_next(sg_miter))
2378 sg_miter->consumed = 0;
2380 sg_miter_stop(sg_miter);
2384 sg_miter_stop(sg_miter);
2386 smp_wmb(); /* drain writebuffer */
2387 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2390 static void dw_mci_write_data_pio(struct dw_mci *host)
2392 struct sg_mapping_iter *sg_miter = &host->sg_miter;
2394 unsigned int offset;
2395 struct mmc_data *data = host->data;
2396 int shift = host->data_shift;
2399 unsigned int fifo_depth = host->fifo_depth;
2400 unsigned int remain, fcnt;
2403 if (!sg_miter_next(sg_miter))
2406 host->sg = sg_miter->piter.sg;
2407 buf = sg_miter->addr;
2408 remain = sg_miter->length;
2412 fcnt = ((fifo_depth -
2413 SDMMC_GET_FCNT(mci_readl(host, STATUS)))
2414 << shift) - host->part_buf_count;
2415 len = min(remain, fcnt);
2418 host->push_data(host, (void *)(buf + offset), len);
2419 data->bytes_xfered += len;
2424 sg_miter->consumed = offset;
2425 status = mci_readl(host, MINTSTS);
2426 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2427 } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
2430 if (!sg_miter_next(sg_miter))
2432 sg_miter->consumed = 0;
2434 sg_miter_stop(sg_miter);
2438 sg_miter_stop(sg_miter);
2440 smp_wmb(); /* drain writebuffer */
2441 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2444 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
2446 if (!host->cmd_status)
2447 host->cmd_status = status;
2449 smp_wmb(); /* drain writebuffer */
2451 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2452 tasklet_schedule(&host->tasklet);
2455 static void dw_mci_handle_cd(struct dw_mci *host)
2459 for (i = 0; i < host->num_slots; i++) {
2460 struct dw_mci_slot *slot = host->slot[i];
2465 if (slot->mmc->ops->card_event)
2466 slot->mmc->ops->card_event(slot->mmc);
2467 mmc_detect_change(slot->mmc,
2468 msecs_to_jiffies(host->pdata->detect_delay_ms));
2472 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
2474 struct dw_mci *host = dev_id;
2478 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
2481 /* Check volt switch first, since it can look like an error */
2482 if ((host->state == STATE_SENDING_CMD11) &&
2483 (pending & SDMMC_INT_VOLT_SWITCH)) {
2484 unsigned long irqflags;
2486 mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH);
2487 pending &= ~SDMMC_INT_VOLT_SWITCH;
2490 * Hold the lock; we know cmd11_timer can't be kicked
2491 * off after the lock is released, so safe to delete.
2493 spin_lock_irqsave(&host->irq_lock, irqflags);
2494 dw_mci_cmd_interrupt(host, pending);
2495 spin_unlock_irqrestore(&host->irq_lock, irqflags);
2497 del_timer(&host->cmd11_timer);
2500 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
2501 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
2502 host->cmd_status = pending;
2503 smp_wmb(); /* drain writebuffer */
2504 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2507 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
2508 /* if there is an error report DATA_ERROR */
2509 mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
2510 host->data_status = pending;
2511 smp_wmb(); /* drain writebuffer */
2512 set_bit(EVENT_DATA_ERROR, &host->pending_events);
2513 tasklet_schedule(&host->tasklet);
2516 if (pending & SDMMC_INT_DATA_OVER) {
2517 del_timer(&host->dto_timer);
2519 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
2520 if (!host->data_status)
2521 host->data_status = pending;
2522 smp_wmb(); /* drain writebuffer */
2523 if (host->dir_status == DW_MCI_RECV_STATUS) {
2524 if (host->sg != NULL)
2525 dw_mci_read_data_pio(host, true);
2527 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2528 tasklet_schedule(&host->tasklet);
2531 if (pending & SDMMC_INT_RXDR) {
2532 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2533 if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
2534 dw_mci_read_data_pio(host, false);
2537 if (pending & SDMMC_INT_TXDR) {
2538 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2539 if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
2540 dw_mci_write_data_pio(host);
2543 if (pending & SDMMC_INT_CMD_DONE) {
2544 mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
2545 dw_mci_cmd_interrupt(host, pending);
2548 if (pending & SDMMC_INT_CD) {
2549 mci_writel(host, RINTSTS, SDMMC_INT_CD);
2550 dw_mci_handle_cd(host);
2553 /* Handle SDIO Interrupts */
2554 for (i = 0; i < host->num_slots; i++) {
2555 struct dw_mci_slot *slot = host->slot[i];
2560 if (pending & SDMMC_INT_SDIO(slot->sdio_id)) {
2561 mci_writel(host, RINTSTS,
2562 SDMMC_INT_SDIO(slot->sdio_id));
2563 mmc_signal_sdio_irq(slot->mmc);
2569 if (host->use_dma != TRANS_MODE_IDMAC)
2572 /* Handle IDMA interrupts */
2573 if (host->dma_64bit_address == 1) {
2574 pending = mci_readl(host, IDSTS64);
2575 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2576 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI |
2577 SDMMC_IDMAC_INT_RI);
2578 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI);
2579 if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
2580 host->dma_ops->complete((void *)host);
2583 pending = mci_readl(host, IDSTS);
2584 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2585 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI |
2586 SDMMC_IDMAC_INT_RI);
2587 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
2588 if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
2589 host->dma_ops->complete((void *)host);
2596 static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
2598 struct mmc_host *mmc;
2599 struct dw_mci_slot *slot;
2600 const struct dw_mci_drv_data *drv_data = host->drv_data;
2604 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
2608 slot = mmc_priv(mmc);
2610 slot->sdio_id = host->sdio_id0 + id;
2613 host->slot[id] = slot;
2615 mmc->ops = &dw_mci_ops;
2616 if (device_property_read_u32_array(host->dev, "clock-freq-min-max",
2618 mmc->f_min = DW_MCI_FREQ_MIN;
2619 mmc->f_max = DW_MCI_FREQ_MAX;
2621 mmc->f_min = freq[0];
2622 mmc->f_max = freq[1];
2625 /*if there are external regulators, get them*/
2626 ret = mmc_regulator_get_supply(mmc);
2627 if (ret == -EPROBE_DEFER)
2628 goto err_host_allocated;
2630 if (!mmc->ocr_avail)
2631 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
2633 if (host->pdata->caps)
2634 mmc->caps = host->pdata->caps;
2637 * Support MMC_CAP_ERASE by default.
2638 * It needs to use trim/discard/erase commands.
2640 mmc->caps |= MMC_CAP_ERASE;
2642 if (host->pdata->pm_caps)
2643 mmc->pm_caps = host->pdata->pm_caps;
2645 if (host->dev->of_node) {
2646 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
2650 ctrl_id = to_platform_device(host->dev)->id;
2652 if (drv_data && drv_data->caps)
2653 mmc->caps |= drv_data->caps[ctrl_id];
2655 if (host->pdata->caps2)
2656 mmc->caps2 = host->pdata->caps2;
2658 ret = mmc_of_parse(mmc);
2660 goto err_host_allocated;
2662 /* Useful defaults if platform data is unset. */
2663 if (host->use_dma == TRANS_MODE_IDMAC) {
2664 mmc->max_segs = host->ring_size;
2665 mmc->max_blk_size = 65535;
2666 mmc->max_seg_size = 0x1000;
2667 mmc->max_req_size = mmc->max_seg_size * host->ring_size;
2668 mmc->max_blk_count = mmc->max_req_size / 512;
2669 } else if (host->use_dma == TRANS_MODE_EDMAC) {
2671 mmc->max_blk_size = 65535;
2672 mmc->max_blk_count = 65535;
2674 mmc->max_blk_size * mmc->max_blk_count;
2675 mmc->max_seg_size = mmc->max_req_size;
2677 /* TRANS_MODE_PIO */
2679 mmc->max_blk_size = 65535; /* BLKSIZ is 16 bits */
2680 mmc->max_blk_count = 512;
2681 mmc->max_req_size = mmc->max_blk_size *
2683 mmc->max_seg_size = mmc->max_req_size;
2688 ret = mmc_add_host(mmc);
2690 goto err_host_allocated;
2692 #if defined(CONFIG_DEBUG_FS)
2693 dw_mci_init_debugfs(slot);
2703 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
2705 /* Debugfs stuff is cleaned up by mmc core */
2706 mmc_remove_host(slot->mmc);
2707 slot->host->slot[id] = NULL;
2708 mmc_free_host(slot->mmc);
2711 static void dw_mci_init_dma(struct dw_mci *host)
2714 struct device *dev = host->dev;
2717 * Check tansfer mode from HCON[17:16]
2718 * Clear the ambiguous description of dw_mmc databook:
2719 * 2b'00: No DMA Interface -> Actually means using Internal DMA block
2720 * 2b'01: DesignWare DMA Interface -> Synopsys DW-DMA block
2721 * 2b'10: Generic DMA Interface -> non-Synopsys generic DMA block
2722 * 2b'11: Non DW DMA Interface -> pio only
2723 * Compared to DesignWare DMA Interface, Generic DMA Interface has a
2724 * simpler request/acknowledge handshake mechanism and both of them
2725 * are regarded as external dma master for dw_mmc.
2727 host->use_dma = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON));
2728 if (host->use_dma == DMA_INTERFACE_IDMA) {
2729 host->use_dma = TRANS_MODE_IDMAC;
2730 } else if (host->use_dma == DMA_INTERFACE_DWDMA ||
2731 host->use_dma == DMA_INTERFACE_GDMA) {
2732 host->use_dma = TRANS_MODE_EDMAC;
2737 /* Determine which DMA interface to use */
2738 if (host->use_dma == TRANS_MODE_IDMAC) {
2740 * Check ADDR_CONFIG bit in HCON to find
2741 * IDMAC address bus width
2743 addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON));
2745 if (addr_config == 1) {
2746 /* host supports IDMAC in 64-bit address mode */
2747 host->dma_64bit_address = 1;
2749 "IDMAC supports 64-bit address mode.\n");
2750 if (!dma_set_mask(host->dev, DMA_BIT_MASK(64)))
2751 dma_set_coherent_mask(host->dev,
2754 /* host supports IDMAC in 32-bit address mode */
2755 host->dma_64bit_address = 0;
2757 "IDMAC supports 32-bit address mode.\n");
2760 /* Alloc memory for sg translation */
2761 host->sg_cpu = dmam_alloc_coherent(host->dev,
2763 &host->sg_dma, GFP_KERNEL);
2764 if (!host->sg_cpu) {
2766 "%s: could not alloc DMA memory\n",
2771 host->dma_ops = &dw_mci_idmac_ops;
2772 dev_info(host->dev, "Using internal DMA controller.\n");
2774 /* TRANS_MODE_EDMAC: check dma bindings again */
2775 if ((device_property_read_string_array(dev, "dma-names",
2777 !device_property_present(dev, "dmas")) {
2780 host->dma_ops = &dw_mci_edmac_ops;
2781 dev_info(host->dev, "Using external DMA controller.\n");
2784 if (host->dma_ops->init && host->dma_ops->start &&
2785 host->dma_ops->stop && host->dma_ops->cleanup) {
2786 if (host->dma_ops->init(host)) {
2787 dev_err(host->dev, "%s: Unable to initialize DMA Controller.\n",
2792 dev_err(host->dev, "DMA initialization not found.\n");
2799 dev_info(host->dev, "Using PIO mode.\n");
2800 host->use_dma = TRANS_MODE_PIO;
2803 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
2805 unsigned long timeout = jiffies + msecs_to_jiffies(500);
2808 ctrl = mci_readl(host, CTRL);
2810 mci_writel(host, CTRL, ctrl);
2812 /* wait till resets clear */
2814 ctrl = mci_readl(host, CTRL);
2815 if (!(ctrl & reset))
2817 } while (time_before(jiffies, timeout));
2820 "Timeout resetting block (ctrl reset %#x)\n",
2826 static bool dw_mci_reset(struct dw_mci *host)
2828 u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET;
2832 * Reseting generates a block interrupt, hence setting
2833 * the scatter-gather pointer to NULL.
2836 sg_miter_stop(&host->sg_miter);
2841 flags |= SDMMC_CTRL_DMA_RESET;
2843 if (dw_mci_ctrl_reset(host, flags)) {
2845 * In all cases we clear the RAWINTS register to clear any
2848 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2850 /* if using dma we wait for dma_req to clear */
2851 if (host->use_dma) {
2852 unsigned long timeout = jiffies + msecs_to_jiffies(500);
2856 status = mci_readl(host, STATUS);
2857 if (!(status & SDMMC_STATUS_DMA_REQ))
2860 } while (time_before(jiffies, timeout));
2862 if (status & SDMMC_STATUS_DMA_REQ) {
2864 "%s: Timeout waiting for dma_req to clear during reset\n",
2869 /* when using DMA next we reset the fifo again */
2870 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET))
2874 /* if the controller reset bit did clear, then set clock regs */
2875 if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) {
2877 "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n",
2883 if (host->use_dma == TRANS_MODE_IDMAC)
2884 /* It is also required that we reinit idmac */
2885 dw_mci_idmac_init(host);
2890 /* After a CTRL reset we need to have CIU set clock registers */
2891 mci_send_cmd(host->cur_slot, SDMMC_CMD_UPD_CLK, 0);
2896 static void dw_mci_cmd11_timer(unsigned long arg)
2898 struct dw_mci *host = (struct dw_mci *)arg;
2900 if (host->state != STATE_SENDING_CMD11) {
2901 dev_warn(host->dev, "Unexpected CMD11 timeout\n");
2905 host->cmd_status = SDMMC_INT_RTO;
2906 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2907 tasklet_schedule(&host->tasklet);
2910 static void dw_mci_dto_timer(unsigned long arg)
2912 struct dw_mci *host = (struct dw_mci *)arg;
2914 switch (host->state) {
2915 case STATE_SENDING_DATA:
2916 case STATE_DATA_BUSY:
2918 * If DTO interrupt does NOT come in sending data state,
2919 * we should notify the driver to terminate current transfer
2920 * and report a data timeout to the core.
2922 host->data_status = SDMMC_INT_DRTO;
2923 set_bit(EVENT_DATA_ERROR, &host->pending_events);
2924 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2925 tasklet_schedule(&host->tasklet);
2933 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2935 struct dw_mci_board *pdata;
2936 struct device *dev = host->dev;
2937 const struct dw_mci_drv_data *drv_data = host->drv_data;
2939 u32 clock_frequency;
2941 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2943 return ERR_PTR(-ENOMEM);
2945 /* find reset controller when exist */
2946 pdata->rstc = devm_reset_control_get_optional(dev, "reset");
2947 if (IS_ERR(pdata->rstc)) {
2948 if (PTR_ERR(pdata->rstc) == -EPROBE_DEFER)
2949 return ERR_PTR(-EPROBE_DEFER);
2952 /* find out number of slots supported */
2953 device_property_read_u32(dev, "num-slots", &pdata->num_slots);
2955 if (device_property_read_u32(dev, "fifo-depth", &pdata->fifo_depth))
2957 "fifo-depth property not found, using value of FIFOTH register as default\n");
2959 device_property_read_u32(dev, "card-detect-delay",
2960 &pdata->detect_delay_ms);
2962 if (!device_property_read_u32(dev, "clock-frequency", &clock_frequency))
2963 pdata->bus_hz = clock_frequency;
2965 if (drv_data && drv_data->parse_dt) {
2966 ret = drv_data->parse_dt(host);
2968 return ERR_PTR(ret);
2974 #else /* CONFIG_OF */
2975 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2977 return ERR_PTR(-EINVAL);
2979 #endif /* CONFIG_OF */
2981 static void dw_mci_enable_cd(struct dw_mci *host)
2983 unsigned long irqflags;
2986 struct dw_mci_slot *slot;
2989 * No need for CD if all slots have a non-error GPIO
2990 * as well as broken card detection is found.
2992 for (i = 0; i < host->num_slots; i++) {
2993 slot = host->slot[i];
2994 if (slot->mmc->caps & MMC_CAP_NEEDS_POLL)
2997 if (mmc_gpio_get_cd(slot->mmc) < 0)
3000 if (i == host->num_slots)
3003 spin_lock_irqsave(&host->irq_lock, irqflags);
3004 temp = mci_readl(host, INTMASK);
3005 temp |= SDMMC_INT_CD;
3006 mci_writel(host, INTMASK, temp);
3007 spin_unlock_irqrestore(&host->irq_lock, irqflags);
3010 int dw_mci_probe(struct dw_mci *host)
3012 const struct dw_mci_drv_data *drv_data = host->drv_data;
3013 int width, i, ret = 0;
3018 host->pdata = dw_mci_parse_dt(host);
3019 if (PTR_ERR(host->pdata) == -EPROBE_DEFER) {
3020 return -EPROBE_DEFER;
3021 } else if (IS_ERR(host->pdata)) {
3022 dev_err(host->dev, "platform data not available\n");
3027 host->biu_clk = devm_clk_get(host->dev, "biu");
3028 if (IS_ERR(host->biu_clk)) {
3029 dev_dbg(host->dev, "biu clock not available\n");
3031 ret = clk_prepare_enable(host->biu_clk);
3033 dev_err(host->dev, "failed to enable biu clock\n");
3038 host->ciu_clk = devm_clk_get(host->dev, "ciu");
3039 if (IS_ERR(host->ciu_clk)) {
3040 dev_dbg(host->dev, "ciu clock not available\n");
3041 host->bus_hz = host->pdata->bus_hz;
3043 ret = clk_prepare_enable(host->ciu_clk);
3045 dev_err(host->dev, "failed to enable ciu clock\n");
3049 if (host->pdata->bus_hz) {
3050 ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz);
3053 "Unable to set bus rate to %uHz\n",
3054 host->pdata->bus_hz);
3056 host->bus_hz = clk_get_rate(host->ciu_clk);
3059 if (!host->bus_hz) {
3061 "Platform data must supply bus speed\n");
3066 if (drv_data && drv_data->init) {
3067 ret = drv_data->init(host);
3070 "implementation specific init failed\n");
3075 if (!IS_ERR(host->pdata->rstc)) {
3076 reset_control_assert(host->pdata->rstc);
3077 usleep_range(10, 50);
3078 reset_control_deassert(host->pdata->rstc);
3081 setup_timer(&host->cmd11_timer,
3082 dw_mci_cmd11_timer, (unsigned long)host);
3084 setup_timer(&host->dto_timer,
3085 dw_mci_dto_timer, (unsigned long)host);
3087 spin_lock_init(&host->lock);
3088 spin_lock_init(&host->irq_lock);
3089 INIT_LIST_HEAD(&host->queue);
3092 * Get the host data width - this assumes that HCON has been set with
3093 * the correct values.
3095 i = SDMMC_GET_HDATA_WIDTH(mci_readl(host, HCON));
3097 host->push_data = dw_mci_push_data16;
3098 host->pull_data = dw_mci_pull_data16;
3100 host->data_shift = 1;
3101 } else if (i == 2) {
3102 host->push_data = dw_mci_push_data64;
3103 host->pull_data = dw_mci_pull_data64;
3105 host->data_shift = 3;
3107 /* Check for a reserved value, and warn if it is */
3109 "HCON reports a reserved host data width!\n"
3110 "Defaulting to 32-bit access.\n");
3111 host->push_data = dw_mci_push_data32;
3112 host->pull_data = dw_mci_pull_data32;
3114 host->data_shift = 2;
3117 /* Reset all blocks */
3118 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
3123 host->dma_ops = host->pdata->dma_ops;
3124 dw_mci_init_dma(host);
3126 /* Clear the interrupts for the host controller */
3127 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3128 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3130 /* Put in max timeout */
3131 mci_writel(host, TMOUT, 0xFFFFFFFF);
3134 * FIFO threshold settings RxMark = fifo_size / 2 - 1,
3135 * Tx Mark = fifo_size / 2 DMA Size = 8
3137 if (!host->pdata->fifo_depth) {
3139 * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
3140 * have been overwritten by the bootloader, just like we're
3141 * about to do, so if you know the value for your hardware, you
3142 * should put it in the platform data.
3144 fifo_size = mci_readl(host, FIFOTH);
3145 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
3147 fifo_size = host->pdata->fifo_depth;
3149 host->fifo_depth = fifo_size;
3151 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2);
3152 mci_writel(host, FIFOTH, host->fifoth_val);
3154 /* disable clock to CIU */
3155 mci_writel(host, CLKENA, 0);
3156 mci_writel(host, CLKSRC, 0);
3159 * In 2.40a spec, Data offset is changed.
3160 * Need to check the version-id and set data-offset for DATA register.
3162 host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
3163 dev_info(host->dev, "Version ID is %04x\n", host->verid);
3165 if (host->verid < DW_MMC_240A)
3166 host->fifo_reg = host->regs + DATA_OFFSET;
3168 host->fifo_reg = host->regs + DATA_240A_OFFSET;
3170 tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
3171 ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
3172 host->irq_flags, "dw-mci", host);
3176 if (host->pdata->num_slots)
3177 host->num_slots = host->pdata->num_slots;
3179 host->num_slots = 1;
3181 if (host->num_slots < 1 ||
3182 host->num_slots > SDMMC_GET_SLOT_NUM(mci_readl(host, HCON))) {
3184 "Platform data must supply correct num_slots.\n");
3190 * Enable interrupts for command done, data over, data empty,
3191 * receive ready and error such as transmit, receive timeout, crc error
3193 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3194 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
3195 DW_MCI_ERROR_FLAGS);
3196 /* Enable mci interrupt */
3197 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3200 "DW MMC controller at irq %d,%d bit host data width,%u deep fifo\n",
3201 host->irq, width, fifo_size);
3203 /* We need at least one slot to succeed */
3204 for (i = 0; i < host->num_slots; i++) {
3205 ret = dw_mci_init_slot(host, i);
3207 dev_dbg(host->dev, "slot %d init failed\n", i);
3213 dev_info(host->dev, "%d slots initialized\n", init_slots);
3216 "attempted to initialize %d slots, but failed on all\n",
3221 /* Now that slots are all setup, we can enable card detect */
3222 dw_mci_enable_cd(host);
3227 if (host->use_dma && host->dma_ops->exit)
3228 host->dma_ops->exit(host);
3230 if (!IS_ERR(host->pdata->rstc))
3231 reset_control_assert(host->pdata->rstc);
3234 clk_disable_unprepare(host->ciu_clk);
3237 clk_disable_unprepare(host->biu_clk);
3241 EXPORT_SYMBOL(dw_mci_probe);
3243 void dw_mci_remove(struct dw_mci *host)
3247 for (i = 0; i < host->num_slots; i++) {
3248 dev_dbg(host->dev, "remove slot %d\n", i);
3250 dw_mci_cleanup_slot(host->slot[i], i);
3253 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3254 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3256 /* disable clock to CIU */
3257 mci_writel(host, CLKENA, 0);
3258 mci_writel(host, CLKSRC, 0);
3260 if (host->use_dma && host->dma_ops->exit)
3261 host->dma_ops->exit(host);
3263 if (!IS_ERR(host->pdata->rstc))
3264 reset_control_assert(host->pdata->rstc);
3266 clk_disable_unprepare(host->ciu_clk);
3267 clk_disable_unprepare(host->biu_clk);
3269 EXPORT_SYMBOL(dw_mci_remove);
3273 #ifdef CONFIG_PM_SLEEP
3275 * TODO: we should probably disable the clock to the card in the suspend path.
3277 int dw_mci_suspend(struct dw_mci *host)
3279 if (host->use_dma && host->dma_ops->exit)
3280 host->dma_ops->exit(host);
3284 EXPORT_SYMBOL(dw_mci_suspend);
3286 int dw_mci_resume(struct dw_mci *host)
3290 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
3295 if (host->use_dma && host->dma_ops->init)
3296 host->dma_ops->init(host);
3299 * Restore the initial value at FIFOTH register
3300 * And Invalidate the prev_blksz with zero
3302 mci_writel(host, FIFOTH, host->fifoth_val);
3303 host->prev_blksz = 0;
3305 /* Put in max timeout */
3306 mci_writel(host, TMOUT, 0xFFFFFFFF);
3308 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3309 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3310 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
3311 DW_MCI_ERROR_FLAGS);
3312 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3314 for (i = 0; i < host->num_slots; i++) {
3315 struct dw_mci_slot *slot = host->slot[i];
3319 if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) {
3320 dw_mci_set_ios(slot->mmc, &slot->mmc->ios);
3321 dw_mci_setup_bus(slot, true);
3325 /* Now that slots are all setup, we can enable card detect */
3326 dw_mci_enable_cd(host);
3330 EXPORT_SYMBOL(dw_mci_resume);
3331 #endif /* CONFIG_PM_SLEEP */
3333 static int __init dw_mci_init(void)
3335 pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
3339 static void __exit dw_mci_exit(void)
3343 module_init(dw_mci_init);
3344 module_exit(dw_mci_exit);
3346 MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
3347 MODULE_AUTHOR("NXP Semiconductor VietNam");
3348 MODULE_AUTHOR("Imagination Technologies Ltd");
3349 MODULE_LICENSE("GPL v2");