drivers/mmc/host/dw_mmc.c

   1 /*
   2  * Synopsys DesignWare Multimedia Card Interface driver
   3  *  (Based on NXP driver for lpc 31xx)
   4  *
   5  * Copyright (C) 2009 NXP Semiconductors
   6  * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #include <linux/blkdev.h>
  15 #include <linux/clk.h>
  16 #include <linux/debugfs.h>
  17 #include <linux/device.h>
  18 #include <linux/dma-mapping.h>
  19 #include <linux/err.h>
  20 #include <linux/init.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/ioport.h>
  23 #include <linux/module.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/seq_file.h>
  26 #include <linux/slab.h>
  27 #include <linux/stat.h>
  28 #include <linux/delay.h>
  29 #include <linux/irq.h>
  30 #include <linux/mmc/card.h>
  31 #include <linux/mmc/host.h>
  32 #include <linux/mmc/mmc.h>
  33 #include <linux/mmc/sd.h>
  34 #include <linux/mmc/sdio.h>
  35 #include <linux/mmc/dw_mmc.h>
  36 #include <linux/bitops.h>
  37 #include <linux/regulator/consumer.h>
  38 #include <linux/of.h>
  39 #include <linux/of_gpio.h>
  40 #include <linux/mmc/slot-gpio.h>
  41
  42 #include "dw_mmc.h"
  43
  44 /* Common flag combinations */
  45 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
  46                                  SDMMC_INT_HTO | SDMMC_INT_SBE  | \
  47                                  SDMMC_INT_EBE)
  48 #define DW_MCI_CMD_ERROR_FLAGS  (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
  49                                  SDMMC_INT_RESP_ERR)
  50 #define DW_MCI_ERROR_FLAGS      (DW_MCI_DATA_ERROR_FLAGS | \
  51                                  DW_MCI_CMD_ERROR_FLAGS  | SDMMC_INT_HLE)
  52 #define DW_MCI_SEND_STATUS      1
  53 #define DW_MCI_RECV_STATUS      2
  54 #define DW_MCI_DMA_THRESHOLD    16
  55
  56 #define DW_MCI_FREQ_MAX 200000000       /* unit: HZ */
  57 #define DW_MCI_FREQ_MIN 400000          /* unit: HZ */
  58
  59 #define IDMAC_INT_CLR           (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
  60                                  SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
  61                                  SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
  62                                  SDMMC_IDMAC_INT_TI)
  63
  64 struct idmac_desc_64addr {
  65         u32             des0;   /* Control Descriptor */
  66
  67         u32             des1;   /* Reserved */
  68
  69         u32             des2;   /*Buffer sizes */
  70 #define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \
  71         ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \
  72          ((cpu_to_le32(s)) & cpu_to_le32(0x1fff)))
  73
  74         u32             des3;   /* Reserved */
  75
  76         u32             des4;   /* Lower 32-bits of Buffer Address Pointer 1*/
  77         u32             des5;   /* Upper 32-bits of Buffer Address Pointer 1*/
  78
  79         u32             des6;   /* Lower 32-bits of Next Descriptor Address */
  80         u32             des7;   /* Upper 32-bits of Next Descriptor Address */
  81 };
  82
  83 struct idmac_desc {
  84         __le32          des0;   /* Control Descriptor */
  85 #define IDMAC_DES0_DIC  BIT(1)
  86 #define IDMAC_DES0_LD   BIT(2)
  87 #define IDMAC_DES0_FD   BIT(3)
  88 #define IDMAC_DES0_CH   BIT(4)
  89 #define IDMAC_DES0_ER   BIT(5)
  90 #define IDMAC_DES0_CES  BIT(30)
  91 #define IDMAC_DES0_OWN  BIT(31)
  92
  93         __le32          des1;   /* Buffer sizes */
  94 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
  95         ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff))
  96
  97         __le32          des2;   /* buffer 1 physical address */
  98
  99         __le32          des3;   /* buffer 2 physical address */
 100 };
 101
 102 /* Each descriptor can transfer up to 4KB of data in chained mode */
 103 #define DW_MCI_DESC_DATA_LENGTH 0x1000
 104
 105 static bool dw_mci_reset(struct dw_mci *host);
 106 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
 107 static int dw_mci_card_busy(struct mmc_host *mmc);
 108
 109 #if defined(CONFIG_DEBUG_FS)
 110 static int dw_mci_req_show(struct seq_file *s, void *v)
 111 {
 112         struct dw_mci_slot *slot = s->private;
 113         struct mmc_request *mrq;
 114         struct mmc_command *cmd;
 115         struct mmc_command *stop;
 116         struct mmc_data *data;
 117
 118         /* Make sure we get a consistent snapshot */
 119         spin_lock_bh(&slot->host->lock);
 120         mrq = slot->mrq;
 121
 122         if (mrq) {
 123                 cmd = mrq->cmd;
 124                 data = mrq->data;
 125                 stop = mrq->stop;
 126
 127                 if (cmd)
 128                         seq_printf(s,
 129                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 130                                    cmd->opcode, cmd->arg, cmd->flags,
 131                                    cmd->resp[0], cmd->resp[1], cmd->resp[2],
 132                                    cmd->resp[2], cmd->error);
 133                 if (data)
 134                         seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
 135                                    data->bytes_xfered, data->blocks,
 136                                    data->blksz, data->flags, data->error);
 137                 if (stop)
 138                         seq_printf(s,
 139                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 140                                    stop->opcode, stop->arg, stop->flags,
 141                                    stop->resp[0], stop->resp[1], stop->resp[2],
 142                                    stop->resp[2], stop->error);
 143         }
 144
 145         spin_unlock_bh(&slot->host->lock);
 146
 147         return 0;
 148 }
 149
 150 static int dw_mci_req_open(struct inode *inode, struct file *file)
 151 {
 152         return single_open(file, dw_mci_req_show, inode->i_private);
 153 }
 154
 155 static const struct file_operations dw_mci_req_fops = {
 156         .owner          = THIS_MODULE,
 157         .open           = dw_mci_req_open,
 158         .read           = seq_read,
 159         .llseek         = seq_lseek,
 160         .release        = single_release,
 161 };
 162
 163 static int dw_mci_regs_show(struct seq_file *s, void *v)
 164 {
 165         seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS);
 166         seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS);
 167         seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD);
 168         seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL);
 169         seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK);
 170         seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA);
 171
 172         return 0;
 173 }
 174
 175 static int dw_mci_regs_open(struct inode *inode, struct file *file)
 176 {
 177         return single_open(file, dw_mci_regs_show, inode->i_private);
 178 }
 179
 180 static const struct file_operations dw_mci_regs_fops = {
 181         .owner          = THIS_MODULE,
 182         .open           = dw_mci_regs_open,
 183         .read           = seq_read,
 184         .llseek         = seq_lseek,
 185         .release        = single_release,
 186 };
 187
 188 static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
 189 {
 190         struct mmc_host *mmc = slot->mmc;
 191         struct dw_mci *host = slot->host;
 192         struct dentry *root;
 193         struct dentry *node;
 194
 195         root = mmc->debugfs_root;
 196         if (!root)
 197                 return;
 198
 199         node = debugfs_create_file("regs", S_IRUSR, root, host,
 200                                    &dw_mci_regs_fops);
 201         if (!node)
 202                 goto err;
 203
 204         node = debugfs_create_file("req", S_IRUSR, root, slot,
 205                                    &dw_mci_req_fops);
 206         if (!node)
 207                 goto err;
 208
 209         node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
 210         if (!node)
 211                 goto err;
 212
 213         node = debugfs_create_x32("pending_events", S_IRUSR, root,
 214                                   (u32 *)&host->pending_events);
 215         if (!node)
 216                 goto err;
 217
 218         node = debugfs_create_x32("completed_events", S_IRUSR, root,
 219                                   (u32 *)&host->completed_events);
 220         if (!node)
 221                 goto err;
 222
 223         return;
 224
 225 err:
 226         dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
 227 }
 228 #endif /* defined(CONFIG_DEBUG_FS) */
 229
 230 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg);
 231
 232 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
 233 {
 234         struct mmc_data *data;
 235         struct dw_mci_slot *slot = mmc_priv(mmc);
 236         struct dw_mci *host = slot->host;
 237         const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
 238         u32 cmdr;
 239
 240         cmd->error = -EINPROGRESS;
 241         cmdr = cmd->opcode;
 242
 243         if (cmd->opcode == MMC_STOP_TRANSMISSION ||
 244             cmd->opcode == MMC_GO_IDLE_STATE ||
 245             cmd->opcode == MMC_GO_INACTIVE_STATE ||
 246             (cmd->opcode == SD_IO_RW_DIRECT &&
 247              ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT))
 248                 cmdr |= SDMMC_CMD_STOP;
 249         else if (cmd->opcode != MMC_SEND_STATUS && cmd->data)
 250                 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
 251
 252         if (cmd->opcode == SD_SWITCH_VOLTAGE) {
 253                 u32 clk_en_a;
 254
 255                 /* Special bit makes CMD11 not die */
 256                 cmdr |= SDMMC_CMD_VOLT_SWITCH;
 257
 258                 /* Change state to continue to handle CMD11 weirdness */
 259                 WARN_ON(slot->host->state != STATE_SENDING_CMD);
 260                 slot->host->state = STATE_SENDING_CMD11;
 261
 262                 /*
 263                  * We need to disable low power mode (automatic clock stop)
 264                  * while doing voltage switch so we don't confuse the card,
 265                  * since stopping the clock is a specific part of the UHS
 266                  * voltage change dance.
 267                  *
 268                  * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be
 269                  * unconditionally turned back on in dw_mci_setup_bus() if it's
 270                  * ever called with a non-zero clock.  That shouldn't happen
 271                  * until the voltage change is all done.
 272                  */
 273                 clk_en_a = mci_readl(host, CLKENA);
 274                 clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id);
 275                 mci_writel(host, CLKENA, clk_en_a);
 276                 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
 277                              SDMMC_CMD_PRV_DAT_WAIT, 0);
 278         }
 279
 280         if (cmd->flags & MMC_RSP_PRESENT) {
 281                 /* We expect a response, so set this bit */
 282                 cmdr |= SDMMC_CMD_RESP_EXP;
 283                 if (cmd->flags & MMC_RSP_136)
 284                         cmdr |= SDMMC_CMD_RESP_LONG;
 285         }
 286
 287         if (cmd->flags & MMC_RSP_CRC)
 288                 cmdr |= SDMMC_CMD_RESP_CRC;
 289
 290         data = cmd->data;
 291         if (data) {
 292                 cmdr |= SDMMC_CMD_DAT_EXP;
 293                 if (data->flags & MMC_DATA_STREAM)
 294                         cmdr |= SDMMC_CMD_STRM_MODE;
 295                 if (data->flags & MMC_DATA_WRITE)
 296                         cmdr |= SDMMC_CMD_DAT_WR;
 297         }
 298
 299         if (drv_data && drv_data->prepare_command)
 300                 drv_data->prepare_command(slot->host, &cmdr);
 301
 302         return cmdr;
 303 }
 304
 305 static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd)
 306 {
 307         struct mmc_command *stop;
 308         u32 cmdr;
 309
 310         if (!cmd->data)
 311                 return 0;
 312
 313         stop = &host->stop_abort;
 314         cmdr = cmd->opcode;
 315         memset(stop, 0, sizeof(struct mmc_command));
 316
 317         if (cmdr == MMC_READ_SINGLE_BLOCK ||
 318             cmdr == MMC_READ_MULTIPLE_BLOCK ||
 319             cmdr == MMC_WRITE_BLOCK ||
 320             cmdr == MMC_WRITE_MULTIPLE_BLOCK ||
 321             cmdr == MMC_SEND_TUNING_BLOCK ||
 322             cmdr == MMC_SEND_TUNING_BLOCK_HS200) {
 323                 stop->opcode = MMC_STOP_TRANSMISSION;
 324                 stop->arg = 0;
 325                 stop->flags = MMC_RSP_R1B | MMC_CMD_AC;
 326         } else if (cmdr == SD_IO_RW_EXTENDED) {
 327                 stop->opcode = SD_IO_RW_DIRECT;
 328                 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
 329                              ((cmd->arg >> 28) & 0x7);
 330                 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC;
 331         } else {
 332                 return 0;
 333         }
 334
 335         cmdr = stop->opcode | SDMMC_CMD_STOP |
 336                 SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP;
 337
 338         return cmdr;
 339 }
 340
 341 static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags)
 342 {
 343         unsigned long timeout = jiffies + msecs_to_jiffies(500);
 344
 345         /*
 346          * Databook says that before issuing a new data transfer command
 347          * we need to check to see if the card is busy.  Data transfer commands
 348          * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that.
 349          *
 350          * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is
 351          * expected.
 352          */
 353         if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) &&
 354             !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) {
 355                 while (mci_readl(host, STATUS) & SDMMC_STATUS_BUSY) {
 356                         if (time_after(jiffies, timeout)) {
 357                                 /* Command will fail; we'll pass error then */
 358                                 dev_err(host->dev, "Busy; trying anyway\n");
 359                                 break;
 360                         }
 361                         udelay(10);
 362                 }
 363         }
 364 }
 365
 366 static void dw_mci_start_command(struct dw_mci *host,
 367                                  struct mmc_command *cmd, u32 cmd_flags)
 368 {
 369         host->cmd = cmd;
 370         dev_vdbg(host->dev,
 371                  "start command: ARGR=0x%08x CMDR=0x%08x\n",
 372                  cmd->arg, cmd_flags);
 373
 374         mci_writel(host, CMDARG, cmd->arg);
 375         wmb(); /* drain writebuffer */
 376         dw_mci_wait_while_busy(host, cmd_flags);
 377
 378         mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
 379 }
 380
 381 static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data)
 382 {
 383         struct mmc_command *stop = &host->stop_abort;
 384
 385         dw_mci_start_command(host, stop, host->stop_cmdr);
 386 }
 387
 388 /* DMA interface functions */
 389 static void dw_mci_stop_dma(struct dw_mci *host)
 390 {
 391         if (host->using_dma) {
 392                 host->dma_ops->stop(host);
 393                 host->dma_ops->cleanup(host);
 394         }
 395
 396         /* Data transfer was stopped by the interrupt handler */
 397         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 398 }
 399
 400 static int dw_mci_get_dma_dir(struct mmc_data *data)
 401 {
 402         if (data->flags & MMC_DATA_WRITE)
 403                 return DMA_TO_DEVICE;
 404         else
 405                 return DMA_FROM_DEVICE;
 406 }
 407
 408 static void dw_mci_dma_cleanup(struct dw_mci *host)
 409 {
 410         struct mmc_data *data = host->data;
 411
 412         if (data)
 413                 if (!data->host_cookie)
 414                         dma_unmap_sg(host->dev,
 415                                      data->sg,
 416                                      data->sg_len,
 417                                      dw_mci_get_dma_dir(data));
 418 }
 419
 420 static void dw_mci_idmac_reset(struct dw_mci *host)
 421 {
 422         u32 bmod = mci_readl(host, BMOD);
 423         /* Software reset of DMA */
 424         bmod |= SDMMC_IDMAC_SWRESET;
 425         mci_writel(host, BMOD, bmod);
 426 }
 427
 428 static void dw_mci_idmac_stop_dma(struct dw_mci *host)
 429 {
 430         u32 temp;
 431
 432         /* Disable and reset the IDMAC interface */
 433         temp = mci_readl(host, CTRL);
 434         temp &= ~SDMMC_CTRL_USE_IDMAC;
 435         temp |= SDMMC_CTRL_DMA_RESET;
 436         mci_writel(host, CTRL, temp);
 437
 438         /* Stop the IDMAC running */
 439         temp = mci_readl(host, BMOD);
 440         temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
 441         temp |= SDMMC_IDMAC_SWRESET;
 442         mci_writel(host, BMOD, temp);
 443 }
 444
 445 static void dw_mci_dmac_complete_dma(void *arg)
 446 {
 447         struct dw_mci *host = arg;
 448         struct mmc_data *data = host->data;
 449
 450         dev_vdbg(host->dev, "DMA complete\n");
 451
 452         if ((host->use_dma == TRANS_MODE_EDMAC) &&
 453             data && (data->flags & MMC_DATA_READ))
 454                 /* Invalidate cache after read */
 455                 dma_sync_sg_for_cpu(mmc_dev(host->cur_slot->mmc),
 456                                     data->sg,
 457                                     data->sg_len,
 458                                     DMA_FROM_DEVICE);
 459
 460         host->dma_ops->cleanup(host);
 461
 462         /*
 463          * If the card was removed, data will be NULL. No point in trying to
 464          * send the stop command or waiting for NBUSY in this case.
 465          */
 466         if (data) {
 467                 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 468                 tasklet_schedule(&host->tasklet);
 469         }
 470 }
 471
 472 static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data,
 473                                     unsigned int sg_len)
 474 {
 475         unsigned int desc_len;
 476         int i;
 477
 478         if (host->dma_64bit_address == 1) {
 479                 struct idmac_desc_64addr *desc_first, *desc_last, *desc;
 480
 481                 desc_first = desc_last = desc = host->sg_cpu;
 482
 483                 for (i = 0; i < sg_len; i++) {
 484                         unsigned int length = sg_dma_len(&data->sg[i]);
 485
 486                         u64 mem_addr = sg_dma_address(&data->sg[i]);
 487
 488                         for ( ; length ; desc++) {
 489                                 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
 490                                            length : DW_MCI_DESC_DATA_LENGTH;
 491
 492                                 length -= desc_len;
 493
 494                                 /*
 495                                  * Set the OWN bit and disable interrupts
 496                                  * for this descriptor
 497                                  */
 498                                 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC |
 499                                                         IDMAC_DES0_CH;
 500
 501                                 /* Buffer length */
 502                                 IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, desc_len);
 503
 504                                 /* Physical address to DMA to/from */
 505                                 desc->des4 = mem_addr & 0xffffffff;
 506                                 desc->des5 = mem_addr >> 32;
 507
 508                                 /* Update physical address for the next desc */
 509                                 mem_addr += desc_len;
 510
 511                                 /* Save pointer to the last descriptor */
 512                                 desc_last = desc;
 513                         }
 514                 }
 515
 516                 /* Set first descriptor */
 517                 desc_first->des0 |= IDMAC_DES0_FD;
 518
 519                 /* Set last descriptor */
 520                 desc_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
 521                 desc_last->des0 |= IDMAC_DES0_LD;
 522
 523         } else {
 524                 struct idmac_desc *desc_first, *desc_last, *desc;
 525
 526                 desc_first = desc_last = desc = host->sg_cpu;
 527
 528                 for (i = 0; i < sg_len; i++) {
 529                         unsigned int length = sg_dma_len(&data->sg[i]);
 530
 531                         u32 mem_addr = sg_dma_address(&data->sg[i]);
 532
 533                         for ( ; length ; desc++) {
 534                                 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
 535                                            length : DW_MCI_DESC_DATA_LENGTH;
 536
 537                                 length -= desc_len;
 538
 539                                 /*
 540                                  * Set the OWN bit and disable interrupts
 541                                  * for this descriptor
 542                                  */
 543                                 desc->des0 = cpu_to_le32(IDMAC_DES0_OWN |
 544                                                          IDMAC_DES0_DIC |
 545                                                          IDMAC_DES0_CH);
 546
 547                                 /* Buffer length */
 548                                 IDMAC_SET_BUFFER1_SIZE(desc, desc_len);
 549
 550                                 /* Physical address to DMA to/from */
 551                                 desc->des2 = cpu_to_le32(mem_addr);
 552
 553                                 /* Update physical address for the next desc */
 554                                 mem_addr += desc_len;
 555
 556                                 /* Save pointer to the last descriptor */
 557                                 desc_last = desc;
 558                         }
 559                 }
 560
 561                 /* Set first descriptor */
 562                 desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD);
 563
 564                 /* Set last descriptor */
 565                 desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH |
 566                                                IDMAC_DES0_DIC));
 567                 desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD);
 568         }
 569
 570         wmb(); /* drain writebuffer */
 571 }
 572
 573 static int dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
 574 {
 575         u32 temp;
 576
 577         dw_mci_translate_sglist(host, host->data, sg_len);
 578
 579         /* Make sure to reset DMA in case we did PIO before this */
 580         dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
 581         dw_mci_idmac_reset(host);
 582
 583         /* Select IDMAC interface */
 584         temp = mci_readl(host, CTRL);
 585         temp |= SDMMC_CTRL_USE_IDMAC;
 586         mci_writel(host, CTRL, temp);
 587
 588         /* drain writebuffer */
 589         wmb();
 590
 591         /* Enable the IDMAC */
 592         temp = mci_readl(host, BMOD);
 593         temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
 594         mci_writel(host, BMOD, temp);
 595
 596         /* Start it running */
 597         mci_writel(host, PLDMND, 1);
 598
 599         return 0;
 600 }
 601
 602 static int dw_mci_idmac_init(struct dw_mci *host)
 603 {
 604         int i;
 605
 606         if (host->dma_64bit_address == 1) {
 607                 struct idmac_desc_64addr *p;
 608                 /* Number of descriptors in the ring buffer */
 609                 host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc_64addr);
 610
 611                 /* Forward link the descriptor list */
 612                 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1;
 613                                                                 i++, p++) {
 614                         p->des6 = (host->sg_dma +
 615                                         (sizeof(struct idmac_desc_64addr) *
 616                                                         (i + 1))) & 0xffffffff;
 617
 618                         p->des7 = (u64)(host->sg_dma +
 619                                         (sizeof(struct idmac_desc_64addr) *
 620                                                         (i + 1))) >> 32;
 621                         /* Initialize reserved and buffer size fields to "0" */
 622                         p->des0 = 0;
 623                         p->des1 = 0;
 624                         p->des2 = 0;
 625                         p->des3 = 0;
 626                 }
 627
 628                 /* Set the last descriptor as the end-of-ring descriptor */
 629                 p->des6 = host->sg_dma & 0xffffffff;
 630                 p->des7 = (u64)host->sg_dma >> 32;
 631                 p->des0 = IDMAC_DES0_ER;
 632
 633         } else {
 634                 struct idmac_desc *p;
 635                 /* Number of descriptors in the ring buffer */
 636                 host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc);
 637
 638                 /* Forward link the descriptor list */
 639                 for (i = 0, p = host->sg_cpu;
 640                      i < host->ring_size - 1;
 641                      i++, p++) {
 642                         p->des3 = cpu_to_le32(host->sg_dma +
 643                                         (sizeof(struct idmac_desc) * (i + 1)));
 644                         p->des0 = 0;
 645                         p->des1 = 0;
 646                 }
 647
 648                 /* Set the last descriptor as the end-of-ring descriptor */
 649                 p->des3 = cpu_to_le32(host->sg_dma);
 650                 p->des0 = cpu_to_le32(IDMAC_DES0_ER);
 651         }
 652
 653         dw_mci_idmac_reset(host);
 654
 655         if (host->dma_64bit_address == 1) {
 656                 /* Mask out interrupts - get Tx & Rx complete only */
 657                 mci_writel(host, IDSTS64, IDMAC_INT_CLR);
 658                 mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI |
 659                                 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
 660
 661                 /* Set the descriptor base address */
 662                 mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff);
 663                 mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32);
 664
 665         } else {
 666                 /* Mask out interrupts - get Tx & Rx complete only */
 667                 mci_writel(host, IDSTS, IDMAC_INT_CLR);
 668                 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI |
 669                                 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
 670
 671                 /* Set the descriptor base address */
 672                 mci_writel(host, DBADDR, host->sg_dma);
 673         }
 674
 675         return 0;
 676 }
 677
 678 static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
 679         .init = dw_mci_idmac_init,
 680         .start = dw_mci_idmac_start_dma,
 681         .stop = dw_mci_idmac_stop_dma,
 682         .complete = dw_mci_dmac_complete_dma,
 683         .cleanup = dw_mci_dma_cleanup,
 684 };
 685
 686 static void dw_mci_edmac_stop_dma(struct dw_mci *host)
 687 {
 688         dmaengine_terminate_all(host->dms->ch);
 689 }
 690
 691 static int dw_mci_edmac_start_dma(struct dw_mci *host,
 692                                             unsigned int sg_len)
 693 {
 694         struct dma_slave_config cfg;
 695         struct dma_async_tx_descriptor *desc = NULL;
 696         struct scatterlist *sgl = host->data->sg;
 697         const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
 698         u32 sg_elems = host->data->sg_len;
 699         u32 fifoth_val;
 700         u32 fifo_offset = host->fifo_reg - host->regs;
 701         int ret = 0;
 702
 703         /* Set external dma config: burst size, burst width */
 704         memset(&cfg, 0, sizeof(cfg));
 705         cfg.dst_addr = host->phy_regs + fifo_offset;
 706         cfg.src_addr = cfg.dst_addr;
 707         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 708         cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 709
 710         /* Match burst msize with external dma config */
 711         fifoth_val = mci_readl(host, FIFOTH);
 712         cfg.dst_maxburst = mszs[(fifoth_val >> 28) & 0x7];
 713         cfg.src_maxburst = cfg.dst_maxburst;
 714
 715         if (host->data->flags & MMC_DATA_WRITE)
 716                 cfg.direction = DMA_MEM_TO_DEV;
 717         else
 718                 cfg.direction = DMA_DEV_TO_MEM;
 719
 720         ret = dmaengine_slave_config(host->dms->ch, &cfg);
 721         if (ret) {
 722                 dev_err(host->dev, "Failed to config edmac.\n");
 723                 return -EBUSY;
 724         }
 725
 726         desc = dmaengine_prep_slave_sg(host->dms->ch, sgl,
 727                                        sg_len, cfg.direction,
 728                                        DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 729         if (!desc) {
 730                 dev_err(host->dev, "Can't prepare slave sg.\n");
 731                 return -EBUSY;
 732         }
 733
 734         /* Set dw_mci_dmac_complete_dma as callback */
 735         desc->callback = dw_mci_dmac_complete_dma;
 736         desc->callback_param = (void *)host;
 737         dmaengine_submit(desc);
 738
 739         /* Flush cache before write */
 740         if (host->data->flags & MMC_DATA_WRITE)
 741                 dma_sync_sg_for_device(mmc_dev(host->cur_slot->mmc), sgl,
 742                                        sg_elems, DMA_TO_DEVICE);
 743
 744         dma_async_issue_pending(host->dms->ch);
 745
 746         return 0;
 747 }
 748
 749 static int dw_mci_edmac_init(struct dw_mci *host)
 750 {
 751         /* Request external dma channel */
 752         host->dms = kzalloc(sizeof(struct dw_mci_dma_slave), GFP_KERNEL);
 753         if (!host->dms)
 754                 return -ENOMEM;
 755
 756         host->dms->ch = dma_request_slave_channel(host->dev, "rx-tx");
 757         if (!host->dms->ch) {
 758                 dev_err(host->dev, "Failed to get external DMA channel.\n");
 759                 kfree(host->dms);
 760                 host->dms = NULL;
 761                 return -ENXIO;
 762         }
 763
 764         return 0;
 765 }
 766
 767 static void dw_mci_edmac_exit(struct dw_mci *host)
 768 {
 769         if (host->dms) {
 770                 if (host->dms->ch) {
 771                         dma_release_channel(host->dms->ch);
 772                         host->dms->ch = NULL;
 773                 }
 774                 kfree(host->dms);
 775                 host->dms = NULL;
 776         }
 777 }
 778
 779 static const struct dw_mci_dma_ops dw_mci_edmac_ops = {
 780         .init = dw_mci_edmac_init,
 781         .exit = dw_mci_edmac_exit,
 782         .start = dw_mci_edmac_start_dma,
 783         .stop = dw_mci_edmac_stop_dma,
 784         .complete = dw_mci_dmac_complete_dma,
 785         .cleanup = dw_mci_dma_cleanup,
 786 };
 787
 788 static int dw_mci_pre_dma_transfer(struct dw_mci *host,
 789                                    struct mmc_data *data,
 790                                    bool next)
 791 {
 792         struct scatterlist *sg;
 793         unsigned int i, sg_len;
 794
 795         if (!next && data->host_cookie)
 796                 return data->host_cookie;
 797
 798         /*
 799          * We don't do DMA on "complex" transfers, i.e. with
 800          * non-word-aligned buffers or lengths. Also, we don't bother
 801          * with all the DMA setup overhead for short transfers.
 802          */
 803         if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
 804                 return -EINVAL;
 805
 806         if (data->blksz & 3)
 807                 return -EINVAL;
 808
 809         for_each_sg(data->sg, sg, data->sg_len, i) {
 810                 if (sg->offset & 3 || sg->length & 3)
 811                         return -EINVAL;
 812         }
 813
 814         sg_len = dma_map_sg(host->dev,
 815                             data->sg,
 816                             data->sg_len,
 817                             dw_mci_get_dma_dir(data));
 818         if (sg_len == 0)
 819                 return -EINVAL;
 820
 821         if (next)
 822                 data->host_cookie = sg_len;
 823
 824         return sg_len;
 825 }
 826
 827 static void dw_mci_pre_req(struct mmc_host *mmc,
 828                            struct mmc_request *mrq,
 829                            bool is_first_req)
 830 {
 831         struct dw_mci_slot *slot = mmc_priv(mmc);
 832         struct mmc_data *data = mrq->data;
 833
 834         if (!slot->host->use_dma || !data)
 835                 return;
 836
 837         if (data->host_cookie) {
 838                 data->host_cookie = 0;
 839                 return;
 840         }
 841
 842         if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0)
 843                 data->host_cookie = 0;
 844 }
 845
 846 static void dw_mci_post_req(struct mmc_host *mmc,
 847                             struct mmc_request *mrq,
 848                             int err)
 849 {
 850         struct dw_mci_slot *slot = mmc_priv(mmc);
 851         struct mmc_data *data = mrq->data;
 852
 853         if (!slot->host->use_dma || !data)
 854                 return;
 855
 856         if (data->host_cookie)
 857                 dma_unmap_sg(slot->host->dev,
 858                              data->sg,
 859                              data->sg_len,
 860                              dw_mci_get_dma_dir(data));
 861         data->host_cookie = 0;
 862 }
 863
 864 static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
 865 {
 866         unsigned int blksz = data->blksz;
 867         const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
 868         u32 fifo_width = 1 << host->data_shift;
 869         u32 blksz_depth = blksz / fifo_width, fifoth_val;
 870         u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
 871         int idx = ARRAY_SIZE(mszs) - 1;
 872
 873         /* pio should ship this scenario */
 874         if (!host->use_dma)
 875                 return;
 876
 877         tx_wmark = (host->fifo_depth) / 2;
 878         tx_wmark_invers = host->fifo_depth - tx_wmark;
 879
 880         /*
 881          * MSIZE is '1',
 882          * if blksz is not a multiple of the FIFO width
 883          */
 884         if (blksz % fifo_width) {
 885                 msize = 0;
 886                 rx_wmark = 1;
 887                 goto done;
 888         }
 889
 890         do {
 891                 if (!((blksz_depth % mszs[idx]) ||
 892                      (tx_wmark_invers % mszs[idx]))) {
 893                         msize = idx;
 894                         rx_wmark = mszs[idx] - 1;
 895                         break;
 896                 }
 897         } while (--idx > 0);
 898         /*
 899          * If idx is '0', it won't be tried
 900          * Thus, initial values are uesed
 901          */
 902 done:
 903         fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
 904         mci_writel(host, FIFOTH, fifoth_val);
 905 }
 906
 907 static void dw_mci_ctrl_rd_thld(struct dw_mci *host, struct mmc_data *data)
 908 {
 909         unsigned int blksz = data->blksz;
 910         u32 blksz_depth, fifo_depth;
 911         u16 thld_size;
 912
 913         WARN_ON(!(data->flags & MMC_DATA_READ));
 914
 915         /*
 916          * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is
 917          * in the FIFO region, so we really shouldn't access it).
 918          */
 919         if (host->verid < DW_MMC_240A)
 920                 return;
 921
 922         if (host->timing != MMC_TIMING_MMC_HS200 &&
 923             host->timing != MMC_TIMING_MMC_HS400 &&
 924             host->timing != MMC_TIMING_UHS_SDR104)
 925                 goto disable;
 926
 927         blksz_depth = blksz / (1 << host->data_shift);
 928         fifo_depth = host->fifo_depth;
 929
 930         if (blksz_depth > fifo_depth)
 931                 goto disable;
 932
 933         /*
 934          * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
 935          * If (blksz_depth) <  (fifo_depth >> 1), should be thld_size = blksz
 936          * Currently just choose blksz.
 937          */
 938         thld_size = blksz;
 939         mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(thld_size, 1));
 940         return;
 941
 942 disable:
 943         mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(0, 0));
 944 }
 945
 946 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
 947 {
 948         unsigned long irqflags;
 949         int sg_len;
 950         u32 temp;
 951
 952         host->using_dma = 0;
 953
 954         /* If we don't have a channel, we can't do DMA */
 955         if (!host->use_dma)
 956                 return -ENODEV;
 957
 958         sg_len = dw_mci_pre_dma_transfer(host, data, 0);
 959         if (sg_len < 0) {
 960                 host->dma_ops->stop(host);
 961                 return sg_len;
 962         }
 963
 964         host->using_dma = 1;
 965
 966         if (host->use_dma == TRANS_MODE_IDMAC)
 967                 dev_vdbg(host->dev,
 968                          "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
 969                          (unsigned long)host->sg_cpu,
 970                          (unsigned long)host->sg_dma,
 971                          sg_len);
 972
 973         /*
 974          * Decide the MSIZE and RX/TX Watermark.
 975          * If current block size is same with previous size,
 976          * no need to update fifoth.
 977          */
 978         if (host->prev_blksz != data->blksz)
 979                 dw_mci_adjust_fifoth(host, data);
 980
 981         /* Enable the DMA interface */
 982         temp = mci_readl(host, CTRL);
 983         temp |= SDMMC_CTRL_DMA_ENABLE;
 984         mci_writel(host, CTRL, temp);
 985
 986         /* Disable RX/TX IRQs, let DMA handle it */
 987         spin_lock_irqsave(&host->irq_lock, irqflags);
 988         temp = mci_readl(host, INTMASK);
 989         temp  &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
 990         mci_writel(host, INTMASK, temp);
 991         spin_unlock_irqrestore(&host->irq_lock, irqflags);
 992
 993         if (host->dma_ops->start(host, sg_len)) {
 994                 /* We can't do DMA */
 995                 dev_err(host->dev, "%s: failed to start DMA.\n", __func__);
 996                 return -ENODEV;
 997         }
 998
 999         return 0;
1000 }
1001
1002 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
1003 {
1004         unsigned long irqflags;
1005         int flags = SG_MITER_ATOMIC;
1006         u32 temp;
1007
1008         data->error = -EINPROGRESS;
1009
1010         WARN_ON(host->data);
1011         host->sg = NULL;
1012         host->data = data;
1013
1014         if (data->flags & MMC_DATA_READ) {
1015                 host->dir_status = DW_MCI_RECV_STATUS;
1016                 dw_mci_ctrl_rd_thld(host, data);
1017         } else {
1018                 host->dir_status = DW_MCI_SEND_STATUS;
1019         }
1020
1021         if (dw_mci_submit_data_dma(host, data)) {
1022                 if (host->data->flags & MMC_DATA_READ)
1023                         flags |= SG_MITER_TO_SG;
1024                 else
1025                         flags |= SG_MITER_FROM_SG;
1026
1027                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
1028                 host->sg = data->sg;
1029                 host->part_buf_start = 0;
1030                 host->part_buf_count = 0;
1031
1032                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
1033
1034                 spin_lock_irqsave(&host->irq_lock, irqflags);
1035                 temp = mci_readl(host, INTMASK);
1036                 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
1037                 mci_writel(host, INTMASK, temp);
1038                 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1039
1040                 temp = mci_readl(host, CTRL);
1041                 temp &= ~SDMMC_CTRL_DMA_ENABLE;
1042                 mci_writel(host, CTRL, temp);
1043
1044                 /*
1045                  * Use the initial fifoth_val for PIO mode.
1046                  * If next issued data may be transfered by DMA mode,
1047                  * prev_blksz should be invalidated.
1048                  */
1049                 mci_writel(host, FIFOTH, host->fifoth_val);
1050                 host->prev_blksz = 0;
1051         } else {
1052                 /*
1053                  * Keep the current block size.
1054                  * It will be used to decide whether to update
1055                  * fifoth register next time.
1056                  */
1057                 host->prev_blksz = data->blksz;
1058         }
1059 }
1060
1061 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
1062 {
1063         struct dw_mci *host = slot->host;
1064         unsigned long timeout = jiffies + msecs_to_jiffies(500);
1065         unsigned int cmd_status = 0;
1066
1067         mci_writel(host, CMDARG, arg);
1068         wmb(); /* drain writebuffer */
1069         dw_mci_wait_while_busy(host, cmd);
1070         mci_writel(host, CMD, SDMMC_CMD_START | cmd);
1071
1072         while (time_before(jiffies, timeout)) {
1073                 cmd_status = mci_readl(host, CMD);
1074                 if (!(cmd_status & SDMMC_CMD_START))
1075                         return;
1076         }
1077         dev_err(&slot->mmc->class_dev,
1078                 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
1079                 cmd, arg, cmd_status);
1080 }
1081
1082 static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
1083 {
1084         struct dw_mci *host = slot->host;
1085         unsigned int clock = slot->clock;
1086         u32 div;
1087         u32 clk_en_a;
1088         u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT;
1089
1090         /* We must continue to set bit 28 in CMD until the change is complete */
1091         if (host->state == STATE_WAITING_CMD11_DONE)
1092                 sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH;
1093
1094         if (!clock) {
1095                 mci_writel(host, CLKENA, 0);
1096                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1097         } else if (clock != host->current_speed || force_clkinit) {
1098                 div = host->bus_hz / clock;
1099                 if (host->bus_hz % clock && host->bus_hz > clock)
1100                         /*
1101                          * move the + 1 after the divide to prevent
1102                          * over-clocking the card.
1103                          */
1104                         div += 1;
1105
1106                 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
1107
1108                 if ((clock << div) != slot->__clk_old || force_clkinit)
1109                         dev_info(&slot->mmc->class_dev,
1110                                  "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
1111                                  slot->id, host->bus_hz, clock,
1112                                  div ? ((host->bus_hz / div) >> 1) :
1113                                  host->bus_hz, div);
1114
1115                 /* disable clock */
1116                 mci_writel(host, CLKENA, 0);
1117                 mci_writel(host, CLKSRC, 0);
1118
1119                 /* inform CIU */
1120                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1121
1122                 /* set clock to desired speed */
1123                 mci_writel(host, CLKDIV, div);
1124
1125                 /* inform CIU */
1126                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1127
1128                 /* enable clock; only low power if no SDIO */
1129                 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
1130                 if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags))
1131                         clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
1132                 mci_writel(host, CLKENA, clk_en_a);
1133
1134                 /* inform CIU */
1135                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1136
1137                 /* keep the clock with reflecting clock dividor */
1138                 slot->__clk_old = clock << div;
1139         }
1140
1141         host->current_speed = clock;
1142
1143         /* Set the current slot bus width */
1144         mci_writel(host, CTYPE, (slot->ctype << slot->id));
1145 }
1146
1147 static void __dw_mci_start_request(struct dw_mci *host,
1148                                    struct dw_mci_slot *slot,
1149                                    struct mmc_command *cmd)
1150 {
1151         struct mmc_request *mrq;
1152         struct mmc_data *data;
1153         u32 cmdflags;
1154
1155         mrq = slot->mrq;
1156
1157         host->cur_slot = slot;
1158         host->mrq = mrq;
1159
1160         host->pending_events = 0;
1161         host->completed_events = 0;
1162         host->cmd_status = 0;
1163         host->data_status = 0;
1164         host->dir_status = 0;
1165
1166         data = cmd->data;
1167         if (data) {
1168                 mci_writel(host, TMOUT, 0xFFFFFFFF);
1169                 mci_writel(host, BYTCNT, data->blksz*data->blocks);
1170                 mci_writel(host, BLKSIZ, data->blksz);
1171         }
1172
1173         cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
1174
1175         /* this is the first command, send the initialization clock */
1176         if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
1177                 cmdflags |= SDMMC_CMD_INIT;
1178
1179         if (data) {
1180                 dw_mci_submit_data(host, data);
1181                 wmb(); /* drain writebuffer */
1182         }
1183
1184         dw_mci_start_command(host, cmd, cmdflags);
1185
1186         if (cmd->opcode == SD_SWITCH_VOLTAGE) {
1187                 unsigned long irqflags;
1188
1189                 /*
1190                  * Databook says to fail after 2ms w/ no response, but evidence
1191                  * shows that sometimes the cmd11 interrupt takes over 130ms.
1192                  * We'll set to 500ms, plus an extra jiffy just in case jiffies
1193                  * is just about to roll over.
1194                  *
1195                  * We do this whole thing under spinlock and only if the
1196                  * command hasn't already completed (indicating the the irq
1197                  * already ran so we don't want the timeout).
1198                  */
1199                 spin_lock_irqsave(&host->irq_lock, irqflags);
1200                 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
1201                         mod_timer(&host->cmd11_timer,
1202                                 jiffies + msecs_to_jiffies(500) + 1);
1203                 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1204         }
1205
1206         host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd);
1207 }
1208
1209 static void dw_mci_start_request(struct dw_mci *host,
1210                                  struct dw_mci_slot *slot)
1211 {
1212         struct mmc_request *mrq = slot->mrq;
1213         struct mmc_command *cmd;
1214
1215         cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
1216         __dw_mci_start_request(host, slot, cmd);
1217 }
1218
1219 /* must be called with host->lock held */
1220 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
1221                                  struct mmc_request *mrq)
1222 {
1223         dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1224                  host->state);
1225
1226         slot->mrq = mrq;
1227
1228         if (host->state == STATE_WAITING_CMD11_DONE) {
1229                 dev_warn(&slot->mmc->class_dev,
1230                          "Voltage change didn't complete\n");
1231                 /*
1232                  * this case isn't expected to happen, so we can
1233                  * either crash here or just try to continue on
1234                  * in the closest possible state
1235                  */
1236                 host->state = STATE_IDLE;
1237         }
1238
1239         if (host->state == STATE_IDLE) {
1240                 host->state = STATE_SENDING_CMD;
1241                 dw_mci_start_request(host, slot);
1242         } else {
1243                 list_add_tail(&slot->queue_node, &host->queue);
1244         }
1245 }
1246
1247 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1248 {
1249         struct dw_mci_slot *slot = mmc_priv(mmc);
1250         struct dw_mci *host = slot->host;
1251
1252         WARN_ON(slot->mrq);
1253
1254         /*
1255          * The check for card presence and queueing of the request must be
1256          * atomic, otherwise the card could be removed in between and the
1257          * request wouldn't fail until another card was inserted.
1258          */
1259         spin_lock_bh(&host->lock);
1260
1261         if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
1262                 spin_unlock_bh(&host->lock);
1263                 mrq->cmd->error = -ENOMEDIUM;
1264                 mmc_request_done(mmc, mrq);
1265                 return;
1266         }
1267
1268         dw_mci_queue_request(host, slot, mrq);
1269
1270         spin_unlock_bh(&host->lock);
1271 }
1272
1273 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1274 {
1275         struct dw_mci_slot *slot = mmc_priv(mmc);
1276         const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
1277         u32 regs;
1278         int ret;
1279
1280         switch (ios->bus_width) {
1281         case MMC_BUS_WIDTH_4:
1282                 slot->ctype = SDMMC_CTYPE_4BIT;
1283                 break;
1284         case MMC_BUS_WIDTH_8:
1285                 slot->ctype = SDMMC_CTYPE_8BIT;
1286                 break;
1287         default:
1288                 /* set default 1 bit mode */
1289                 slot->ctype = SDMMC_CTYPE_1BIT;
1290         }
1291
1292         regs = mci_readl(slot->host, UHS_REG);
1293
1294         /* DDR mode set */
1295         if (ios->timing == MMC_TIMING_MMC_DDR52 ||
1296             ios->timing == MMC_TIMING_UHS_DDR50 ||
1297             ios->timing == MMC_TIMING_MMC_HS400)
1298                 regs |= ((0x1 << slot->id) << 16);
1299         else
1300                 regs &= ~((0x1 << slot->id) << 16);
1301
1302         mci_writel(slot->host, UHS_REG, regs);
1303         slot->host->timing = ios->timing;
1304
1305         /*
1306          * Use mirror of ios->clock to prevent race with mmc
1307          * core ios update when finding the minimum.
1308          */
1309         slot->clock = ios->clock;
1310
1311         if (drv_data && drv_data->set_ios)
1312                 drv_data->set_ios(slot->host, ios);
1313
1314         switch (ios->power_mode) {
1315         case MMC_POWER_UP:
1316                 if (!IS_ERR(mmc->supply.vmmc)) {
1317                         ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1318                                         ios->vdd);
1319                         if (ret) {
1320                                 dev_err(slot->host->dev,
1321                                         "failed to enable vmmc regulator\n");
1322                                 /*return, if failed turn on vmmc*/
1323                                 return;
1324                         }
1325                 }
1326                 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
1327                 regs = mci_readl(slot->host, PWREN);
1328                 regs |= (1 << slot->id);
1329                 mci_writel(slot->host, PWREN, regs);
1330                 break;
1331         case MMC_POWER_ON:
1332                 if (!slot->host->vqmmc_enabled) {
1333                         if (!IS_ERR(mmc->supply.vqmmc)) {
1334                                 ret = regulator_enable(mmc->supply.vqmmc);
1335                                 if (ret < 0)
1336                                         dev_err(slot->host->dev,
1337                                                 "failed to enable vqmmc\n");
1338                                 else
1339                                         slot->host->vqmmc_enabled = true;
1340
1341                         } else {
1342                                 /* Keep track so we don't reset again */
1343                                 slot->host->vqmmc_enabled = true;
1344                         }
1345
1346                         /* Reset our state machine after powering on */
1347                         dw_mci_ctrl_reset(slot->host,
1348                                           SDMMC_CTRL_ALL_RESET_FLAGS);
1349                 }
1350
1351                 /* Adjust clock / bus width after power is up */
1352                 dw_mci_setup_bus(slot, false);
1353
1354                 break;
1355         case MMC_POWER_OFF:
1356                 /* Turn clock off before power goes down */
1357                 dw_mci_setup_bus(slot, false);
1358
1359                 if (!IS_ERR(mmc->supply.vmmc))
1360                         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1361
1362                 if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled)
1363                         regulator_disable(mmc->supply.vqmmc);
1364                 slot->host->vqmmc_enabled = false;
1365
1366                 regs = mci_readl(slot->host, PWREN);
1367                 regs &= ~(1 << slot->id);
1368                 mci_writel(slot->host, PWREN, regs);
1369                 break;
1370         default:
1371                 break;
1372         }
1373
1374         if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0)
1375                 slot->host->state = STATE_IDLE;
1376 }
1377
1378 static int dw_mci_card_busy(struct mmc_host *mmc)
1379 {
1380         struct dw_mci_slot *slot = mmc_priv(mmc);
1381         u32 status;
1382
1383         /*
1384          * Check the busy bit which is low when DAT[3:0]
1385          * (the data lines) are 0000
1386          */
1387         status = mci_readl(slot->host, STATUS);
1388
1389         return !!(status & SDMMC_STATUS_BUSY);
1390 }
1391
1392 static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1393 {
1394         struct dw_mci_slot *slot = mmc_priv(mmc);
1395         struct dw_mci *host = slot->host;
1396         const struct dw_mci_drv_data *drv_data = host->drv_data;
1397         u32 uhs;
1398         u32 v18 = SDMMC_UHS_18V << slot->id;
1399         int ret;
1400
1401         if (drv_data && drv_data->switch_voltage)
1402                 return drv_data->switch_voltage(mmc, ios);
1403
1404         /*
1405          * Program the voltage.  Note that some instances of dw_mmc may use
1406          * the UHS_REG for this.  For other instances (like exynos) the UHS_REG
1407          * does no harm but you need to set the regulator directly.  Try both.
1408          */
1409         uhs = mci_readl(host, UHS_REG);
1410         if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1411                 uhs &= ~v18;
1412         else
1413                 uhs |= v18;
1414
1415         if (!IS_ERR(mmc->supply.vqmmc)) {
1416                 ret = mmc_regulator_set_vqmmc(mmc, ios);
1417
1418                 if (ret) {
1419                         dev_dbg(&mmc->class_dev,
1420                                          "Regulator set error %d - %s V\n",
1421                                          ret, uhs & v18 ? "1.8" : "3.3");
1422                         return ret;
1423                 }
1424         }
1425         mci_writel(host, UHS_REG, uhs);
1426
1427         return 0;
1428 }
1429
1430 static int dw_mci_get_ro(struct mmc_host *mmc)
1431 {
1432         int read_only;
1433         struct dw_mci_slot *slot = mmc_priv(mmc);
1434         int gpio_ro = mmc_gpio_get_ro(mmc);
1435
1436         /* Use platform get_ro function, else try on board write protect */
1437         if (!IS_ERR_VALUE(gpio_ro))
1438                 read_only = gpio_ro;
1439         else
1440                 read_only =
1441                         mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
1442
1443         dev_dbg(&mmc->class_dev, "card is %s\n",
1444                 read_only ? "read-only" : "read-write");
1445
1446         return read_only;
1447 }
1448
1449 static int dw_mci_get_cd(struct mmc_host *mmc)
1450 {
1451         int present;
1452         struct dw_mci_slot *slot = mmc_priv(mmc);
1453         struct dw_mci_board *brd = slot->host->pdata;
1454         struct dw_mci *host = slot->host;
1455         int gpio_cd = mmc_gpio_get_cd(mmc);
1456
1457         /* Use platform get_cd function, else try onboard card detect */
1458         if ((brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION) ||
1459             (mmc->caps & MMC_CAP_NONREMOVABLE))
1460                 present = 1;
1461         else if (!IS_ERR_VALUE(gpio_cd))
1462                 present = gpio_cd;
1463         else
1464                 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
1465                         == 0 ? 1 : 0;
1466
1467         spin_lock_bh(&host->lock);
1468         if (present) {
1469                 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1470                 dev_dbg(&mmc->class_dev, "card is present\n");
1471         } else {
1472                 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1473                 dev_dbg(&mmc->class_dev, "card is not present\n");
1474         }
1475         spin_unlock_bh(&host->lock);
1476
1477         return present;
1478 }
1479
1480 static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card)
1481 {
1482         struct dw_mci_slot *slot = mmc_priv(mmc);
1483         struct dw_mci *host = slot->host;
1484
1485         /*
1486          * Low power mode will stop the card clock when idle.  According to the
1487          * description of the CLKENA register we should disable low power mode
1488          * for SDIO cards if we need SDIO interrupts to work.
1489          */
1490         if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1491                 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
1492                 u32 clk_en_a_old;
1493                 u32 clk_en_a;
1494
1495                 clk_en_a_old = mci_readl(host, CLKENA);
1496
1497                 if (card->type == MMC_TYPE_SDIO ||
1498                     card->type == MMC_TYPE_SD_COMBO) {
1499                         set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1500                         clk_en_a = clk_en_a_old & ~clken_low_pwr;
1501                 } else {
1502                         clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1503                         clk_en_a = clk_en_a_old | clken_low_pwr;
1504                 }
1505
1506                 if (clk_en_a != clk_en_a_old) {
1507                         mci_writel(host, CLKENA, clk_en_a);
1508                         mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
1509                                      SDMMC_CMD_PRV_DAT_WAIT, 0);
1510                 }
1511         }
1512 }
1513
1514 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
1515 {
1516         struct dw_mci_slot *slot = mmc_priv(mmc);
1517         struct dw_mci *host = slot->host;
1518         unsigned long irqflags;
1519         u32 int_mask;
1520
1521         spin_lock_irqsave(&host->irq_lock, irqflags);
1522
1523         /* Enable/disable Slot Specific SDIO interrupt */
1524         int_mask = mci_readl(host, INTMASK);
1525         if (enb)
1526                 int_mask |= SDMMC_INT_SDIO(slot->sdio_id);
1527         else
1528                 int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id);
1529         mci_writel(host, INTMASK, int_mask);
1530
1531         spin_unlock_irqrestore(&host->irq_lock, irqflags);
1532 }
1533
1534 static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1535 {
1536         struct dw_mci_slot *slot = mmc_priv(mmc);
1537         struct dw_mci *host = slot->host;
1538         const struct dw_mci_drv_data *drv_data = host->drv_data;
1539         int err = -EINVAL;
1540
1541         if (drv_data && drv_data->execute_tuning)
1542                 err = drv_data->execute_tuning(slot, opcode);
1543         return err;
1544 }
1545
1546 static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc,
1547                                        struct mmc_ios *ios)
1548 {
1549         struct dw_mci_slot *slot = mmc_priv(mmc);
1550         struct dw_mci *host = slot->host;
1551         const struct dw_mci_drv_data *drv_data = host->drv_data;
1552
1553         if (drv_data && drv_data->prepare_hs400_tuning)
1554                 return drv_data->prepare_hs400_tuning(host, ios);
1555
1556         return 0;
1557 }
1558
1559 static const struct mmc_host_ops dw_mci_ops = {
1560         .request                = dw_mci_request,
1561         .pre_req                = dw_mci_pre_req,
1562         .post_req               = dw_mci_post_req,
1563         .set_ios                = dw_mci_set_ios,
1564         .get_ro                 = dw_mci_get_ro,
1565         .get_cd                 = dw_mci_get_cd,
1566         .enable_sdio_irq        = dw_mci_enable_sdio_irq,
1567         .execute_tuning         = dw_mci_execute_tuning,
1568         .card_busy              = dw_mci_card_busy,
1569         .start_signal_voltage_switch = dw_mci_switch_voltage,
1570         .init_card              = dw_mci_init_card,
1571         .prepare_hs400_tuning   = dw_mci_prepare_hs400_tuning,
1572 };
1573
1574 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
1575         __releases(&host->lock)
1576         __acquires(&host->lock)
1577 {
1578         struct dw_mci_slot *slot;
1579         struct mmc_host *prev_mmc = host->cur_slot->mmc;
1580
1581         WARN_ON(host->cmd || host->data);
1582
1583         host->cur_slot->mrq = NULL;
1584         host->mrq = NULL;
1585         if (!list_empty(&host->queue)) {
1586                 slot = list_entry(host->queue.next,
1587                                   struct dw_mci_slot, queue_node);
1588                 list_del(&slot->queue_node);
1589                 dev_vdbg(host->dev, "list not empty: %s is next\n",
1590                          mmc_hostname(slot->mmc));
1591                 host->state = STATE_SENDING_CMD;
1592                 dw_mci_start_request(host, slot);
1593         } else {
1594                 dev_vdbg(host->dev, "list empty\n");
1595
1596                 if (host->state == STATE_SENDING_CMD11)
1597                         host->state = STATE_WAITING_CMD11_DONE;
1598                 else
1599                         host->state = STATE_IDLE;
1600         }
1601
1602         spin_unlock(&host->lock);
1603         mmc_request_done(prev_mmc, mrq);
1604         spin_lock(&host->lock);
1605 }
1606
1607 static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
1608 {
1609         u32 status = host->cmd_status;
1610
1611         host->cmd_status = 0;
1612
1613         /* Read the response from the card (up to 16 bytes) */
1614         if (cmd->flags & MMC_RSP_PRESENT) {
1615                 if (cmd->flags & MMC_RSP_136) {
1616                         cmd->resp[3] = mci_readl(host, RESP0);
1617                         cmd->resp[2] = mci_readl(host, RESP1);
1618                         cmd->resp[1] = mci_readl(host, RESP2);
1619                         cmd->resp[0] = mci_readl(host, RESP3);
1620                 } else {
1621                         cmd->resp[0] = mci_readl(host, RESP0);
1622                         cmd->resp[1] = 0;
1623                         cmd->resp[2] = 0;
1624                         cmd->resp[3] = 0;
1625                 }
1626         }
1627
1628         if (status & SDMMC_INT_RTO)
1629                 cmd->error = -ETIMEDOUT;
1630         else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
1631                 cmd->error = -EILSEQ;
1632         else if (status & SDMMC_INT_RESP_ERR)
1633                 cmd->error = -EIO;
1634         else
1635                 cmd->error = 0;
1636
1637         if (cmd->error) {
1638                 /* newer ip versions need a delay between retries */
1639                 if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY)
1640                         mdelay(20);
1641         }
1642
1643         return cmd->error;
1644 }
1645
1646 static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data)
1647 {
1648         u32 status = host->data_status;
1649
1650         if (status & DW_MCI_DATA_ERROR_FLAGS) {
1651                 if (status & SDMMC_INT_DRTO) {
1652                         data->error = -ETIMEDOUT;
1653                 } else if (status & SDMMC_INT_DCRC) {
1654                         data->error = -EILSEQ;
1655                 } else if (status & SDMMC_INT_EBE) {
1656                         if (host->dir_status ==
1657                                 DW_MCI_SEND_STATUS) {
1658                                 /*
1659                                  * No data CRC status was returned.
1660                                  * The number of bytes transferred
1661                                  * will be exaggerated in PIO mode.
1662                                  */
1663                                 data->bytes_xfered = 0;
1664                                 data->error = -ETIMEDOUT;
1665                         } else if (host->dir_status ==
1666                                         DW_MCI_RECV_STATUS) {
1667                                 data->error = -EIO;
1668                         }
1669                 } else {
1670                         /* SDMMC_INT_SBE is included */
1671                         data->error = -EIO;
1672                 }
1673
1674                 dev_dbg(host->dev, "data error, status 0x%08x\n", status);
1675
1676                 /*
1677                  * After an error, there may be data lingering
1678                  * in the FIFO
1679                  */
1680                 dw_mci_reset(host);
1681         } else {
1682                 data->bytes_xfered = data->blocks * data->blksz;
1683                 data->error = 0;
1684         }
1685
1686         return data->error;
1687 }
1688
1689 static void dw_mci_set_drto(struct dw_mci *host)
1690 {
1691         unsigned int drto_clks;
1692         unsigned int drto_ms;
1693
1694         drto_clks = mci_readl(host, TMOUT) >> 8;
1695         drto_ms = DIV_ROUND_UP(drto_clks, host->bus_hz / 1000);
1696
1697         /* add a bit spare time */
1698         drto_ms += 10;
1699
1700         mod_timer(&host->dto_timer, jiffies + msecs_to_jiffies(drto_ms));
1701 }
1702
1703 static void dw_mci_tasklet_func(unsigned long priv)
1704 {
1705         struct dw_mci *host = (struct dw_mci *)priv;
1706         struct mmc_data *data;
1707         struct mmc_command *cmd;
1708         struct mmc_request *mrq;
1709         enum dw_mci_state state;
1710         enum dw_mci_state prev_state;
1711         unsigned int err;
1712
1713         spin_lock(&host->lock);
1714
1715         state = host->state;
1716         data = host->data;
1717         mrq = host->mrq;
1718
1719         do {
1720                 prev_state = state;
1721
1722                 switch (state) {
1723                 case STATE_IDLE:
1724                 case STATE_WAITING_CMD11_DONE:
1725                         break;
1726
1727                 case STATE_SENDING_CMD11:
1728                 case STATE_SENDING_CMD:
1729                         if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1730                                                 &host->pending_events))
1731                                 break;
1732
1733                         cmd = host->cmd;
1734                         host->cmd = NULL;
1735                         set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
1736                         err = dw_mci_command_complete(host, cmd);
1737                         if (cmd == mrq->sbc && !err) {
1738                                 prev_state = state = STATE_SENDING_CMD;
1739                                 __dw_mci_start_request(host, host->cur_slot,
1740                                                        mrq->cmd);
1741                                 goto unlock;
1742                         }
1743
1744                         if (cmd->data && err) {
1745                                 /*
1746                                  * During UHS tuning sequence, sending the stop
1747                                  * command after the response CRC error would
1748                                  * throw the system into a confused state
1749                                  * causing all future tuning phases to report
1750                                  * failure.
1751                                  *
1752                                  * In such case controller will move into a data
1753                                  * transfer state after a response error or
1754                                  * response CRC error. Let's let that finish
1755                                  * before trying to send a stop, so we'll go to
1756                                  * STATE_SENDING_DATA.
1757                                  *
1758                                  * Although letting the data transfer take place
1759                                  * will waste a bit of time (we already know
1760                                  * the command was bad), it can't cause any
1761                                  * errors since it's possible it would have
1762                                  * taken place anyway if this tasklet got
1763                                  * delayed. Allowing the transfer to take place
1764                                  * avoids races and keeps things simple.
1765                                  */
1766                                 if (err != -ETIMEDOUT) {
1767                                         state = STATE_SENDING_DATA;
1768                                         continue;
1769                                 }
1770
1771                                 send_stop_abort(host, data);
1772                                 dw_mci_stop_dma(host);
1773                                 state = STATE_SENDING_STOP;
1774                                 break;
1775                         }
1776
1777                         if (!cmd->data || err) {
1778                                 dw_mci_request_end(host, mrq);
1779                                 goto unlock;
1780                         }
1781
1782                         prev_state = state = STATE_SENDING_DATA;
1783                         /* fall through */
1784
1785                 case STATE_SENDING_DATA:
1786                         /*
1787                          * We could get a data error and never a transfer
1788                          * complete so we'd better check for it here.
1789                          *
1790                          * Note that we don't really care if we also got a
1791                          * transfer complete; stopping the DMA and sending an
1792                          * abort won't hurt.
1793                          */
1794                         if (test_and_clear_bit(EVENT_DATA_ERROR,
1795                                                &host->pending_events)) {
1796                                 if (!(host->data_status & (SDMMC_INT_DRTO |
1797                                                            SDMMC_INT_EBE)))
1798                                         send_stop_abort(host, data);
1799                                 dw_mci_stop_dma(host);
1800                                 state = STATE_DATA_ERROR;
1801                                 break;
1802                         }
1803
1804                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1805                                                 &host->pending_events)) {
1806                                 /*
1807                                  * If all data-related interrupts don't come
1808                                  * within the given time in reading data state.
1809                                  */
1810                                 if ((host->quirks & DW_MCI_QUIRK_BROKEN_DTO) &&
1811                                     (host->dir_status == DW_MCI_RECV_STATUS))
1812                                         dw_mci_set_drto(host);
1813                                 break;
1814                         }
1815
1816                         set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
1817
1818                         /*
1819                          * Handle an EVENT_DATA_ERROR that might have shown up
1820                          * before the transfer completed.  This might not have
1821                          * been caught by the check above because the interrupt
1822                          * could have gone off between the previous check and
1823                          * the check for transfer complete.
1824                          *
1825                          * Technically this ought not be needed assuming we
1826                          * get a DATA_COMPLETE eventually (we'll notice the
1827                          * error and end the request), but it shouldn't hurt.
1828                          *
1829                          * This has the advantage of sending the stop command.
1830                          */
1831                         if (test_and_clear_bit(EVENT_DATA_ERROR,
1832                                                &host->pending_events)) {
1833                                 if (!(host->data_status & (SDMMC_INT_DRTO |
1834                                                            SDMMC_INT_EBE)))
1835                                         send_stop_abort(host, data);
1836                                 dw_mci_stop_dma(host);
1837                                 state = STATE_DATA_ERROR;
1838                                 break;
1839                         }
1840                         prev_state = state = STATE_DATA_BUSY;
1841
1842                         /* fall through */
1843
1844                 case STATE_DATA_BUSY:
1845                         if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
1846                                                 &host->pending_events)) {
1847                                 /*
1848                                  * If data error interrupt comes but data over
1849                                  * interrupt doesn't come within the given time.
1850                                  * in reading data state.
1851                                  */
1852                                 if ((host->quirks & DW_MCI_QUIRK_BROKEN_DTO) &&
1853                                     (host->dir_status == DW_MCI_RECV_STATUS))
1854                                         dw_mci_set_drto(host);
1855                                 break;
1856                         }
1857
1858                         host->data = NULL;
1859                         set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
1860                         err = dw_mci_data_complete(host, data);
1861
1862                         if (!err) {
1863                                 if (!data->stop || mrq->sbc) {
1864                                         if (mrq->sbc && data->stop)
1865                                                 data->stop->error = 0;
1866                                         dw_mci_request_end(host, mrq);
1867                                         goto unlock;
1868                                 }
1869
1870                                 /* stop command for open-ended transfer*/
1871                                 if (data->stop)
1872                                         send_stop_abort(host, data);
1873                         } else {
1874                                 /*
1875                                  * If we don't have a command complete now we'll
1876                                  * never get one since we just reset everything;
1877                                  * better end the request.
1878                                  *
1879                                  * If we do have a command complete we'll fall
1880                                  * through to the SENDING_STOP command and
1881                                  * everything will be peachy keen.
1882                                  */
1883                                 if (!test_bit(EVENT_CMD_COMPLETE,
1884                                               &host->pending_events)) {
1885                                         host->cmd = NULL;
1886                                         dw_mci_request_end(host, mrq);
1887                                         goto unlock;
1888                                 }
1889                         }
1890
1891                         /*
1892                          * If err has non-zero,
1893                          * stop-abort command has been already issued.
1894                          */
1895                         prev_state = state = STATE_SENDING_STOP;
1896
1897                         /* fall through */
1898
1899                 case STATE_SENDING_STOP:
1900                         if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1901                                                 &host->pending_events))
1902                                 break;
1903
1904                         /* CMD error in data command */
1905                         if (mrq->cmd->error && mrq->data)
1906                                 dw_mci_reset(host);
1907
1908                         host->cmd = NULL;
1909                         host->data = NULL;
1910
1911                         if (!mrq->sbc && mrq->stop)
1912                                 dw_mci_command_complete(host, mrq->stop);
1913                         else
1914                                 host->cmd_status = 0;
1915
1916                         dw_mci_request_end(host, mrq);
1917                         goto unlock;
1918
1919                 case STATE_DATA_ERROR:
1920                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1921                                                 &host->pending_events))
1922                                 break;
1923
1924                         state = STATE_DATA_BUSY;
1925                         break;
1926                 }
1927         } while (state != prev_state);
1928
1929         host->state = state;
1930 unlock:
1931         spin_unlock(&host->lock);
1932
1933 }
1934
1935 /* push final bytes to part_buf, only use during push */
1936 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
1937 {
1938         memcpy((void *)&host->part_buf, buf, cnt);
1939         host->part_buf_count = cnt;
1940 }
1941
1942 /* append bytes to part_buf, only use during push */
1943 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
1944 {
1945         cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
1946         memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
1947         host->part_buf_count += cnt;
1948         return cnt;
1949 }
1950
1951 /* pull first bytes from part_buf, only use during pull */
1952 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
1953 {
1954         cnt = min_t(int, cnt, host->part_buf_count);
1955         if (cnt) {
1956                 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
1957                        cnt);
1958                 host->part_buf_count -= cnt;
1959                 host->part_buf_start += cnt;
1960         }
1961         return cnt;
1962 }
1963
1964 /* pull final bytes from the part_buf, assuming it's just been filled */
1965 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
1966 {
1967         memcpy(buf, &host->part_buf, cnt);
1968         host->part_buf_start = cnt;
1969         host->part_buf_count = (1 << host->data_shift) - cnt;
1970 }
1971
1972 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
1973 {
1974         struct mmc_data *data = host->data;
1975         int init_cnt = cnt;
1976
1977         /* try and push anything in the part_buf */
1978         if (unlikely(host->part_buf_count)) {
1979                 int len = dw_mci_push_part_bytes(host, buf, cnt);
1980
1981                 buf += len;
1982                 cnt -= len;
1983                 if (host->part_buf_count == 2) {
1984                         mci_fifo_writew(host->fifo_reg, host->part_buf16);
1985                         host->part_buf_count = 0;
1986                 }
1987         }
1988 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1989         if (unlikely((unsigned long)buf & 0x1)) {
1990                 while (cnt >= 2) {
1991                         u16 aligned_buf[64];
1992                         int len = min(cnt & -2, (int)sizeof(aligned_buf));
1993                         int items = len >> 1;
1994                         int i;
1995                         /* memcpy from input buffer into aligned buffer */
1996                         memcpy(aligned_buf, buf, len);
1997                         buf += len;
1998                         cnt -= len;
1999                         /* push data from aligned buffer into fifo */
2000                         for (i = 0; i < items; ++i)
2001                                 mci_fifo_writew(host->fifo_reg, aligned_buf[i]);
2002                 }
2003         } else
2004 #endif
2005         {
2006                 u16 *pdata = buf;
2007
2008                 for (; cnt >= 2; cnt -= 2)
2009                         mci_fifo_writew(host->fifo_reg, *pdata++);
2010                 buf = pdata;
2011         }
2012         /* put anything remaining in the part_buf */
2013         if (cnt) {
2014                 dw_mci_set_part_bytes(host, buf, cnt);
2015                  /* Push data if we have reached the expected data length */
2016                 if ((data->bytes_xfered + init_cnt) ==
2017                     (data->blksz * data->blocks))
2018                         mci_fifo_writew(host->fifo_reg, host->part_buf16);
2019         }
2020 }
2021
2022 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
2023 {
2024 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2025         if (unlikely((unsigned long)buf & 0x1)) {
2026                 while (cnt >= 2) {
2027                         /* pull data from fifo into aligned buffer */
2028                         u16 aligned_buf[64];
2029                         int len = min(cnt & -2, (int)sizeof(aligned_buf));
2030                         int items = len >> 1;
2031                         int i;
2032
2033                         for (i = 0; i < items; ++i)
2034                                 aligned_buf[i] = mci_fifo_readw(host->fifo_reg);
2035                         /* memcpy from aligned buffer into output buffer */
2036                         memcpy(buf, aligned_buf, len);
2037                         buf += len;
2038                         cnt -= len;
2039                 }
2040         } else
2041 #endif
2042         {
2043                 u16 *pdata = buf;
2044
2045                 for (; cnt >= 2; cnt -= 2)
2046                         *pdata++ = mci_fifo_readw(host->fifo_reg);
2047                 buf = pdata;
2048         }
2049         if (cnt) {
2050                 host->part_buf16 = mci_fifo_readw(host->fifo_reg);
2051                 dw_mci_pull_final_bytes(host, buf, cnt);
2052         }
2053 }
2054
2055 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
2056 {
2057         struct mmc_data *data = host->data;
2058         int init_cnt = cnt;
2059
2060         /* try and push anything in the part_buf */
2061         if (unlikely(host->part_buf_count)) {
2062                 int len = dw_mci_push_part_bytes(host, buf, cnt);
2063
2064                 buf += len;
2065                 cnt -= len;
2066                 if (host->part_buf_count == 4) {
2067                         mci_fifo_writel(host->fifo_reg, host->part_buf32);
2068                         host->part_buf_count = 0;
2069                 }
2070         }
2071 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2072         if (unlikely((unsigned long)buf & 0x3)) {
2073                 while (cnt >= 4) {
2074                         u32 aligned_buf[32];
2075                         int len = min(cnt & -4, (int)sizeof(aligned_buf));
2076                         int items = len >> 2;
2077                         int i;
2078                         /* memcpy from input buffer into aligned buffer */
2079                         memcpy(aligned_buf, buf, len);
2080                         buf += len;
2081                         cnt -= len;
2082                         /* push data from aligned buffer into fifo */
2083                         for (i = 0; i < items; ++i)
2084                                 mci_fifo_writel(host->fifo_reg, aligned_buf[i]);
2085                 }
2086         } else
2087 #endif
2088         {
2089                 u32 *pdata = buf;
2090
2091                 for (; cnt >= 4; cnt -= 4)
2092                         mci_fifo_writel(host->fifo_reg, *pdata++);
2093                 buf = pdata;
2094         }
2095         /* put anything remaining in the part_buf */
2096         if (cnt) {
2097                 dw_mci_set_part_bytes(host, buf, cnt);
2098                  /* Push data if we have reached the expected data length */
2099                 if ((data->bytes_xfered + init_cnt) ==
2100                     (data->blksz * data->blocks))
2101                         mci_fifo_writel(host->fifo_reg, host->part_buf32);
2102         }
2103 }
2104
2105 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
2106 {
2107 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2108         if (unlikely((unsigned long)buf & 0x3)) {
2109                 while (cnt >= 4) {
2110                         /* pull data from fifo into aligned buffer */
2111                         u32 aligned_buf[32];
2112                         int len = min(cnt & -4, (int)sizeof(aligned_buf));
2113                         int items = len >> 2;
2114                         int i;
2115
2116                         for (i = 0; i < items; ++i)
2117                                 aligned_buf[i] = mci_fifo_readl(host->fifo_reg);
2118                         /* memcpy from aligned buffer into output buffer */
2119                         memcpy(buf, aligned_buf, len);
2120                         buf += len;
2121                         cnt -= len;
2122                 }
2123         } else
2124 #endif
2125         {
2126                 u32 *pdata = buf;
2127
2128                 for (; cnt >= 4; cnt -= 4)
2129                         *pdata++ = mci_fifo_readl(host->fifo_reg);
2130                 buf = pdata;
2131         }
2132         if (cnt) {
2133                 host->part_buf32 = mci_fifo_readl(host->fifo_reg);
2134                 dw_mci_pull_final_bytes(host, buf, cnt);
2135         }
2136 }
2137
2138 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
2139 {
2140         struct mmc_data *data = host->data;
2141         int init_cnt = cnt;
2142
2143         /* try and push anything in the part_buf */
2144         if (unlikely(host->part_buf_count)) {
2145                 int len = dw_mci_push_part_bytes(host, buf, cnt);
2146
2147                 buf += len;
2148                 cnt -= len;
2149
2150                 if (host->part_buf_count == 8) {
2151                         mci_fifo_writeq(host->fifo_reg, host->part_buf);
2152                         host->part_buf_count = 0;
2153                 }
2154         }
2155 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2156         if (unlikely((unsigned long)buf & 0x7)) {
2157                 while (cnt >= 8) {
2158                         u64 aligned_buf[16];
2159                         int len = min(cnt & -8, (int)sizeof(aligned_buf));
2160                         int items = len >> 3;
2161                         int i;
2162                         /* memcpy from input buffer into aligned buffer */
2163                         memcpy(aligned_buf, buf, len);
2164                         buf += len;
2165                         cnt -= len;
2166                         /* push data from aligned buffer into fifo */
2167                         for (i = 0; i < items; ++i)
2168                                 mci_fifo_writeq(host->fifo_reg, aligned_buf[i]);
2169                 }
2170         } else
2171 #endif
2172         {
2173                 u64 *pdata = buf;
2174
2175                 for (; cnt >= 8; cnt -= 8)
2176                         mci_fifo_writeq(host->fifo_reg, *pdata++);
2177                 buf = pdata;
2178         }
2179         /* put anything remaining in the part_buf */
2180         if (cnt) {
2181                 dw_mci_set_part_bytes(host, buf, cnt);
2182                 /* Push data if we have reached the expected data length */
2183                 if ((data->bytes_xfered + init_cnt) ==
2184                     (data->blksz * data->blocks))
2185                         mci_fifo_writeq(host->fifo_reg, host->part_buf);
2186         }
2187 }
2188
2189 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
2190 {
2191 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2192         if (unlikely((unsigned long)buf & 0x7)) {
2193                 while (cnt >= 8) {
2194                         /* pull data from fifo into aligned buffer */
2195                         u64 aligned_buf[16];
2196                         int len = min(cnt & -8, (int)sizeof(aligned_buf));
2197                         int items = len >> 3;
2198                         int i;
2199
2200                         for (i = 0; i < items; ++i)
2201                                 aligned_buf[i] = mci_fifo_readq(host->fifo_reg);
2202
2203                         /* memcpy from aligned buffer into output buffer */
2204                         memcpy(buf, aligned_buf, len);
2205                         buf += len;
2206                         cnt -= len;
2207                 }
2208         } else
2209 #endif
2210         {
2211                 u64 *pdata = buf;
2212
2213                 for (; cnt >= 8; cnt -= 8)
2214                         *pdata++ = mci_fifo_readq(host->fifo_reg);
2215                 buf = pdata;
2216         }
2217         if (cnt) {
2218                 host->part_buf = mci_fifo_readq(host->fifo_reg);
2219                 dw_mci_pull_final_bytes(host, buf, cnt);
2220         }
2221 }
2222
2223 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
2224 {
2225         int len;
2226
2227         /* get remaining partial bytes */
2228         len = dw_mci_pull_part_bytes(host, buf, cnt);
2229         if (unlikely(len == cnt))
2230                 return;
2231         buf += len;
2232         cnt -= len;
2233
2234         /* get the rest of the data */
2235         host->pull_data(host, buf, cnt);
2236 }
2237
2238 static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
2239 {
2240         struct sg_mapping_iter *sg_miter = &host->sg_miter;
2241         void *buf;
2242         unsigned int offset;
2243         struct mmc_data *data = host->data;
2244         int shift = host->data_shift;
2245         u32 status;
2246         unsigned int len;
2247         unsigned int remain, fcnt;
2248
2249         do {
2250                 if (!sg_miter_next(sg_miter))
2251                         goto done;
2252
2253                 host->sg = sg_miter->piter.sg;
2254                 buf = sg_miter->addr;
2255                 remain = sg_miter->length;
2256                 offset = 0;
2257
2258                 do {
2259                         fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
2260                                         << shift) + host->part_buf_count;
2261                         len = min(remain, fcnt);
2262                         if (!len)
2263                                 break;
2264                         dw_mci_pull_data(host, (void *)(buf + offset), len);
2265                         data->bytes_xfered += len;
2266                         offset += len;
2267                         remain -= len;
2268                 } while (remain);
2269
2270                 sg_miter->consumed = offset;
2271                 status = mci_readl(host, MINTSTS);
2272                 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2273         /* if the RXDR is ready read again */
2274         } while ((status & SDMMC_INT_RXDR) ||
2275                  (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
2276
2277         if (!remain) {
2278                 if (!sg_miter_next(sg_miter))
2279                         goto done;
2280                 sg_miter->consumed = 0;
2281         }
2282         sg_miter_stop(sg_miter);
2283         return;
2284
2285 done:
2286         sg_miter_stop(sg_miter);
2287         host->sg = NULL;
2288         smp_wmb(); /* drain writebuffer */
2289         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2290 }
2291
2292 static void dw_mci_write_data_pio(struct dw_mci *host)
2293 {
2294         struct sg_mapping_iter *sg_miter = &host->sg_miter;
2295         void *buf;
2296         unsigned int offset;
2297         struct mmc_data *data = host->data;
2298         int shift = host->data_shift;
2299         u32 status;
2300         unsigned int len;
2301         unsigned int fifo_depth = host->fifo_depth;
2302         unsigned int remain, fcnt;
2303
2304         do {
2305                 if (!sg_miter_next(sg_miter))
2306                         goto done;
2307
2308                 host->sg = sg_miter->piter.sg;
2309                 buf = sg_miter->addr;
2310                 remain = sg_miter->length;
2311                 offset = 0;
2312
2313                 do {
2314                         fcnt = ((fifo_depth -
2315                                  SDMMC_GET_FCNT(mci_readl(host, STATUS)))
2316                                         << shift) - host->part_buf_count;
2317                         len = min(remain, fcnt);
2318                         if (!len)
2319                                 break;
2320                         host->push_data(host, (void *)(buf + offset), len);
2321                         data->bytes_xfered += len;
2322                         offset += len;
2323                         remain -= len;
2324                 } while (remain);
2325
2326                 sg_miter->consumed = offset;
2327                 status = mci_readl(host, MINTSTS);
2328                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2329         } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
2330
2331         if (!remain) {
2332                 if (!sg_miter_next(sg_miter))
2333                         goto done;
2334                 sg_miter->consumed = 0;
2335         }
2336         sg_miter_stop(sg_miter);
2337         return;
2338
2339 done:
2340         sg_miter_stop(sg_miter);
2341         host->sg = NULL;
2342         smp_wmb(); /* drain writebuffer */
2343         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2344 }
2345
2346 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
2347 {
2348         if (!host->cmd_status)
2349                 host->cmd_status = status;
2350
2351         smp_wmb(); /* drain writebuffer */
2352
2353         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2354         tasklet_schedule(&host->tasklet);
2355 }
2356
2357 static void dw_mci_handle_cd(struct dw_mci *host)
2358 {
2359         int i;
2360
2361         for (i = 0; i < host->num_slots; i++) {
2362                 struct dw_mci_slot *slot = host->slot[i];
2363
2364                 if (!slot)
2365                         continue;
2366
2367                 if (slot->mmc->ops->card_event)
2368                         slot->mmc->ops->card_event(slot->mmc);
2369                 mmc_detect_change(slot->mmc,
2370                         msecs_to_jiffies(host->pdata->detect_delay_ms));
2371         }
2372 }
2373
2374 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
2375 {
2376         struct dw_mci *host = dev_id;
2377         u32 pending;
2378         int i;
2379
2380         pending = mci_readl(host, MINTSTS); /* read-only mask reg */
2381
2382         /*
2383          * DTO fix - version 2.10a and below, and only if internal DMA
2384          * is configured.
2385          */
2386         if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) {
2387                 if (!pending &&
2388                     ((mci_readl(host, STATUS) >> 17) & 0x1fff))
2389                         pending |= SDMMC_INT_DATA_OVER;
2390         }
2391
2392         if (pending) {
2393                 /* Check volt switch first, since it can look like an error */
2394                 if ((host->state == STATE_SENDING_CMD11) &&
2395                     (pending & SDMMC_INT_VOLT_SWITCH)) {
2396                         unsigned long irqflags;
2397
2398                         mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH);
2399                         pending &= ~SDMMC_INT_VOLT_SWITCH;
2400
2401                         /*
2402                          * Hold the lock; we know cmd11_timer can't be kicked
2403                          * off after the lock is released, so safe to delete.
2404                          */
2405                         spin_lock_irqsave(&host->irq_lock, irqflags);
2406                         dw_mci_cmd_interrupt(host, pending);
2407                         spin_unlock_irqrestore(&host->irq_lock, irqflags);
2408
2409                         del_timer(&host->cmd11_timer);
2410                 }
2411
2412                 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
2413                         mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
2414                         host->cmd_status = pending;
2415                         smp_wmb(); /* drain writebuffer */
2416                         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2417                 }
2418
2419                 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
2420                         /* if there is an error report DATA_ERROR */
2421                         mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
2422                         host->data_status = pending;
2423                         smp_wmb(); /* drain writebuffer */
2424                         set_bit(EVENT_DATA_ERROR, &host->pending_events);
2425                         tasklet_schedule(&host->tasklet);
2426                 }
2427
2428                 if (pending & SDMMC_INT_DATA_OVER) {
2429                         if (host->quirks & DW_MCI_QUIRK_BROKEN_DTO)
2430                                 del_timer(&host->dto_timer);
2431
2432                         mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
2433                         if (!host->data_status)
2434                                 host->data_status = pending;
2435                         smp_wmb(); /* drain writebuffer */
2436                         if (host->dir_status == DW_MCI_RECV_STATUS) {
2437                                 if (host->sg != NULL)
2438                                         dw_mci_read_data_pio(host, true);
2439                         }
2440                         set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2441                         tasklet_schedule(&host->tasklet);
2442                 }
2443
2444                 if (pending & SDMMC_INT_RXDR) {
2445                         mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2446                         if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
2447                                 dw_mci_read_data_pio(host, false);
2448                 }
2449
2450                 if (pending & SDMMC_INT_TXDR) {
2451                         mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2452                         if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
2453                                 dw_mci_write_data_pio(host);
2454                 }
2455
2456                 if (pending & SDMMC_INT_CMD_DONE) {
2457                         mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
2458                         dw_mci_cmd_interrupt(host, pending);
2459                 }
2460
2461                 if (pending & SDMMC_INT_CD) {
2462                         mci_writel(host, RINTSTS, SDMMC_INT_CD);
2463                         dw_mci_handle_cd(host);
2464                 }
2465
2466                 /* Handle SDIO Interrupts */
2467                 for (i = 0; i < host->num_slots; i++) {
2468                         struct dw_mci_slot *slot = host->slot[i];
2469
2470                         if (!slot)
2471                                 continue;
2472
2473                         if (pending & SDMMC_INT_SDIO(slot->sdio_id)) {
2474                                 mci_writel(host, RINTSTS,
2475                                            SDMMC_INT_SDIO(slot->sdio_id));
2476                                 mmc_signal_sdio_irq(slot->mmc);
2477                         }
2478                 }
2479
2480         }
2481
2482         if (host->use_dma != TRANS_MODE_IDMAC)
2483                 return IRQ_HANDLED;
2484
2485         /* Handle IDMA interrupts */
2486         if (host->dma_64bit_address == 1) {
2487                 pending = mci_readl(host, IDSTS64);
2488                 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2489                         mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI |
2490                                                         SDMMC_IDMAC_INT_RI);
2491                         mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI);
2492                         host->dma_ops->complete((void *)host);
2493                 }
2494         } else {
2495                 pending = mci_readl(host, IDSTS);
2496                 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2497                         mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI |
2498                                                         SDMMC_IDMAC_INT_RI);
2499                         mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
2500                         host->dma_ops->complete((void *)host);
2501                 }
2502         }
2503
2504         return IRQ_HANDLED;
2505 }
2506
2507 #ifdef CONFIG_OF
2508 /* given a slot, find out the device node representing that slot */
2509 static struct device_node *dw_mci_of_find_slot_node(struct dw_mci_slot *slot)
2510 {
2511         struct device *dev = slot->mmc->parent;
2512         struct device_node *np;
2513         const __be32 *addr;
2514         int len;
2515
2516         if (!dev || !dev->of_node)
2517                 return NULL;
2518
2519         for_each_child_of_node(dev->of_node, np) {
2520                 addr = of_get_property(np, "reg", &len);
2521                 if (!addr || (len < sizeof(int)))
2522                         continue;
2523                 if (be32_to_cpup(addr) == slot->id)
2524                         return np;
2525         }
2526         return NULL;
2527 }
2528
2529 static void dw_mci_slot_of_parse(struct dw_mci_slot *slot)
2530 {
2531         struct device_node *np = dw_mci_of_find_slot_node(slot);
2532
2533         if (!np)
2534                 return;
2535
2536         if (of_property_read_bool(np, "disable-wp")) {
2537                 slot->mmc->caps2 |= MMC_CAP2_NO_WRITE_PROTECT;
2538                 dev_warn(slot->mmc->parent,
2539                         "Slot quirk 'disable-wp' is deprecated\n");
2540         }
2541 }
2542 #else /* CONFIG_OF */
2543 static void dw_mci_slot_of_parse(struct dw_mci_slot *slot)
2544 {
2545 }
2546 #endif /* CONFIG_OF */
2547
2548 static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
2549 {
2550         struct mmc_host *mmc;
2551         struct dw_mci_slot *slot;
2552         const struct dw_mci_drv_data *drv_data = host->drv_data;
2553         int ctrl_id, ret;
2554         u32 freq[2];
2555
2556         mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
2557         if (!mmc)
2558                 return -ENOMEM;
2559
2560         slot = mmc_priv(mmc);
2561         slot->id = id;
2562         slot->sdio_id = host->sdio_id0 + id;
2563         slot->mmc = mmc;
2564         slot->host = host;
2565         host->slot[id] = slot;
2566
2567         mmc->ops = &dw_mci_ops;
2568         if (of_property_read_u32_array(host->dev->of_node,
2569                                        "clock-freq-min-max", freq, 2)) {
2570                 mmc->f_min = DW_MCI_FREQ_MIN;
2571                 mmc->f_max = DW_MCI_FREQ_MAX;
2572         } else {
2573                 mmc->f_min = freq[0];
2574                 mmc->f_max = freq[1];
2575         }
2576
2577         /*if there are external regulators, get them*/
2578         ret = mmc_regulator_get_supply(mmc);
2579         if (ret == -EPROBE_DEFER)
2580                 goto err_host_allocated;
2581
2582         if (!mmc->ocr_avail)
2583                 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
2584
2585         if (host->pdata->caps)
2586                 mmc->caps = host->pdata->caps;
2587
2588         if (host->pdata->pm_caps)
2589                 mmc->pm_caps = host->pdata->pm_caps;
2590
2591         if (host->dev->of_node) {
2592                 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
2593                 if (ctrl_id < 0)
2594                         ctrl_id = 0;
2595         } else {
2596                 ctrl_id = to_platform_device(host->dev)->id;
2597         }
2598         if (drv_data && drv_data->caps)
2599                 mmc->caps |= drv_data->caps[ctrl_id];
2600
2601         if (host->pdata->caps2)
2602                 mmc->caps2 = host->pdata->caps2;
2603
2604         dw_mci_slot_of_parse(slot);
2605
2606         ret = mmc_of_parse(mmc);
2607         if (ret)
2608                 goto err_host_allocated;
2609
2610         /* Useful defaults if platform data is unset. */
2611         if (host->use_dma == TRANS_MODE_IDMAC) {
2612                 mmc->max_segs = host->ring_size;
2613                 mmc->max_blk_size = 65536;
2614                 mmc->max_seg_size = 0x1000;
2615                 mmc->max_req_size = mmc->max_seg_size * host->ring_size;
2616                 mmc->max_blk_count = mmc->max_req_size / 512;
2617         } else if (host->use_dma == TRANS_MODE_EDMAC) {
2618                 mmc->max_segs = 64;
2619                 mmc->max_blk_size = 65536;
2620                 mmc->max_blk_count = 65535;
2621                 mmc->max_req_size =
2622                                 mmc->max_blk_size * mmc->max_blk_count;
2623                 mmc->max_seg_size = mmc->max_req_size;
2624         } else {
2625                 /* TRANS_MODE_PIO */
2626                 mmc->max_segs = 64;
2627                 mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
2628                 mmc->max_blk_count = 512;
2629                 mmc->max_req_size = mmc->max_blk_size *
2630                                     mmc->max_blk_count;
2631                 mmc->max_seg_size = mmc->max_req_size;
2632         }
2633
2634         if (dw_mci_get_cd(mmc))
2635                 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
2636         else
2637                 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
2638
2639         ret = mmc_add_host(mmc);
2640         if (ret)
2641                 goto err_host_allocated;
2642
2643 #if defined(CONFIG_DEBUG_FS)
2644         dw_mci_init_debugfs(slot);
2645 #endif
2646
2647         return 0;
2648
2649 err_host_allocated:
2650         mmc_free_host(mmc);
2651         return ret;
2652 }
2653
2654 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
2655 {
2656         /* Debugfs stuff is cleaned up by mmc core */
2657         mmc_remove_host(slot->mmc);
2658         slot->host->slot[id] = NULL;
2659         mmc_free_host(slot->mmc);
2660 }
2661
2662 static void dw_mci_init_dma(struct dw_mci *host)
2663 {
2664         int addr_config;
2665         struct device *dev = host->dev;
2666         struct device_node *np = dev->of_node;
2667
2668         /*
2669         * Check tansfer mode from HCON[17:16]
2670         * Clear the ambiguous description of dw_mmc databook:
2671         * 2b'00: No DMA Interface -> Actually means using Internal DMA block
2672         * 2b'01: DesignWare DMA Interface -> Synopsys DW-DMA block
2673         * 2b'10: Generic DMA Interface -> non-Synopsys generic DMA block
2674         * 2b'11: Non DW DMA Interface -> pio only
2675         * Compared to DesignWare DMA Interface, Generic DMA Interface has a
2676         * simpler request/acknowledge handshake mechanism and both of them
2677         * are regarded as external dma master for dw_mmc.
2678         */
2679         host->use_dma = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON));
2680         if (host->use_dma == DMA_INTERFACE_IDMA) {
2681                 host->use_dma = TRANS_MODE_IDMAC;
2682         } else if (host->use_dma == DMA_INTERFACE_DWDMA ||
2683                    host->use_dma == DMA_INTERFACE_GDMA) {
2684                 host->use_dma = TRANS_MODE_EDMAC;
2685         } else {
2686                 goto no_dma;
2687         }
2688
2689         /* Determine which DMA interface to use */
2690         if (host->use_dma == TRANS_MODE_IDMAC) {
2691                 /*
2692                 * Check ADDR_CONFIG bit in HCON to find
2693                 * IDMAC address bus width
2694                 */
2695                 addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON));
2696
2697                 if (addr_config == 1) {
2698                         /* host supports IDMAC in 64-bit address mode */
2699                         host->dma_64bit_address = 1;
2700                         dev_info(host->dev,
2701                                  "IDMAC supports 64-bit address mode.\n");
2702                         if (!dma_set_mask(host->dev, DMA_BIT_MASK(64)))
2703                                 dma_set_coherent_mask(host->dev,
2704                                                       DMA_BIT_MASK(64));
2705                 } else {
2706                         /* host supports IDMAC in 32-bit address mode */
2707                         host->dma_64bit_address = 0;
2708                         dev_info(host->dev,
2709                                  "IDMAC supports 32-bit address mode.\n");
2710                 }
2711
2712                 /* Alloc memory for sg translation */
2713                 host->sg_cpu = dmam_alloc_coherent(host->dev, PAGE_SIZE,
2714                                                    &host->sg_dma, GFP_KERNEL);
2715                 if (!host->sg_cpu) {
2716                         dev_err(host->dev,
2717                                 "%s: could not alloc DMA memory\n",
2718                                 __func__);
2719                         goto no_dma;
2720                 }
2721
2722                 host->dma_ops = &dw_mci_idmac_ops;
2723                 dev_info(host->dev, "Using internal DMA controller.\n");
2724         } else {
2725                 /* TRANS_MODE_EDMAC: check dma bindings again */
2726                 if ((of_property_count_strings(np, "dma-names") < 0) ||
2727                     (!of_find_property(np, "dmas", NULL))) {
2728                         goto no_dma;
2729                 }
2730                 host->dma_ops = &dw_mci_edmac_ops;
2731                 dev_info(host->dev, "Using external DMA controller.\n");
2732         }
2733
2734         if (host->dma_ops->init && host->dma_ops->start &&
2735             host->dma_ops->stop && host->dma_ops->cleanup) {
2736                 if (host->dma_ops->init(host)) {
2737                         dev_err(host->dev, "%s: Unable to initialize DMA Controller.\n",
2738                                 __func__);
2739                         goto no_dma;
2740                 }
2741         } else {
2742                 dev_err(host->dev, "DMA initialization not found.\n");
2743                 goto no_dma;
2744         }
2745
2746         return;
2747
2748 no_dma:
2749         dev_info(host->dev, "Using PIO mode.\n");
2750         host->use_dma = TRANS_MODE_PIO;
2751 }
2752
2753 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
2754 {
2755         unsigned long timeout = jiffies + msecs_to_jiffies(500);
2756         u32 ctrl;
2757
2758         ctrl = mci_readl(host, CTRL);
2759         ctrl |= reset;
2760         mci_writel(host, CTRL, ctrl);
2761
2762         /* wait till resets clear */
2763         do {
2764                 ctrl = mci_readl(host, CTRL);
2765                 if (!(ctrl & reset))
2766                         return true;
2767         } while (time_before(jiffies, timeout));
2768
2769         dev_err(host->dev,
2770                 "Timeout resetting block (ctrl reset %#x)\n",
2771                 ctrl & reset);
2772
2773         return false;
2774 }
2775
2776 static bool dw_mci_reset(struct dw_mci *host)
2777 {
2778         u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET;
2779         bool ret = false;
2780
2781         /*
2782          * Reseting generates a block interrupt, hence setting
2783          * the scatter-gather pointer to NULL.
2784          */
2785         if (host->sg) {
2786                 sg_miter_stop(&host->sg_miter);
2787                 host->sg = NULL;
2788         }
2789
2790         if (host->use_dma)
2791                 flags |= SDMMC_CTRL_DMA_RESET;
2792
2793         if (dw_mci_ctrl_reset(host, flags)) {
2794                 /*
2795                  * In all cases we clear the RAWINTS register to clear any
2796                  * interrupts.
2797                  */
2798                 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2799
2800                 /* if using dma we wait for dma_req to clear */
2801                 if (host->use_dma) {
2802                         unsigned long timeout = jiffies + msecs_to_jiffies(500);
2803                         u32 status;
2804
2805                         do {
2806                                 status = mci_readl(host, STATUS);
2807                                 if (!(status & SDMMC_STATUS_DMA_REQ))
2808                                         break;
2809                                 cpu_relax();
2810                         } while (time_before(jiffies, timeout));
2811
2812                         if (status & SDMMC_STATUS_DMA_REQ) {
2813                                 dev_err(host->dev,
2814                                         "%s: Timeout waiting for dma_req to clear during reset\n",
2815                                         __func__);
2816                                 goto ciu_out;
2817                         }
2818
2819                         /* when using DMA next we reset the fifo again */
2820                         if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET))
2821                                 goto ciu_out;
2822                 }
2823         } else {
2824                 /* if the controller reset bit did clear, then set clock regs */
2825                 if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) {
2826                         dev_err(host->dev,
2827                                 "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n",
2828                                 __func__);
2829                         goto ciu_out;
2830                 }
2831         }
2832
2833         if (host->use_dma == TRANS_MODE_IDMAC)
2834                 /* It is also required that we reinit idmac */
2835                 dw_mci_idmac_init(host);
2836
2837         ret = true;
2838
2839 ciu_out:
2840         /* After a CTRL reset we need to have CIU set clock registers  */
2841         mci_send_cmd(host->cur_slot, SDMMC_CMD_UPD_CLK, 0);
2842
2843         return ret;
2844 }
2845
2846 static void dw_mci_cmd11_timer(unsigned long arg)
2847 {
2848         struct dw_mci *host = (struct dw_mci *)arg;
2849
2850         if (host->state != STATE_SENDING_CMD11) {
2851                 dev_warn(host->dev, "Unexpected CMD11 timeout\n");
2852                 return;
2853         }
2854
2855         host->cmd_status = SDMMC_INT_RTO;
2856         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2857         tasklet_schedule(&host->tasklet);
2858 }
2859
2860 static void dw_mci_dto_timer(unsigned long arg)
2861 {
2862         struct dw_mci *host = (struct dw_mci *)arg;
2863
2864         switch (host->state) {
2865         case STATE_SENDING_DATA:
2866         case STATE_DATA_BUSY:
2867                 /*
2868                  * If DTO interrupt does NOT come in sending data state,
2869                  * we should notify the driver to terminate current transfer
2870                  * and report a data timeout to the core.
2871                  */
2872                 host->data_status = SDMMC_INT_DRTO;
2873                 set_bit(EVENT_DATA_ERROR, &host->pending_events);
2874                 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2875                 tasklet_schedule(&host->tasklet);
2876                 break;
2877         default:
2878                 break;
2879         }
2880 }
2881
2882 #ifdef CONFIG_OF
2883 static struct dw_mci_of_quirks {
2884         char *quirk;
2885         int id;
2886 } of_quirks[] = {
2887         {
2888                 .quirk  = "broken-cd",
2889                 .id     = DW_MCI_QUIRK_BROKEN_CARD_DETECTION,
2890         },
2891 };
2892
2893 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2894 {
2895         struct dw_mci_board *pdata;
2896         struct device *dev = host->dev;
2897         struct device_node *np = dev->of_node;
2898         const struct dw_mci_drv_data *drv_data = host->drv_data;
2899         int idx, ret;
2900         u32 clock_frequency;
2901
2902         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2903         if (!pdata)
2904                 return ERR_PTR(-ENOMEM);
2905
2906         /* find out number of slots supported */
2907         if (of_property_read_u32(dev->of_node, "num-slots",
2908                                 &pdata->num_slots)) {
2909                 dev_info(dev,
2910                          "num-slots property not found, assuming 1 slot is available\n");
2911                 pdata->num_slots = 1;
2912         }
2913
2914         /* get quirks */
2915         for (idx = 0; idx < ARRAY_SIZE(of_quirks); idx++)
2916                 if (of_get_property(np, of_quirks[idx].quirk, NULL))
2917                         pdata->quirks |= of_quirks[idx].id;
2918
2919         if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth))
2920                 dev_info(dev,
2921                          "fifo-depth property not found, using value of FIFOTH register as default\n");
2922
2923         of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms);
2924
2925         if (!of_property_read_u32(np, "clock-frequency", &clock_frequency))
2926                 pdata->bus_hz = clock_frequency;
2927
2928         if (drv_data && drv_data->parse_dt) {
2929                 ret = drv_data->parse_dt(host);
2930                 if (ret)
2931                         return ERR_PTR(ret);
2932         }
2933
2934         if (of_find_property(np, "supports-highspeed", NULL)) {
2935                 dev_info(dev, "supports-highspeed property is deprecated.\n");
2936                 pdata->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
2937         }
2938
2939         return pdata;
2940 }
2941
2942 #else /* CONFIG_OF */
2943 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2944 {
2945         return ERR_PTR(-EINVAL);
2946 }
2947 #endif /* CONFIG_OF */
2948
2949 static void dw_mci_enable_cd(struct dw_mci *host)
2950 {
2951         struct dw_mci_board *brd = host->pdata;
2952         unsigned long irqflags;
2953         u32 temp;
2954         int i;
2955
2956         /* No need for CD if broken card detection */
2957         if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
2958                 return;
2959
2960         /* No need for CD if all slots have a non-error GPIO */
2961         for (i = 0; i < host->num_slots; i++) {
2962                 struct dw_mci_slot *slot = host->slot[i];
2963
2964                 if (IS_ERR_VALUE(mmc_gpio_get_cd(slot->mmc)))
2965                         break;
2966         }
2967         if (i == host->num_slots)
2968                 return;
2969
2970         spin_lock_irqsave(&host->irq_lock, irqflags);
2971         temp = mci_readl(host, INTMASK);
2972         temp  |= SDMMC_INT_CD;
2973         mci_writel(host, INTMASK, temp);
2974         spin_unlock_irqrestore(&host->irq_lock, irqflags);
2975 }
2976
2977 int dw_mci_probe(struct dw_mci *host)
2978 {
2979         const struct dw_mci_drv_data *drv_data = host->drv_data;
2980         int width, i, ret = 0;
2981         u32 fifo_size;
2982         int init_slots = 0;
2983
2984         if (!host->pdata) {
2985                 host->pdata = dw_mci_parse_dt(host);
2986                 if (IS_ERR(host->pdata)) {
2987                         dev_err(host->dev, "platform data not available\n");
2988                         return -EINVAL;
2989                 }
2990         }
2991
2992         if (host->pdata->num_slots < 1) {
2993                 dev_err(host->dev,
2994                         "Platform data must supply num_slots.\n");
2995                 return -ENODEV;
2996         }
2997
2998         host->biu_clk = devm_clk_get(host->dev, "biu");
2999         if (IS_ERR(host->biu_clk)) {
3000                 dev_dbg(host->dev, "biu clock not available\n");
3001         } else {
3002                 ret = clk_prepare_enable(host->biu_clk);
3003                 if (ret) {
3004                         dev_err(host->dev, "failed to enable biu clock\n");
3005                         return ret;
3006                 }
3007         }
3008
3009         host->ciu_clk = devm_clk_get(host->dev, "ciu");
3010         if (IS_ERR(host->ciu_clk)) {
3011                 dev_dbg(host->dev, "ciu clock not available\n");
3012                 host->bus_hz = host->pdata->bus_hz;
3013         } else {
3014                 ret = clk_prepare_enable(host->ciu_clk);
3015                 if (ret) {
3016                         dev_err(host->dev, "failed to enable ciu clock\n");
3017                         goto err_clk_biu;
3018                 }
3019
3020                 if (host->pdata->bus_hz) {
3021                         ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz);
3022                         if (ret)
3023                                 dev_warn(host->dev,
3024                                          "Unable to set bus rate to %uHz\n",
3025                                          host->pdata->bus_hz);
3026                 }
3027                 host->bus_hz = clk_get_rate(host->ciu_clk);
3028         }
3029
3030         if (!host->bus_hz) {
3031                 dev_err(host->dev,
3032                         "Platform data must supply bus speed\n");
3033                 ret = -ENODEV;
3034                 goto err_clk_ciu;
3035         }
3036
3037         if (drv_data && drv_data->init) {
3038                 ret = drv_data->init(host);
3039                 if (ret) {
3040                         dev_err(host->dev,
3041                                 "implementation specific init failed\n");
3042                         goto err_clk_ciu;
3043                 }
3044         }
3045
3046         if (drv_data && drv_data->setup_clock) {
3047                 ret = drv_data->setup_clock(host);
3048                 if (ret) {
3049                         dev_err(host->dev,
3050                                 "implementation specific clock setup failed\n");
3051                         goto err_clk_ciu;
3052                 }
3053         }
3054
3055         setup_timer(&host->cmd11_timer,
3056                     dw_mci_cmd11_timer, (unsigned long)host);
3057
3058         host->quirks = host->pdata->quirks;
3059
3060         if (host->quirks & DW_MCI_QUIRK_BROKEN_DTO)
3061                 setup_timer(&host->dto_timer,
3062                             dw_mci_dto_timer, (unsigned long)host);
3063
3064         spin_lock_init(&host->lock);
3065         spin_lock_init(&host->irq_lock);
3066         INIT_LIST_HEAD(&host->queue);
3067
3068         /*
3069          * Get the host data width - this assumes that HCON has been set with
3070          * the correct values.
3071          */
3072         i = SDMMC_GET_HDATA_WIDTH(mci_readl(host, HCON));
3073         if (!i) {
3074                 host->push_data = dw_mci_push_data16;
3075                 host->pull_data = dw_mci_pull_data16;
3076                 width = 16;
3077                 host->data_shift = 1;
3078         } else if (i == 2) {
3079                 host->push_data = dw_mci_push_data64;
3080                 host->pull_data = dw_mci_pull_data64;
3081                 width = 64;
3082                 host->data_shift = 3;
3083         } else {
3084                 /* Check for a reserved value, and warn if it is */
3085                 WARN((i != 1),
3086                      "HCON reports a reserved host data width!\n"
3087                      "Defaulting to 32-bit access.\n");
3088                 host->push_data = dw_mci_push_data32;
3089                 host->pull_data = dw_mci_pull_data32;
3090                 width = 32;
3091                 host->data_shift = 2;
3092         }
3093
3094         /* Reset all blocks */
3095         if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS))
3096                 return -ENODEV;
3097
3098         host->dma_ops = host->pdata->dma_ops;
3099         dw_mci_init_dma(host);
3100
3101         /* Clear the interrupts for the host controller */
3102         mci_writel(host, RINTSTS, 0xFFFFFFFF);
3103         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3104
3105         /* Put in max timeout */
3106         mci_writel(host, TMOUT, 0xFFFFFFFF);
3107
3108         /*
3109          * FIFO threshold settings  RxMark  = fifo_size / 2 - 1,
3110          *                          Tx Mark = fifo_size / 2 DMA Size = 8
3111          */
3112         if (!host->pdata->fifo_depth) {
3113                 /*
3114                  * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
3115                  * have been overwritten by the bootloader, just like we're
3116                  * about to do, so if you know the value for your hardware, you
3117                  * should put it in the platform data.
3118                  */
3119                 fifo_size = mci_readl(host, FIFOTH);
3120                 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
3121         } else {
3122                 fifo_size = host->pdata->fifo_depth;
3123         }
3124         host->fifo_depth = fifo_size;
3125         host->fifoth_val =
3126                 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2);
3127         mci_writel(host, FIFOTH, host->fifoth_val);
3128
3129         /* disable clock to CIU */
3130         mci_writel(host, CLKENA, 0);
3131         mci_writel(host, CLKSRC, 0);
3132
3133         /*
3134          * In 2.40a spec, Data offset is changed.
3135          * Need to check the version-id and set data-offset for DATA register.
3136          */
3137         host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
3138         dev_info(host->dev, "Version ID is %04x\n", host->verid);
3139
3140         if (host->verid < DW_MMC_240A)
3141                 host->fifo_reg = host->regs + DATA_OFFSET;
3142         else
3143                 host->fifo_reg = host->regs + DATA_240A_OFFSET;
3144
3145         tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
3146         ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
3147                                host->irq_flags, "dw-mci", host);
3148         if (ret)
3149                 goto err_dmaunmap;
3150
3151         if (host->pdata->num_slots)
3152                 host->num_slots = host->pdata->num_slots;
3153         else
3154                 host->num_slots = SDMMC_GET_SLOT_NUM(mci_readl(host, HCON));
3155
3156         /*
3157          * Enable interrupts for command done, data over, data empty,
3158          * receive ready and error such as transmit, receive timeout, crc error
3159          */
3160         mci_writel(host, RINTSTS, 0xFFFFFFFF);
3161         mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3162                    SDMMC_INT_TXDR | SDMMC_INT_RXDR |
3163                    DW_MCI_ERROR_FLAGS);
3164         /* Enable mci interrupt */
3165         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3166
3167         dev_info(host->dev,
3168                  "DW MMC controller at irq %d,%d bit host data width,%u deep fifo\n",
3169                  host->irq, width, fifo_size);
3170
3171         /* We need at least one slot to succeed */
3172         for (i = 0; i < host->num_slots; i++) {
3173                 ret = dw_mci_init_slot(host, i);
3174                 if (ret)
3175                         dev_dbg(host->dev, "slot %d init failed\n", i);
3176                 else
3177                         init_slots++;
3178         }
3179
3180         if (init_slots) {
3181                 dev_info(host->dev, "%d slots initialized\n", init_slots);
3182         } else {
3183                 dev_dbg(host->dev,
3184                         "attempted to initialize %d slots, but failed on all\n",
3185                         host->num_slots);
3186                 goto err_dmaunmap;
3187         }
3188
3189         /* Now that slots are all setup, we can enable card detect */
3190         dw_mci_enable_cd(host);
3191
3192         if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO)
3193                 dev_info(host->dev, "Internal DMAC interrupt fix enabled.\n");
3194
3195         return 0;
3196
3197 err_dmaunmap:
3198         if (host->use_dma && host->dma_ops->exit)
3199                 host->dma_ops->exit(host);
3200
3201 err_clk_ciu:
3202         if (!IS_ERR(host->ciu_clk))
3203                 clk_disable_unprepare(host->ciu_clk);
3204
3205 err_clk_biu:
3206         if (!IS_ERR(host->biu_clk))
3207                 clk_disable_unprepare(host->biu_clk);
3208
3209         return ret;
3210 }
3211 EXPORT_SYMBOL(dw_mci_probe);
3212
3213 void dw_mci_remove(struct dw_mci *host)
3214 {
3215         int i;
3216
3217         for (i = 0; i < host->num_slots; i++) {
3218                 dev_dbg(host->dev, "remove slot %d\n", i);
3219                 if (host->slot[i])
3220                         dw_mci_cleanup_slot(host->slot[i], i);
3221         }
3222
3223         mci_writel(host, RINTSTS, 0xFFFFFFFF);
3224         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3225
3226         /* disable clock to CIU */
3227         mci_writel(host, CLKENA, 0);
3228         mci_writel(host, CLKSRC, 0);
3229
3230         if (host->use_dma && host->dma_ops->exit)
3231                 host->dma_ops->exit(host);
3232
3233         if (!IS_ERR(host->ciu_clk))
3234                 clk_disable_unprepare(host->ciu_clk);
3235
3236         if (!IS_ERR(host->biu_clk))
3237                 clk_disable_unprepare(host->biu_clk);
3238 }
3239 EXPORT_SYMBOL(dw_mci_remove);
3240
3241
3242
3243 #ifdef CONFIG_PM_SLEEP
3244 /*
3245  * TODO: we should probably disable the clock to the card in the suspend path.
3246  */
3247 int dw_mci_suspend(struct dw_mci *host)
3248 {
3249         if (host->use_dma && host->dma_ops->exit)
3250                 host->dma_ops->exit(host);
3251
3252         return 0;
3253 }
3254 EXPORT_SYMBOL(dw_mci_suspend);
3255
3256 int dw_mci_resume(struct dw_mci *host)
3257 {
3258         int i, ret;
3259
3260         if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
3261                 ret = -ENODEV;
3262                 return ret;
3263         }
3264
3265         if (host->use_dma && host->dma_ops->init)
3266                 host->dma_ops->init(host);
3267
3268         /*
3269          * Restore the initial value at FIFOTH register
3270          * And Invalidate the prev_blksz with zero
3271          */
3272         mci_writel(host, FIFOTH, host->fifoth_val);
3273         host->prev_blksz = 0;
3274
3275         /* Put in max timeout */
3276         mci_writel(host, TMOUT, 0xFFFFFFFF);
3277
3278         mci_writel(host, RINTSTS, 0xFFFFFFFF);
3279         mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3280                    SDMMC_INT_TXDR | SDMMC_INT_RXDR |
3281                    DW_MCI_ERROR_FLAGS);
3282         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3283
3284         for (i = 0; i < host->num_slots; i++) {
3285                 struct dw_mci_slot *slot = host->slot[i];
3286
3287                 if (!slot)
3288                         continue;
3289                 if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) {
3290                         dw_mci_set_ios(slot->mmc, &slot->mmc->ios);
3291                         dw_mci_setup_bus(slot, true);
3292                 }
3293         }
3294
3295         /* Now that slots are all setup, we can enable card detect */
3296         dw_mci_enable_cd(host);
3297
3298         return 0;
3299 }
3300 EXPORT_SYMBOL(dw_mci_resume);
3301 #endif /* CONFIG_PM_SLEEP */
3302
3303 static int __init dw_mci_init(void)
3304 {
3305         pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
3306         return 0;
3307 }
3308
3309 static void __exit dw_mci_exit(void)
3310 {
3311 }
3312
3313 module_init(dw_mci_init);
3314 module_exit(dw_mci_exit);
3315
3316 MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
3317 MODULE_AUTHOR("NXP Semiconductor VietNam");
3318 MODULE_AUTHOR("Imagination Technologies Ltd");
3319 MODULE_LICENSE("GPL v2");