2 * Exynos Specific Extensions for Synopsys DW Multimedia Card Interface driver
4 * Copyright (C) 2012, Samsung Electronics Co., Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
12 #include <linux/module.h>
13 #include <linux/platform_device.h>
14 #include <linux/clk.h>
15 #include <linux/mmc/host.h>
16 #include <linux/mmc/dw_mmc.h>
17 #include <linux/mmc/mmc.h>
19 #include <linux/of_gpio.h>
20 #include <linux/slab.h>
23 #include "dw_mmc-pltfm.h"
24 #include "dw_mmc-exynos.h"
26 /* Variations in Exynos specific dw-mshc controller */
27 enum dw_mci_exynos_type {
28 DW_MCI_TYPE_EXYNOS4210,
29 DW_MCI_TYPE_EXYNOS4412,
30 DW_MCI_TYPE_EXYNOS5250,
31 DW_MCI_TYPE_EXYNOS5420,
32 DW_MCI_TYPE_EXYNOS5420_SMU,
34 DW_MCI_TYPE_EXYNOS7_SMU,
37 /* Exynos implementation specific driver private data */
38 struct dw_mci_exynos_priv_data {
39 enum dw_mci_exynos_type ctrl_type;
48 u32 saved_strobe_ctrl;
51 static struct dw_mci_exynos_compatible {
53 enum dw_mci_exynos_type ctrl_type;
56 .compatible = "samsung,exynos4210-dw-mshc",
57 .ctrl_type = DW_MCI_TYPE_EXYNOS4210,
59 .compatible = "samsung,exynos4412-dw-mshc",
60 .ctrl_type = DW_MCI_TYPE_EXYNOS4412,
62 .compatible = "samsung,exynos5250-dw-mshc",
63 .ctrl_type = DW_MCI_TYPE_EXYNOS5250,
65 .compatible = "samsung,exynos5420-dw-mshc",
66 .ctrl_type = DW_MCI_TYPE_EXYNOS5420,
68 .compatible = "samsung,exynos5420-dw-mshc-smu",
69 .ctrl_type = DW_MCI_TYPE_EXYNOS5420_SMU,
71 .compatible = "samsung,exynos7-dw-mshc",
72 .ctrl_type = DW_MCI_TYPE_EXYNOS7,
74 .compatible = "samsung,exynos7-dw-mshc-smu",
75 .ctrl_type = DW_MCI_TYPE_EXYNOS7_SMU,
79 static inline u8 dw_mci_exynos_get_ciu_div(struct dw_mci *host)
81 struct dw_mci_exynos_priv_data *priv = host->priv;
83 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4412)
84 return EXYNOS4412_FIXED_CIU_CLK_DIV;
85 else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4210)
86 return EXYNOS4210_FIXED_CIU_CLK_DIV;
87 else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
88 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
89 return SDMMC_CLKSEL_GET_DIV(mci_readl(host, CLKSEL64)) + 1;
91 return SDMMC_CLKSEL_GET_DIV(mci_readl(host, CLKSEL)) + 1;
94 static void dw_mci_exynos_config_smu(struct dw_mci *host)
96 struct dw_mci_exynos_priv_data *priv = host->priv;
99 * If Exynos is provided the Security management,
100 * set for non-ecryption mode at this time.
102 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420_SMU ||
103 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) {
104 mci_writel(host, MPSBEGIN0, 0);
105 mci_writel(host, MPSEND0, SDMMC_ENDING_SEC_NR_MAX);
106 mci_writel(host, MPSCTRL0, SDMMC_MPSCTRL_SECURE_WRITE_BIT |
107 SDMMC_MPSCTRL_NON_SECURE_READ_BIT |
108 SDMMC_MPSCTRL_VALID |
109 SDMMC_MPSCTRL_NON_SECURE_WRITE_BIT);
113 static int dw_mci_exynos_priv_init(struct dw_mci *host)
115 struct dw_mci_exynos_priv_data *priv = host->priv;
117 dw_mci_exynos_config_smu(host);
119 if (priv->ctrl_type >= DW_MCI_TYPE_EXYNOS5420) {
120 priv->saved_strobe_ctrl = mci_readl(host, HS400_DLINE_CTRL);
121 priv->saved_dqs_en = mci_readl(host, HS400_DQS_EN);
122 priv->saved_dqs_en |= AXI_NON_BLOCKING_WR;
123 mci_writel(host, HS400_DQS_EN, priv->saved_dqs_en);
124 if (!priv->dqs_delay)
126 DQS_CTRL_GET_RD_DELAY(priv->saved_strobe_ctrl);
129 host->bus_hz /= (priv->ciu_div + 1);
134 static void dw_mci_exynos_set_clksel_timing(struct dw_mci *host, u32 timing)
136 struct dw_mci_exynos_priv_data *priv = host->priv;
139 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
140 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
141 clksel = mci_readl(host, CLKSEL64);
143 clksel = mci_readl(host, CLKSEL);
145 clksel = (clksel & ~SDMMC_CLKSEL_TIMING_MASK) | timing;
147 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
148 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
149 mci_writel(host, CLKSEL64, clksel);
151 mci_writel(host, CLKSEL, clksel);
154 * Exynos4412 and Exynos5250 extends the use of CMD register with the
155 * use of bit 29 (which is reserved on standard MSHC controllers) for
156 * optionally bypassing the HOLD register for command and data. The
157 * HOLD register should be bypassed in case there is no phase shift
158 * applied on CMD/DATA that is sent to the card.
160 if (!SDMMC_CLKSEL_GET_DRV_WD3(clksel) && host->cur_slot)
161 set_bit(DW_MMC_CARD_NO_USE_HOLD, &host->cur_slot->flags);
164 #ifdef CONFIG_PM_SLEEP
165 static int dw_mci_exynos_suspend(struct device *dev)
167 struct dw_mci *host = dev_get_drvdata(dev);
169 return dw_mci_suspend(host);
172 static int dw_mci_exynos_resume(struct device *dev)
174 struct dw_mci *host = dev_get_drvdata(dev);
176 dw_mci_exynos_config_smu(host);
177 return dw_mci_resume(host);
181 * dw_mci_exynos_resume_noirq - Exynos-specific resume code
183 * On exynos5420 there is a silicon errata that will sometimes leave the
184 * WAKEUP_INT bit in the CLKSEL register asserted. This bit is 1 to indicate
185 * that it fired and we can clear it by writing a 1 back. Clear it to prevent
186 * interrupts from going off constantly.
188 * We run this code on all exynos variants because it doesn't hurt.
191 static int dw_mci_exynos_resume_noirq(struct device *dev)
193 struct dw_mci *host = dev_get_drvdata(dev);
194 struct dw_mci_exynos_priv_data *priv = host->priv;
197 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
198 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
199 clksel = mci_readl(host, CLKSEL64);
201 clksel = mci_readl(host, CLKSEL);
203 if (clksel & SDMMC_CLKSEL_WAKEUP_INT) {
204 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
205 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
206 mci_writel(host, CLKSEL64, clksel);
208 mci_writel(host, CLKSEL, clksel);
214 #define dw_mci_exynos_suspend NULL
215 #define dw_mci_exynos_resume NULL
216 #define dw_mci_exynos_resume_noirq NULL
217 #endif /* CONFIG_PM_SLEEP */
219 static void dw_mci_exynos_config_hs400(struct dw_mci *host, u32 timing)
221 struct dw_mci_exynos_priv_data *priv = host->priv;
225 * Not supported to configure register
228 if (priv->ctrl_type < DW_MCI_TYPE_EXYNOS5420) {
229 if (timing == MMC_TIMING_MMC_HS400)
231 "cannot configure HS400, unsupported chipset\n");
235 dqs = priv->saved_dqs_en;
236 strobe = priv->saved_strobe_ctrl;
238 if (timing == MMC_TIMING_MMC_HS400) {
239 dqs |= DATA_STROBE_EN;
240 strobe = DQS_CTRL_RD_DELAY(strobe, priv->dqs_delay);
242 dqs &= ~DATA_STROBE_EN;
245 mci_writel(host, HS400_DQS_EN, dqs);
246 mci_writel(host, HS400_DLINE_CTRL, strobe);
249 static void dw_mci_exynos_adjust_clock(struct dw_mci *host, unsigned int wanted)
251 struct dw_mci_exynos_priv_data *priv = host->priv;
252 unsigned long actual;
256 * Don't care if wanted clock is zero or
257 * ciu clock is unavailable
259 if (!wanted || IS_ERR(host->ciu_clk))
262 /* Guaranteed minimum frequency for cclkin */
263 if (wanted < EXYNOS_CCLKIN_MIN)
264 wanted = EXYNOS_CCLKIN_MIN;
266 if (wanted == priv->cur_speed)
269 div = dw_mci_exynos_get_ciu_div(host);
270 ret = clk_set_rate(host->ciu_clk, wanted * div);
273 "failed to set clk-rate %u error: %d\n",
275 actual = clk_get_rate(host->ciu_clk);
276 host->bus_hz = actual / div;
277 priv->cur_speed = wanted;
278 host->current_speed = 0;
281 static void dw_mci_exynos_set_ios(struct dw_mci *host, struct mmc_ios *ios)
283 struct dw_mci_exynos_priv_data *priv = host->priv;
284 unsigned int wanted = ios->clock;
285 u32 timing = ios->timing, clksel;
288 case MMC_TIMING_MMC_HS400:
289 /* Update tuned sample timing */
290 clksel = SDMMC_CLKSEL_UP_SAMPLE(
291 priv->hs400_timing, priv->tuned_sample);
294 case MMC_TIMING_MMC_DDR52:
295 clksel = priv->ddr_timing;
296 /* Should be double rate for DDR mode */
297 if (ios->bus_width == MMC_BUS_WIDTH_8)
301 clksel = priv->sdr_timing;
304 /* Set clock timing for the requested speed mode*/
305 dw_mci_exynos_set_clksel_timing(host, clksel);
307 /* Configure setting for HS400 */
308 dw_mci_exynos_config_hs400(host, timing);
310 /* Configure clock rate */
311 dw_mci_exynos_adjust_clock(host, wanted);
314 static int dw_mci_exynos_parse_dt(struct dw_mci *host)
316 struct dw_mci_exynos_priv_data *priv;
317 struct device_node *np = host->dev->of_node;
323 priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
327 for (idx = 0; idx < ARRAY_SIZE(exynos_compat); idx++) {
328 if (of_device_is_compatible(np, exynos_compat[idx].compatible))
329 priv->ctrl_type = exynos_compat[idx].ctrl_type;
332 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4412)
333 priv->ciu_div = EXYNOS4412_FIXED_CIU_CLK_DIV - 1;
334 else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4210)
335 priv->ciu_div = EXYNOS4210_FIXED_CIU_CLK_DIV - 1;
337 of_property_read_u32(np, "samsung,dw-mshc-ciu-div", &div);
341 ret = of_property_read_u32_array(np,
342 "samsung,dw-mshc-sdr-timing", timing, 2);
346 priv->sdr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
348 ret = of_property_read_u32_array(np,
349 "samsung,dw-mshc-ddr-timing", timing, 2);
353 priv->ddr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
355 ret = of_property_read_u32_array(np,
356 "samsung,dw-mshc-hs400-timing", timing, 2);
357 if (!ret && of_property_read_u32(np,
358 "samsung,read-strobe-delay", &priv->dqs_delay))
360 "read-strobe-delay is not found, assuming usage of default value\n");
362 priv->hs400_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1],
363 HS400_FIXED_CIU_CLK_DIV);
368 static inline u8 dw_mci_exynos_get_clksmpl(struct dw_mci *host)
370 struct dw_mci_exynos_priv_data *priv = host->priv;
372 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
373 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
374 return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL64));
376 return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL));
379 static inline void dw_mci_exynos_set_clksmpl(struct dw_mci *host, u8 sample)
382 struct dw_mci_exynos_priv_data *priv = host->priv;
384 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
385 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
386 clksel = mci_readl(host, CLKSEL64);
388 clksel = mci_readl(host, CLKSEL);
389 clksel = SDMMC_CLKSEL_UP_SAMPLE(clksel, sample);
390 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
391 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
392 mci_writel(host, CLKSEL64, clksel);
394 mci_writel(host, CLKSEL, clksel);
397 static inline u8 dw_mci_exynos_move_next_clksmpl(struct dw_mci *host)
399 struct dw_mci_exynos_priv_data *priv = host->priv;
403 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
404 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
405 clksel = mci_readl(host, CLKSEL64);
407 clksel = mci_readl(host, CLKSEL);
409 sample = (clksel + 1) & 0x7;
410 clksel = SDMMC_CLKSEL_UP_SAMPLE(clksel, sample);
412 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
413 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
414 mci_writel(host, CLKSEL64, clksel);
416 mci_writel(host, CLKSEL, clksel);
421 static s8 dw_mci_exynos_get_best_clksmpl(u8 candiates)
427 for (i = 0; i < iter; i++) {
428 __c = ror8(candiates, i);
429 if ((__c & 0xc7) == 0xc7) {
435 for (i = 0; i < iter; i++) {
436 __c = ror8(candiates, i);
437 if ((__c & 0x83) == 0x83) {
444 * If there is no cadiates value, then it needs to return -EIO.
445 * If there are candiates values and don't find bset clk sample value,
446 * then use a first candiates clock sample value.
448 for (i = 0; i < iter; i++) {
449 __c = ror8(candiates, i);
450 if ((__c & 0x1) == 0x1) {
459 static int dw_mci_exynos_execute_tuning(struct dw_mci_slot *slot, u32 opcode)
461 struct dw_mci *host = slot->host;
462 struct dw_mci_exynos_priv_data *priv = host->priv;
463 struct mmc_host *mmc = slot->mmc;
464 u8 start_smpl, smpl, candiates = 0;
468 start_smpl = dw_mci_exynos_get_clksmpl(host);
471 mci_writel(host, TMOUT, ~0);
472 smpl = dw_mci_exynos_move_next_clksmpl(host);
474 if (!mmc_send_tuning(mmc, opcode, NULL))
475 candiates |= (1 << smpl);
477 } while (start_smpl != smpl);
479 found = dw_mci_exynos_get_best_clksmpl(candiates);
481 dw_mci_exynos_set_clksmpl(host, found);
482 priv->tuned_sample = found;
485 dev_warn(&mmc->class_dev,
486 "There is no candiates value about clksmpl!\n");
492 static int dw_mci_exynos_prepare_hs400_tuning(struct dw_mci *host,
495 struct dw_mci_exynos_priv_data *priv = host->priv;
497 dw_mci_exynos_set_clksel_timing(host, priv->hs400_timing);
498 dw_mci_exynos_adjust_clock(host, (ios->clock) << 1);
503 /* Common capabilities of Exynos4/Exynos5 SoC */
504 static unsigned long exynos_dwmmc_caps[4] = {
505 MMC_CAP_1_8V_DDR | MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23,
511 static const struct dw_mci_drv_data exynos_drv_data = {
512 .caps = exynos_dwmmc_caps,
513 .init = dw_mci_exynos_priv_init,
514 .set_ios = dw_mci_exynos_set_ios,
515 .parse_dt = dw_mci_exynos_parse_dt,
516 .execute_tuning = dw_mci_exynos_execute_tuning,
517 .prepare_hs400_tuning = dw_mci_exynos_prepare_hs400_tuning,
520 static const struct of_device_id dw_mci_exynos_match[] = {
521 { .compatible = "samsung,exynos4412-dw-mshc",
522 .data = &exynos_drv_data, },
523 { .compatible = "samsung,exynos5250-dw-mshc",
524 .data = &exynos_drv_data, },
525 { .compatible = "samsung,exynos5420-dw-mshc",
526 .data = &exynos_drv_data, },
527 { .compatible = "samsung,exynos5420-dw-mshc-smu",
528 .data = &exynos_drv_data, },
529 { .compatible = "samsung,exynos7-dw-mshc",
530 .data = &exynos_drv_data, },
531 { .compatible = "samsung,exynos7-dw-mshc-smu",
532 .data = &exynos_drv_data, },
535 MODULE_DEVICE_TABLE(of, dw_mci_exynos_match);
537 static int dw_mci_exynos_probe(struct platform_device *pdev)
539 const struct dw_mci_drv_data *drv_data;
540 const struct of_device_id *match;
542 match = of_match_node(dw_mci_exynos_match, pdev->dev.of_node);
543 drv_data = match->data;
544 return dw_mci_pltfm_register(pdev, drv_data);
547 static const struct dev_pm_ops dw_mci_exynos_pmops = {
548 SET_SYSTEM_SLEEP_PM_OPS(dw_mci_exynos_suspend, dw_mci_exynos_resume)
549 .resume_noirq = dw_mci_exynos_resume_noirq,
550 .thaw_noirq = dw_mci_exynos_resume_noirq,
551 .restore_noirq = dw_mci_exynos_resume_noirq,
554 static struct platform_driver dw_mci_exynos_pltfm_driver = {
555 .probe = dw_mci_exynos_probe,
556 .remove = dw_mci_pltfm_remove,
558 .name = "dwmmc_exynos",
559 .of_match_table = dw_mci_exynos_match,
560 .pm = &dw_mci_exynos_pmops,
564 module_platform_driver(dw_mci_exynos_pltfm_driver);
566 MODULE_DESCRIPTION("Samsung Specific DW-MSHC Driver Extension");
567 MODULE_AUTHOR("Thomas Abraham <thomas.ab@samsung.com");
568 MODULE_LICENSE("GPL v2");
569 MODULE_ALIAS("platform:dwmmc_exynos");