drivers/mmc/host/dw_mmc-exynos.c

   1 /*
   2  * Exynos Specific Extensions for Synopsys DW Multimedia Card Interface driver
   3  *
   4  * Copyright (C) 2012, Samsung Electronics Co., Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/clk.h>
  15 #include <linux/mmc/host.h>
  16 #include <linux/mmc/mmc.h>
  17 #include <linux/of.h>
  18 #include <linux/of_gpio.h>
  19 #include <linux/pm_runtime.h>
  20 #include <linux/slab.h>
  21
  22 #include "dw_mmc.h"
  23 #include "dw_mmc-pltfm.h"
  24 #include "dw_mmc-exynos.h"
  25
  26 /* Variations in Exynos specific dw-mshc controller */
  27 enum dw_mci_exynos_type {
  28         DW_MCI_TYPE_EXYNOS4210,
  29         DW_MCI_TYPE_EXYNOS4412,
  30         DW_MCI_TYPE_EXYNOS5250,
  31         DW_MCI_TYPE_EXYNOS5420,
  32         DW_MCI_TYPE_EXYNOS5420_SMU,
  33         DW_MCI_TYPE_EXYNOS7,
  34         DW_MCI_TYPE_EXYNOS7_SMU,
  35 };
  36
  37 /* Exynos implementation specific driver private data */
  38 struct dw_mci_exynos_priv_data {
  39         enum dw_mci_exynos_type         ctrl_type;
  40         u8                              ciu_div;
  41         u32                             sdr_timing;
  42         u32                             ddr_timing;
  43         u32                             hs400_timing;
  44         u32                             tuned_sample;
  45         u32                             cur_speed;
  46         u32                             dqs_delay;
  47         u32                             saved_dqs_en;
  48         u32                             saved_strobe_ctrl;
  49 };
  50
  51 static struct dw_mci_exynos_compatible {
  52         char                            *compatible;
  53         enum dw_mci_exynos_type         ctrl_type;
  54 } exynos_compat[] = {
  55         {
  56                 .compatible     = "samsung,exynos4210-dw-mshc",
  57                 .ctrl_type      = DW_MCI_TYPE_EXYNOS4210,
  58         }, {
  59                 .compatible     = "samsung,exynos4412-dw-mshc",
  60                 .ctrl_type      = DW_MCI_TYPE_EXYNOS4412,
  61         }, {
  62                 .compatible     = "samsung,exynos5250-dw-mshc",
  63                 .ctrl_type      = DW_MCI_TYPE_EXYNOS5250,
  64         }, {
  65                 .compatible     = "samsung,exynos5420-dw-mshc",
  66                 .ctrl_type      = DW_MCI_TYPE_EXYNOS5420,
  67         }, {
  68                 .compatible     = "samsung,exynos5420-dw-mshc-smu",
  69                 .ctrl_type      = DW_MCI_TYPE_EXYNOS5420_SMU,
  70         }, {
  71                 .compatible     = "samsung,exynos7-dw-mshc",
  72                 .ctrl_type      = DW_MCI_TYPE_EXYNOS7,
  73         }, {
  74                 .compatible     = "samsung,exynos7-dw-mshc-smu",
  75                 .ctrl_type      = DW_MCI_TYPE_EXYNOS7_SMU,
  76         },
  77 };
  78
  79 static inline u8 dw_mci_exynos_get_ciu_div(struct dw_mci *host)
  80 {
  81         struct dw_mci_exynos_priv_data *priv = host->priv;
  82
  83         if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4412)
  84                 return EXYNOS4412_FIXED_CIU_CLK_DIV;
  85         else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4210)
  86                 return EXYNOS4210_FIXED_CIU_CLK_DIV;
  87         else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
  88                         priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
  89                 return SDMMC_CLKSEL_GET_DIV(mci_readl(host, CLKSEL64)) + 1;
  90         else
  91                 return SDMMC_CLKSEL_GET_DIV(mci_readl(host, CLKSEL)) + 1;
  92 }
  93
  94 static void dw_mci_exynos_config_smu(struct dw_mci *host)
  95 {
  96         struct dw_mci_exynos_priv_data *priv = host->priv;
  97
  98         /*
  99          * If Exynos is provided the Security management,
 100          * set for non-ecryption mode at this time.
 101          */
 102         if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420_SMU ||
 103                 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) {
 104                 mci_writel(host, MPSBEGIN0, 0);
 105                 mci_writel(host, MPSEND0, SDMMC_ENDING_SEC_NR_MAX);
 106                 mci_writel(host, MPSCTRL0, SDMMC_MPSCTRL_SECURE_WRITE_BIT |
 107                            SDMMC_MPSCTRL_NON_SECURE_READ_BIT |
 108                            SDMMC_MPSCTRL_VALID |
 109                            SDMMC_MPSCTRL_NON_SECURE_WRITE_BIT);
 110         }
 111 }
 112
 113 static int dw_mci_exynos_priv_init(struct dw_mci *host)
 114 {
 115         struct dw_mci_exynos_priv_data *priv = host->priv;
 116
 117         dw_mci_exynos_config_smu(host);
 118
 119         if (priv->ctrl_type >= DW_MCI_TYPE_EXYNOS5420) {
 120                 priv->saved_strobe_ctrl = mci_readl(host, HS400_DLINE_CTRL);
 121                 priv->saved_dqs_en = mci_readl(host, HS400_DQS_EN);
 122                 priv->saved_dqs_en |= AXI_NON_BLOCKING_WR;
 123                 mci_writel(host, HS400_DQS_EN, priv->saved_dqs_en);
 124                 if (!priv->dqs_delay)
 125                         priv->dqs_delay =
 126                                 DQS_CTRL_GET_RD_DELAY(priv->saved_strobe_ctrl);
 127         }
 128
 129         host->bus_hz /= (priv->ciu_div + 1);
 130
 131         return 0;
 132 }
 133
 134 static void dw_mci_exynos_set_clksel_timing(struct dw_mci *host, u32 timing)
 135 {
 136         struct dw_mci_exynos_priv_data *priv = host->priv;
 137         u32 clksel;
 138
 139         if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
 140                 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
 141                 clksel = mci_readl(host, CLKSEL64);
 142         else
 143                 clksel = mci_readl(host, CLKSEL);
 144
 145         clksel = (clksel & ~SDMMC_CLKSEL_TIMING_MASK) | timing;
 146
 147         if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
 148                 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
 149                 mci_writel(host, CLKSEL64, clksel);
 150         else
 151                 mci_writel(host, CLKSEL, clksel);
 152
 153         /*
 154          * Exynos4412 and Exynos5250 extends the use of CMD register with the
 155          * use of bit 29 (which is reserved on standard MSHC controllers) for
 156          * optionally bypassing the HOLD register for command and data. The
 157          * HOLD register should be bypassed in case there is no phase shift
 158          * applied on CMD/DATA that is sent to the card.
 159          */
 160         if (!SDMMC_CLKSEL_GET_DRV_WD3(clksel) && host->slot)
 161                 set_bit(DW_MMC_CARD_NO_USE_HOLD, &host->slot->flags);
 162 }
 163
 164 #ifdef CONFIG_PM
 165 static int dw_mci_exynos_runtime_resume(struct device *dev)
 166 {
 167         struct dw_mci *host = dev_get_drvdata(dev);
 168         int ret;
 169
 170         ret = dw_mci_runtime_resume(dev);
 171         if (ret)
 172                 return ret;
 173
 174         dw_mci_exynos_config_smu(host);
 175
 176         return ret;
 177 }
 178 #endif /* CONFIG_PM */
 179
 180 #ifdef CONFIG_PM_SLEEP
 181 /**
 182  * dw_mci_exynos_suspend_noirq - Exynos-specific suspend code
 183  *
 184  * This ensures that device will be in runtime active state in
 185  * dw_mci_exynos_resume_noirq after calling pm_runtime_force_resume()
 186  */
 187 static int dw_mci_exynos_suspend_noirq(struct device *dev)
 188 {
 189         pm_runtime_get_noresume(dev);
 190         return pm_runtime_force_suspend(dev);
 191 }
 192
 193 /**
 194  * dw_mci_exynos_resume_noirq - Exynos-specific resume code
 195  *
 196  * On exynos5420 there is a silicon errata that will sometimes leave the
 197  * WAKEUP_INT bit in the CLKSEL register asserted.  This bit is 1 to indicate
 198  * that it fired and we can clear it by writing a 1 back.  Clear it to prevent
 199  * interrupts from going off constantly.
 200  *
 201  * We run this code on all exynos variants because it doesn't hurt.
 202  */
 203 static int dw_mci_exynos_resume_noirq(struct device *dev)
 204 {
 205         struct dw_mci *host = dev_get_drvdata(dev);
 206         struct dw_mci_exynos_priv_data *priv = host->priv;
 207         u32 clksel;
 208         int ret;
 209
 210         ret = pm_runtime_force_resume(dev);
 211         if (ret)
 212                 return ret;
 213
 214         if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
 215                 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
 216                 clksel = mci_readl(host, CLKSEL64);
 217         else
 218                 clksel = mci_readl(host, CLKSEL);
 219
 220         if (clksel & SDMMC_CLKSEL_WAKEUP_INT) {
 221                 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
 222                         priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
 223                         mci_writel(host, CLKSEL64, clksel);
 224                 else
 225                         mci_writel(host, CLKSEL, clksel);
 226         }
 227
 228         pm_runtime_put(dev);
 229
 230         return 0;
 231 }
 232 #endif /* CONFIG_PM_SLEEP */
 233
 234 static void dw_mci_exynos_config_hs400(struct dw_mci *host, u32 timing)
 235 {
 236         struct dw_mci_exynos_priv_data *priv = host->priv;
 237         u32 dqs, strobe;
 238
 239         /*
 240          * Not supported to configure register
 241          * related to HS400
 242          */
 243         if (priv->ctrl_type < DW_MCI_TYPE_EXYNOS5420) {
 244                 if (timing == MMC_TIMING_MMC_HS400)
 245                         dev_warn(host->dev,
 246                                  "cannot configure HS400, unsupported chipset\n");
 247                 return;
 248         }
 249
 250         dqs = priv->saved_dqs_en;
 251         strobe = priv->saved_strobe_ctrl;
 252
 253         if (timing == MMC_TIMING_MMC_HS400) {
 254                 dqs |= DATA_STROBE_EN;
 255                 strobe = DQS_CTRL_RD_DELAY(strobe, priv->dqs_delay);
 256         } else {
 257                 dqs &= ~DATA_STROBE_EN;
 258         }
 259
 260         mci_writel(host, HS400_DQS_EN, dqs);
 261         mci_writel(host, HS400_DLINE_CTRL, strobe);
 262 }
 263
 264 static void dw_mci_exynos_adjust_clock(struct dw_mci *host, unsigned int wanted)
 265 {
 266         struct dw_mci_exynos_priv_data *priv = host->priv;
 267         unsigned long actual;
 268         u8 div;
 269         int ret;
 270         /*
 271          * Don't care if wanted clock is zero or
 272          * ciu clock is unavailable
 273          */
 274         if (!wanted || IS_ERR(host->ciu_clk))
 275                 return;
 276
 277         /* Guaranteed minimum frequency for cclkin */
 278         if (wanted < EXYNOS_CCLKIN_MIN)
 279                 wanted = EXYNOS_CCLKIN_MIN;
 280
 281         if (wanted == priv->cur_speed)
 282                 return;
 283
 284         div = dw_mci_exynos_get_ciu_div(host);
 285         ret = clk_set_rate(host->ciu_clk, wanted * div);
 286         if (ret)
 287                 dev_warn(host->dev,
 288                         "failed to set clk-rate %u error: %d\n",
 289                         wanted * div, ret);
 290         actual = clk_get_rate(host->ciu_clk);
 291         host->bus_hz = actual / div;
 292         priv->cur_speed = wanted;
 293         host->current_speed = 0;
 294 }
 295
 296 static void dw_mci_exynos_set_ios(struct dw_mci *host, struct mmc_ios *ios)
 297 {
 298         struct dw_mci_exynos_priv_data *priv = host->priv;
 299         unsigned int wanted = ios->clock;
 300         u32 timing = ios->timing, clksel;
 301
 302         switch (timing) {
 303         case MMC_TIMING_MMC_HS400:
 304                 /* Update tuned sample timing */
 305                 clksel = SDMMC_CLKSEL_UP_SAMPLE(
 306                                 priv->hs400_timing, priv->tuned_sample);
 307                 wanted <<= 1;
 308                 break;
 309         case MMC_TIMING_MMC_DDR52:
 310                 clksel = priv->ddr_timing;
 311                 /* Should be double rate for DDR mode */
 312                 if (ios->bus_width == MMC_BUS_WIDTH_8)
 313                         wanted <<= 1;
 314                 break;
 315         default:
 316                 clksel = priv->sdr_timing;
 317         }
 318
 319         /* Set clock timing for the requested speed mode*/
 320         dw_mci_exynos_set_clksel_timing(host, clksel);
 321
 322         /* Configure setting for HS400 */
 323         dw_mci_exynos_config_hs400(host, timing);
 324
 325         /* Configure clock rate */
 326         dw_mci_exynos_adjust_clock(host, wanted);
 327 }
 328
 329 static int dw_mci_exynos_parse_dt(struct dw_mci *host)
 330 {
 331         struct dw_mci_exynos_priv_data *priv;
 332         struct device_node *np = host->dev->of_node;
 333         u32 timing[2];
 334         u32 div = 0;
 335         int idx;
 336         int ret;
 337
 338         priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
 339         if (!priv)
 340                 return -ENOMEM;
 341
 342         for (idx = 0; idx < ARRAY_SIZE(exynos_compat); idx++) {
 343                 if (of_device_is_compatible(np, exynos_compat[idx].compatible))
 344                         priv->ctrl_type = exynos_compat[idx].ctrl_type;
 345         }
 346
 347         if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4412)
 348                 priv->ciu_div = EXYNOS4412_FIXED_CIU_CLK_DIV - 1;
 349         else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4210)
 350                 priv->ciu_div = EXYNOS4210_FIXED_CIU_CLK_DIV - 1;
 351         else {
 352                 of_property_read_u32(np, "samsung,dw-mshc-ciu-div", &div);
 353                 priv->ciu_div = div;
 354         }
 355
 356         ret = of_property_read_u32_array(np,
 357                         "samsung,dw-mshc-sdr-timing", timing, 2);
 358         if (ret)
 359                 return ret;
 360
 361         priv->sdr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
 362
 363         ret = of_property_read_u32_array(np,
 364                         "samsung,dw-mshc-ddr-timing", timing, 2);
 365         if (ret)
 366                 return ret;
 367
 368         priv->ddr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
 369
 370         ret = of_property_read_u32_array(np,
 371                         "samsung,dw-mshc-hs400-timing", timing, 2);
 372         if (!ret && of_property_read_u32(np,
 373                                 "samsung,read-strobe-delay", &priv->dqs_delay))
 374                 dev_dbg(host->dev,
 375                         "read-strobe-delay is not found, assuming usage of default value\n");
 376
 377         priv->hs400_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1],
 378                                                 HS400_FIXED_CIU_CLK_DIV);
 379         host->priv = priv;
 380         return 0;
 381 }
 382
 383 static inline u8 dw_mci_exynos_get_clksmpl(struct dw_mci *host)
 384 {
 385         struct dw_mci_exynos_priv_data *priv = host->priv;
 386
 387         if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
 388                 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
 389                 return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL64));
 390         else
 391                 return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL));
 392 }
 393
 394 static inline void dw_mci_exynos_set_clksmpl(struct dw_mci *host, u8 sample)
 395 {
 396         u32 clksel;
 397         struct dw_mci_exynos_priv_data *priv = host->priv;
 398
 399         if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
 400                 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
 401                 clksel = mci_readl(host, CLKSEL64);
 402         else
 403                 clksel = mci_readl(host, CLKSEL);
 404         clksel = SDMMC_CLKSEL_UP_SAMPLE(clksel, sample);
 405         if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
 406                 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
 407                 mci_writel(host, CLKSEL64, clksel);
 408         else
 409                 mci_writel(host, CLKSEL, clksel);
 410 }
 411
 412 static inline u8 dw_mci_exynos_move_next_clksmpl(struct dw_mci *host)
 413 {
 414         struct dw_mci_exynos_priv_data *priv = host->priv;
 415         u32 clksel;
 416         u8 sample;
 417
 418         if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
 419                 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
 420                 clksel = mci_readl(host, CLKSEL64);
 421         else
 422                 clksel = mci_readl(host, CLKSEL);
 423
 424         sample = (clksel + 1) & 0x7;
 425         clksel = SDMMC_CLKSEL_UP_SAMPLE(clksel, sample);
 426
 427         if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
 428                 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
 429                 mci_writel(host, CLKSEL64, clksel);
 430         else
 431                 mci_writel(host, CLKSEL, clksel);
 432
 433         return sample;
 434 }
 435
 436 static s8 dw_mci_exynos_get_best_clksmpl(u8 candiates)
 437 {
 438         const u8 iter = 8;
 439         u8 __c;
 440         s8 i, loc = -1;
 441
 442         for (i = 0; i < iter; i++) {
 443                 __c = ror8(candiates, i);
 444                 if ((__c & 0xc7) == 0xc7) {
 445                         loc = i;
 446                         goto out;
 447                 }
 448         }
 449
 450         for (i = 0; i < iter; i++) {
 451                 __c = ror8(candiates, i);
 452                 if ((__c & 0x83) == 0x83) {
 453                         loc = i;
 454                         goto out;
 455                 }
 456         }
 457
 458 out:
 459         return loc;
 460 }
 461
 462 static int dw_mci_exynos_execute_tuning(struct dw_mci_slot *slot, u32 opcode)
 463 {
 464         struct dw_mci *host = slot->host;
 465         struct dw_mci_exynos_priv_data *priv = host->priv;
 466         struct mmc_host *mmc = slot->mmc;
 467         u8 start_smpl, smpl, candiates = 0;
 468         s8 found = -1;
 469         int ret = 0;
 470
 471         start_smpl = dw_mci_exynos_get_clksmpl(host);
 472
 473         do {
 474                 mci_writel(host, TMOUT, ~0);
 475                 smpl = dw_mci_exynos_move_next_clksmpl(host);
 476
 477                 if (!mmc_send_tuning(mmc, opcode, NULL))
 478                         candiates |= (1 << smpl);
 479
 480         } while (start_smpl != smpl);
 481
 482         found = dw_mci_exynos_get_best_clksmpl(candiates);
 483         if (found >= 0) {
 484                 dw_mci_exynos_set_clksmpl(host, found);
 485                 priv->tuned_sample = found;
 486         } else {
 487                 ret = -EIO;
 488         }
 489
 490         return ret;
 491 }
 492
 493 static int dw_mci_exynos_prepare_hs400_tuning(struct dw_mci *host,
 494                                         struct mmc_ios *ios)
 495 {
 496         struct dw_mci_exynos_priv_data *priv = host->priv;
 497
 498         dw_mci_exynos_set_clksel_timing(host, priv->hs400_timing);
 499         dw_mci_exynos_adjust_clock(host, (ios->clock) << 1);
 500
 501         return 0;
 502 }
 503
 504 /* Common capabilities of Exynos4/Exynos5 SoC */
 505 static unsigned long exynos_dwmmc_caps[4] = {
 506         MMC_CAP_1_8V_DDR | MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23,
 507         MMC_CAP_CMD23,
 508         MMC_CAP_CMD23,
 509         MMC_CAP_CMD23,
 510 };
 511
 512 static const struct dw_mci_drv_data exynos_drv_data = {
 513         .caps                   = exynos_dwmmc_caps,
 514         .num_caps               = ARRAY_SIZE(exynos_dwmmc_caps),
 515         .init                   = dw_mci_exynos_priv_init,
 516         .set_ios                = dw_mci_exynos_set_ios,
 517         .parse_dt               = dw_mci_exynos_parse_dt,
 518         .execute_tuning         = dw_mci_exynos_execute_tuning,
 519         .prepare_hs400_tuning   = dw_mci_exynos_prepare_hs400_tuning,
 520 };
 521
 522 static const struct of_device_id dw_mci_exynos_match[] = {
 523         { .compatible = "samsung,exynos4412-dw-mshc",
 524                         .data = &exynos_drv_data, },
 525         { .compatible = "samsung,exynos5250-dw-mshc",
 526                         .data = &exynos_drv_data, },
 527         { .compatible = "samsung,exynos5420-dw-mshc",
 528                         .data = &exynos_drv_data, },
 529         { .compatible = "samsung,exynos5420-dw-mshc-smu",
 530                         .data = &exynos_drv_data, },
 531         { .compatible = "samsung,exynos7-dw-mshc",
 532                         .data = &exynos_drv_data, },
 533         { .compatible = "samsung,exynos7-dw-mshc-smu",
 534                         .data = &exynos_drv_data, },
 535         {},
 536 };
 537 MODULE_DEVICE_TABLE(of, dw_mci_exynos_match);
 538
 539 static int dw_mci_exynos_probe(struct platform_device *pdev)
 540 {
 541         const struct dw_mci_drv_data *drv_data;
 542         const struct of_device_id *match;
 543         int ret;
 544
 545         match = of_match_node(dw_mci_exynos_match, pdev->dev.of_node);
 546         drv_data = match->data;
 547
 548         pm_runtime_get_noresume(&pdev->dev);
 549         pm_runtime_set_active(&pdev->dev);
 550         pm_runtime_enable(&pdev->dev);
 551
 552         ret = dw_mci_pltfm_register(pdev, drv_data);
 553         if (ret) {
 554                 pm_runtime_disable(&pdev->dev);
 555                 pm_runtime_set_suspended(&pdev->dev);
 556                 pm_runtime_put_noidle(&pdev->dev);
 557
 558                 return ret;
 559         }
 560
 561         return 0;
 562 }
 563
 564 static int dw_mci_exynos_remove(struct platform_device *pdev)
 565 {
 566         pm_runtime_disable(&pdev->dev);
 567         pm_runtime_set_suspended(&pdev->dev);
 568         pm_runtime_put_noidle(&pdev->dev);
 569
 570         return dw_mci_pltfm_remove(pdev);
 571 }
 572
 573 static const struct dev_pm_ops dw_mci_exynos_pmops = {
 574         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(dw_mci_exynos_suspend_noirq,
 575                                       dw_mci_exynos_resume_noirq)
 576         SET_RUNTIME_PM_OPS(dw_mci_runtime_suspend,
 577                            dw_mci_exynos_runtime_resume,
 578                            NULL)
 579 };
 580
 581 static struct platform_driver dw_mci_exynos_pltfm_driver = {
 582         .probe          = dw_mci_exynos_probe,
 583         .remove         = dw_mci_exynos_remove,
 584         .driver         = {
 585                 .name           = "dwmmc_exynos",
 586                 .of_match_table = dw_mci_exynos_match,
 587                 .pm             = &dw_mci_exynos_pmops,
 588         },
 589 };
 590
 591 module_platform_driver(dw_mci_exynos_pltfm_driver);
 592
 593 MODULE_DESCRIPTION("Samsung Specific DW-MSHC Driver Extension");
 594 MODULE_AUTHOR("Thomas Abraham <thomas.ab@samsung.com");
 595 MODULE_LICENSE("GPL v2");
 596 MODULE_ALIAS("platform:dwmmc_exynos");