1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * davinci_mmc.c - TI DaVinci MMC/SD/SDIO driver
5 * Copyright (C) 2006 Texas Instruments.
6 * Original author: Purushotam Kumar
7 * Copyright (C) 2009 David Brownell
10 #include <linux/module.h>
11 #include <linux/ioport.h>
12 #include <linux/platform_device.h>
13 #include <linux/clk.h>
14 #include <linux/err.h>
15 #include <linux/cpufreq.h>
16 #include <linux/mmc/host.h>
18 #include <linux/irq.h>
19 #include <linux/delay.h>
20 #include <linux/dmaengine.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/mmc/mmc.h>
24 #include <linux/mmc/slot-gpio.h>
25 #include <linux/interrupt.h>
27 #include <linux/platform_data/mmc-davinci.h>
30 * Register Definitions
32 #define DAVINCI_MMCCTL 0x00 /* Control Register */
33 #define DAVINCI_MMCCLK 0x04 /* Memory Clock Control Register */
34 #define DAVINCI_MMCST0 0x08 /* Status Register 0 */
35 #define DAVINCI_MMCST1 0x0C /* Status Register 1 */
36 #define DAVINCI_MMCIM 0x10 /* Interrupt Mask Register */
37 #define DAVINCI_MMCTOR 0x14 /* Response Time-Out Register */
38 #define DAVINCI_MMCTOD 0x18 /* Data Read Time-Out Register */
39 #define DAVINCI_MMCBLEN 0x1C /* Block Length Register */
40 #define DAVINCI_MMCNBLK 0x20 /* Number of Blocks Register */
41 #define DAVINCI_MMCNBLC 0x24 /* Number of Blocks Counter Register */
42 #define DAVINCI_MMCDRR 0x28 /* Data Receive Register */
43 #define DAVINCI_MMCDXR 0x2C /* Data Transmit Register */
44 #define DAVINCI_MMCCMD 0x30 /* Command Register */
45 #define DAVINCI_MMCARGHL 0x34 /* Argument Register */
46 #define DAVINCI_MMCRSP01 0x38 /* Response Register 0 and 1 */
47 #define DAVINCI_MMCRSP23 0x3C /* Response Register 0 and 1 */
48 #define DAVINCI_MMCRSP45 0x40 /* Response Register 0 and 1 */
49 #define DAVINCI_MMCRSP67 0x44 /* Response Register 0 and 1 */
50 #define DAVINCI_MMCDRSP 0x48 /* Data Response Register */
51 #define DAVINCI_MMCETOK 0x4C
52 #define DAVINCI_MMCCIDX 0x50 /* Command Index Register */
53 #define DAVINCI_MMCCKC 0x54
54 #define DAVINCI_MMCTORC 0x58
55 #define DAVINCI_MMCTODC 0x5C
56 #define DAVINCI_MMCBLNC 0x60
57 #define DAVINCI_SDIOCTL 0x64
58 #define DAVINCI_SDIOST0 0x68
59 #define DAVINCI_SDIOIEN 0x6C
60 #define DAVINCI_SDIOIST 0x70
61 #define DAVINCI_MMCFIFOCTL 0x74 /* FIFO Control Register */
63 /* DAVINCI_MMCCTL definitions */
64 #define MMCCTL_DATRST (1 << 0)
65 #define MMCCTL_CMDRST (1 << 1)
66 #define MMCCTL_WIDTH_8_BIT (1 << 8)
67 #define MMCCTL_WIDTH_4_BIT (1 << 2)
68 #define MMCCTL_DATEG_DISABLED (0 << 6)
69 #define MMCCTL_DATEG_RISING (1 << 6)
70 #define MMCCTL_DATEG_FALLING (2 << 6)
71 #define MMCCTL_DATEG_BOTH (3 << 6)
72 #define MMCCTL_PERMDR_LE (0 << 9)
73 #define MMCCTL_PERMDR_BE (1 << 9)
74 #define MMCCTL_PERMDX_LE (0 << 10)
75 #define MMCCTL_PERMDX_BE (1 << 10)
77 /* DAVINCI_MMCCLK definitions */
78 #define MMCCLK_CLKEN (1 << 8)
79 #define MMCCLK_CLKRT_MASK (0xFF << 0)
81 /* IRQ bit definitions, for DAVINCI_MMCST0 and DAVINCI_MMCIM */
82 #define MMCST0_DATDNE BIT(0) /* data done */
83 #define MMCST0_BSYDNE BIT(1) /* busy done */
84 #define MMCST0_RSPDNE BIT(2) /* command done */
85 #define MMCST0_TOUTRD BIT(3) /* data read timeout */
86 #define MMCST0_TOUTRS BIT(4) /* command response timeout */
87 #define MMCST0_CRCWR BIT(5) /* data write CRC error */
88 #define MMCST0_CRCRD BIT(6) /* data read CRC error */
89 #define MMCST0_CRCRS BIT(7) /* command response CRC error */
90 #define MMCST0_DXRDY BIT(9) /* data transmit ready (fifo empty) */
91 #define MMCST0_DRRDY BIT(10) /* data receive ready (data in fifo)*/
92 #define MMCST0_DATED BIT(11) /* DAT3 edge detect */
93 #define MMCST0_TRNDNE BIT(12) /* transfer done */
95 /* DAVINCI_MMCST1 definitions */
96 #define MMCST1_BUSY (1 << 0)
98 /* DAVINCI_MMCCMD definitions */
99 #define MMCCMD_CMD_MASK (0x3F << 0)
100 #define MMCCMD_PPLEN (1 << 7)
101 #define MMCCMD_BSYEXP (1 << 8)
102 #define MMCCMD_RSPFMT_MASK (3 << 9)
103 #define MMCCMD_RSPFMT_NONE (0 << 9)
104 #define MMCCMD_RSPFMT_R1456 (1 << 9)
105 #define MMCCMD_RSPFMT_R2 (2 << 9)
106 #define MMCCMD_RSPFMT_R3 (3 << 9)
107 #define MMCCMD_DTRW (1 << 11)
108 #define MMCCMD_STRMTP (1 << 12)
109 #define MMCCMD_WDATX (1 << 13)
110 #define MMCCMD_INITCK (1 << 14)
111 #define MMCCMD_DCLR (1 << 15)
112 #define MMCCMD_DMATRIG (1 << 16)
114 /* DAVINCI_MMCFIFOCTL definitions */
115 #define MMCFIFOCTL_FIFORST (1 << 0)
116 #define MMCFIFOCTL_FIFODIR_WR (1 << 1)
117 #define MMCFIFOCTL_FIFODIR_RD (0 << 1)
118 #define MMCFIFOCTL_FIFOLEV (1 << 2) /* 0 = 128 bits, 1 = 256 bits */
119 #define MMCFIFOCTL_ACCWD_4 (0 << 3) /* access width of 4 bytes */
120 #define MMCFIFOCTL_ACCWD_3 (1 << 3) /* access width of 3 bytes */
121 #define MMCFIFOCTL_ACCWD_2 (2 << 3) /* access width of 2 bytes */
122 #define MMCFIFOCTL_ACCWD_1 (3 << 3) /* access width of 1 byte */
124 /* DAVINCI_SDIOST0 definitions */
125 #define SDIOST0_DAT1_HI BIT(0)
127 /* DAVINCI_SDIOIEN definitions */
128 #define SDIOIEN_IOINTEN BIT(0)
130 /* DAVINCI_SDIOIST definitions */
131 #define SDIOIST_IOINT BIT(0)
133 /* MMCSD Init clock in Hz in opendrain mode */
134 #define MMCSD_INIT_CLOCK 200000
137 * One scatterlist dma "segment" is at most MAX_CCNT rw_threshold units,
138 * and we handle up to MAX_NR_SG segments. MMC_BLOCK_BOUNCE kicks in only
139 * for drivers with max_segs == 1, making the segments bigger (64KB)
140 * than the page or two that's otherwise typical. nr_sg (passed from
141 * platform data) == 16 gives at least the same throughput boost, using
142 * EDMA transfer linkage instead of spending CPU time copying pages.
144 #define MAX_CCNT ((1 << 16) - 1)
148 static unsigned rw_threshold = 32;
149 module_param(rw_threshold, uint, S_IRUGO);
150 MODULE_PARM_DESC(rw_threshold,
151 "Read/Write threshold. Default = 32");
153 static unsigned poll_threshold = 128;
154 module_param(poll_threshold, uint, S_IRUGO);
155 MODULE_PARM_DESC(poll_threshold,
156 "Polling transaction size threshold. Default = 128");
158 static unsigned poll_loopcount = 32;
159 module_param(poll_loopcount, uint, S_IRUGO);
160 MODULE_PARM_DESC(poll_loopcount,
161 "Maximum polling loop count. Default = 32");
163 static unsigned use_dma = 1;
164 module_param(use_dma, uint, 0);
165 MODULE_PARM_DESC(use_dma, "Whether to use DMA or not. Default = 1");
167 struct mmc_davinci_host {
168 struct mmc_command *cmd;
169 struct mmc_data *data;
170 struct mmc_host *mmc;
172 unsigned int mmc_input_clk;
174 struct resource *mem_res;
175 int mmc_irq, sdio_irq;
176 unsigned char bus_mode;
178 #define DAVINCI_MMC_DATADIR_NONE 0
179 #define DAVINCI_MMC_DATADIR_READ 1
180 #define DAVINCI_MMC_DATADIR_WRITE 2
181 unsigned char data_dir;
183 /* buffer is used during PIO of one scatterlist segment, and
184 * is updated along with buffer_bytes_left. bytes_left applies
185 * to all N blocks of the PIO transfer.
188 u32 buffer_bytes_left;
191 struct dma_chan *dma_tx;
192 struct dma_chan *dma_rx;
198 /* For PIO we walk scatterlists one segment at a time. */
200 struct scatterlist *sg;
202 /* Version of the MMC/SD controller */
204 /* for ns in one cycle calculation */
205 unsigned ns_in_one_cycle;
206 /* Number of sg segments */
208 #ifdef CONFIG_CPU_FREQ
209 struct notifier_block freq_transition;
213 static irqreturn_t mmc_davinci_irq(int irq, void *dev_id);
216 static void mmc_davinci_sg_to_buf(struct mmc_davinci_host *host)
218 host->buffer_bytes_left = sg_dma_len(host->sg);
219 host->buffer = sg_virt(host->sg);
220 if (host->buffer_bytes_left > host->bytes_left)
221 host->buffer_bytes_left = host->bytes_left;
224 static void davinci_fifo_data_trans(struct mmc_davinci_host *host,
230 if (host->buffer_bytes_left == 0) {
231 host->sg = sg_next(host->data->sg);
232 mmc_davinci_sg_to_buf(host);
236 if (n > host->buffer_bytes_left)
237 n = host->buffer_bytes_left;
238 host->buffer_bytes_left -= n;
239 host->bytes_left -= n;
241 /* NOTE: we never transfer more than rw_threshold bytes
242 * to/from the fifo here; there's no I/O overlap.
243 * This also assumes that access width( i.e. ACCWD) is 4 bytes
245 if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) {
246 for (i = 0; i < (n >> 2); i++) {
247 writel(*((u32 *)p), host->base + DAVINCI_MMCDXR);
251 iowrite8_rep(host->base + DAVINCI_MMCDXR, p, (n & 3));
255 for (i = 0; i < (n >> 2); i++) {
256 *((u32 *)p) = readl(host->base + DAVINCI_MMCDRR);
260 ioread8_rep(host->base + DAVINCI_MMCDRR, p, (n & 3));
267 static void mmc_davinci_start_command(struct mmc_davinci_host *host,
268 struct mmc_command *cmd)
273 dev_dbg(mmc_dev(host->mmc), "CMD%d, arg 0x%08x%s\n",
274 cmd->opcode, cmd->arg,
276 switch (mmc_resp_type(cmd)) {
278 s = ", R1/R5/R6/R7 response";
281 s = ", R1b response";
287 s = ", R3/R4 response";
290 s = ", (R? response)";
295 switch (mmc_resp_type(cmd)) {
297 /* There's some spec confusion about when R1B is
298 * allowed, but if the card doesn't issue a BUSY
299 * then it's harmless for us to allow it.
301 cmd_reg |= MMCCMD_BSYEXP;
303 case MMC_RSP_R1: /* 48 bits, CRC */
304 cmd_reg |= MMCCMD_RSPFMT_R1456;
306 case MMC_RSP_R2: /* 136 bits, CRC */
307 cmd_reg |= MMCCMD_RSPFMT_R2;
309 case MMC_RSP_R3: /* 48 bits, no CRC */
310 cmd_reg |= MMCCMD_RSPFMT_R3;
313 cmd_reg |= MMCCMD_RSPFMT_NONE;
314 dev_dbg(mmc_dev(host->mmc), "unknown resp_type %04x\n",
319 /* Set command index */
320 cmd_reg |= cmd->opcode;
322 /* Enable EDMA transfer triggers */
324 cmd_reg |= MMCCMD_DMATRIG;
326 if (host->version == MMC_CTLR_VERSION_2 && host->data != NULL &&
327 host->data_dir == DAVINCI_MMC_DATADIR_READ)
328 cmd_reg |= MMCCMD_DMATRIG;
330 /* Setting whether command involves data transfer or not */
332 cmd_reg |= MMCCMD_WDATX;
334 /* Setting whether data read or write */
335 if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE)
336 cmd_reg |= MMCCMD_DTRW;
338 if (host->bus_mode == MMC_BUSMODE_PUSHPULL)
339 cmd_reg |= MMCCMD_PPLEN;
341 /* set Command timeout */
342 writel(0x1FFF, host->base + DAVINCI_MMCTOR);
344 /* Enable interrupt (calculate here, defer until FIFO is stuffed). */
345 im_val = MMCST0_RSPDNE | MMCST0_CRCRS | MMCST0_TOUTRS;
346 if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) {
347 im_val |= MMCST0_DATDNE | MMCST0_CRCWR;
350 im_val |= MMCST0_DXRDY;
351 } else if (host->data_dir == DAVINCI_MMC_DATADIR_READ) {
352 im_val |= MMCST0_DATDNE | MMCST0_CRCRD | MMCST0_TOUTRD;
355 im_val |= MMCST0_DRRDY;
359 * Before non-DMA WRITE commands the controller needs priming:
360 * FIFO should be populated with 32 bytes i.e. whatever is the FIFO size
362 if (!host->do_dma && (host->data_dir == DAVINCI_MMC_DATADIR_WRITE))
363 davinci_fifo_data_trans(host, rw_threshold);
365 writel(cmd->arg, host->base + DAVINCI_MMCARGHL);
366 writel(cmd_reg, host->base + DAVINCI_MMCCMD);
368 host->active_request = true;
370 if (!host->do_dma && host->bytes_left <= poll_threshold) {
371 u32 count = poll_loopcount;
373 while (host->active_request && count--) {
374 mmc_davinci_irq(0, host);
379 if (host->active_request)
380 writel(im_val, host->base + DAVINCI_MMCIM);
383 /*----------------------------------------------------------------------*/
385 /* DMA infrastructure */
387 static void davinci_abort_dma(struct mmc_davinci_host *host)
389 struct dma_chan *sync_dev;
391 if (host->data_dir == DAVINCI_MMC_DATADIR_READ)
392 sync_dev = host->dma_rx;
394 sync_dev = host->dma_tx;
396 dmaengine_terminate_all(sync_dev);
399 static int mmc_davinci_send_dma_request(struct mmc_davinci_host *host,
400 struct mmc_data *data)
402 struct dma_chan *chan;
403 struct dma_async_tx_descriptor *desc;
406 if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) {
407 struct dma_slave_config dma_tx_conf = {
408 .direction = DMA_MEM_TO_DEV,
409 .dst_addr = host->mem_res->start + DAVINCI_MMCDXR,
410 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
412 rw_threshold / DMA_SLAVE_BUSWIDTH_4_BYTES,
415 dmaengine_slave_config(host->dma_tx, &dma_tx_conf);
417 desc = dmaengine_prep_slave_sg(host->dma_tx,
421 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
423 dev_dbg(mmc_dev(host->mmc),
424 "failed to allocate DMA TX descriptor");
429 struct dma_slave_config dma_rx_conf = {
430 .direction = DMA_DEV_TO_MEM,
431 .src_addr = host->mem_res->start + DAVINCI_MMCDRR,
432 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
434 rw_threshold / DMA_SLAVE_BUSWIDTH_4_BYTES,
437 dmaengine_slave_config(host->dma_rx, &dma_rx_conf);
439 desc = dmaengine_prep_slave_sg(host->dma_rx,
443 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
445 dev_dbg(mmc_dev(host->mmc),
446 "failed to allocate DMA RX descriptor");
452 dmaengine_submit(desc);
453 dma_async_issue_pending(chan);
459 static int mmc_davinci_start_dma_transfer(struct mmc_davinci_host *host,
460 struct mmc_data *data)
463 int mask = rw_threshold - 1;
466 host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
467 mmc_get_dma_dir(data));
469 /* no individual DMA segment should need a partial FIFO */
470 for (i = 0; i < host->sg_len; i++) {
471 if (sg_dma_len(data->sg + i) & mask) {
472 dma_unmap_sg(mmc_dev(host->mmc),
473 data->sg, data->sg_len,
474 mmc_get_dma_dir(data));
480 ret = mmc_davinci_send_dma_request(host, data);
485 static void davinci_release_dma_channels(struct mmc_davinci_host *host)
490 dma_release_channel(host->dma_tx);
491 dma_release_channel(host->dma_rx);
494 static int davinci_acquire_dma_channels(struct mmc_davinci_host *host)
496 host->dma_tx = dma_request_chan(mmc_dev(host->mmc), "tx");
497 if (IS_ERR(host->dma_tx)) {
498 dev_err(mmc_dev(host->mmc), "Can't get dma_tx channel\n");
499 return PTR_ERR(host->dma_tx);
502 host->dma_rx = dma_request_chan(mmc_dev(host->mmc), "rx");
503 if (IS_ERR(host->dma_rx)) {
504 dev_err(mmc_dev(host->mmc), "Can't get dma_rx channel\n");
505 dma_release_channel(host->dma_tx);
506 return PTR_ERR(host->dma_rx);
512 /*----------------------------------------------------------------------*/
515 mmc_davinci_prepare_data(struct mmc_davinci_host *host, struct mmc_request *req)
517 int fifo_lev = (rw_threshold == 32) ? MMCFIFOCTL_FIFOLEV : 0;
519 struct mmc_data *data = req->data;
521 if (host->version == MMC_CTLR_VERSION_2)
522 fifo_lev = (rw_threshold == 64) ? MMCFIFOCTL_FIFOLEV : 0;
526 host->data_dir = DAVINCI_MMC_DATADIR_NONE;
527 writel(0, host->base + DAVINCI_MMCBLEN);
528 writel(0, host->base + DAVINCI_MMCNBLK);
532 dev_dbg(mmc_dev(host->mmc), "%s, %d blocks of %d bytes\n",
533 (data->flags & MMC_DATA_WRITE) ? "write" : "read",
534 data->blocks, data->blksz);
535 dev_dbg(mmc_dev(host->mmc), " DTO %d cycles + %d ns\n",
536 data->timeout_clks, data->timeout_ns);
537 timeout = data->timeout_clks +
538 (data->timeout_ns / host->ns_in_one_cycle);
539 if (timeout > 0xffff)
542 writel(timeout, host->base + DAVINCI_MMCTOD);
543 writel(data->blocks, host->base + DAVINCI_MMCNBLK);
544 writel(data->blksz, host->base + DAVINCI_MMCBLEN);
546 /* Configure the FIFO */
547 if (data->flags & MMC_DATA_WRITE) {
548 host->data_dir = DAVINCI_MMC_DATADIR_WRITE;
549 writel(fifo_lev | MMCFIFOCTL_FIFODIR_WR | MMCFIFOCTL_FIFORST,
550 host->base + DAVINCI_MMCFIFOCTL);
551 writel(fifo_lev | MMCFIFOCTL_FIFODIR_WR,
552 host->base + DAVINCI_MMCFIFOCTL);
554 host->data_dir = DAVINCI_MMC_DATADIR_READ;
555 writel(fifo_lev | MMCFIFOCTL_FIFODIR_RD | MMCFIFOCTL_FIFORST,
556 host->base + DAVINCI_MMCFIFOCTL);
557 writel(fifo_lev | MMCFIFOCTL_FIFODIR_RD,
558 host->base + DAVINCI_MMCFIFOCTL);
562 host->bytes_left = data->blocks * data->blksz;
564 /* For now we try to use DMA whenever we won't need partial FIFO
565 * reads or writes, either for the whole transfer (as tested here)
566 * or for any individual scatterlist segment (tested when we call
567 * start_dma_transfer).
569 * While we *could* change that, unusual block sizes are rarely
570 * used. The occasional fallback to PIO should't hurt.
572 if (host->use_dma && (host->bytes_left & (rw_threshold - 1)) == 0
573 && mmc_davinci_start_dma_transfer(host, data) == 0) {
574 /* zero this to ensure we take no PIO paths */
575 host->bytes_left = 0;
577 /* Revert to CPU Copy */
578 host->sg_len = data->sg_len;
579 host->sg = host->data->sg;
580 mmc_davinci_sg_to_buf(host);
584 static void mmc_davinci_request(struct mmc_host *mmc, struct mmc_request *req)
586 struct mmc_davinci_host *host = mmc_priv(mmc);
587 unsigned long timeout = jiffies + msecs_to_jiffies(900);
590 /* Card may still be sending BUSY after a previous operation,
591 * typically some kind of write. If so, we can't proceed yet.
593 while (time_before(jiffies, timeout)) {
594 mmcst1 = readl(host->base + DAVINCI_MMCST1);
595 if (!(mmcst1 & MMCST1_BUSY))
599 if (mmcst1 & MMCST1_BUSY) {
600 dev_err(mmc_dev(host->mmc), "still BUSY? bad ... \n");
601 req->cmd->error = -ETIMEDOUT;
602 mmc_request_done(mmc, req);
607 mmc_davinci_prepare_data(host, req);
608 mmc_davinci_start_command(host, req->cmd);
611 static unsigned int calculate_freq_for_card(struct mmc_davinci_host *host,
612 unsigned int mmc_req_freq)
614 unsigned int mmc_freq = 0, mmc_pclk = 0, mmc_push_pull_divisor = 0;
616 mmc_pclk = host->mmc_input_clk;
617 if (mmc_req_freq && mmc_pclk > (2 * mmc_req_freq))
618 mmc_push_pull_divisor = ((unsigned int)mmc_pclk
619 / (2 * mmc_req_freq)) - 1;
621 mmc_push_pull_divisor = 0;
623 mmc_freq = (unsigned int)mmc_pclk
624 / (2 * (mmc_push_pull_divisor + 1));
626 if (mmc_freq > mmc_req_freq)
627 mmc_push_pull_divisor = mmc_push_pull_divisor + 1;
628 /* Convert ns to clock cycles */
629 if (mmc_req_freq <= 400000)
630 host->ns_in_one_cycle = (1000000) / (((mmc_pclk
631 / (2 * (mmc_push_pull_divisor + 1)))/1000));
633 host->ns_in_one_cycle = (1000000) / (((mmc_pclk
634 / (2 * (mmc_push_pull_divisor + 1)))/1000000));
636 return mmc_push_pull_divisor;
639 static void calculate_clk_divider(struct mmc_host *mmc, struct mmc_ios *ios)
641 unsigned int open_drain_freq = 0, mmc_pclk = 0;
642 unsigned int mmc_push_pull_freq = 0;
643 struct mmc_davinci_host *host = mmc_priv(mmc);
645 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) {
648 /* Ignoring the init clock value passed for fixing the inter
649 * operability with different cards.
651 open_drain_freq = ((unsigned int)mmc_pclk
652 / (2 * MMCSD_INIT_CLOCK)) - 1;
654 if (open_drain_freq > 0xFF)
655 open_drain_freq = 0xFF;
657 temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKRT_MASK;
658 temp |= open_drain_freq;
659 writel(temp, host->base + DAVINCI_MMCCLK);
661 /* Convert ns to clock cycles */
662 host->ns_in_one_cycle = (1000000) / (MMCSD_INIT_CLOCK/1000);
665 mmc_push_pull_freq = calculate_freq_for_card(host, ios->clock);
667 if (mmc_push_pull_freq > 0xFF)
668 mmc_push_pull_freq = 0xFF;
670 temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKEN;
671 writel(temp, host->base + DAVINCI_MMCCLK);
675 temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKRT_MASK;
676 temp |= mmc_push_pull_freq;
677 writel(temp, host->base + DAVINCI_MMCCLK);
679 writel(temp | MMCCLK_CLKEN, host->base + DAVINCI_MMCCLK);
685 static void mmc_davinci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
687 struct mmc_davinci_host *host = mmc_priv(mmc);
688 struct platform_device *pdev = to_platform_device(mmc->parent);
689 struct davinci_mmc_config *config = pdev->dev.platform_data;
691 dev_dbg(mmc_dev(host->mmc),
692 "clock %dHz busmode %d powermode %d Vdd %04x\n",
693 ios->clock, ios->bus_mode, ios->power_mode,
696 switch (ios->power_mode) {
698 if (config && config->set_power)
699 config->set_power(pdev->id, false);
702 if (config && config->set_power)
703 config->set_power(pdev->id, true);
707 switch (ios->bus_width) {
708 case MMC_BUS_WIDTH_8:
709 dev_dbg(mmc_dev(host->mmc), "Enabling 8 bit mode\n");
710 writel((readl(host->base + DAVINCI_MMCCTL) &
711 ~MMCCTL_WIDTH_4_BIT) | MMCCTL_WIDTH_8_BIT,
712 host->base + DAVINCI_MMCCTL);
714 case MMC_BUS_WIDTH_4:
715 dev_dbg(mmc_dev(host->mmc), "Enabling 4 bit mode\n");
716 if (host->version == MMC_CTLR_VERSION_2)
717 writel((readl(host->base + DAVINCI_MMCCTL) &
718 ~MMCCTL_WIDTH_8_BIT) | MMCCTL_WIDTH_4_BIT,
719 host->base + DAVINCI_MMCCTL);
721 writel(readl(host->base + DAVINCI_MMCCTL) |
723 host->base + DAVINCI_MMCCTL);
725 case MMC_BUS_WIDTH_1:
726 dev_dbg(mmc_dev(host->mmc), "Enabling 1 bit mode\n");
727 if (host->version == MMC_CTLR_VERSION_2)
728 writel(readl(host->base + DAVINCI_MMCCTL) &
729 ~(MMCCTL_WIDTH_8_BIT | MMCCTL_WIDTH_4_BIT),
730 host->base + DAVINCI_MMCCTL);
732 writel(readl(host->base + DAVINCI_MMCCTL) &
734 host->base + DAVINCI_MMCCTL);
738 calculate_clk_divider(mmc, ios);
740 host->bus_mode = ios->bus_mode;
741 if (ios->power_mode == MMC_POWER_UP) {
742 unsigned long timeout = jiffies + msecs_to_jiffies(50);
745 /* Send clock cycles, poll completion */
746 writel(0, host->base + DAVINCI_MMCARGHL);
747 writel(MMCCMD_INITCK, host->base + DAVINCI_MMCCMD);
748 while (time_before(jiffies, timeout)) {
749 u32 tmp = readl(host->base + DAVINCI_MMCST0);
751 if (tmp & MMCST0_RSPDNE) {
758 dev_warn(mmc_dev(host->mmc), "powerup timeout\n");
761 /* FIXME on power OFF, reset things ... */
765 mmc_davinci_xfer_done(struct mmc_davinci_host *host, struct mmc_data *data)
769 if (host->mmc->caps & MMC_CAP_SDIO_IRQ) {
771 * SDIO Interrupt Detection work-around as suggested by
772 * Davinci Errata (TMS320DM355 Silicon Revision 1.1 Errata
773 * 2.1.6): Signal SDIO interrupt only if it is enabled by core
775 if (host->sdio_int && !(readl(host->base + DAVINCI_SDIOST0) &
777 writel(SDIOIST_IOINT, host->base + DAVINCI_SDIOIST);
778 mmc_signal_sdio_irq(host->mmc);
783 davinci_abort_dma(host);
785 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
786 mmc_get_dma_dir(data));
787 host->do_dma = false;
789 host->data_dir = DAVINCI_MMC_DATADIR_NONE;
791 if (!data->stop || (host->cmd && host->cmd->error)) {
792 mmc_request_done(host->mmc, data->mrq);
793 writel(0, host->base + DAVINCI_MMCIM);
794 host->active_request = false;
796 mmc_davinci_start_command(host, data->stop);
799 static void mmc_davinci_cmd_done(struct mmc_davinci_host *host,
800 struct mmc_command *cmd)
804 if (cmd->flags & MMC_RSP_PRESENT) {
805 if (cmd->flags & MMC_RSP_136) {
806 /* response type 2 */
807 cmd->resp[3] = readl(host->base + DAVINCI_MMCRSP01);
808 cmd->resp[2] = readl(host->base + DAVINCI_MMCRSP23);
809 cmd->resp[1] = readl(host->base + DAVINCI_MMCRSP45);
810 cmd->resp[0] = readl(host->base + DAVINCI_MMCRSP67);
812 /* response types 1, 1b, 3, 4, 5, 6 */
813 cmd->resp[0] = readl(host->base + DAVINCI_MMCRSP67);
817 if (host->data == NULL || cmd->error) {
818 if (cmd->error == -ETIMEDOUT)
819 cmd->mrq->cmd->retries = 0;
820 mmc_request_done(host->mmc, cmd->mrq);
821 writel(0, host->base + DAVINCI_MMCIM);
822 host->active_request = false;
826 static inline void mmc_davinci_reset_ctrl(struct mmc_davinci_host *host,
831 temp = readl(host->base + DAVINCI_MMCCTL);
833 temp |= MMCCTL_CMDRST | MMCCTL_DATRST;
835 temp &= ~(MMCCTL_CMDRST | MMCCTL_DATRST);
837 writel(temp, host->base + DAVINCI_MMCCTL);
842 davinci_abort_data(struct mmc_davinci_host *host, struct mmc_data *data)
844 mmc_davinci_reset_ctrl(host, 1);
845 mmc_davinci_reset_ctrl(host, 0);
848 static irqreturn_t mmc_davinci_sdio_irq(int irq, void *dev_id)
850 struct mmc_davinci_host *host = dev_id;
853 status = readl(host->base + DAVINCI_SDIOIST);
854 if (status & SDIOIST_IOINT) {
855 dev_dbg(mmc_dev(host->mmc),
856 "SDIO interrupt status %x\n", status);
857 writel(status | SDIOIST_IOINT, host->base + DAVINCI_SDIOIST);
858 mmc_signal_sdio_irq(host->mmc);
863 static irqreturn_t mmc_davinci_irq(int irq, void *dev_id)
865 struct mmc_davinci_host *host = (struct mmc_davinci_host *)dev_id;
866 unsigned int status, qstatus;
868 int end_transfer = 0;
869 struct mmc_data *data = host->data;
871 if (host->cmd == NULL && host->data == NULL) {
872 status = readl(host->base + DAVINCI_MMCST0);
873 dev_dbg(mmc_dev(host->mmc),
874 "Spurious interrupt 0x%04x\n", status);
875 /* Disable the interrupt from mmcsd */
876 writel(0, host->base + DAVINCI_MMCIM);
880 status = readl(host->base + DAVINCI_MMCST0);
883 /* handle FIFO first when using PIO for data.
884 * bytes_left will decrease to zero as I/O progress and status will
885 * read zero over iteration because this controller status
886 * register(MMCST0) reports any status only once and it is cleared
887 * by read. So, it is not unbouned loop even in the case of
890 if (host->bytes_left && (status & (MMCST0_DXRDY | MMCST0_DRRDY))) {
891 unsigned long im_val;
894 * If interrupts fire during the following loop, they will be
895 * handled by the handler, but the PIC will still buffer these.
896 * As a result, the handler will be called again to serve these
897 * needlessly. In order to avoid these spurious interrupts,
898 * keep interrupts masked during the loop.
900 im_val = readl(host->base + DAVINCI_MMCIM);
901 writel(0, host->base + DAVINCI_MMCIM);
904 davinci_fifo_data_trans(host, rw_threshold);
905 status = readl(host->base + DAVINCI_MMCST0);
907 } while (host->bytes_left &&
908 (status & (MMCST0_DXRDY | MMCST0_DRRDY)));
911 * If an interrupt is pending, it is assumed it will fire when
912 * it is unmasked. This assumption is also taken when the MMCIM
913 * is first set. Otherwise, writing to MMCIM after reading the
914 * status is race-prone.
916 writel(im_val, host->base + DAVINCI_MMCIM);
919 if (qstatus & MMCST0_DATDNE) {
920 /* All blocks sent/received, and CRC checks passed */
922 if ((host->do_dma == 0) && (host->bytes_left > 0)) {
923 /* if datasize < rw_threshold
924 * no RX ints are generated
926 davinci_fifo_data_trans(host, host->bytes_left);
929 data->bytes_xfered = data->blocks * data->blksz;
931 dev_err(mmc_dev(host->mmc),
932 "DATDNE with no host->data\n");
936 if (qstatus & MMCST0_TOUTRD) {
937 /* Read data timeout */
938 data->error = -ETIMEDOUT;
941 dev_dbg(mmc_dev(host->mmc),
942 "read data timeout, status %x\n",
945 davinci_abort_data(host, data);
948 if (qstatus & (MMCST0_CRCWR | MMCST0_CRCRD)) {
950 data->error = -EILSEQ;
953 /* NOTE: this controller uses CRCWR to report both CRC
954 * errors and timeouts (on writes). MMCDRSP values are
955 * only weakly documented, but 0x9f was clearly a timeout
956 * case and the two three-bit patterns in various SD specs
957 * (101, 010) aren't part of it ...
959 if (qstatus & MMCST0_CRCWR) {
960 u32 temp = readb(host->base + DAVINCI_MMCDRSP);
963 data->error = -ETIMEDOUT;
965 dev_dbg(mmc_dev(host->mmc), "data %s %s error\n",
966 (qstatus & MMCST0_CRCWR) ? "write" : "read",
967 (data->error == -ETIMEDOUT) ? "timeout" : "CRC");
969 davinci_abort_data(host, data);
972 if (qstatus & MMCST0_TOUTRS) {
973 /* Command timeout */
975 dev_dbg(mmc_dev(host->mmc),
976 "CMD%d timeout, status %x\n",
977 host->cmd->opcode, qstatus);
978 host->cmd->error = -ETIMEDOUT;
981 davinci_abort_data(host, data);
987 if (qstatus & MMCST0_CRCRS) {
988 /* Command CRC error */
989 dev_dbg(mmc_dev(host->mmc), "Command CRC error\n");
991 host->cmd->error = -EILSEQ;
996 if (qstatus & MMCST0_RSPDNE) {
997 /* End of command phase */
998 end_command = host->cmd ? 1 : 0;
1002 mmc_davinci_cmd_done(host, host->cmd);
1004 mmc_davinci_xfer_done(host, data);
1008 static int mmc_davinci_get_cd(struct mmc_host *mmc)
1010 struct platform_device *pdev = to_platform_device(mmc->parent);
1011 struct davinci_mmc_config *config = pdev->dev.platform_data;
1013 if (config && config->get_cd)
1014 return config->get_cd(pdev->id);
1016 return mmc_gpio_get_cd(mmc);
1019 static int mmc_davinci_get_ro(struct mmc_host *mmc)
1021 struct platform_device *pdev = to_platform_device(mmc->parent);
1022 struct davinci_mmc_config *config = pdev->dev.platform_data;
1024 if (config && config->get_ro)
1025 return config->get_ro(pdev->id);
1027 return mmc_gpio_get_ro(mmc);
1030 static void mmc_davinci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1032 struct mmc_davinci_host *host = mmc_priv(mmc);
1035 if (!(readl(host->base + DAVINCI_SDIOST0) & SDIOST0_DAT1_HI)) {
1036 writel(SDIOIST_IOINT, host->base + DAVINCI_SDIOIST);
1037 mmc_signal_sdio_irq(host->mmc);
1039 host->sdio_int = true;
1040 writel(readl(host->base + DAVINCI_SDIOIEN) |
1041 SDIOIEN_IOINTEN, host->base + DAVINCI_SDIOIEN);
1044 host->sdio_int = false;
1045 writel(readl(host->base + DAVINCI_SDIOIEN) & ~SDIOIEN_IOINTEN,
1046 host->base + DAVINCI_SDIOIEN);
1050 static const struct mmc_host_ops mmc_davinci_ops = {
1051 .request = mmc_davinci_request,
1052 .set_ios = mmc_davinci_set_ios,
1053 .get_cd = mmc_davinci_get_cd,
1054 .get_ro = mmc_davinci_get_ro,
1055 .enable_sdio_irq = mmc_davinci_enable_sdio_irq,
1058 /*----------------------------------------------------------------------*/
1060 #ifdef CONFIG_CPU_FREQ
1061 static int mmc_davinci_cpufreq_transition(struct notifier_block *nb,
1062 unsigned long val, void *data)
1064 struct mmc_davinci_host *host;
1065 unsigned int mmc_pclk;
1066 struct mmc_host *mmc;
1067 unsigned long flags;
1069 host = container_of(nb, struct mmc_davinci_host, freq_transition);
1071 mmc_pclk = clk_get_rate(host->clk);
1073 if (val == CPUFREQ_POSTCHANGE) {
1074 spin_lock_irqsave(&mmc->lock, flags);
1075 host->mmc_input_clk = mmc_pclk;
1076 calculate_clk_divider(mmc, &mmc->ios);
1077 spin_unlock_irqrestore(&mmc->lock, flags);
1083 static inline int mmc_davinci_cpufreq_register(struct mmc_davinci_host *host)
1085 host->freq_transition.notifier_call = mmc_davinci_cpufreq_transition;
1087 return cpufreq_register_notifier(&host->freq_transition,
1088 CPUFREQ_TRANSITION_NOTIFIER);
1091 static inline void mmc_davinci_cpufreq_deregister(struct mmc_davinci_host *host)
1093 cpufreq_unregister_notifier(&host->freq_transition,
1094 CPUFREQ_TRANSITION_NOTIFIER);
1097 static inline int mmc_davinci_cpufreq_register(struct mmc_davinci_host *host)
1102 static inline void mmc_davinci_cpufreq_deregister(struct mmc_davinci_host *host)
1106 static void init_mmcsd_host(struct mmc_davinci_host *host)
1109 mmc_davinci_reset_ctrl(host, 1);
1111 writel(0, host->base + DAVINCI_MMCCLK);
1112 writel(MMCCLK_CLKEN, host->base + DAVINCI_MMCCLK);
1114 writel(0x1FFF, host->base + DAVINCI_MMCTOR);
1115 writel(0xFFFF, host->base + DAVINCI_MMCTOD);
1117 mmc_davinci_reset_ctrl(host, 0);
1120 static const struct platform_device_id davinci_mmc_devtype[] = {
1122 .name = "dm6441-mmc",
1123 .driver_data = MMC_CTLR_VERSION_1,
1125 .name = "da830-mmc",
1126 .driver_data = MMC_CTLR_VERSION_2,
1130 MODULE_DEVICE_TABLE(platform, davinci_mmc_devtype);
1132 static const struct of_device_id davinci_mmc_dt_ids[] = {
1134 .compatible = "ti,dm6441-mmc",
1135 .data = &davinci_mmc_devtype[MMC_CTLR_VERSION_1],
1138 .compatible = "ti,da830-mmc",
1139 .data = &davinci_mmc_devtype[MMC_CTLR_VERSION_2],
1143 MODULE_DEVICE_TABLE(of, davinci_mmc_dt_ids);
1145 static int mmc_davinci_parse_pdata(struct mmc_host *mmc)
1147 struct platform_device *pdev = to_platform_device(mmc->parent);
1148 struct davinci_mmc_config *pdata = pdev->dev.platform_data;
1149 struct mmc_davinci_host *host;
1155 host = mmc_priv(mmc);
1159 if (pdata && pdata->nr_sg)
1160 host->nr_sg = pdata->nr_sg - 1;
1162 if (pdata && (pdata->wires == 4 || pdata->wires == 0))
1163 mmc->caps |= MMC_CAP_4_BIT_DATA;
1165 if (pdata && (pdata->wires == 8))
1166 mmc->caps |= (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA);
1168 mmc->f_min = 312500;
1169 mmc->f_max = 25000000;
1170 if (pdata && pdata->max_freq)
1171 mmc->f_max = pdata->max_freq;
1172 if (pdata && pdata->caps)
1173 mmc->caps |= pdata->caps;
1175 /* Register a cd gpio, if there is not one, enable polling */
1176 ret = mmc_gpiod_request_cd(mmc, "cd", 0, false, 0);
1177 if (ret == -EPROBE_DEFER)
1180 mmc->caps |= MMC_CAP_NEEDS_POLL;
1182 ret = mmc_gpiod_request_ro(mmc, "wp", 0, 0);
1183 if (ret == -EPROBE_DEFER)
1189 static int davinci_mmcsd_probe(struct platform_device *pdev)
1191 struct mmc_davinci_host *host = NULL;
1192 struct mmc_host *mmc = NULL;
1193 struct resource *r, *mem = NULL;
1196 const struct platform_device_id *id_entry;
1198 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1201 irq = platform_get_irq(pdev, 0);
1205 mem_size = resource_size(r);
1206 mem = devm_request_mem_region(&pdev->dev, r->start, mem_size,
1211 mmc = mmc_alloc_host(sizeof(struct mmc_davinci_host), &pdev->dev);
1215 host = mmc_priv(mmc);
1216 host->mmc = mmc; /* Important */
1218 host->mem_res = mem;
1219 host->base = devm_ioremap(&pdev->dev, mem->start, mem_size);
1225 host->clk = devm_clk_get(&pdev->dev, NULL);
1226 if (IS_ERR(host->clk)) {
1227 ret = PTR_ERR(host->clk);
1230 ret = clk_prepare_enable(host->clk);
1232 goto clk_prepare_enable_fail;
1234 host->mmc_input_clk = clk_get_rate(host->clk);
1236 pdev->id_entry = of_device_get_match_data(&pdev->dev);
1237 if (pdev->id_entry) {
1238 ret = mmc_of_parse(mmc);
1240 dev_err_probe(&pdev->dev, ret,
1241 "could not parse of data\n");
1245 ret = mmc_davinci_parse_pdata(mmc);
1248 "could not parse platform data: %d\n", ret);
1252 if (host->nr_sg > MAX_NR_SG || !host->nr_sg)
1253 host->nr_sg = MAX_NR_SG;
1255 init_mmcsd_host(host);
1257 host->use_dma = use_dma;
1258 host->mmc_irq = irq;
1259 host->sdio_irq = platform_get_irq_optional(pdev, 1);
1261 if (host->use_dma) {
1262 ret = davinci_acquire_dma_channels(host);
1263 if (ret == -EPROBE_DEFER)
1264 goto dma_probe_defer;
1269 mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
1271 id_entry = platform_get_device_id(pdev);
1273 host->version = id_entry->driver_data;
1275 mmc->ops = &mmc_davinci_ops;
1276 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1278 /* With no iommu coalescing pages, each phys_seg is a hw_seg.
1279 * Each hw_seg uses one EDMA parameter RAM slot, always one
1280 * channel and then usually some linked slots.
1282 mmc->max_segs = MAX_NR_SG;
1284 /* EDMA limit per hw segment (one or two MBytes) */
1285 mmc->max_seg_size = MAX_CCNT * rw_threshold;
1287 /* MMC/SD controller limits for multiblock requests */
1288 mmc->max_blk_size = 4095; /* BLEN is 12 bits */
1289 mmc->max_blk_count = 65535; /* NBLK is 16 bits */
1290 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1292 dev_dbg(mmc_dev(host->mmc), "max_segs=%d\n", mmc->max_segs);
1293 dev_dbg(mmc_dev(host->mmc), "max_blk_size=%d\n", mmc->max_blk_size);
1294 dev_dbg(mmc_dev(host->mmc), "max_req_size=%d\n", mmc->max_req_size);
1295 dev_dbg(mmc_dev(host->mmc), "max_seg_size=%d\n", mmc->max_seg_size);
1297 platform_set_drvdata(pdev, host);
1299 ret = mmc_davinci_cpufreq_register(host);
1301 dev_err(&pdev->dev, "failed to register cpufreq\n");
1305 ret = mmc_add_host(mmc);
1307 goto mmc_add_host_fail;
1309 ret = devm_request_irq(&pdev->dev, irq, mmc_davinci_irq, 0,
1310 mmc_hostname(mmc), host);
1312 goto request_irq_fail;
1314 if (host->sdio_irq >= 0) {
1315 ret = devm_request_irq(&pdev->dev, host->sdio_irq,
1316 mmc_davinci_sdio_irq, 0,
1317 mmc_hostname(mmc), host);
1319 mmc->caps |= MMC_CAP_SDIO_IRQ;
1322 rename_region(mem, mmc_hostname(mmc));
1324 dev_info(mmc_dev(host->mmc), "Using %s, %d-bit mode\n",
1325 host->use_dma ? "DMA" : "PIO",
1326 (mmc->caps & MMC_CAP_4_BIT_DATA) ? 4 : 1);
1331 mmc_remove_host(mmc);
1333 mmc_davinci_cpufreq_deregister(host);
1335 davinci_release_dma_channels(host);
1338 clk_disable_unprepare(host->clk);
1339 clk_prepare_enable_fail:
1347 static void __exit davinci_mmcsd_remove(struct platform_device *pdev)
1349 struct mmc_davinci_host *host = platform_get_drvdata(pdev);
1351 mmc_remove_host(host->mmc);
1352 mmc_davinci_cpufreq_deregister(host);
1353 davinci_release_dma_channels(host);
1354 clk_disable_unprepare(host->clk);
1355 mmc_free_host(host->mmc);
1359 static int davinci_mmcsd_suspend(struct device *dev)
1361 struct mmc_davinci_host *host = dev_get_drvdata(dev);
1363 writel(0, host->base + DAVINCI_MMCIM);
1364 mmc_davinci_reset_ctrl(host, 1);
1365 clk_disable(host->clk);
1370 static int davinci_mmcsd_resume(struct device *dev)
1372 struct mmc_davinci_host *host = dev_get_drvdata(dev);
1375 ret = clk_enable(host->clk);
1379 mmc_davinci_reset_ctrl(host, 0);
1384 static const struct dev_pm_ops davinci_mmcsd_pm = {
1385 .suspend = davinci_mmcsd_suspend,
1386 .resume = davinci_mmcsd_resume,
1389 #define davinci_mmcsd_pm_ops (&davinci_mmcsd_pm)
1391 #define davinci_mmcsd_pm_ops NULL
1394 static struct platform_driver davinci_mmcsd_driver = {
1396 .name = "davinci_mmc",
1397 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1398 .pm = davinci_mmcsd_pm_ops,
1399 .of_match_table = davinci_mmc_dt_ids,
1401 .probe = davinci_mmcsd_probe,
1402 .remove_new = __exit_p(davinci_mmcsd_remove),
1403 .id_table = davinci_mmc_devtype,
1406 module_platform_driver(davinci_mmcsd_driver);
1408 MODULE_AUTHOR("Texas Instruments India");
1409 MODULE_LICENSE("GPL");
1410 MODULE_DESCRIPTION("MMC/SD driver for Davinci MMC controller");
1411 MODULE_ALIAS("platform:davinci_mmc");