1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * SN Platform GRU Driver
5 * FAULT HANDLER FOR GRU DETECTED TLB MISSES
7 * This file contains code that handles TLB misses within the GRU.
8 * These misses are reported either via interrupts or user polling of
11 * Copyright (c) 2008 Silicon Graphics, Inc. All Rights Reserved.
14 #include <linux/kernel.h>
15 #include <linux/errno.h>
16 #include <linux/spinlock.h>
18 #include <linux/hugetlb.h>
19 #include <linux/device.h>
21 #include <linux/uaccess.h>
22 #include <linux/security.h>
23 #include <linux/sync_core.h>
24 #include <linux/prefetch.h>
26 #include "grutables.h"
28 #include "gru_instructions.h"
29 #include <asm/uv/uv_hub.h>
31 /* Return codes for vtop functions */
32 #define VTOP_SUCCESS 0
33 #define VTOP_INVALID -1
38 * Test if a physical address is a valid GRU GSEG address
40 static inline int is_gru_paddr(unsigned long paddr)
42 return paddr >= gru_start_paddr && paddr < gru_end_paddr;
46 * Find the vma of a GRU segment. Caller must hold mmap_lock.
48 struct vm_area_struct *gru_find_vma(unsigned long vaddr)
50 struct vm_area_struct *vma;
52 vma = find_vma(current->mm, vaddr);
53 if (vma && vma->vm_start <= vaddr && vma->vm_ops == &gru_vm_ops)
59 * Find and lock the gts that contains the specified user vaddr.
62 * - *gts with the mmap_lock locked for read and the GTS locked.
63 * - NULL if vaddr invalid OR is not a valid GSEG vaddr.
66 static struct gru_thread_state *gru_find_lock_gts(unsigned long vaddr)
68 struct mm_struct *mm = current->mm;
69 struct vm_area_struct *vma;
70 struct gru_thread_state *gts = NULL;
73 vma = gru_find_vma(vaddr);
75 gts = gru_find_thread_state(vma, TSID(vaddr, vma));
77 mutex_lock(>s->ts_ctxlock);
83 static struct gru_thread_state *gru_alloc_locked_gts(unsigned long vaddr)
85 struct mm_struct *mm = current->mm;
86 struct vm_area_struct *vma;
87 struct gru_thread_state *gts = ERR_PTR(-EINVAL);
90 vma = gru_find_vma(vaddr);
94 gts = gru_alloc_thread_state(vma, TSID(vaddr, vma));
97 mutex_lock(>s->ts_ctxlock);
98 mmap_write_downgrade(mm);
102 mmap_write_unlock(mm);
107 * Unlock a GTS that was previously locked with gru_find_lock_gts().
109 static void gru_unlock_gts(struct gru_thread_state *gts)
111 mutex_unlock(>s->ts_ctxlock);
112 mmap_read_unlock(current->mm);
116 * Set a CB.istatus to active using a user virtual address. This must be done
117 * just prior to a TFH RESTART. The new cb.istatus is an in-cache status ONLY.
118 * If the line is evicted, the status may be lost. The in-cache update
119 * is necessary to prevent the user from seeing a stale cb.istatus that will
120 * change as soon as the TFH restart is complete. Races may cause an
121 * occasional failure to clear the cb.istatus, but that is ok.
123 static void gru_cb_set_istatus_active(struct gru_instruction_bits *cbk)
126 cbk->istatus = CBS_ACTIVE;
133 * The GRU has an array of fault maps. A map is private to a cpu
134 * Only one cpu will be accessing a cpu's fault map.
136 * This function scans the cpu-private fault map & clears all bits that
137 * are set. The function returns a bitmap that indicates the bits that
138 * were cleared. Note that sense the maps may be updated asynchronously by
139 * the GRU, atomic operations must be used to clear bits.
141 static void get_clear_fault_map(struct gru_state *gru,
142 struct gru_tlb_fault_map *imap,
143 struct gru_tlb_fault_map *dmap)
146 struct gru_tlb_fault_map *tfm;
148 tfm = get_tfm_for_cpu(gru, gru_cpu_fault_map_id());
149 prefetchw(tfm); /* Helps on hardware, required for emulator */
150 for (i = 0; i < BITS_TO_LONGS(GRU_NUM_CBE); i++) {
151 k = tfm->fault_bits[i];
153 k = xchg(&tfm->fault_bits[i], 0UL);
154 imap->fault_bits[i] = k;
155 k = tfm->done_bits[i];
157 k = xchg(&tfm->done_bits[i], 0UL);
158 dmap->fault_bits[i] = k;
162 * Not functionally required but helps performance. (Required
165 gru_flush_cache(tfm);
169 * Atomic (interrupt context) & non-atomic (user context) functions to
170 * convert a vaddr into a physical address. The size of the page
171 * is returned in pageshift.
175 * 1 - (atomic only) try again in non-atomic context
177 static int non_atomic_pte_lookup(struct vm_area_struct *vma,
178 unsigned long vaddr, int write,
179 unsigned long *paddr, int *pageshift)
183 #ifdef CONFIG_HUGETLB_PAGE
184 *pageshift = is_vm_hugetlb_page(vma) ? HPAGE_SHIFT : PAGE_SHIFT;
186 *pageshift = PAGE_SHIFT;
188 if (get_user_pages(vaddr, 1, write ? FOLL_WRITE : 0, &page, NULL) <= 0)
190 *paddr = page_to_phys(page);
198 * Convert a user virtual address to a physical address
199 * Only supports Intel large pages (2MB only) on x86_64.
200 * ZZZ - hugepage support is incomplete
202 * NOTE: mmap_lock is already held on entry to this function. This
203 * guarantees existence of the page tables.
205 static int atomic_pte_lookup(struct vm_area_struct *vma, unsigned long vaddr,
206 int write, unsigned long *paddr, int *pageshift)
214 pgdp = pgd_offset(vma->vm_mm, vaddr);
215 if (unlikely(pgd_none(*pgdp)))
218 p4dp = p4d_offset(pgdp, vaddr);
219 if (unlikely(p4d_none(*p4dp)))
222 pudp = pud_offset(p4dp, vaddr);
223 if (unlikely(pud_none(*pudp)))
226 pmdp = pmd_offset(pudp, vaddr);
227 if (unlikely(pmd_none(*pmdp)))
230 if (unlikely(pmd_large(*pmdp)))
231 pte = *(pte_t *) pmdp;
234 pte = *pte_offset_kernel(pmdp, vaddr);
236 if (unlikely(!pte_present(pte) ||
237 (write && (!pte_write(pte) || !pte_dirty(pte)))))
240 *paddr = pte_pfn(pte) << PAGE_SHIFT;
241 #ifdef CONFIG_HUGETLB_PAGE
242 *pageshift = is_vm_hugetlb_page(vma) ? HPAGE_SHIFT : PAGE_SHIFT;
244 *pageshift = PAGE_SHIFT;
252 static int gru_vtop(struct gru_thread_state *gts, unsigned long vaddr,
253 int write, int atomic, unsigned long *gpa, int *pageshift)
255 struct mm_struct *mm = gts->ts_mm;
256 struct vm_area_struct *vma;
260 vma = find_vma(mm, vaddr);
265 * Atomic lookup is faster & usually works even if called in non-atomic
268 rmb(); /* Must/check ms_range_active before loading PTEs */
269 ret = atomic_pte_lookup(vma, vaddr, write, &paddr, &ps);
273 if (non_atomic_pte_lookup(vma, vaddr, write, &paddr, &ps))
276 if (is_gru_paddr(paddr))
278 paddr = paddr & ~((1UL << ps) - 1);
279 *gpa = uv_soc_phys_ram_to_gpa(paddr);
291 * Flush a CBE from cache. The CBE is clean in the cache. Dirty the
292 * CBE cacheline so that the line will be written back to home agent.
293 * Otherwise the line may be silently dropped. This has no impact
294 * except on performance.
296 static void gru_flush_cache_cbe(struct gru_control_block_extended *cbe)
299 cbe->cbrexecstatus = 0; /* make CL dirty */
300 gru_flush_cache(cbe);
305 * Preload the TLB with entries that may be required. Currently, preloading
306 * is implemented only for BCOPY. Preload <tlb_preload_count> pages OR to
307 * the end of the bcopy tranfer, whichever is smaller.
309 static void gru_preload_tlb(struct gru_state *gru,
310 struct gru_thread_state *gts, int atomic,
311 unsigned long fault_vaddr, int asid, int write,
312 unsigned char tlb_preload_count,
313 struct gru_tlb_fault_handle *tfh,
314 struct gru_control_block_extended *cbe)
316 unsigned long vaddr = 0, gpa;
319 if (cbe->opccpy != OP_BCOPY)
322 if (fault_vaddr == cbe->cbe_baddr0)
323 vaddr = fault_vaddr + GRU_CACHE_LINE_BYTES * cbe->cbe_src_cl - 1;
324 else if (fault_vaddr == cbe->cbe_baddr1)
325 vaddr = fault_vaddr + (1 << cbe->xtypecpy) * cbe->cbe_nelemcur - 1;
327 fault_vaddr &= PAGE_MASK;
329 vaddr = min(vaddr, fault_vaddr + tlb_preload_count * PAGE_SIZE);
331 while (vaddr > fault_vaddr) {
332 ret = gru_vtop(gts, vaddr, write, atomic, &gpa, &pageshift);
333 if (ret || tfh_write_only(tfh, gpa, GAA_RAM, vaddr, asid, write,
334 GRU_PAGESIZE(pageshift)))
337 "%s: gid %d, gts 0x%p, tfh 0x%p, vaddr 0x%lx, asid 0x%x, rw %d, ps %d, gpa 0x%lx\n",
338 atomic ? "atomic" : "non-atomic", gru->gs_gid, gts, tfh,
339 vaddr, asid, write, pageshift, gpa);
341 STAT(tlb_preload_page);
346 * Drop a TLB entry into the GRU. The fault is described by info in an TFH.
348 * cb Address of user CBR. Null if not running in user context
350 * 0 = dropin, exception, or switch to UPM successful
351 * 1 = range invalidate active
355 static int gru_try_dropin(struct gru_state *gru,
356 struct gru_thread_state *gts,
357 struct gru_tlb_fault_handle *tfh,
358 struct gru_instruction_bits *cbk)
360 struct gru_control_block_extended *cbe = NULL;
361 unsigned char tlb_preload_count = gts->ts_tlb_preload_count;
362 int pageshift = 0, asid, write, ret, atomic = !cbk, indexway;
363 unsigned long gpa = 0, vaddr = 0;
366 * NOTE: The GRU contains magic hardware that eliminates races between
367 * TLB invalidates and TLB dropins. If an invalidate occurs
368 * in the window between reading the TFH and the subsequent TLB dropin,
369 * the dropin is ignored. This eliminates the need for additional locks.
373 * Prefetch the CBE if doing TLB preloading
375 if (unlikely(tlb_preload_count)) {
376 cbe = gru_tfh_to_cbe(tfh);
381 * Error if TFH state is IDLE or FMM mode & the user issuing a UPM call.
382 * Might be a hardware race OR a stupid user. Ignore FMM because FMM
383 * is a transient state.
385 if (tfh->status != TFHSTATUS_EXCEPTION) {
386 gru_flush_cache(tfh);
388 if (tfh->status != TFHSTATUS_EXCEPTION)
389 goto failnoexception;
390 STAT(tfh_stale_on_fault);
392 if (tfh->state == TFHSTATE_IDLE)
394 if (tfh->state == TFHSTATE_MISS_FMM && cbk)
397 write = (tfh->cause & TFHCAUSE_TLB_MOD) != 0;
398 vaddr = tfh->missvaddr;
399 asid = tfh->missasid;
400 indexway = tfh->indexway;
404 rmb(); /* TFH must be cache resident before reading ms_range_active */
407 * TFH is cache resident - at least briefly. Fail the dropin
408 * if a range invalidate is active.
410 if (atomic_read(>s->ts_gms->ms_range_active))
413 ret = gru_vtop(gts, vaddr, write, atomic, &gpa, &pageshift);
414 if (ret == VTOP_INVALID)
416 if (ret == VTOP_RETRY)
419 if (!(gts->ts_sizeavail & GRU_SIZEAVAIL(pageshift))) {
420 gts->ts_sizeavail |= GRU_SIZEAVAIL(pageshift);
421 if (atomic || !gru_update_cch(gts)) {
422 gts->ts_force_cch_reload = 1;
427 if (unlikely(cbe) && pageshift == PAGE_SHIFT) {
428 gru_preload_tlb(gru, gts, atomic, vaddr, asid, write, tlb_preload_count, tfh, cbe);
429 gru_flush_cache_cbe(cbe);
432 gru_cb_set_istatus_active(cbk);
433 gts->ustats.tlbdropin++;
434 tfh_write_restart(tfh, gpa, GAA_RAM, vaddr, asid, write,
435 GRU_PAGESIZE(pageshift));
437 "%s: gid %d, gts 0x%p, tfh 0x%p, vaddr 0x%lx, asid 0x%x, indexway 0x%x,"
438 " rw %d, ps %d, gpa 0x%lx\n",
439 atomic ? "atomic" : "non-atomic", gru->gs_gid, gts, tfh, vaddr, asid,
440 indexway, write, pageshift, gpa);
445 /* No asid (delayed unload). */
446 STAT(tlb_dropin_fail_no_asid);
447 gru_dbg(grudev, "FAILED no_asid tfh: 0x%p, vaddr 0x%lx\n", tfh, vaddr);
449 tfh_user_polling_mode(tfh);
451 gru_flush_cache(tfh);
452 gru_flush_cache_cbe(cbe);
456 /* Atomic failure switch CBR to UPM */
457 tfh_user_polling_mode(tfh);
458 gru_flush_cache_cbe(cbe);
459 STAT(tlb_dropin_fail_upm);
460 gru_dbg(grudev, "FAILED upm tfh: 0x%p, vaddr 0x%lx\n", tfh, vaddr);
464 /* FMM state on UPM call */
465 gru_flush_cache(tfh);
466 gru_flush_cache_cbe(cbe);
467 STAT(tlb_dropin_fail_fmm);
468 gru_dbg(grudev, "FAILED fmm tfh: 0x%p, state %d\n", tfh, tfh->state);
472 /* TFH status did not show exception pending */
473 gru_flush_cache(tfh);
474 gru_flush_cache_cbe(cbe);
476 gru_flush_cache(cbk);
477 STAT(tlb_dropin_fail_no_exception);
478 gru_dbg(grudev, "FAILED non-exception tfh: 0x%p, status %d, state %d\n",
479 tfh, tfh->status, tfh->state);
483 /* TFH state was idle - no miss pending */
484 gru_flush_cache(tfh);
485 gru_flush_cache_cbe(cbe);
487 gru_flush_cache(cbk);
488 STAT(tlb_dropin_fail_idle);
489 gru_dbg(grudev, "FAILED idle tfh: 0x%p, state %d\n", tfh, tfh->state);
493 /* All errors (atomic & non-atomic) switch CBR to EXCEPTION state */
495 gru_flush_cache_cbe(cbe);
496 STAT(tlb_dropin_fail_invalid);
497 gru_dbg(grudev, "FAILED inval tfh: 0x%p, vaddr 0x%lx\n", tfh, vaddr);
501 /* Range invalidate active. Switch to UPM iff atomic */
503 tfh_user_polling_mode(tfh);
505 gru_flush_cache(tfh);
506 gru_flush_cache_cbe(cbe);
507 STAT(tlb_dropin_fail_range_active);
508 gru_dbg(grudev, "FAILED range active: tfh 0x%p, vaddr 0x%lx\n",
514 * Process an external interrupt from the GRU. This interrupt is
515 * caused by a TLB miss.
516 * Note that this is the interrupt handler that is registered with linux
517 * interrupt handlers.
519 static irqreturn_t gru_intr(int chiplet, int blade)
521 struct gru_state *gru;
522 struct gru_tlb_fault_map imap, dmap;
523 struct gru_thread_state *gts;
524 struct gru_tlb_fault_handle *tfh = NULL;
525 struct completion *cmp;
530 gru = &gru_base[blade]->bs_grus[chiplet];
532 dev_err(grudev, "GRU: invalid interrupt: cpu %d, chiplet %d\n",
533 raw_smp_processor_id(), chiplet);
536 get_clear_fault_map(gru, &imap, &dmap);
538 "cpu %d, chiplet %d, gid %d, imap %016lx %016lx, dmap %016lx %016lx\n",
539 smp_processor_id(), chiplet, gru->gs_gid,
540 imap.fault_bits[0], imap.fault_bits[1],
541 dmap.fault_bits[0], dmap.fault_bits[1]);
543 for_each_cbr_in_tfm(cbrnum, dmap.fault_bits) {
545 cmp = gru->gs_blade->bs_async_wq;
548 gru_dbg(grudev, "gid %d, cbr_done %d, done %d\n",
549 gru->gs_gid, cbrnum, cmp ? cmp->done : -1);
552 for_each_cbr_in_tfm(cbrnum, imap.fault_bits) {
554 tfh = get_tfh_by_index(gru, cbrnum);
555 prefetchw(tfh); /* Helps on hdw, required for emulator */
558 * When hardware sets a bit in the faultmap, it implicitly
559 * locks the GRU context so that it cannot be unloaded.
560 * The gts cannot change until a TFH start/writestart command
563 ctxnum = tfh->ctxnum;
564 gts = gru->gs_gts[ctxnum];
566 /* Spurious interrupts can cause this. Ignore. */
573 * This is running in interrupt context. Trylock the mmap_lock.
574 * If it fails, retry the fault in user context.
576 gts->ustats.fmm_tlbmiss++;
577 if (!gts->ts_force_cch_reload &&
578 mmap_read_trylock(gts->ts_mm)) {
579 gru_try_dropin(gru, gts, tfh, NULL);
580 mmap_read_unlock(gts->ts_mm);
582 tfh_user_polling_mode(tfh);
583 STAT(intr_mm_lock_failed);
589 irqreturn_t gru0_intr(int irq, void *dev_id)
591 return gru_intr(0, uv_numa_blade_id());
594 irqreturn_t gru1_intr(int irq, void *dev_id)
596 return gru_intr(1, uv_numa_blade_id());
599 irqreturn_t gru_intr_mblade(int irq, void *dev_id)
603 for_each_possible_blade(blade) {
604 if (uv_blade_nr_possible_cpus(blade))
613 static int gru_user_dropin(struct gru_thread_state *gts,
614 struct gru_tlb_fault_handle *tfh,
617 struct gru_mm_struct *gms = gts->ts_gms;
620 gts->ustats.upm_tlbmiss++;
622 wait_event(gms->ms_wait_queue,
623 atomic_read(&gms->ms_range_active) == 0);
624 prefetchw(tfh); /* Helps on hdw, required for emulator */
625 ret = gru_try_dropin(gts->ts_gru, gts, tfh, cb);
628 STAT(call_os_wait_queue);
633 * This interface is called as a result of a user detecting a "call OS" bit
634 * in a user CB. Normally means that a TLB fault has occurred.
635 * cb - user virtual address of the CB
637 int gru_handle_user_call_os(unsigned long cb)
639 struct gru_tlb_fault_handle *tfh;
640 struct gru_thread_state *gts;
642 int ucbnum, cbrnum, ret = -EINVAL;
646 /* sanity check the cb pointer */
647 ucbnum = get_cb_number((void *)cb);
648 if ((cb & (GRU_HANDLE_STRIDE - 1)) || ucbnum >= GRU_NUM_CB)
652 gts = gru_find_lock_gts(cb);
655 gru_dbg(grudev, "address 0x%lx, gid %d, gts 0x%p\n", cb, gts->ts_gru ? gts->ts_gru->gs_gid : -1, gts);
657 if (ucbnum >= gts->ts_cbr_au_count * GRU_CBR_AU_SIZE)
660 if (gru_check_context_placement(gts)) {
662 gru_unload_context(gts, 1);
667 * CCH may contain stale data if ts_force_cch_reload is set.
669 if (gts->ts_gru && gts->ts_force_cch_reload) {
670 gts->ts_force_cch_reload = 0;
675 cbrnum = thread_cbr_number(gts, ucbnum);
677 tfh = get_tfh_by_index(gts->ts_gru, cbrnum);
678 cbk = get_gseg_base_address_cb(gts->ts_gru->gs_gru_base_vaddr,
679 gts->ts_ctxnum, ucbnum);
680 ret = gru_user_dropin(gts, tfh, cbk);
688 * Fetch the exception detail information for a CB that terminated with
691 int gru_get_exception_detail(unsigned long arg)
693 struct control_block_extended_exc_detail excdet;
694 struct gru_control_block_extended *cbe;
695 struct gru_thread_state *gts;
696 int ucbnum, cbrnum, ret;
698 STAT(user_exception);
699 if (copy_from_user(&excdet, (void __user *)arg, sizeof(excdet)))
702 gts = gru_find_lock_gts(excdet.cb);
706 gru_dbg(grudev, "address 0x%lx, gid %d, gts 0x%p\n", excdet.cb, gts->ts_gru ? gts->ts_gru->gs_gid : -1, gts);
707 ucbnum = get_cb_number((void *)excdet.cb);
708 if (ucbnum >= gts->ts_cbr_au_count * GRU_CBR_AU_SIZE) {
710 } else if (gts->ts_gru) {
711 cbrnum = thread_cbr_number(gts, ucbnum);
712 cbe = get_cbe_by_index(gts->ts_gru, cbrnum);
713 gru_flush_cache(cbe); /* CBE not coherent */
714 sync_core(); /* make sure we are have current data */
715 excdet.opc = cbe->opccpy;
716 excdet.exopc = cbe->exopccpy;
717 excdet.ecause = cbe->ecause;
718 excdet.exceptdet0 = cbe->idef1upd;
719 excdet.exceptdet1 = cbe->idef3upd;
720 excdet.cbrstate = cbe->cbrstate;
721 excdet.cbrexecstatus = cbe->cbrexecstatus;
722 gru_flush_cache_cbe(cbe);
730 "cb 0x%lx, op %d, exopc %d, cbrstate %d, cbrexecstatus 0x%x, ecause 0x%x, "
731 "exdet0 0x%lx, exdet1 0x%x\n",
732 excdet.cb, excdet.opc, excdet.exopc, excdet.cbrstate, excdet.cbrexecstatus,
733 excdet.ecause, excdet.exceptdet0, excdet.exceptdet1);
734 if (!ret && copy_to_user((void __user *)arg, &excdet, sizeof(excdet)))
740 * User request to unload a context. Content is saved for possible reload.
742 static int gru_unload_all_contexts(void)
744 struct gru_thread_state *gts;
745 struct gru_state *gru;
748 if (!capable(CAP_SYS_ADMIN))
751 gru = GID_TO_GRU(gid);
752 spin_lock(&gru->gs_lock);
753 for (ctxnum = 0; ctxnum < GRU_NUM_CCH; ctxnum++) {
754 gts = gru->gs_gts[ctxnum];
755 if (gts && mutex_trylock(>s->ts_ctxlock)) {
756 spin_unlock(&gru->gs_lock);
757 gru_unload_context(gts, 1);
758 mutex_unlock(>s->ts_ctxlock);
759 spin_lock(&gru->gs_lock);
762 spin_unlock(&gru->gs_lock);
767 int gru_user_unload_context(unsigned long arg)
769 struct gru_thread_state *gts;
770 struct gru_unload_context_req req;
772 STAT(user_unload_context);
773 if (copy_from_user(&req, (void __user *)arg, sizeof(req)))
776 gru_dbg(grudev, "gseg 0x%lx\n", req.gseg);
779 return gru_unload_all_contexts();
781 gts = gru_find_lock_gts(req.gseg);
786 gru_unload_context(gts, 1);
793 * User request to flush a range of virtual addresses from the GRU TLB
794 * (Mainly for testing).
796 int gru_user_flush_tlb(unsigned long arg)
798 struct gru_thread_state *gts;
799 struct gru_flush_tlb_req req;
800 struct gru_mm_struct *gms;
802 STAT(user_flush_tlb);
803 if (copy_from_user(&req, (void __user *)arg, sizeof(req)))
806 gru_dbg(grudev, "gseg 0x%lx, vaddr 0x%lx, len 0x%lx\n", req.gseg,
809 gts = gru_find_lock_gts(req.gseg);
815 gru_flush_tlb_range(gms, req.vaddr, req.len);
821 * Fetch GSEG statisticss
823 long gru_get_gseg_statistics(unsigned long arg)
825 struct gru_thread_state *gts;
826 struct gru_get_gseg_statistics_req req;
828 if (copy_from_user(&req, (void __user *)arg, sizeof(req)))
832 * The library creates arrays of contexts for threaded programs.
833 * If no gts exists in the array, the context has never been used & all
834 * statistics are implicitly 0.
836 gts = gru_find_lock_gts(req.gseg);
838 memcpy(&req.stats, >s->ustats, sizeof(gts->ustats));
841 memset(&req.stats, 0, sizeof(gts->ustats));
844 if (copy_to_user((void __user *)arg, &req, sizeof(req)))
851 * Register the current task as the user of the GSEG slice.
852 * Needed for TLB fault interrupt targeting.
854 int gru_set_context_option(unsigned long arg)
856 struct gru_thread_state *gts;
857 struct gru_set_context_option_req req;
860 STAT(set_context_option);
861 if (copy_from_user(&req, (void __user *)arg, sizeof(req)))
863 gru_dbg(grudev, "op %d, gseg 0x%lx, value1 0x%lx\n", req.op, req.gseg, req.val1);
865 gts = gru_find_lock_gts(req.gseg);
867 gts = gru_alloc_locked_gts(req.gseg);
873 case sco_blade_chiplet:
874 /* Select blade/chiplet for GRU context */
875 if (req.val0 < -1 || req.val0 >= GRU_CHIPLETS_PER_HUB ||
876 req.val1 < -1 || req.val1 >= GRU_MAX_BLADES ||
877 (req.val1 >= 0 && !gru_base[req.val1])) {
880 gts->ts_user_blade_id = req.val1;
881 gts->ts_user_chiplet_id = req.val0;
882 if (gru_check_context_placement(gts)) {
884 gru_unload_context(gts, 1);
890 /* Register the current task as the GSEG owner */
891 gts->ts_tgid_owner = current->tgid;
893 case sco_cch_req_slice:
894 /* Set the CCH slice option */
895 gts->ts_cch_req_slice = req.val1 & 3;