1 // SPDX-License-Identifier: GPL-2.0-only
3 * Host side test driver to test endpoint functionality
5 * Copyright (C) 2017 Texas Instruments
6 * Author: Kishon Vijay Abraham I <kishon@ti.com>
9 #include <linux/crc32.h>
10 #include <linux/delay.h>
13 #include <linux/interrupt.h>
14 #include <linux/irq.h>
15 #include <linux/miscdevice.h>
16 #include <linux/module.h>
17 #include <linux/mutex.h>
18 #include <linux/random.h>
19 #include <linux/slab.h>
20 #include <linux/uaccess.h>
21 #include <linux/pci.h>
22 #include <linux/pci_ids.h>
24 #include <linux/pci_regs.h>
26 #include <uapi/linux/pcitest.h>
28 #define DRV_MODULE_NAME "pci-endpoint-test"
30 #define IRQ_TYPE_UNDEFINED -1
31 #define IRQ_TYPE_LEGACY 0
32 #define IRQ_TYPE_MSI 1
33 #define IRQ_TYPE_MSIX 2
35 #define PCI_ENDPOINT_TEST_MAGIC 0x0
37 #define PCI_ENDPOINT_TEST_COMMAND 0x4
38 #define COMMAND_RAISE_LEGACY_IRQ BIT(0)
39 #define COMMAND_RAISE_MSI_IRQ BIT(1)
40 #define COMMAND_RAISE_MSIX_IRQ BIT(2)
41 #define COMMAND_READ BIT(3)
42 #define COMMAND_WRITE BIT(4)
43 #define COMMAND_COPY BIT(5)
45 #define PCI_ENDPOINT_TEST_STATUS 0x8
46 #define STATUS_READ_SUCCESS BIT(0)
47 #define STATUS_READ_FAIL BIT(1)
48 #define STATUS_WRITE_SUCCESS BIT(2)
49 #define STATUS_WRITE_FAIL BIT(3)
50 #define STATUS_COPY_SUCCESS BIT(4)
51 #define STATUS_COPY_FAIL BIT(5)
52 #define STATUS_IRQ_RAISED BIT(6)
53 #define STATUS_SRC_ADDR_INVALID BIT(7)
54 #define STATUS_DST_ADDR_INVALID BIT(8)
56 #define PCI_ENDPOINT_TEST_LOWER_SRC_ADDR 0x0c
57 #define PCI_ENDPOINT_TEST_UPPER_SRC_ADDR 0x10
59 #define PCI_ENDPOINT_TEST_LOWER_DST_ADDR 0x14
60 #define PCI_ENDPOINT_TEST_UPPER_DST_ADDR 0x18
62 #define PCI_ENDPOINT_TEST_SIZE 0x1c
63 #define PCI_ENDPOINT_TEST_CHECKSUM 0x20
65 #define PCI_ENDPOINT_TEST_IRQ_TYPE 0x24
66 #define PCI_ENDPOINT_TEST_IRQ_NUMBER 0x28
68 #define PCI_ENDPOINT_TEST_FLAGS 0x2c
69 #define FLAG_USE_DMA BIT(0)
71 #define PCI_DEVICE_ID_TI_J721E 0xb00d
72 #define PCI_DEVICE_ID_TI_AM654 0xb00c
73 #define PCI_DEVICE_ID_TI_J7200 0xb00f
74 #define PCI_DEVICE_ID_TI_AM64 0xb010
75 #define PCI_DEVICE_ID_TI_J721S2 0xb013
76 #define PCI_DEVICE_ID_LS1088A 0x80c0
78 #define is_am654_pci_dev(pdev) \
79 ((pdev)->device == PCI_DEVICE_ID_TI_AM654)
81 #define PCI_DEVICE_ID_RENESAS_R8A774A1 0x0028
82 #define PCI_DEVICE_ID_RENESAS_R8A774B1 0x002b
83 #define PCI_DEVICE_ID_RENESAS_R8A774C0 0x002d
84 #define PCI_DEVICE_ID_RENESAS_R8A774E1 0x0025
85 #define PCI_DEVICE_ID_RENESAS_R8A779F0 0x0031
87 static DEFINE_IDA(pci_endpoint_test_ida);
89 #define to_endpoint_test(priv) container_of((priv), struct pci_endpoint_test, \
93 module_param(no_msi, bool, 0444);
94 MODULE_PARM_DESC(no_msi, "Disable MSI interrupt in pci_endpoint_test");
96 static int irq_type = IRQ_TYPE_MSI;
97 module_param(irq_type, int, 0444);
98 MODULE_PARM_DESC(irq_type, "IRQ mode selection in pci_endpoint_test (0 - Legacy, 1 - MSI, 2 - MSI-X)");
109 struct pci_endpoint_test {
110 struct pci_dev *pdev;
112 void __iomem *bar[PCI_STD_NUM_BARS];
113 struct completion irq_raised;
117 /* mutex to protect the ioctls */
119 struct miscdevice miscdev;
120 enum pci_barno test_reg_bar;
125 struct pci_endpoint_test_data {
126 enum pci_barno test_reg_bar;
131 static inline u32 pci_endpoint_test_readl(struct pci_endpoint_test *test,
134 return readl(test->base + offset);
137 static inline void pci_endpoint_test_writel(struct pci_endpoint_test *test,
138 u32 offset, u32 value)
140 writel(value, test->base + offset);
143 static inline u32 pci_endpoint_test_bar_readl(struct pci_endpoint_test *test,
146 return readl(test->bar[bar] + offset);
149 static inline void pci_endpoint_test_bar_writel(struct pci_endpoint_test *test,
150 int bar, u32 offset, u32 value)
152 writel(value, test->bar[bar] + offset);
155 static irqreturn_t pci_endpoint_test_irqhandler(int irq, void *dev_id)
157 struct pci_endpoint_test *test = dev_id;
160 reg = pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_STATUS);
161 if (reg & STATUS_IRQ_RAISED) {
162 test->last_irq = irq;
163 complete(&test->irq_raised);
164 reg &= ~STATUS_IRQ_RAISED;
166 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_STATUS,
172 static void pci_endpoint_test_free_irq_vectors(struct pci_endpoint_test *test)
174 struct pci_dev *pdev = test->pdev;
176 pci_free_irq_vectors(pdev);
177 test->irq_type = IRQ_TYPE_UNDEFINED;
180 static bool pci_endpoint_test_alloc_irq_vectors(struct pci_endpoint_test *test,
184 struct pci_dev *pdev = test->pdev;
185 struct device *dev = &pdev->dev;
189 case IRQ_TYPE_LEGACY:
190 irq = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_LEGACY);
192 dev_err(dev, "Failed to get Legacy interrupt\n");
195 irq = pci_alloc_irq_vectors(pdev, 1, 32, PCI_IRQ_MSI);
197 dev_err(dev, "Failed to get MSI interrupts\n");
200 irq = pci_alloc_irq_vectors(pdev, 1, 2048, PCI_IRQ_MSIX);
202 dev_err(dev, "Failed to get MSI-X interrupts\n");
205 dev_err(dev, "Invalid IRQ type selected\n");
213 test->irq_type = type;
214 test->num_irqs = irq;
219 static void pci_endpoint_test_release_irq(struct pci_endpoint_test *test)
222 struct pci_dev *pdev = test->pdev;
223 struct device *dev = &pdev->dev;
225 for (i = 0; i < test->num_irqs; i++)
226 devm_free_irq(dev, pci_irq_vector(pdev, i), test);
231 static bool pci_endpoint_test_request_irq(struct pci_endpoint_test *test)
235 struct pci_dev *pdev = test->pdev;
236 struct device *dev = &pdev->dev;
238 for (i = 0; i < test->num_irqs; i++) {
239 err = devm_request_irq(dev, pci_irq_vector(pdev, i),
240 pci_endpoint_test_irqhandler,
241 IRQF_SHARED, test->name, test);
250 case IRQ_TYPE_LEGACY:
251 dev_err(dev, "Failed to request IRQ %d for Legacy\n",
252 pci_irq_vector(pdev, i));
255 dev_err(dev, "Failed to request IRQ %d for MSI %d\n",
256 pci_irq_vector(pdev, i),
260 dev_err(dev, "Failed to request IRQ %d for MSI-X %d\n",
261 pci_irq_vector(pdev, i),
269 static bool pci_endpoint_test_bar(struct pci_endpoint_test *test,
270 enum pci_barno barno)
275 struct pci_dev *pdev = test->pdev;
277 if (!test->bar[barno])
280 size = pci_resource_len(pdev, barno);
282 if (barno == test->test_reg_bar)
285 for (j = 0; j < size; j += 4)
286 pci_endpoint_test_bar_writel(test, barno, j, 0xA0A0A0A0);
288 for (j = 0; j < size; j += 4) {
289 val = pci_endpoint_test_bar_readl(test, barno, j);
290 if (val != 0xA0A0A0A0)
297 static bool pci_endpoint_test_legacy_irq(struct pci_endpoint_test *test)
301 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE,
303 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 0);
304 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
305 COMMAND_RAISE_LEGACY_IRQ);
306 val = wait_for_completion_timeout(&test->irq_raised,
307 msecs_to_jiffies(1000));
314 static bool pci_endpoint_test_msi_irq(struct pci_endpoint_test *test,
315 u16 msi_num, bool msix)
318 struct pci_dev *pdev = test->pdev;
320 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE,
321 msix == false ? IRQ_TYPE_MSI :
323 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, msi_num);
324 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
325 msix == false ? COMMAND_RAISE_MSI_IRQ :
326 COMMAND_RAISE_MSIX_IRQ);
327 val = wait_for_completion_timeout(&test->irq_raised,
328 msecs_to_jiffies(1000));
332 if (pci_irq_vector(pdev, msi_num - 1) == test->last_irq)
338 static int pci_endpoint_test_validate_xfer_params(struct device *dev,
339 struct pci_endpoint_test_xfer_param *param, size_t alignment)
342 dev_dbg(dev, "Data size is zero\n");
346 if (param->size > SIZE_MAX - alignment) {
347 dev_dbg(dev, "Maximum transfer data size exceeded\n");
354 static bool pci_endpoint_test_copy(struct pci_endpoint_test *test,
357 struct pci_endpoint_test_xfer_param param;
364 dma_addr_t src_phys_addr;
365 dma_addr_t dst_phys_addr;
366 struct pci_dev *pdev = test->pdev;
367 struct device *dev = &pdev->dev;
369 dma_addr_t orig_src_phys_addr;
371 dma_addr_t orig_dst_phys_addr;
373 size_t alignment = test->alignment;
374 int irq_type = test->irq_type;
379 err = copy_from_user(¶m, (void __user *)arg, sizeof(param));
381 dev_err(dev, "Failed to get transfer param\n");
385 err = pci_endpoint_test_validate_xfer_params(dev, ¶m, alignment);
391 use_dma = !!(param.flags & PCITEST_FLAGS_USE_DMA);
393 flags |= FLAG_USE_DMA;
395 if (irq_type < IRQ_TYPE_LEGACY || irq_type > IRQ_TYPE_MSIX) {
396 dev_err(dev, "Invalid IRQ type option\n");
400 orig_src_addr = kzalloc(size + alignment, GFP_KERNEL);
401 if (!orig_src_addr) {
402 dev_err(dev, "Failed to allocate source buffer\n");
407 get_random_bytes(orig_src_addr, size + alignment);
408 orig_src_phys_addr = dma_map_single(dev, orig_src_addr,
409 size + alignment, DMA_TO_DEVICE);
410 if (dma_mapping_error(dev, orig_src_phys_addr)) {
411 dev_err(dev, "failed to map source buffer address\n");
413 goto err_src_phys_addr;
416 if (alignment && !IS_ALIGNED(orig_src_phys_addr, alignment)) {
417 src_phys_addr = PTR_ALIGN(orig_src_phys_addr, alignment);
418 offset = src_phys_addr - orig_src_phys_addr;
419 src_addr = orig_src_addr + offset;
421 src_phys_addr = orig_src_phys_addr;
422 src_addr = orig_src_addr;
425 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_SRC_ADDR,
426 lower_32_bits(src_phys_addr));
428 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_SRC_ADDR,
429 upper_32_bits(src_phys_addr));
431 src_crc32 = crc32_le(~0, src_addr, size);
433 orig_dst_addr = kzalloc(size + alignment, GFP_KERNEL);
434 if (!orig_dst_addr) {
435 dev_err(dev, "Failed to allocate destination address\n");
440 orig_dst_phys_addr = dma_map_single(dev, orig_dst_addr,
441 size + alignment, DMA_FROM_DEVICE);
442 if (dma_mapping_error(dev, orig_dst_phys_addr)) {
443 dev_err(dev, "failed to map destination buffer address\n");
445 goto err_dst_phys_addr;
448 if (alignment && !IS_ALIGNED(orig_dst_phys_addr, alignment)) {
449 dst_phys_addr = PTR_ALIGN(orig_dst_phys_addr, alignment);
450 offset = dst_phys_addr - orig_dst_phys_addr;
451 dst_addr = orig_dst_addr + offset;
453 dst_phys_addr = orig_dst_phys_addr;
454 dst_addr = orig_dst_addr;
457 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_DST_ADDR,
458 lower_32_bits(dst_phys_addr));
459 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_DST_ADDR,
460 upper_32_bits(dst_phys_addr));
462 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE,
465 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_FLAGS, flags);
466 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, irq_type);
467 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1);
468 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
471 wait_for_completion(&test->irq_raised);
473 dma_unmap_single(dev, orig_dst_phys_addr, size + alignment,
476 dst_crc32 = crc32_le(~0, dst_addr, size);
477 if (dst_crc32 == src_crc32)
481 kfree(orig_dst_addr);
484 dma_unmap_single(dev, orig_src_phys_addr, size + alignment,
488 kfree(orig_src_addr);
494 static bool pci_endpoint_test_write(struct pci_endpoint_test *test,
497 struct pci_endpoint_test_xfer_param param;
503 dma_addr_t phys_addr;
504 struct pci_dev *pdev = test->pdev;
505 struct device *dev = &pdev->dev;
507 dma_addr_t orig_phys_addr;
509 size_t alignment = test->alignment;
510 int irq_type = test->irq_type;
515 err = copy_from_user(¶m, (void __user *)arg, sizeof(param));
517 dev_err(dev, "Failed to get transfer param\n");
521 err = pci_endpoint_test_validate_xfer_params(dev, ¶m, alignment);
527 use_dma = !!(param.flags & PCITEST_FLAGS_USE_DMA);
529 flags |= FLAG_USE_DMA;
531 if (irq_type < IRQ_TYPE_LEGACY || irq_type > IRQ_TYPE_MSIX) {
532 dev_err(dev, "Invalid IRQ type option\n");
536 orig_addr = kzalloc(size + alignment, GFP_KERNEL);
538 dev_err(dev, "Failed to allocate address\n");
543 get_random_bytes(orig_addr, size + alignment);
545 orig_phys_addr = dma_map_single(dev, orig_addr, size + alignment,
547 if (dma_mapping_error(dev, orig_phys_addr)) {
548 dev_err(dev, "failed to map source buffer address\n");
553 if (alignment && !IS_ALIGNED(orig_phys_addr, alignment)) {
554 phys_addr = PTR_ALIGN(orig_phys_addr, alignment);
555 offset = phys_addr - orig_phys_addr;
556 addr = orig_addr + offset;
558 phys_addr = orig_phys_addr;
562 crc32 = crc32_le(~0, addr, size);
563 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_CHECKSUM,
566 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_SRC_ADDR,
567 lower_32_bits(phys_addr));
568 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_SRC_ADDR,
569 upper_32_bits(phys_addr));
571 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size);
573 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_FLAGS, flags);
574 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, irq_type);
575 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1);
576 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
579 wait_for_completion(&test->irq_raised);
581 reg = pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_STATUS);
582 if (reg & STATUS_READ_SUCCESS)
585 dma_unmap_single(dev, orig_phys_addr, size + alignment,
595 static bool pci_endpoint_test_read(struct pci_endpoint_test *test,
598 struct pci_endpoint_test_xfer_param param;
604 dma_addr_t phys_addr;
605 struct pci_dev *pdev = test->pdev;
606 struct device *dev = &pdev->dev;
608 dma_addr_t orig_phys_addr;
610 size_t alignment = test->alignment;
611 int irq_type = test->irq_type;
615 err = copy_from_user(¶m, (void __user *)arg, sizeof(param));
617 dev_err(dev, "Failed to get transfer param\n");
621 err = pci_endpoint_test_validate_xfer_params(dev, ¶m, alignment);
627 use_dma = !!(param.flags & PCITEST_FLAGS_USE_DMA);
629 flags |= FLAG_USE_DMA;
631 if (irq_type < IRQ_TYPE_LEGACY || irq_type > IRQ_TYPE_MSIX) {
632 dev_err(dev, "Invalid IRQ type option\n");
636 orig_addr = kzalloc(size + alignment, GFP_KERNEL);
638 dev_err(dev, "Failed to allocate destination address\n");
643 orig_phys_addr = dma_map_single(dev, orig_addr, size + alignment,
645 if (dma_mapping_error(dev, orig_phys_addr)) {
646 dev_err(dev, "failed to map source buffer address\n");
651 if (alignment && !IS_ALIGNED(orig_phys_addr, alignment)) {
652 phys_addr = PTR_ALIGN(orig_phys_addr, alignment);
653 offset = phys_addr - orig_phys_addr;
654 addr = orig_addr + offset;
656 phys_addr = orig_phys_addr;
660 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_DST_ADDR,
661 lower_32_bits(phys_addr));
662 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_DST_ADDR,
663 upper_32_bits(phys_addr));
665 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size);
667 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_FLAGS, flags);
668 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, irq_type);
669 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1);
670 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
673 wait_for_completion(&test->irq_raised);
675 dma_unmap_single(dev, orig_phys_addr, size + alignment,
678 crc32 = crc32_le(~0, addr, size);
679 if (crc32 == pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_CHECKSUM))
688 static bool pci_endpoint_test_clear_irq(struct pci_endpoint_test *test)
690 pci_endpoint_test_release_irq(test);
691 pci_endpoint_test_free_irq_vectors(test);
695 static bool pci_endpoint_test_set_irq(struct pci_endpoint_test *test,
698 struct pci_dev *pdev = test->pdev;
699 struct device *dev = &pdev->dev;
701 if (req_irq_type < IRQ_TYPE_LEGACY || req_irq_type > IRQ_TYPE_MSIX) {
702 dev_err(dev, "Invalid IRQ type option\n");
706 if (test->irq_type == req_irq_type)
709 pci_endpoint_test_release_irq(test);
710 pci_endpoint_test_free_irq_vectors(test);
712 if (!pci_endpoint_test_alloc_irq_vectors(test, req_irq_type))
715 if (!pci_endpoint_test_request_irq(test))
721 pci_endpoint_test_free_irq_vectors(test);
725 static long pci_endpoint_test_ioctl(struct file *file, unsigned int cmd,
730 struct pci_endpoint_test *test = to_endpoint_test(file->private_data);
731 struct pci_dev *pdev = test->pdev;
733 mutex_lock(&test->mutex);
735 reinit_completion(&test->irq_raised);
736 test->last_irq = -ENODATA;
741 if (bar < 0 || bar > 5)
743 if (is_am654_pci_dev(pdev) && bar == BAR_0)
745 ret = pci_endpoint_test_bar(test, bar);
747 case PCITEST_LEGACY_IRQ:
748 ret = pci_endpoint_test_legacy_irq(test);
752 ret = pci_endpoint_test_msi_irq(test, arg, cmd == PCITEST_MSIX);
755 ret = pci_endpoint_test_write(test, arg);
758 ret = pci_endpoint_test_read(test, arg);
761 ret = pci_endpoint_test_copy(test, arg);
763 case PCITEST_SET_IRQTYPE:
764 ret = pci_endpoint_test_set_irq(test, arg);
766 case PCITEST_GET_IRQTYPE:
769 case PCITEST_CLEAR_IRQ:
770 ret = pci_endpoint_test_clear_irq(test);
775 mutex_unlock(&test->mutex);
779 static const struct file_operations pci_endpoint_test_fops = {
780 .owner = THIS_MODULE,
781 .unlocked_ioctl = pci_endpoint_test_ioctl,
784 static int pci_endpoint_test_probe(struct pci_dev *pdev,
785 const struct pci_device_id *ent)
792 struct device *dev = &pdev->dev;
793 struct pci_endpoint_test *test;
794 struct pci_endpoint_test_data *data;
795 enum pci_barno test_reg_bar = BAR_0;
796 struct miscdevice *misc_device;
798 if (pci_is_bridge(pdev))
801 test = devm_kzalloc(dev, sizeof(*test), GFP_KERNEL);
805 test->test_reg_bar = 0;
808 test->irq_type = IRQ_TYPE_UNDEFINED;
811 irq_type = IRQ_TYPE_LEGACY;
813 data = (struct pci_endpoint_test_data *)ent->driver_data;
815 test_reg_bar = data->test_reg_bar;
816 test->test_reg_bar = test_reg_bar;
817 test->alignment = data->alignment;
818 irq_type = data->irq_type;
821 init_completion(&test->irq_raised);
822 mutex_init(&test->mutex);
824 if ((dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(48)) != 0) &&
825 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
826 dev_err(dev, "Cannot set DMA mask\n");
830 err = pci_enable_device(pdev);
832 dev_err(dev, "Cannot enable PCI device\n");
836 err = pci_request_regions(pdev, DRV_MODULE_NAME);
838 dev_err(dev, "Cannot obtain PCI resources\n");
839 goto err_disable_pdev;
842 pci_set_master(pdev);
844 if (!pci_endpoint_test_alloc_irq_vectors(test, irq_type)) {
846 goto err_disable_irq;
849 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
850 if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
851 base = pci_ioremap_bar(pdev, bar);
853 dev_err(dev, "Failed to read BAR%d\n", bar);
854 WARN_ON(bar == test_reg_bar);
856 test->bar[bar] = base;
860 test->base = test->bar[test_reg_bar];
863 dev_err(dev, "Cannot perform PCI test without BAR%d\n",
868 pci_set_drvdata(pdev, test);
870 id = ida_simple_get(&pci_endpoint_test_ida, 0, 0, GFP_KERNEL);
873 dev_err(dev, "Unable to get id\n");
877 snprintf(name, sizeof(name), DRV_MODULE_NAME ".%d", id);
878 test->name = kstrdup(name, GFP_KERNEL);
884 if (!pci_endpoint_test_request_irq(test)) {
886 goto err_kfree_test_name;
889 misc_device = &test->miscdev;
890 misc_device->minor = MISC_DYNAMIC_MINOR;
891 misc_device->name = kstrdup(name, GFP_KERNEL);
892 if (!misc_device->name) {
894 goto err_release_irq;
896 misc_device->fops = &pci_endpoint_test_fops,
898 err = misc_register(misc_device);
900 dev_err(dev, "Failed to register device\n");
907 kfree(misc_device->name);
910 pci_endpoint_test_release_irq(test);
916 ida_simple_remove(&pci_endpoint_test_ida, id);
919 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
921 pci_iounmap(pdev, test->bar[bar]);
925 pci_endpoint_test_free_irq_vectors(test);
926 pci_release_regions(pdev);
929 pci_disable_device(pdev);
934 static void pci_endpoint_test_remove(struct pci_dev *pdev)
938 struct pci_endpoint_test *test = pci_get_drvdata(pdev);
939 struct miscdevice *misc_device = &test->miscdev;
941 if (sscanf(misc_device->name, DRV_MODULE_NAME ".%d", &id) != 1)
946 pci_endpoint_test_release_irq(test);
947 pci_endpoint_test_free_irq_vectors(test);
949 misc_deregister(&test->miscdev);
950 kfree(misc_device->name);
952 ida_simple_remove(&pci_endpoint_test_ida, id);
953 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
955 pci_iounmap(pdev, test->bar[bar]);
958 pci_release_regions(pdev);
959 pci_disable_device(pdev);
962 static const struct pci_endpoint_test_data default_data = {
963 .test_reg_bar = BAR_0,
965 .irq_type = IRQ_TYPE_MSI,
968 static const struct pci_endpoint_test_data am654_data = {
969 .test_reg_bar = BAR_2,
971 .irq_type = IRQ_TYPE_MSI,
974 static const struct pci_endpoint_test_data j721e_data = {
976 .irq_type = IRQ_TYPE_MSI,
979 static const struct pci_device_id pci_endpoint_test_tbl[] = {
980 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA74x),
981 .driver_data = (kernel_ulong_t)&default_data,
983 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA72x),
984 .driver_data = (kernel_ulong_t)&default_data,
986 { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, 0x81c0),
987 .driver_data = (kernel_ulong_t)&default_data,
989 { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, PCI_DEVICE_ID_LS1088A),
990 .driver_data = (kernel_ulong_t)&default_data,
992 { PCI_DEVICE_DATA(SYNOPSYS, EDDA, NULL) },
993 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_AM654),
994 .driver_data = (kernel_ulong_t)&am654_data
996 { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774A1),},
997 { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774B1),},
998 { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774C0),},
999 { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774E1),},
1000 { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A779F0),
1001 .driver_data = (kernel_ulong_t)&default_data,
1003 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_J721E),
1004 .driver_data = (kernel_ulong_t)&j721e_data,
1006 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_J7200),
1007 .driver_data = (kernel_ulong_t)&j721e_data,
1009 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_AM64),
1010 .driver_data = (kernel_ulong_t)&j721e_data,
1012 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_J721S2),
1013 .driver_data = (kernel_ulong_t)&j721e_data,
1017 MODULE_DEVICE_TABLE(pci, pci_endpoint_test_tbl);
1019 static struct pci_driver pci_endpoint_test_driver = {
1020 .name = DRV_MODULE_NAME,
1021 .id_table = pci_endpoint_test_tbl,
1022 .probe = pci_endpoint_test_probe,
1023 .remove = pci_endpoint_test_remove,
1025 module_pci_driver(pci_endpoint_test_driver);
1027 MODULE_DESCRIPTION("PCI ENDPOINT TEST HOST DRIVER");
1028 MODULE_AUTHOR("Kishon Vijay Abraham I <kishon@ti.com>");
1029 MODULE_LICENSE("GPL v2");