1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright 2017 IBM Corp.
4 #include <asm/pnv-ocxl.h>
5 #include <misc/ocxl-config.h>
6 #include "ocxl_internal.h"
8 #define EXTRACT_BIT(val, bit) (!!(val & BIT(bit)))
9 #define EXTRACT_BITS(val, s, e) ((val & GENMASK(e, s)) >> s)
11 #define OCXL_DVSEC_AFU_IDX_MASK GENMASK(5, 0)
12 #define OCXL_DVSEC_ACTAG_MASK GENMASK(11, 0)
13 #define OCXL_DVSEC_PASID_MASK GENMASK(19, 0)
14 #define OCXL_DVSEC_PASID_LOG_MASK GENMASK(4, 0)
16 #define OCXL_DVSEC_TEMPL_VERSION 0x0
17 #define OCXL_DVSEC_TEMPL_NAME 0x4
18 #define OCXL_DVSEC_TEMPL_AFU_VERSION 0x1C
19 #define OCXL_DVSEC_TEMPL_MMIO_GLOBAL 0x20
20 #define OCXL_DVSEC_TEMPL_MMIO_GLOBAL_SZ 0x28
21 #define OCXL_DVSEC_TEMPL_MMIO_PP 0x30
22 #define OCXL_DVSEC_TEMPL_MMIO_PP_SZ 0x38
23 #define OCXL_DVSEC_TEMPL_ALL_MEM_SZ 0x3C
24 #define OCXL_DVSEC_TEMPL_LPC_MEM_START 0x40
25 #define OCXL_DVSEC_TEMPL_WWID 0x48
26 #define OCXL_DVSEC_TEMPL_LPC_MEM_SZ 0x58
28 #define OCXL_MAX_AFU_PER_FUNCTION 64
29 #define OCXL_TEMPL_LEN_1_0 0x58
30 #define OCXL_TEMPL_LEN_1_1 0x60
31 #define OCXL_TEMPL_NAME_LEN 24
32 #define OCXL_CFG_TIMEOUT 3
34 static int find_dvsec(struct pci_dev *dev, int dvsec_id)
39 while ((vsec = pci_find_next_ext_capability(dev, vsec,
40 OCXL_EXT_CAP_ID_DVSEC))) {
41 pci_read_config_word(dev, vsec + OCXL_DVSEC_VENDOR_OFFSET,
43 pci_read_config_word(dev, vsec + OCXL_DVSEC_ID_OFFSET, &id);
44 if (vendor == PCI_VENDOR_ID_IBM && id == dvsec_id)
50 static int find_dvsec_afu_ctrl(struct pci_dev *dev, u8 afu_idx)
56 while ((vsec = pci_find_next_ext_capability(dev, vsec,
57 OCXL_EXT_CAP_ID_DVSEC))) {
58 pci_read_config_word(dev, vsec + OCXL_DVSEC_VENDOR_OFFSET,
60 pci_read_config_word(dev, vsec + OCXL_DVSEC_ID_OFFSET, &id);
62 if (vendor == PCI_VENDOR_ID_IBM &&
63 id == OCXL_DVSEC_AFU_CTRL_ID) {
64 pci_read_config_byte(dev,
65 vsec + OCXL_DVSEC_AFU_CTRL_AFU_IDX,
75 * get_function_0() - Find a related PCI device (function 0)
76 * @device: PCI device to match
78 * Returns a pointer to the related device, or null if not found
80 static struct pci_dev *get_function_0(struct pci_dev *dev)
82 unsigned int devfn = PCI_DEVFN(PCI_SLOT(dev->devfn), 0);
84 return pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus),
85 dev->bus->number, devfn);
88 static void read_pasid(struct pci_dev *dev, struct ocxl_fn_config *fn)
93 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_PASID);
96 * PASID capability is not mandatory, but there
97 * shouldn't be any AFU
99 dev_dbg(&dev->dev, "Function doesn't require any PASID\n");
100 fn->max_pasid_log = -1;
103 pci_read_config_word(dev, pos + PCI_PASID_CAP, &val);
104 fn->max_pasid_log = EXTRACT_BITS(val, 8, 12);
107 dev_dbg(&dev->dev, "PASID capability:\n");
108 dev_dbg(&dev->dev, " Max PASID log = %d\n", fn->max_pasid_log);
111 static int read_dvsec_tl(struct pci_dev *dev, struct ocxl_fn_config *fn)
115 pos = find_dvsec(dev, OCXL_DVSEC_TL_ID);
116 if (!pos && PCI_FUNC(dev->devfn) == 0) {
117 dev_err(&dev->dev, "Can't find TL DVSEC\n");
120 if (pos && PCI_FUNC(dev->devfn) != 0) {
121 dev_err(&dev->dev, "TL DVSEC is only allowed on function 0\n");
124 fn->dvsec_tl_pos = pos;
128 static int read_dvsec_function(struct pci_dev *dev, struct ocxl_fn_config *fn)
130 int pos, afu_present;
133 pos = find_dvsec(dev, OCXL_DVSEC_FUNC_ID);
135 dev_err(&dev->dev, "Can't find function DVSEC\n");
138 fn->dvsec_function_pos = pos;
140 pci_read_config_dword(dev, pos + OCXL_DVSEC_FUNC_OFF_INDEX, &val);
141 afu_present = EXTRACT_BIT(val, 31);
143 fn->max_afu_index = -1;
144 dev_dbg(&dev->dev, "Function doesn't define any AFU\n");
147 fn->max_afu_index = EXTRACT_BITS(val, 24, 29);
150 dev_dbg(&dev->dev, "Function DVSEC:\n");
151 dev_dbg(&dev->dev, " Max AFU index = %d\n", fn->max_afu_index);
155 static int read_dvsec_afu_info(struct pci_dev *dev, struct ocxl_fn_config *fn)
159 if (fn->max_afu_index < 0) {
160 fn->dvsec_afu_info_pos = -1;
164 pos = find_dvsec(dev, OCXL_DVSEC_AFU_INFO_ID);
166 dev_err(&dev->dev, "Can't find AFU information DVSEC\n");
169 fn->dvsec_afu_info_pos = pos;
173 static int read_dvsec_vendor(struct pci_dev *dev)
176 u32 cfg, tlx, dlx, reset_reload;
179 * vendor specific DVSEC, for IBM images only. Some older
180 * images may not have it
182 * It's only used on function 0 to specify the version of some
183 * logic blocks and to give access to special registers to
184 * enable host-based flashing.
186 if (PCI_FUNC(dev->devfn) != 0)
189 pos = find_dvsec(dev, OCXL_DVSEC_VENDOR_ID);
193 pci_read_config_dword(dev, pos + OCXL_DVSEC_VENDOR_CFG_VERS, &cfg);
194 pci_read_config_dword(dev, pos + OCXL_DVSEC_VENDOR_TLX_VERS, &tlx);
195 pci_read_config_dword(dev, pos + OCXL_DVSEC_VENDOR_DLX_VERS, &dlx);
196 pci_read_config_dword(dev, pos + OCXL_DVSEC_VENDOR_RESET_RELOAD,
199 dev_dbg(&dev->dev, "Vendor specific DVSEC:\n");
200 dev_dbg(&dev->dev, " CFG version = 0x%x\n", cfg);
201 dev_dbg(&dev->dev, " TLX version = 0x%x\n", tlx);
202 dev_dbg(&dev->dev, " DLX version = 0x%x\n", dlx);
203 dev_dbg(&dev->dev, " ResetReload = 0x%x\n", reset_reload);
207 static int get_dvsec_vendor0(struct pci_dev *dev, struct pci_dev **dev0,
212 if (PCI_FUNC(dev->devfn) != 0) {
213 dev = get_function_0(dev);
217 pos = find_dvsec(dev, OCXL_DVSEC_VENDOR_ID);
225 int ocxl_config_get_reset_reload(struct pci_dev *dev, int *val)
227 struct pci_dev *dev0;
231 if (get_dvsec_vendor0(dev, &dev0, &pos))
234 pci_read_config_dword(dev0, pos + OCXL_DVSEC_VENDOR_RESET_RELOAD,
236 *val = !!(reset_reload & BIT(0));
240 int ocxl_config_set_reset_reload(struct pci_dev *dev, int val)
242 struct pci_dev *dev0;
246 if (get_dvsec_vendor0(dev, &dev0, &pos))
249 pci_read_config_dword(dev0, pos + OCXL_DVSEC_VENDOR_RESET_RELOAD,
252 reset_reload |= BIT(0);
254 reset_reload &= ~BIT(0);
255 pci_write_config_dword(dev0, pos + OCXL_DVSEC_VENDOR_RESET_RELOAD,
260 static int validate_function(struct pci_dev *dev, struct ocxl_fn_config *fn)
262 if (fn->max_pasid_log == -1 && fn->max_afu_index >= 0) {
264 "AFUs are defined but no PASIDs are requested\n");
268 if (fn->max_afu_index > OCXL_MAX_AFU_PER_FUNCTION) {
270 "Max AFU index out of architectural limit (%d vs %d)\n",
271 fn->max_afu_index, OCXL_MAX_AFU_PER_FUNCTION);
277 int ocxl_config_read_function(struct pci_dev *dev, struct ocxl_fn_config *fn)
283 rc = read_dvsec_tl(dev, fn);
286 "Invalid Transaction Layer DVSEC configuration: %d\n",
291 rc = read_dvsec_function(dev, fn);
294 "Invalid Function DVSEC configuration: %d\n", rc);
298 rc = read_dvsec_afu_info(dev, fn);
300 dev_err(&dev->dev, "Invalid AFU configuration: %d\n", rc);
304 rc = read_dvsec_vendor(dev);
307 "Invalid vendor specific DVSEC configuration: %d\n",
312 rc = validate_function(dev, fn);
315 EXPORT_SYMBOL_GPL(ocxl_config_read_function);
317 static int read_afu_info(struct pci_dev *dev, struct ocxl_fn_config *fn,
318 int offset, u32 *data)
321 unsigned long timeout = jiffies + (HZ * OCXL_CFG_TIMEOUT);
322 int pos = fn->dvsec_afu_info_pos;
324 /* Protect 'data valid' bit */
325 if (EXTRACT_BIT(offset, 31)) {
326 dev_err(&dev->dev, "Invalid offset in AFU info DVSEC\n");
330 pci_write_config_dword(dev, pos + OCXL_DVSEC_AFU_INFO_OFF, offset);
331 pci_read_config_dword(dev, pos + OCXL_DVSEC_AFU_INFO_OFF, &val);
332 while (!EXTRACT_BIT(val, 31)) {
333 if (time_after_eq(jiffies, timeout)) {
335 "Timeout while reading AFU info DVSEC (offset=%d)\n",
340 pci_read_config_dword(dev, pos + OCXL_DVSEC_AFU_INFO_OFF, &val);
342 pci_read_config_dword(dev, pos + OCXL_DVSEC_AFU_INFO_DATA, data);
347 * read_template_version() - Read the template version from the AFU
348 * @dev: the device for the AFU
349 * @fn: the AFU offsets
350 * @len: outputs the template length
351 * @version: outputs the major<<8,minor version
353 * Returns 0 on success, negative on failure
355 static int read_template_version(struct pci_dev *dev, struct ocxl_fn_config *fn,
356 u16 *len, u16 *version)
362 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_VERSION, &val32);
366 *len = EXTRACT_BITS(val32, 16, 31);
367 major = EXTRACT_BITS(val32, 8, 15);
368 minor = EXTRACT_BITS(val32, 0, 7);
369 *version = (major << 8) + minor;
373 int ocxl_config_check_afu_index(struct pci_dev *dev,
374 struct ocxl_fn_config *fn, int afu_idx)
378 u16 len, expected_len;
380 pci_write_config_byte(dev,
381 fn->dvsec_afu_info_pos + OCXL_DVSEC_AFU_INFO_AFU_IDX,
384 rc = read_template_version(dev, fn, &len, &templ_version);
388 /* AFU index map can have holes, in which case we read all 0's */
389 if (!templ_version && !len)
392 dev_dbg(&dev->dev, "AFU descriptor template version %d.%d\n",
393 templ_version >> 8, templ_version & 0xFF);
395 switch (templ_version) {
396 case 0x0005: // v0.5 was used prior to the spec approval
398 expected_len = OCXL_TEMPL_LEN_1_0;
401 expected_len = OCXL_TEMPL_LEN_1_1;
404 dev_warn(&dev->dev, "Unknown AFU template version %#x\n",
408 if (len != expected_len)
410 "Unexpected template length %#x in AFU information, expected %#x for version %#x\n",
411 len, expected_len, templ_version);
415 static int read_afu_name(struct pci_dev *dev, struct ocxl_fn_config *fn,
416 struct ocxl_afu_config *afu)
421 BUILD_BUG_ON(OCXL_AFU_NAME_SZ < OCXL_TEMPL_NAME_LEN);
422 for (i = 0; i < OCXL_TEMPL_NAME_LEN; i += 4) {
423 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_NAME + i, &val);
426 ptr = (u32 *) &afu->name[i];
427 *ptr = le32_to_cpu((__force __le32) val);
429 afu->name[OCXL_AFU_NAME_SZ - 1] = '\0'; /* play safe */
433 static int read_afu_mmio(struct pci_dev *dev, struct ocxl_fn_config *fn,
434 struct ocxl_afu_config *afu)
442 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_GLOBAL, &val);
445 afu->global_mmio_bar = EXTRACT_BITS(val, 0, 2);
446 afu->global_mmio_offset = EXTRACT_BITS(val, 16, 31) << 16;
448 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_GLOBAL + 4, &val);
451 afu->global_mmio_offset += (u64) val << 32;
453 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_GLOBAL_SZ, &val);
456 afu->global_mmio_size = val;
461 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_PP, &val);
464 afu->pp_mmio_bar = EXTRACT_BITS(val, 0, 2);
465 afu->pp_mmio_offset = EXTRACT_BITS(val, 16, 31) << 16;
467 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_PP + 4, &val);
470 afu->pp_mmio_offset += (u64) val << 32;
472 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_PP_SZ, &val);
475 afu->pp_mmio_stride = val;
480 static int read_afu_control(struct pci_dev *dev, struct ocxl_afu_config *afu)
486 pos = find_dvsec_afu_ctrl(dev, afu->idx);
488 dev_err(&dev->dev, "Can't find AFU control DVSEC for AFU %d\n",
492 afu->dvsec_afu_control_pos = pos;
494 pci_read_config_byte(dev, pos + OCXL_DVSEC_AFU_CTRL_PASID_SUP, &val8);
495 afu->pasid_supported_log = EXTRACT_BITS(val8, 0, 4);
497 pci_read_config_word(dev, pos + OCXL_DVSEC_AFU_CTRL_ACTAG_SUP, &val16);
498 afu->actag_supported = EXTRACT_BITS(val16, 0, 11);
502 static bool char_allowed(int c)
505 * Permitted Characters : Alphanumeric, hyphen, underscore, comma
507 if ((c >= 0x30 && c <= 0x39) /* digits */ ||
508 (c >= 0x41 && c <= 0x5A) /* upper case */ ||
509 (c >= 0x61 && c <= 0x7A) /* lower case */ ||
518 static int validate_afu(struct pci_dev *dev, struct ocxl_afu_config *afu)
523 dev_err(&dev->dev, "Empty AFU name\n");
526 for (i = 0; i < OCXL_TEMPL_NAME_LEN; i++) {
527 if (!char_allowed(afu->name[i])) {
529 "Invalid character in AFU name\n");
534 if (afu->global_mmio_bar != 0 &&
535 afu->global_mmio_bar != 2 &&
536 afu->global_mmio_bar != 4) {
537 dev_err(&dev->dev, "Invalid global MMIO bar number\n");
540 if (afu->pp_mmio_bar != 0 &&
541 afu->pp_mmio_bar != 2 &&
542 afu->pp_mmio_bar != 4) {
543 dev_err(&dev->dev, "Invalid per-process MMIO bar number\n");
550 * read_afu_lpc_memory_info() - Populate AFU metadata regarding LPC memory
551 * @dev: the device for the AFU
552 * @fn: the AFU offsets
553 * @afu: the AFU struct to populate the LPC metadata into
555 * Returns 0 on success, negative on failure
557 static int read_afu_lpc_memory_info(struct pci_dev *dev,
558 struct ocxl_fn_config *fn,
559 struct ocxl_afu_config *afu)
565 u64 total_mem_size = 0;
566 u64 lpc_mem_size = 0;
568 afu->lpc_mem_offset = 0;
569 afu->lpc_mem_size = 0;
570 afu->special_purpose_mem_offset = 0;
571 afu->special_purpose_mem_size = 0;
573 * For AFUs following template v1.0, the LPC memory covers the
574 * total memory. Its size is a power of 2.
576 * For AFUs with template >= v1.01, the total memory size is
577 * still a power of 2, but it is split in 2 parts:
578 * - the LPC memory, whose size can now be anything
579 * - the remainder memory is a special purpose memory, whose
580 * definition is AFU-dependent. It is not accessible through
581 * the usual commands for LPC memory
583 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_ALL_MEM_SZ, &val32);
587 val32 = EXTRACT_BITS(val32, 0, 7);
589 return 0; /* No LPC memory */
592 * The configuration space spec allows for a memory size of up
595 * Current generation hardware uses 56-bit physical addresses,
596 * but we won't be able to get near close to that, as we won't
597 * have a hole big enough in the memory map. Let it pass in
598 * the driver for now. We'll get an error from the firmware
599 * when trying to configure something too big.
601 total_mem_size = 1ull << val32;
603 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_LPC_MEM_START, &val32);
607 afu->lpc_mem_offset = val32;
609 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_LPC_MEM_START + 4, &val32);
613 afu->lpc_mem_offset |= (u64) val32 << 32;
615 rc = read_template_version(dev, fn, &templ_len, &templ_version);
619 if (templ_version >= 0x0101) {
620 rc = read_afu_info(dev, fn,
621 OCXL_DVSEC_TEMPL_LPC_MEM_SZ, &val32);
624 lpc_mem_size = val32;
626 rc = read_afu_info(dev, fn,
627 OCXL_DVSEC_TEMPL_LPC_MEM_SZ + 4, &val32);
630 lpc_mem_size |= (u64) val32 << 32;
632 lpc_mem_size = total_mem_size;
634 afu->lpc_mem_size = lpc_mem_size;
636 if (lpc_mem_size < total_mem_size) {
637 afu->special_purpose_mem_offset =
638 afu->lpc_mem_offset + lpc_mem_size;
639 afu->special_purpose_mem_size =
640 total_mem_size - lpc_mem_size;
645 int ocxl_config_read_afu(struct pci_dev *dev, struct ocxl_fn_config *fn,
646 struct ocxl_afu_config *afu, u8 afu_idx)
652 * First, we need to write the AFU idx for the AFU we want to
655 WARN_ON((afu_idx & OCXL_DVSEC_AFU_IDX_MASK) != afu_idx);
657 pci_write_config_byte(dev,
658 fn->dvsec_afu_info_pos + OCXL_DVSEC_AFU_INFO_AFU_IDX,
661 rc = read_afu_name(dev, fn, afu);
665 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_AFU_VERSION, &val32);
668 afu->version_major = EXTRACT_BITS(val32, 24, 31);
669 afu->version_minor = EXTRACT_BITS(val32, 16, 23);
670 afu->afuc_type = EXTRACT_BITS(val32, 14, 15);
671 afu->afum_type = EXTRACT_BITS(val32, 12, 13);
672 afu->profile = EXTRACT_BITS(val32, 0, 7);
674 rc = read_afu_mmio(dev, fn, afu);
678 rc = read_afu_lpc_memory_info(dev, fn, afu);
682 rc = read_afu_control(dev, afu);
686 dev_dbg(&dev->dev, "AFU configuration:\n");
687 dev_dbg(&dev->dev, " name = %s\n", afu->name);
688 dev_dbg(&dev->dev, " version = %d.%d\n", afu->version_major,
690 dev_dbg(&dev->dev, " global mmio bar = %hhu\n", afu->global_mmio_bar);
691 dev_dbg(&dev->dev, " global mmio offset = %#llx\n",
692 afu->global_mmio_offset);
693 dev_dbg(&dev->dev, " global mmio size = %#x\n", afu->global_mmio_size);
694 dev_dbg(&dev->dev, " pp mmio bar = %hhu\n", afu->pp_mmio_bar);
695 dev_dbg(&dev->dev, " pp mmio offset = %#llx\n", afu->pp_mmio_offset);
696 dev_dbg(&dev->dev, " pp mmio stride = %#x\n", afu->pp_mmio_stride);
697 dev_dbg(&dev->dev, " lpc_mem offset = %#llx\n", afu->lpc_mem_offset);
698 dev_dbg(&dev->dev, " lpc_mem size = %#llx\n", afu->lpc_mem_size);
699 dev_dbg(&dev->dev, " special purpose mem offset = %#llx\n",
700 afu->special_purpose_mem_offset);
701 dev_dbg(&dev->dev, " special purpose mem size = %#llx\n",
702 afu->special_purpose_mem_size);
703 dev_dbg(&dev->dev, " pasid supported (log) = %u\n",
704 afu->pasid_supported_log);
705 dev_dbg(&dev->dev, " actag supported = %u\n",
706 afu->actag_supported);
708 rc = validate_afu(dev, afu);
711 EXPORT_SYMBOL_GPL(ocxl_config_read_afu);
713 int ocxl_config_get_actag_info(struct pci_dev *dev, u16 *base, u16 *enabled,
719 * This is really a simple wrapper for the kernel API, to
720 * avoid an external driver using ocxl as a library to call
721 * platform-dependent code
723 rc = pnv_ocxl_get_actag(dev, base, enabled, supported);
725 dev_err(&dev->dev, "Can't get actag for device: %d\n", rc);
730 EXPORT_SYMBOL_GPL(ocxl_config_get_actag_info);
732 void ocxl_config_set_afu_actag(struct pci_dev *dev, int pos, int actag_base,
737 val = actag_count & OCXL_DVSEC_ACTAG_MASK;
738 pci_write_config_byte(dev, pos + OCXL_DVSEC_AFU_CTRL_ACTAG_EN, val);
740 val = actag_base & OCXL_DVSEC_ACTAG_MASK;
741 pci_write_config_dword(dev, pos + OCXL_DVSEC_AFU_CTRL_ACTAG_BASE, val);
743 EXPORT_SYMBOL_GPL(ocxl_config_set_afu_actag);
745 int ocxl_config_get_pasid_info(struct pci_dev *dev, int *count)
747 return pnv_ocxl_get_pasid_count(dev, count);
750 void ocxl_config_set_afu_pasid(struct pci_dev *dev, int pos, int pasid_base,
756 val8 = pasid_count_log & OCXL_DVSEC_PASID_LOG_MASK;
757 pci_write_config_byte(dev, pos + OCXL_DVSEC_AFU_CTRL_PASID_EN, val8);
759 pci_read_config_dword(dev, pos + OCXL_DVSEC_AFU_CTRL_PASID_BASE,
761 val32 &= ~OCXL_DVSEC_PASID_MASK;
762 val32 |= pasid_base & OCXL_DVSEC_PASID_MASK;
763 pci_write_config_dword(dev, pos + OCXL_DVSEC_AFU_CTRL_PASID_BASE,
766 EXPORT_SYMBOL_GPL(ocxl_config_set_afu_pasid);
768 void ocxl_config_set_afu_state(struct pci_dev *dev, int pos, int enable)
772 pci_read_config_byte(dev, pos + OCXL_DVSEC_AFU_CTRL_ENABLE, &val);
777 pci_write_config_byte(dev, pos + OCXL_DVSEC_AFU_CTRL_ENABLE, val);
779 EXPORT_SYMBOL_GPL(ocxl_config_set_afu_state);
781 int ocxl_config_set_TL(struct pci_dev *dev, int tl_dvsec)
791 * Skip on function != 0, as the TL can only be defined on 0
793 if (PCI_FUNC(dev->devfn) != 0)
796 recv_rate = kzalloc(PNV_OCXL_TL_RATE_BUF_SIZE, GFP_KERNEL);
800 * The spec defines 64 templates for messages in the
801 * Transaction Layer (TL).
803 * The host and device each support a subset, so we need to
804 * configure the transmitters on each side to send only
805 * templates the receiver understands, at a rate the receiver
806 * can process. Per the spec, template 0 must be supported by
807 * everybody. That's the template which has been used by the
808 * host and device so far.
810 * The sending rate limit must be set before the template is
817 rc = pnv_ocxl_get_tl_cap(dev, &recv_cap, recv_rate,
818 PNV_OCXL_TL_RATE_BUF_SIZE);
822 for (i = 0; i < PNV_OCXL_TL_RATE_BUF_SIZE; i += 4) {
823 be32ptr = (__be32 *) &recv_rate[i];
824 pci_write_config_dword(dev,
825 tl_dvsec + OCXL_DVSEC_TL_SEND_RATE + i,
826 be32_to_cpu(*be32ptr));
828 val = recv_cap >> 32;
829 pci_write_config_dword(dev, tl_dvsec + OCXL_DVSEC_TL_SEND_CAP, val);
830 val = recv_cap & GENMASK(31, 0);
831 pci_write_config_dword(dev, tl_dvsec + OCXL_DVSEC_TL_SEND_CAP + 4, val);
836 for (i = 0; i < PNV_OCXL_TL_RATE_BUF_SIZE; i += 4) {
837 pci_read_config_dword(dev,
838 tl_dvsec + OCXL_DVSEC_TL_RECV_RATE + i,
840 be32ptr = (__be32 *) &recv_rate[i];
841 *be32ptr = cpu_to_be32(val);
843 pci_read_config_dword(dev, tl_dvsec + OCXL_DVSEC_TL_RECV_CAP, &val);
844 recv_cap = (long) val << 32;
845 pci_read_config_dword(dev, tl_dvsec + OCXL_DVSEC_TL_RECV_CAP + 4, &val);
848 rc = pnv_ocxl_set_tl_conf(dev, recv_cap, __pa(recv_rate),
849 PNV_OCXL_TL_RATE_BUF_SIZE);
854 * Opencapi commands needing to be retried are classified per
855 * the TL in 2 groups: short and long commands.
857 * The short back off timer it not used for now. It will be
860 * The long back off timer is typically used when an AFU hits
861 * a page fault but the NPU is already processing one. So the
862 * AFU needs to wait before it can resubmit. Having a value
863 * too low doesn't break anything, but can generate extra
864 * traffic on the link.
865 * We set it to 1.6 us for now. It's shorter than, but in the
866 * same order of magnitude as the time spent to process a page
869 timers = 0x2 << 4; /* long timer = 1.6 us */
870 pci_write_config_byte(dev, tl_dvsec + OCXL_DVSEC_TL_BACKOFF_TIMERS,
878 EXPORT_SYMBOL_GPL(ocxl_config_set_TL);
880 int ocxl_config_terminate_pasid(struct pci_dev *dev, int afu_control, int pasid)
883 unsigned long timeout;
885 pci_read_config_dword(dev, afu_control + OCXL_DVSEC_AFU_CTRL_TERM_PASID,
887 if (EXTRACT_BIT(val, 20)) {
889 "Can't terminate PASID %#x, previous termination didn't complete\n",
894 val &= ~OCXL_DVSEC_PASID_MASK;
895 val |= pasid & OCXL_DVSEC_PASID_MASK;
897 pci_write_config_dword(dev,
898 afu_control + OCXL_DVSEC_AFU_CTRL_TERM_PASID,
901 timeout = jiffies + (HZ * OCXL_CFG_TIMEOUT);
902 pci_read_config_dword(dev, afu_control + OCXL_DVSEC_AFU_CTRL_TERM_PASID,
904 while (EXTRACT_BIT(val, 20)) {
905 if (time_after_eq(jiffies, timeout)) {
907 "Timeout while waiting for AFU to terminate PASID %#x\n",
912 pci_read_config_dword(dev,
913 afu_control + OCXL_DVSEC_AFU_CTRL_TERM_PASID,
918 EXPORT_SYMBOL_GPL(ocxl_config_terminate_pasid);
920 void ocxl_config_set_actag(struct pci_dev *dev, int func_dvsec, u32 tag_first,
925 val = (tag_first & OCXL_DVSEC_ACTAG_MASK) << 16;
926 val |= tag_count & OCXL_DVSEC_ACTAG_MASK;
927 pci_write_config_dword(dev, func_dvsec + OCXL_DVSEC_FUNC_OFF_ACTAG,
930 EXPORT_SYMBOL_GPL(ocxl_config_set_actag);