drivers/misc/mei/pci-me.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2003-2020, Intel Corporation. All rights reserved.
   4  * Intel Management Engine Interface (Intel MEI) Linux driver
   5  */
   6
   7 #include <linux/module.h>
   8 #include <linux/kernel.h>
   9 #include <linux/device.h>
  10 #include <linux/errno.h>
  11 #include <linux/types.h>
  12 #include <linux/pci.h>
  13 #include <linux/sched.h>
  14 #include <linux/interrupt.h>
  15
  16 #include <linux/pm_domain.h>
  17 #include <linux/pm_runtime.h>
  18
  19 #include <linux/mei.h>
  20
  21 #include "mei_dev.h"
  22 #include "client.h"
  23 #include "hw-me-regs.h"
  24 #include "hw-me.h"
  25
  26 /* mei_pci_tbl - PCI Device ID Table */
  27 static const struct pci_device_id mei_me_pci_tbl[] = {
  28         {MEI_PCI_DEVICE(MEI_DEV_ID_82946GZ, MEI_ME_ICH_CFG)},
  29         {MEI_PCI_DEVICE(MEI_DEV_ID_82G35, MEI_ME_ICH_CFG)},
  30         {MEI_PCI_DEVICE(MEI_DEV_ID_82Q965, MEI_ME_ICH_CFG)},
  31         {MEI_PCI_DEVICE(MEI_DEV_ID_82G965, MEI_ME_ICH_CFG)},
  32         {MEI_PCI_DEVICE(MEI_DEV_ID_82GM965, MEI_ME_ICH_CFG)},
  33         {MEI_PCI_DEVICE(MEI_DEV_ID_82GME965, MEI_ME_ICH_CFG)},
  34         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q35, MEI_ME_ICH_CFG)},
  35         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82G33, MEI_ME_ICH_CFG)},
  36         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q33, MEI_ME_ICH_CFG)},
  37         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82X38, MEI_ME_ICH_CFG)},
  38         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_3200, MEI_ME_ICH_CFG)},
  39
  40         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_6, MEI_ME_ICH_CFG)},
  41         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_7, MEI_ME_ICH_CFG)},
  42         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_8, MEI_ME_ICH_CFG)},
  43         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_9, MEI_ME_ICH_CFG)},
  44         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_10, MEI_ME_ICH_CFG)},
  45         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_1, MEI_ME_ICH_CFG)},
  46         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_2, MEI_ME_ICH_CFG)},
  47         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_3, MEI_ME_ICH_CFG)},
  48         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_4, MEI_ME_ICH_CFG)},
  49
  50         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_1, MEI_ME_ICH10_CFG)},
  51         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_2, MEI_ME_ICH10_CFG)},
  52         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_3, MEI_ME_ICH10_CFG)},
  53         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_4, MEI_ME_ICH10_CFG)},
  54
  55         {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_1, MEI_ME_PCH6_CFG)},
  56         {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_2, MEI_ME_PCH6_CFG)},
  57         {MEI_PCI_DEVICE(MEI_DEV_ID_CPT_1, MEI_ME_PCH_CPT_PBG_CFG)},
  58         {MEI_PCI_DEVICE(MEI_DEV_ID_PBG_1, MEI_ME_PCH_CPT_PBG_CFG)},
  59         {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, MEI_ME_PCH7_CFG)},
  60         {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, MEI_ME_PCH7_CFG)},
  61         {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, MEI_ME_PCH7_CFG)},
  62         {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, MEI_ME_PCH8_SPS_4_CFG)},
  63         {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, MEI_ME_PCH8_SPS_4_CFG)},
  64         {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, MEI_ME_PCH8_CFG)},
  65         {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, MEI_ME_PCH8_SPS_4_CFG)},
  66         {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, MEI_ME_PCH8_CFG)},
  67         {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP_2, MEI_ME_PCH8_CFG)},
  68
  69         {MEI_PCI_DEVICE(MEI_DEV_ID_SPT, MEI_ME_PCH8_CFG)},
  70         {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2, MEI_ME_PCH8_CFG)},
  71         {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_3, MEI_ME_PCH8_ITOUCH_CFG)},
  72         {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, MEI_ME_PCH8_SPS_4_CFG)},
  73         {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, MEI_ME_PCH8_SPS_4_CFG)},
  74         {MEI_PCI_DEVICE(MEI_DEV_ID_LBG, MEI_ME_PCH12_SPS_4_CFG)},
  75
  76         {MEI_PCI_DEVICE(MEI_DEV_ID_BXT_M, MEI_ME_PCH8_CFG)},
  77         {MEI_PCI_DEVICE(MEI_DEV_ID_APL_I, MEI_ME_PCH8_CFG)},
  78
  79         {MEI_PCI_DEVICE(MEI_DEV_ID_DNV_IE, MEI_ME_PCH8_CFG)},
  80
  81         {MEI_PCI_DEVICE(MEI_DEV_ID_GLK, MEI_ME_PCH8_CFG)},
  82
  83         {MEI_PCI_DEVICE(MEI_DEV_ID_KBP, MEI_ME_PCH8_CFG)},
  84         {MEI_PCI_DEVICE(MEI_DEV_ID_KBP_2, MEI_ME_PCH8_CFG)},
  85         {MEI_PCI_DEVICE(MEI_DEV_ID_KBP_3, MEI_ME_PCH8_CFG)},
  86
  87         {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP, MEI_ME_PCH12_CFG)},
  88         {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP_3, MEI_ME_PCH8_ITOUCH_CFG)},
  89         {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H, MEI_ME_PCH12_SPS_CFG)},
  90         {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H_3, MEI_ME_PCH12_SPS_ITOUCH_CFG)},
  91
  92         {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP, MEI_ME_PCH12_CFG)},
  93         {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP_3, MEI_ME_PCH8_ITOUCH_CFG)},
  94         {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_V, MEI_ME_PCH12_CFG)},
  95         {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H, MEI_ME_PCH12_CFG)},
  96         {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H_3, MEI_ME_PCH8_ITOUCH_CFG)},
  97
  98         {MEI_PCI_DEVICE(MEI_DEV_ID_ICP_LP, MEI_ME_PCH12_CFG)},
  99         {MEI_PCI_DEVICE(MEI_DEV_ID_ICP_N, MEI_ME_PCH12_CFG)},
 100
 101         {MEI_PCI_DEVICE(MEI_DEV_ID_TGP_LP, MEI_ME_PCH15_CFG)},
 102         {MEI_PCI_DEVICE(MEI_DEV_ID_TGP_H, MEI_ME_PCH15_SPS_CFG)},
 103
 104         {MEI_PCI_DEVICE(MEI_DEV_ID_JSP_N, MEI_ME_PCH15_CFG)},
 105
 106         {MEI_PCI_DEVICE(MEI_DEV_ID_MCC, MEI_ME_PCH15_CFG)},
 107         {MEI_PCI_DEVICE(MEI_DEV_ID_MCC_4, MEI_ME_PCH8_CFG)},
 108
 109         {MEI_PCI_DEVICE(MEI_DEV_ID_CDF, MEI_ME_PCH8_CFG)},
 110
 111         {MEI_PCI_DEVICE(MEI_DEV_ID_EBG, MEI_ME_PCH15_SPS_CFG)},
 112
 113         {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_S, MEI_ME_PCH15_CFG)},
 114         {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_LP, MEI_ME_PCH15_CFG)},
 115         {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_P, MEI_ME_PCH15_CFG)},
 116         {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_N, MEI_ME_PCH15_CFG)},
 117
 118         {MEI_PCI_DEVICE(MEI_DEV_ID_RPL_S, MEI_ME_PCH15_CFG)},
 119
 120         {MEI_PCI_DEVICE(MEI_DEV_ID_MTL_M, MEI_ME_PCH15_CFG)},
 121         {MEI_PCI_DEVICE(MEI_DEV_ID_ARL_S, MEI_ME_PCH15_CFG)},
 122         {MEI_PCI_DEVICE(MEI_DEV_ID_ARL_H, MEI_ME_PCH15_CFG)},
 123
 124         /* required last entry */
 125         {0, }
 126 };
 127
 128 MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl);
 129
 130 #ifdef CONFIG_PM
 131 static inline void mei_me_set_pm_domain(struct mei_device *dev);
 132 static inline void mei_me_unset_pm_domain(struct mei_device *dev);
 133 #else
 134 static inline void mei_me_set_pm_domain(struct mei_device *dev) {}
 135 static inline void mei_me_unset_pm_domain(struct mei_device *dev) {}
 136 #endif /* CONFIG_PM */
 137
 138 static int mei_me_read_fws(const struct mei_device *dev, int where, u32 *val)
 139 {
 140         struct pci_dev *pdev = to_pci_dev(dev->dev);
 141
 142         return pci_read_config_dword(pdev, where, val);
 143 }
 144
 145 /**
 146  * mei_me_quirk_probe - probe for devices that doesn't valid ME interface
 147  *
 148  * @pdev: PCI device structure
 149  * @cfg: per generation config
 150  *
 151  * Return: true if ME Interface is valid, false otherwise
 152  */
 153 static bool mei_me_quirk_probe(struct pci_dev *pdev,
 154                                 const struct mei_cfg *cfg)
 155 {
 156         if (cfg->quirk_probe && cfg->quirk_probe(pdev)) {
 157                 dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n");
 158                 return false;
 159         }
 160
 161         return true;
 162 }
 163
 164 /**
 165  * mei_me_probe - Device Initialization Routine
 166  *
 167  * @pdev: PCI device structure
 168  * @ent: entry in kcs_pci_tbl
 169  *
 170  * Return: 0 on success, <0 on failure.
 171  */
 172 static int mei_me_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 173 {
 174         const struct mei_cfg *cfg;
 175         struct mei_device *dev;
 176         struct mei_me_hw *hw;
 177         unsigned int irqflags;
 178         int err;
 179
 180         cfg = mei_me_get_cfg(ent->driver_data);
 181         if (!cfg)
 182                 return -ENODEV;
 183
 184         if (!mei_me_quirk_probe(pdev, cfg))
 185                 return -ENODEV;
 186
 187         /* enable pci dev */
 188         err = pcim_enable_device(pdev);
 189         if (err) {
 190                 dev_err(&pdev->dev, "failed to enable pci device.\n");
 191                 goto end;
 192         }
 193         /* set PCI host mastering  */
 194         pci_set_master(pdev);
 195         /* pci request regions and mapping IO device memory for mei driver */
 196         err = pcim_iomap_regions(pdev, BIT(0), KBUILD_MODNAME);
 197         if (err) {
 198                 dev_err(&pdev->dev, "failed to get pci regions.\n");
 199                 goto end;
 200         }
 201
 202         if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) ||
 203             dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
 204
 205                 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
 206                 if (err)
 207                         err = dma_set_coherent_mask(&pdev->dev,
 208                                                     DMA_BIT_MASK(32));
 209         }
 210         if (err) {
 211                 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
 212                 goto end;
 213         }
 214
 215         /* allocates and initializes the mei dev structure */
 216         dev = mei_me_dev_init(&pdev->dev, cfg);
 217         if (!dev) {
 218                 err = -ENOMEM;
 219                 goto end;
 220         }
 221         hw = to_me_hw(dev);
 222         hw->mem_addr = pcim_iomap_table(pdev)[0];
 223         hw->read_fws = mei_me_read_fws;
 224
 225         pci_enable_msi(pdev);
 226
 227         hw->irq = pdev->irq;
 228
 229          /* request and enable interrupt */
 230         irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
 231
 232         err = request_threaded_irq(pdev->irq,
 233                         mei_me_irq_quick_handler,
 234                         mei_me_irq_thread_handler,
 235                         irqflags, KBUILD_MODNAME, dev);
 236         if (err) {
 237                 dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n",
 238                        pdev->irq);
 239                 goto end;
 240         }
 241
 242         if (mei_start(dev)) {
 243                 dev_err(&pdev->dev, "init hw failure.\n");
 244                 err = -ENODEV;
 245                 goto release_irq;
 246         }
 247
 248         pm_runtime_set_autosuspend_delay(&pdev->dev, MEI_ME_RPM_TIMEOUT);
 249         pm_runtime_use_autosuspend(&pdev->dev);
 250
 251         err = mei_register(dev, &pdev->dev);
 252         if (err)
 253                 goto stop;
 254
 255         pci_set_drvdata(pdev, dev);
 256
 257         /*
 258          * MEI requires to resume from runtime suspend mode
 259          * in order to perform link reset flow upon system suspend.
 260          */
 261         dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
 262
 263         /*
 264          * ME maps runtime suspend/resume to D0i states,
 265          * hence we need to go around native PCI runtime service which
 266          * eventually brings the device into D3cold/hot state,
 267          * but the mei device cannot wake up from D3 unlike from D0i3.
 268          * To get around the PCI device native runtime pm,
 269          * ME uses runtime pm domain handlers which take precedence
 270          * over the driver's pm handlers.
 271          */
 272         mei_me_set_pm_domain(dev);
 273
 274         if (mei_pg_is_enabled(dev)) {
 275                 pm_runtime_put_noidle(&pdev->dev);
 276                 if (hw->d0i3_supported)
 277                         pm_runtime_allow(&pdev->dev);
 278         }
 279
 280         dev_dbg(&pdev->dev, "initialization successful.\n");
 281
 282         return 0;
 283
 284 stop:
 285         mei_stop(dev);
 286 release_irq:
 287         mei_cancel_work(dev);
 288         mei_disable_interrupts(dev);
 289         free_irq(pdev->irq, dev);
 290 end:
 291         dev_err(&pdev->dev, "initialization failed.\n");
 292         return err;
 293 }
 294
 295 /**
 296  * mei_me_shutdown - Device Removal Routine
 297  *
 298  * @pdev: PCI device structure
 299  *
 300  * mei_me_shutdown is called from the reboot notifier
 301  * it's a simplified version of remove so we go down
 302  * faster.
 303  */
 304 static void mei_me_shutdown(struct pci_dev *pdev)
 305 {
 306         struct mei_device *dev;
 307
 308         dev = pci_get_drvdata(pdev);
 309         if (!dev)
 310                 return;
 311
 312         dev_dbg(&pdev->dev, "shutdown\n");
 313         mei_stop(dev);
 314
 315         mei_me_unset_pm_domain(dev);
 316
 317         mei_disable_interrupts(dev);
 318         free_irq(pdev->irq, dev);
 319 }
 320
 321 /**
 322  * mei_me_remove - Device Removal Routine
 323  *
 324  * @pdev: PCI device structure
 325  *
 326  * mei_me_remove is called by the PCI subsystem to alert the driver
 327  * that it should release a PCI device.
 328  */
 329 static void mei_me_remove(struct pci_dev *pdev)
 330 {
 331         struct mei_device *dev;
 332
 333         dev = pci_get_drvdata(pdev);
 334         if (!dev)
 335                 return;
 336
 337         if (mei_pg_is_enabled(dev))
 338                 pm_runtime_get_noresume(&pdev->dev);
 339
 340         dev_dbg(&pdev->dev, "stop\n");
 341         mei_stop(dev);
 342
 343         mei_me_unset_pm_domain(dev);
 344
 345         mei_disable_interrupts(dev);
 346
 347         free_irq(pdev->irq, dev);
 348
 349         mei_deregister(dev);
 350 }
 351
 352 #ifdef CONFIG_PM_SLEEP
 353 static int mei_me_pci_suspend(struct device *device)
 354 {
 355         struct pci_dev *pdev = to_pci_dev(device);
 356         struct mei_device *dev = pci_get_drvdata(pdev);
 357
 358         if (!dev)
 359                 return -ENODEV;
 360
 361         dev_dbg(&pdev->dev, "suspend\n");
 362
 363         mei_stop(dev);
 364
 365         mei_disable_interrupts(dev);
 366
 367         free_irq(pdev->irq, dev);
 368         pci_disable_msi(pdev);
 369
 370         return 0;
 371 }
 372
 373 static int mei_me_pci_resume(struct device *device)
 374 {
 375         struct pci_dev *pdev = to_pci_dev(device);
 376         struct mei_device *dev;
 377         unsigned int irqflags;
 378         int err;
 379
 380         dev = pci_get_drvdata(pdev);
 381         if (!dev)
 382                 return -ENODEV;
 383
 384         pci_enable_msi(pdev);
 385
 386         irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
 387
 388         /* request and enable interrupt */
 389         err = request_threaded_irq(pdev->irq,
 390                         mei_me_irq_quick_handler,
 391                         mei_me_irq_thread_handler,
 392                         irqflags, KBUILD_MODNAME, dev);
 393
 394         if (err) {
 395                 dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n",
 396                                 pdev->irq);
 397                 return err;
 398         }
 399
 400         err = mei_restart(dev);
 401         if (err)
 402                 return err;
 403
 404         /* Start timer if stopped in suspend */
 405         schedule_delayed_work(&dev->timer_work, HZ);
 406
 407         return 0;
 408 }
 409 #endif /* CONFIG_PM_SLEEP */
 410
 411 #ifdef CONFIG_PM
 412 static int mei_me_pm_runtime_idle(struct device *device)
 413 {
 414         struct mei_device *dev;
 415
 416         dev_dbg(device, "rpm: me: runtime_idle\n");
 417
 418         dev = dev_get_drvdata(device);
 419         if (!dev)
 420                 return -ENODEV;
 421         if (mei_write_is_idle(dev))
 422                 pm_runtime_autosuspend(device);
 423
 424         return -EBUSY;
 425 }
 426
 427 static int mei_me_pm_runtime_suspend(struct device *device)
 428 {
 429         struct mei_device *dev;
 430         int ret;
 431
 432         dev_dbg(device, "rpm: me: runtime suspend\n");
 433
 434         dev = dev_get_drvdata(device);
 435         if (!dev)
 436                 return -ENODEV;
 437
 438         mutex_lock(&dev->device_lock);
 439
 440         if (mei_write_is_idle(dev))
 441                 ret = mei_me_pg_enter_sync(dev);
 442         else
 443                 ret = -EAGAIN;
 444
 445         mutex_unlock(&dev->device_lock);
 446
 447         dev_dbg(device, "rpm: me: runtime suspend ret=%d\n", ret);
 448
 449         if (ret && ret != -EAGAIN)
 450                 schedule_work(&dev->reset_work);
 451
 452         return ret;
 453 }
 454
 455 static int mei_me_pm_runtime_resume(struct device *device)
 456 {
 457         struct mei_device *dev;
 458         int ret;
 459
 460         dev_dbg(device, "rpm: me: runtime resume\n");
 461
 462         dev = dev_get_drvdata(device);
 463         if (!dev)
 464                 return -ENODEV;
 465
 466         mutex_lock(&dev->device_lock);
 467
 468         ret = mei_me_pg_exit_sync(dev);
 469
 470         mutex_unlock(&dev->device_lock);
 471
 472         dev_dbg(device, "rpm: me: runtime resume ret = %d\n", ret);
 473
 474         if (ret)
 475                 schedule_work(&dev->reset_work);
 476
 477         return ret;
 478 }
 479
 480 /**
 481  * mei_me_set_pm_domain - fill and set pm domain structure for device
 482  *
 483  * @dev: mei_device
 484  */
 485 static inline void mei_me_set_pm_domain(struct mei_device *dev)
 486 {
 487         struct pci_dev *pdev  = to_pci_dev(dev->dev);
 488
 489         if (pdev->dev.bus && pdev->dev.bus->pm) {
 490                 dev->pg_domain.ops = *pdev->dev.bus->pm;
 491
 492                 dev->pg_domain.ops.runtime_suspend = mei_me_pm_runtime_suspend;
 493                 dev->pg_domain.ops.runtime_resume = mei_me_pm_runtime_resume;
 494                 dev->pg_domain.ops.runtime_idle = mei_me_pm_runtime_idle;
 495
 496                 dev_pm_domain_set(&pdev->dev, &dev->pg_domain);
 497         }
 498 }
 499
 500 /**
 501  * mei_me_unset_pm_domain - clean pm domain structure for device
 502  *
 503  * @dev: mei_device
 504  */
 505 static inline void mei_me_unset_pm_domain(struct mei_device *dev)
 506 {
 507         /* stop using pm callbacks if any */
 508         dev_pm_domain_set(dev->dev, NULL);
 509 }
 510
 511 static const struct dev_pm_ops mei_me_pm_ops = {
 512         SET_SYSTEM_SLEEP_PM_OPS(mei_me_pci_suspend,
 513                                 mei_me_pci_resume)
 514         SET_RUNTIME_PM_OPS(
 515                 mei_me_pm_runtime_suspend,
 516                 mei_me_pm_runtime_resume,
 517                 mei_me_pm_runtime_idle)
 518 };
 519
 520 #define MEI_ME_PM_OPS   (&mei_me_pm_ops)
 521 #else
 522 #define MEI_ME_PM_OPS   NULL
 523 #endif /* CONFIG_PM */
 524 /*
 525  *  PCI driver structure
 526  */
 527 static struct pci_driver mei_me_driver = {
 528         .name = KBUILD_MODNAME,
 529         .id_table = mei_me_pci_tbl,
 530         .probe = mei_me_probe,
 531         .remove = mei_me_remove,
 532         .shutdown = mei_me_shutdown,
 533         .driver.pm = MEI_ME_PM_OPS,
 534         .driver.probe_type = PROBE_PREFER_ASYNCHRONOUS,
 535 };
 536
 537 module_pci_driver(mei_me_driver);
 538
 539 MODULE_AUTHOR("Intel Corporation");
 540 MODULE_DESCRIPTION("Intel(R) Management Engine Interface");
 541 MODULE_LICENSE("GPL v2");