1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright 2019-2020 HabanaLabs, Ltd.
11 #include <uapi/misc/habanalabs.h>
12 #include "../common/habanalabs.h"
13 #include "../include/common/hl_boot_if.h"
14 #include "../include/gaudi/gaudi_packets.h"
15 #include "../include/gaudi/gaudi.h"
16 #include "../include/gaudi/gaudi_async_events.h"
18 #define NUMBER_OF_EXT_HW_QUEUES 12
19 #define NUMBER_OF_CMPLT_QUEUES NUMBER_OF_EXT_HW_QUEUES
20 #define NUMBER_OF_CPU_HW_QUEUES 1
21 #define NUMBER_OF_INT_HW_QUEUES 100
22 #define NUMBER_OF_HW_QUEUES (NUMBER_OF_EXT_HW_QUEUES + \
23 NUMBER_OF_CPU_HW_QUEUES + \
24 NUMBER_OF_INT_HW_QUEUES)
27 * Number of MSI interrupts IDS:
28 * Each completion queue has 1 ID
29 * The event queue has 1 ID
31 #define NUMBER_OF_INTERRUPTS (NUMBER_OF_CMPLT_QUEUES + \
32 NUMBER_OF_CPU_HW_QUEUES)
34 #if (NUMBER_OF_INTERRUPTS > GAUDI_MSI_ENTRIES)
35 #error "Number of MSI interrupts must be smaller or equal to GAUDI_MSI_ENTRIES"
38 #define CORESIGHT_TIMEOUT_USEC 100000 /* 100 ms */
40 #define GAUDI_MAX_CLK_FREQ 2200000000ull /* 2200 MHz */
42 #define MAX_POWER_DEFAULT_PCI 200000 /* 200W */
43 #define MAX_POWER_DEFAULT_PMC 350000 /* 350W */
45 #define GAUDI_CPU_TIMEOUT_USEC 30000000 /* 30s */
47 #define TPC_ENABLED_MASK 0xFF
49 #define GAUDI_HBM_SIZE_32GB 0x800000000ull
50 #define GAUDI_HBM_DEVICES 4
51 #define GAUDI_HBM_CHANNELS 8
52 #define GAUDI_HBM_CFG_BASE (mmHBM0_BASE - CFG_BASE)
53 #define GAUDI_HBM_CFG_OFFSET (mmHBM1_BASE - mmHBM0_BASE)
55 #define DMA_MAX_TRANSFER_SIZE U32_MAX
57 #define GAUDI_DEFAULT_CARD_NAME "HL2000"
59 #define GAUDI_MAX_PENDING_CS 1024
61 #if !IS_MAX_PENDING_CS_VALID(GAUDI_MAX_PENDING_CS)
62 #error "GAUDI_MAX_PENDING_CS must be power of 2 and greater than 1"
65 #define PCI_DMA_NUMBER_OF_CHNLS 3
66 #define HBM_DMA_NUMBER_OF_CHNLS 5
67 #define DMA_NUMBER_OF_CHNLS (PCI_DMA_NUMBER_OF_CHNLS + \
68 HBM_DMA_NUMBER_OF_CHNLS)
70 #define MME_NUMBER_OF_SLAVE_ENGINES 2
71 #define MME_NUMBER_OF_ENGINES (MME_NUMBER_OF_MASTER_ENGINES + \
72 MME_NUMBER_OF_SLAVE_ENGINES)
73 #define MME_NUMBER_OF_QMANS (MME_NUMBER_OF_MASTER_ENGINES * \
76 #define QMAN_STREAMS 4
78 #define DMA_QMAN_OFFSET (mmDMA1_QM_BASE - mmDMA0_QM_BASE)
79 #define TPC_QMAN_OFFSET (mmTPC1_QM_BASE - mmTPC0_QM_BASE)
80 #define MME_QMAN_OFFSET (mmMME1_QM_BASE - mmMME0_QM_BASE)
81 #define NIC_MACRO_QMAN_OFFSET (mmNIC1_QM0_BASE - mmNIC0_QM0_BASE)
83 #define TPC_CFG_OFFSET (mmTPC1_CFG_BASE - mmTPC0_CFG_BASE)
85 #define DMA_CORE_OFFSET (mmDMA1_CORE_BASE - mmDMA0_CORE_BASE)
87 #define QMAN_LDMA_SRC_OFFSET (mmDMA0_CORE_SRC_BASE_LO - mmDMA0_CORE_CFG_0)
88 #define QMAN_LDMA_DST_OFFSET (mmDMA0_CORE_DST_BASE_LO - mmDMA0_CORE_CFG_0)
89 #define QMAN_LDMA_SIZE_OFFSET (mmDMA0_CORE_DST_TSIZE_0 - mmDMA0_CORE_CFG_0)
91 #define QMAN_CPDMA_SRC_OFFSET (mmDMA0_QM_CQ_PTR_LO_4 - mmDMA0_CORE_CFG_0)
92 #define QMAN_CPDMA_DST_OFFSET (mmDMA0_CORE_DST_BASE_LO - mmDMA0_CORE_CFG_0)
93 #define QMAN_CPDMA_SIZE_OFFSET (mmDMA0_QM_CQ_TSIZE_4 - mmDMA0_CORE_CFG_0)
95 #define SIF_RTR_CTRL_OFFSET (mmSIF_RTR_CTRL_1_BASE - mmSIF_RTR_CTRL_0_BASE)
97 #define NIF_RTR_CTRL_OFFSET (mmNIF_RTR_CTRL_1_BASE - mmNIF_RTR_CTRL_0_BASE)
99 #define MME_ACC_OFFSET (mmMME1_ACC_BASE - mmMME0_ACC_BASE)
100 #define SRAM_BANK_OFFSET (mmSRAM_Y0_X1_RTR_BASE - mmSRAM_Y0_X0_RTR_BASE)
102 #define NUM_OF_SOB_IN_BLOCK \
103 (((mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_2047 - \
104 mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0) + 4) >> 2)
106 #define NUM_OF_MONITORS_IN_BLOCK \
107 (((mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_STATUS_511 - \
108 mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_STATUS_0) + 4) >> 2)
111 /* DRAM Memory Map */
113 #define CPU_FW_IMAGE_SIZE 0x10000000 /* 256MB */
114 #define MMU_PAGE_TABLES_SIZE 0x0BF00000 /* 191MB */
115 #define MMU_CACHE_MNG_SIZE 0x00100000 /* 1MB */
116 #define RESERVED 0x04000000 /* 64MB */
118 #define CPU_FW_IMAGE_ADDR DRAM_PHYS_BASE
119 #define MMU_PAGE_TABLES_ADDR (CPU_FW_IMAGE_ADDR + CPU_FW_IMAGE_SIZE)
120 #define MMU_CACHE_MNG_ADDR (MMU_PAGE_TABLES_ADDR + MMU_PAGE_TABLES_SIZE)
122 #define DRAM_DRIVER_END_ADDR (MMU_CACHE_MNG_ADDR + MMU_CACHE_MNG_SIZE +\
125 #define DRAM_BASE_ADDR_USER 0x20000000
127 #if (DRAM_DRIVER_END_ADDR > DRAM_BASE_ADDR_USER)
128 #error "Driver must reserve no more than 512MB"
131 /* Internal QMANs PQ sizes */
133 #define MME_QMAN_LENGTH 1024
134 #define MME_QMAN_SIZE_IN_BYTES (MME_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE)
136 #define HBM_DMA_QMAN_LENGTH 1024
137 #define HBM_DMA_QMAN_SIZE_IN_BYTES \
138 (HBM_DMA_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE)
140 #define TPC_QMAN_LENGTH 1024
141 #define TPC_QMAN_SIZE_IN_BYTES (TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE)
143 #define SRAM_USER_BASE_OFFSET GAUDI_DRIVER_SRAM_RESERVED_SIZE_FROM_START
145 /* Virtual address space */
146 #define VA_HOST_SPACE_START 0x1000000000000ull /* 256TB */
147 #define VA_HOST_SPACE_END 0x3FF8000000000ull /* 1PB - 1TB */
148 #define VA_HOST_SPACE_SIZE (VA_HOST_SPACE_END - \
149 VA_HOST_SPACE_START) /* 767TB */
151 #define HW_CAP_PLL BIT(0)
152 #define HW_CAP_HBM BIT(1)
153 #define HW_CAP_MMU BIT(2)
154 #define HW_CAP_MME BIT(3)
155 #define HW_CAP_CPU BIT(4)
156 #define HW_CAP_PCI_DMA BIT(5)
157 #define HW_CAP_MSI BIT(6)
158 #define HW_CAP_CPU_Q BIT(7)
159 #define HW_CAP_HBM_DMA BIT(8)
160 #define HW_CAP_CLK_GATE BIT(9)
161 #define HW_CAP_SRAM_SCRAMBLER BIT(10)
162 #define HW_CAP_HBM_SCRAMBLER BIT(11)
164 #define HW_CAP_TPC0 BIT(24)
165 #define HW_CAP_TPC1 BIT(25)
166 #define HW_CAP_TPC2 BIT(26)
167 #define HW_CAP_TPC3 BIT(27)
168 #define HW_CAP_TPC4 BIT(28)
169 #define HW_CAP_TPC5 BIT(29)
170 #define HW_CAP_TPC6 BIT(30)
171 #define HW_CAP_TPC7 BIT(31)
172 #define HW_CAP_TPC_MASK GENMASK(31, 24)
173 #define HW_CAP_TPC_SHIFT 24
175 #define GAUDI_CPU_PCI_MSB_ADDR(addr) (((addr) & GENMASK_ULL(49, 39)) >> 39)
176 #define GAUDI_PCI_TO_CPU_ADDR(addr) \
178 (addr) &= ~GENMASK_ULL(49, 39); \
179 (addr) |= BIT_ULL(39); \
181 #define GAUDI_CPU_TO_PCI_ADDR(addr, extension) \
183 (addr) &= ~GENMASK_ULL(49, 39); \
184 (addr) |= (u64) (extension) << 39; \
187 enum gaudi_dma_channels {
199 enum gaudi_tpc_mask {
200 GAUDI_TPC_MASK_TPC0 = 0x01,
201 GAUDI_TPC_MASK_TPC1 = 0x02,
202 GAUDI_TPC_MASK_TPC2 = 0x04,
203 GAUDI_TPC_MASK_TPC3 = 0x08,
204 GAUDI_TPC_MASK_TPC4 = 0x10,
205 GAUDI_TPC_MASK_TPC5 = 0x20,
206 GAUDI_TPC_MASK_TPC6 = 0x40,
207 GAUDI_TPC_MASK_TPC7 = 0x80,
208 GAUDI_TPC_MASK_ALL = 0xFF
212 * struct gaudi_internal_qman_info - Internal QMAN information.
213 * @pq_kernel_addr: Kernel address of the PQ memory area in the host.
214 * @pq_dma_addr: DMA address of the PQ memory area in the host.
215 * @pq_size: Size of allocated host memory for PQ.
217 struct gaudi_internal_qman_info {
218 void *pq_kernel_addr;
219 dma_addr_t pq_dma_addr;
224 * struct gaudi_device - ASIC specific manage structure.
225 * @cpucp_info_get: get information on device from CPU-CP
226 * @hw_queues_lock: protects the H/W queues from concurrent access.
227 * @clk_gate_mutex: protects code areas that require clock gating to be disabled
229 * @internal_qmans: Internal QMANs information. The array size is larger than
230 * the actual number of internal queues because they are not in
232 * @hbm_bar_cur_addr: current address of HBM PCI bar.
233 * @max_freq_value: current max clk frequency.
234 * @events: array that holds all event id's
235 * @events_stat: array that holds histogram of all received events.
236 * @events_stat_aggregate: same as events_stat but doesn't get cleared on reset
237 * @hw_cap_initialized: This field contains a bit per H/W engine. When that
238 * engine is initialized, that bit is set by the driver to
239 * signal we can use this engine in later code paths.
240 * Each bit is cleared upon reset of its corresponding H/W
242 * @multi_msi_mode: whether we are working in multi MSI single MSI mode.
243 * Multi MSI is possible only with IOMMU enabled.
244 * @mmu_cache_inv_pi: PI for MMU cache invalidation flow. The H/W expects an
245 * 8-bit value so use u8.
247 struct gaudi_device {
248 int (*cpucp_info_get)(struct hl_device *hdev);
250 /* TODO: remove hw_queues_lock after moving to scheduler code */
251 spinlock_t hw_queues_lock;
252 struct mutex clk_gate_mutex;
254 struct gaudi_internal_qman_info internal_qmans[GAUDI_QUEUE_ID_SIZE];
256 u64 hbm_bar_cur_addr;
259 u32 events[GAUDI_EVENT_SIZE];
260 u32 events_stat[GAUDI_EVENT_SIZE];
261 u32 events_stat_aggregate[GAUDI_EVENT_SIZE];
262 u32 hw_cap_initialized;
267 void gaudi_init_security(struct hl_device *hdev);
268 void gaudi_add_device_attr(struct hl_device *hdev,
269 struct attribute_group *dev_attr_grp);
270 void gaudi_set_pll_profile(struct hl_device *hdev, enum hl_pll_frequency freq);
271 int gaudi_debug_coresight(struct hl_device *hdev, void *data);
272 void gaudi_halt_coresight(struct hl_device *hdev);
273 int gaudi_get_clk_rate(struct hl_device *hdev, u32 *cur_clk, u32 *max_clk);
274 void gaudi_mmu_prepare_reg(struct hl_device *hdev, u64 reg, u32 asid);
276 #endif /* GAUDIP_H_ */