1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2016-2019 HabanaLabs, Ltd.
8 #include "habanalabs.h"
9 #include "../include/hw_ip/mmu/mmu_general.h"
11 #include <linux/genalloc.h>
12 #include <linux/slab.h>
14 static inline u64 get_phys_addr(struct hl_ctx *ctx, u64 shadow_addr);
16 static struct pgt_info *get_pgt_info(struct hl_ctx *ctx, u64 hop_addr)
18 struct pgt_info *pgt_info = NULL;
20 hash_for_each_possible(ctx->mmu_shadow_hash, pgt_info, node,
21 (unsigned long) hop_addr)
22 if (hop_addr == pgt_info->shadow_addr)
28 static void _free_hop(struct hl_ctx *ctx, struct pgt_info *pgt_info)
30 struct hl_device *hdev = ctx->hdev;
32 gen_pool_free(hdev->mmu_priv.mmu_pgt_pool, pgt_info->phys_addr,
33 hdev->asic_prop.mmu_hop_table_size);
34 hash_del(&pgt_info->node);
35 kfree((u64 *) (uintptr_t) pgt_info->shadow_addr);
39 static void free_hop(struct hl_ctx *ctx, u64 hop_addr)
41 struct pgt_info *pgt_info = get_pgt_info(ctx, hop_addr);
43 _free_hop(ctx, pgt_info);
46 static u64 alloc_hop(struct hl_ctx *ctx)
48 struct hl_device *hdev = ctx->hdev;
49 struct asic_fixed_properties *prop = &hdev->asic_prop;
50 struct pgt_info *pgt_info;
51 u64 phys_addr, shadow_addr;
53 pgt_info = kmalloc(sizeof(*pgt_info), GFP_KERNEL);
57 phys_addr = (u64) gen_pool_alloc(hdev->mmu_priv.mmu_pgt_pool,
58 prop->mmu_hop_table_size);
60 dev_err(hdev->dev, "failed to allocate page\n");
64 shadow_addr = (u64) (uintptr_t) kzalloc(prop->mmu_hop_table_size,
69 pgt_info->phys_addr = phys_addr;
70 pgt_info->shadow_addr = shadow_addr;
72 pgt_info->num_of_ptes = 0;
73 hash_add(ctx->mmu_shadow_hash, &pgt_info->node, shadow_addr);
78 gen_pool_free(hdev->mmu_priv.mmu_pgt_pool, phys_addr,
79 prop->mmu_hop_table_size);
86 static inline u64 get_phys_hop0_addr(struct hl_ctx *ctx)
88 return ctx->hdev->asic_prop.mmu_pgt_addr +
89 (ctx->asid * ctx->hdev->asic_prop.mmu_hop_table_size);
92 static inline u64 get_hop0_addr(struct hl_ctx *ctx)
94 return (u64) (uintptr_t) ctx->hdev->mmu_priv.mmu_shadow_hop0 +
95 (ctx->asid * ctx->hdev->asic_prop.mmu_hop_table_size);
98 static void flush(struct hl_ctx *ctx)
100 /* flush all writes from all cores to reach PCI */
102 ctx->hdev->asic_funcs->read_pte(ctx->hdev, get_phys_hop0_addr(ctx));
105 /* transform the value to physical address when writing to H/W */
106 static inline void write_pte(struct hl_ctx *ctx, u64 shadow_pte_addr, u64 val)
109 * The value to write is actually the address of the next shadow hop +
110 * flags at the 12 LSBs.
111 * Hence in order to get the value to write to the physical PTE, we
112 * clear the 12 LSBs and translate the shadow hop to its associated
113 * physical hop, and add back the original 12 LSBs.
115 u64 phys_val = get_phys_addr(ctx, val & HOP_PHYS_ADDR_MASK) |
118 ctx->hdev->asic_funcs->write_pte(ctx->hdev,
119 get_phys_addr(ctx, shadow_pte_addr),
122 *(u64 *) (uintptr_t) shadow_pte_addr = val;
125 /* do not transform the value to physical address when writing to H/W */
126 static inline void write_final_pte(struct hl_ctx *ctx, u64 shadow_pte_addr,
129 ctx->hdev->asic_funcs->write_pte(ctx->hdev,
130 get_phys_addr(ctx, shadow_pte_addr),
132 *(u64 *) (uintptr_t) shadow_pte_addr = val;
135 /* clear the last and present bits */
136 static inline void clear_pte(struct hl_ctx *ctx, u64 pte_addr)
138 /* no need to transform the value to physical address */
139 write_final_pte(ctx, pte_addr, 0);
142 static inline void get_pte(struct hl_ctx *ctx, u64 hop_addr)
144 get_pgt_info(ctx, hop_addr)->num_of_ptes++;
148 * put_pte - decrement the num of ptes and free the hop if possible
150 * @ctx: pointer to the context structure
151 * @hop_addr: addr of the hop
153 * This function returns the number of ptes left on this hop. If the number is
154 * 0, it means the pte was freed.
156 static inline int put_pte(struct hl_ctx *ctx, u64 hop_addr)
158 struct pgt_info *pgt_info = get_pgt_info(ctx, hop_addr);
159 int num_of_ptes_left;
161 pgt_info->num_of_ptes--;
164 * Need to save the number of ptes left because free_hop might free
167 num_of_ptes_left = pgt_info->num_of_ptes;
168 if (!num_of_ptes_left)
169 _free_hop(ctx, pgt_info);
171 return num_of_ptes_left;
174 static inline u64 get_hopN_pte_addr(struct hl_ctx *ctx, u64 hop_addr,
175 u64 virt_addr, u64 mask, u64 shift)
177 return hop_addr + ctx->hdev->asic_prop.mmu_pte_size *
178 ((virt_addr & mask) >> shift);
181 static inline u64 get_hop0_pte_addr(struct hl_ctx *ctx,
182 struct hl_mmu_properties *mmu_prop,
183 u64 hop_addr, u64 vaddr)
185 return get_hopN_pte_addr(ctx, hop_addr, vaddr, mmu_prop->hop0_mask,
186 mmu_prop->hop0_shift);
189 static inline u64 get_hop1_pte_addr(struct hl_ctx *ctx,
190 struct hl_mmu_properties *mmu_prop,
191 u64 hop_addr, u64 vaddr)
193 return get_hopN_pte_addr(ctx, hop_addr, vaddr, mmu_prop->hop1_mask,
194 mmu_prop->hop1_shift);
197 static inline u64 get_hop2_pte_addr(struct hl_ctx *ctx,
198 struct hl_mmu_properties *mmu_prop,
199 u64 hop_addr, u64 vaddr)
201 return get_hopN_pte_addr(ctx, hop_addr, vaddr, mmu_prop->hop2_mask,
202 mmu_prop->hop2_shift);
205 static inline u64 get_hop3_pte_addr(struct hl_ctx *ctx,
206 struct hl_mmu_properties *mmu_prop,
207 u64 hop_addr, u64 vaddr)
209 return get_hopN_pte_addr(ctx, hop_addr, vaddr, mmu_prop->hop3_mask,
210 mmu_prop->hop3_shift);
213 static inline u64 get_hop4_pte_addr(struct hl_ctx *ctx,
214 struct hl_mmu_properties *mmu_prop,
215 u64 hop_addr, u64 vaddr)
217 return get_hopN_pte_addr(ctx, hop_addr, vaddr, mmu_prop->hop4_mask,
218 mmu_prop->hop4_shift);
221 static inline u64 get_next_hop_addr(struct hl_ctx *ctx, u64 curr_pte)
223 if (curr_pte & PAGE_PRESENT_MASK)
224 return curr_pte & HOP_PHYS_ADDR_MASK;
229 static inline u64 get_alloc_next_hop_addr(struct hl_ctx *ctx, u64 curr_pte,
232 u64 hop_addr = get_next_hop_addr(ctx, curr_pte);
234 if (hop_addr == ULLONG_MAX) {
235 hop_addr = alloc_hop(ctx);
236 *is_new_hop = (hop_addr != ULLONG_MAX);
242 /* translates shadow address inside hop to a physical address */
243 static inline u64 get_phys_addr(struct hl_ctx *ctx, u64 shadow_addr)
245 u64 page_mask = (ctx->hdev->asic_prop.mmu_hop_table_size - 1);
246 u64 shadow_hop_addr = shadow_addr & ~page_mask;
247 u64 pte_offset = shadow_addr & page_mask;
250 if (shadow_hop_addr != get_hop0_addr(ctx))
251 phys_hop_addr = get_pgt_info(ctx, shadow_hop_addr)->phys_addr;
253 phys_hop_addr = get_phys_hop0_addr(ctx);
255 return phys_hop_addr + pte_offset;
258 static int dram_default_mapping_init(struct hl_ctx *ctx)
260 struct hl_device *hdev = ctx->hdev;
261 struct asic_fixed_properties *prop = &hdev->asic_prop;
262 u64 num_of_hop3, total_hops, hop0_addr, hop1_addr, hop2_addr,
263 hop2_pte_addr, hop3_pte_addr, pte_val;
264 int rc, i, j, hop3_allocated = 0;
266 if ((!hdev->dram_supports_virtual_memory) ||
267 (!hdev->dram_default_page_mapping) ||
268 (ctx->asid == HL_KERNEL_ASID_ID))
271 num_of_hop3 = prop->dram_size_for_default_page_mapping;
272 do_div(num_of_hop3, prop->dram_page_size);
273 do_div(num_of_hop3, PTE_ENTRIES_IN_HOP);
275 /* add hop1 and hop2 */
276 total_hops = num_of_hop3 + 2;
278 ctx->dram_default_hops = kzalloc(HL_PTE_SIZE * total_hops, GFP_KERNEL);
279 if (!ctx->dram_default_hops)
282 hop0_addr = get_hop0_addr(ctx);
284 hop1_addr = alloc_hop(ctx);
285 if (hop1_addr == ULLONG_MAX) {
286 dev_err(hdev->dev, "failed to alloc hop 1\n");
291 ctx->dram_default_hops[total_hops - 1] = hop1_addr;
293 hop2_addr = alloc_hop(ctx);
294 if (hop2_addr == ULLONG_MAX) {
295 dev_err(hdev->dev, "failed to alloc hop 2\n");
300 ctx->dram_default_hops[total_hops - 2] = hop2_addr;
302 for (i = 0 ; i < num_of_hop3 ; i++) {
303 ctx->dram_default_hops[i] = alloc_hop(ctx);
304 if (ctx->dram_default_hops[i] == ULLONG_MAX) {
305 dev_err(hdev->dev, "failed to alloc hop 3, i: %d\n", i);
312 /* need only pte 0 in hops 0 and 1 */
313 pte_val = (hop1_addr & HOP_PHYS_ADDR_MASK) | PAGE_PRESENT_MASK;
314 write_pte(ctx, hop0_addr, pte_val);
316 pte_val = (hop2_addr & HOP_PHYS_ADDR_MASK) | PAGE_PRESENT_MASK;
317 write_pte(ctx, hop1_addr, pte_val);
318 get_pte(ctx, hop1_addr);
320 hop2_pte_addr = hop2_addr;
321 for (i = 0 ; i < num_of_hop3 ; i++) {
322 pte_val = (ctx->dram_default_hops[i] & HOP_PHYS_ADDR_MASK) |
324 write_pte(ctx, hop2_pte_addr, pte_val);
325 get_pte(ctx, hop2_addr);
326 hop2_pte_addr += HL_PTE_SIZE;
329 pte_val = (prop->mmu_dram_default_page_addr & HOP_PHYS_ADDR_MASK) |
330 LAST_MASK | PAGE_PRESENT_MASK;
332 for (i = 0 ; i < num_of_hop3 ; i++) {
333 hop3_pte_addr = ctx->dram_default_hops[i];
334 for (j = 0 ; j < PTE_ENTRIES_IN_HOP ; j++) {
335 write_final_pte(ctx, hop3_pte_addr, pte_val);
336 get_pte(ctx, ctx->dram_default_hops[i]);
337 hop3_pte_addr += HL_PTE_SIZE;
346 for (i = 0 ; i < hop3_allocated ; i++)
347 free_hop(ctx, ctx->dram_default_hops[i]);
349 free_hop(ctx, hop2_addr);
351 free_hop(ctx, hop1_addr);
353 kfree(ctx->dram_default_hops);
358 static void dram_default_mapping_fini(struct hl_ctx *ctx)
360 struct hl_device *hdev = ctx->hdev;
361 struct asic_fixed_properties *prop = &hdev->asic_prop;
362 u64 num_of_hop3, total_hops, hop0_addr, hop1_addr, hop2_addr,
363 hop2_pte_addr, hop3_pte_addr;
366 if ((!hdev->dram_supports_virtual_memory) ||
367 (!hdev->dram_default_page_mapping) ||
368 (ctx->asid == HL_KERNEL_ASID_ID))
371 num_of_hop3 = prop->dram_size_for_default_page_mapping;
372 do_div(num_of_hop3, prop->dram_page_size);
373 do_div(num_of_hop3, PTE_ENTRIES_IN_HOP);
375 hop0_addr = get_hop0_addr(ctx);
376 /* add hop1 and hop2 */
377 total_hops = num_of_hop3 + 2;
378 hop1_addr = ctx->dram_default_hops[total_hops - 1];
379 hop2_addr = ctx->dram_default_hops[total_hops - 2];
381 for (i = 0 ; i < num_of_hop3 ; i++) {
382 hop3_pte_addr = ctx->dram_default_hops[i];
383 for (j = 0 ; j < PTE_ENTRIES_IN_HOP ; j++) {
384 clear_pte(ctx, hop3_pte_addr);
385 put_pte(ctx, ctx->dram_default_hops[i]);
386 hop3_pte_addr += HL_PTE_SIZE;
390 hop2_pte_addr = hop2_addr;
391 hop2_pte_addr = hop2_addr;
392 for (i = 0 ; i < num_of_hop3 ; i++) {
393 clear_pte(ctx, hop2_pte_addr);
394 put_pte(ctx, hop2_addr);
395 hop2_pte_addr += HL_PTE_SIZE;
398 clear_pte(ctx, hop1_addr);
399 put_pte(ctx, hop1_addr);
400 clear_pte(ctx, hop0_addr);
402 kfree(ctx->dram_default_hops);
408 * hl_mmu_v1_init() - initialize the MMU module.
409 * @hdev: habanalabs device structure.
411 * This function does the following:
412 * - Create a pool of pages for pgt_infos.
413 * - Create a shadow table for pgt
415 * Return: 0 for success, non-zero for failure.
417 static int hl_mmu_v1_init(struct hl_device *hdev)
419 struct asic_fixed_properties *prop = &hdev->asic_prop;
422 hdev->mmu_priv.mmu_pgt_pool =
423 gen_pool_create(__ffs(prop->mmu_hop_table_size), -1);
425 if (!hdev->mmu_priv.mmu_pgt_pool) {
426 dev_err(hdev->dev, "Failed to create page gen pool\n");
430 rc = gen_pool_add(hdev->mmu_priv.mmu_pgt_pool, prop->mmu_pgt_addr +
431 prop->mmu_hop0_tables_total_size,
432 prop->mmu_pgt_size - prop->mmu_hop0_tables_total_size,
435 dev_err(hdev->dev, "Failed to add memory to page gen pool\n");
439 hdev->mmu_priv.mmu_shadow_hop0 = kvmalloc_array(prop->max_asid,
440 prop->mmu_hop_table_size,
441 GFP_KERNEL | __GFP_ZERO);
442 if (ZERO_OR_NULL_PTR(hdev->mmu_priv.mmu_shadow_hop0)) {
447 /* MMU H/W init will be done in device hw_init() */
452 gen_pool_destroy(hdev->mmu_priv.mmu_pgt_pool);
458 * hl_mmu_fini() - release the MMU module.
459 * @hdev: habanalabs device structure.
461 * This function does the following:
462 * - Disable MMU in H/W.
463 * - Free the pgt_infos pool.
465 * All contexts should be freed before calling this function.
467 static void hl_mmu_v1_fini(struct hl_device *hdev)
469 /* MMU H/W fini was already done in device hw_fini() */
471 kvfree(hdev->mmu_priv.mmu_shadow_hop0);
472 gen_pool_destroy(hdev->mmu_priv.mmu_pgt_pool);
476 * hl_mmu_ctx_init() - initialize a context for using the MMU module.
477 * @ctx: pointer to the context structure to initialize.
479 * Initialize a mutex to protect the concurrent mapping flow, a hash to hold all
480 * page tables hops related to this context.
481 * Return: 0 on success, non-zero otherwise.
483 static int hl_mmu_v1_ctx_init(struct hl_ctx *ctx)
485 mutex_init(&ctx->mmu_lock);
486 hash_init(ctx->mmu_shadow_hash);
488 return dram_default_mapping_init(ctx);
492 * hl_mmu_ctx_fini - disable a ctx from using the mmu module
494 * @ctx: pointer to the context structure
496 * This function does the following:
497 * - Free any pgts which were not freed yet
499 * - Free DRAM default page mapping hops
501 static void hl_mmu_v1_ctx_fini(struct hl_ctx *ctx)
503 struct hl_device *hdev = ctx->hdev;
504 struct pgt_info *pgt_info;
505 struct hlist_node *tmp;
508 dram_default_mapping_fini(ctx);
510 if (!hash_empty(ctx->mmu_shadow_hash))
511 dev_err(hdev->dev, "ctx %d is freed while it has pgts in use\n",
514 hash_for_each_safe(ctx->mmu_shadow_hash, i, tmp, pgt_info, node) {
515 dev_err_ratelimited(hdev->dev,
516 "pgt_info of addr 0x%llx of asid %d was not destroyed, num_ptes: %d\n",
517 pgt_info->phys_addr, ctx->asid, pgt_info->num_of_ptes);
518 _free_hop(ctx, pgt_info);
521 mutex_destroy(&ctx->mmu_lock);
524 static int _hl_mmu_v1_unmap(struct hl_ctx *ctx,
525 u64 virt_addr, bool is_dram_addr)
527 struct hl_device *hdev = ctx->hdev;
528 struct asic_fixed_properties *prop = &hdev->asic_prop;
529 struct hl_mmu_properties *mmu_prop;
530 u64 hop0_addr = 0, hop0_pte_addr = 0,
531 hop1_addr = 0, hop1_pte_addr = 0,
532 hop2_addr = 0, hop2_pte_addr = 0,
533 hop3_addr = 0, hop3_pte_addr = 0,
534 hop4_addr = 0, hop4_pte_addr = 0,
536 bool is_huge, clear_hop3 = true;
538 /* shifts and masks are the same in PMMU and HPMMU, use one of them */
539 mmu_prop = is_dram_addr ? &prop->dmmu : &prop->pmmu;
541 hop0_addr = get_hop0_addr(ctx);
542 hop0_pte_addr = get_hop0_pte_addr(ctx, mmu_prop, hop0_addr, virt_addr);
544 curr_pte = *(u64 *) (uintptr_t) hop0_pte_addr;
546 hop1_addr = get_next_hop_addr(ctx, curr_pte);
548 if (hop1_addr == ULLONG_MAX)
551 hop1_pte_addr = get_hop1_pte_addr(ctx, mmu_prop, hop1_addr, virt_addr);
553 curr_pte = *(u64 *) (uintptr_t) hop1_pte_addr;
555 hop2_addr = get_next_hop_addr(ctx, curr_pte);
557 if (hop2_addr == ULLONG_MAX)
560 hop2_pte_addr = get_hop2_pte_addr(ctx, mmu_prop, hop2_addr, virt_addr);
562 curr_pte = *(u64 *) (uintptr_t) hop2_pte_addr;
564 hop3_addr = get_next_hop_addr(ctx, curr_pte);
566 if (hop3_addr == ULLONG_MAX)
569 hop3_pte_addr = get_hop3_pte_addr(ctx, mmu_prop, hop3_addr, virt_addr);
571 curr_pte = *(u64 *) (uintptr_t) hop3_pte_addr;
573 is_huge = curr_pte & LAST_MASK;
575 if (is_dram_addr && !is_huge) {
577 "DRAM unmapping should use huge pages only\n");
582 hop4_addr = get_next_hop_addr(ctx, curr_pte);
584 if (hop4_addr == ULLONG_MAX)
587 hop4_pte_addr = get_hop4_pte_addr(ctx, mmu_prop, hop4_addr,
590 curr_pte = *(u64 *) (uintptr_t) hop4_pte_addr;
595 if (hdev->dram_default_page_mapping && is_dram_addr) {
596 u64 default_pte = (prop->mmu_dram_default_page_addr &
597 HOP_PHYS_ADDR_MASK) | LAST_MASK |
599 if (curr_pte == default_pte) {
601 "DRAM: hop3 PTE points to zero page, can't unmap, va: 0x%llx\n",
606 if (!(curr_pte & PAGE_PRESENT_MASK)) {
608 "DRAM: hop3 PTE is cleared! can't unmap, va: 0x%llx\n",
613 write_final_pte(ctx, hop3_pte_addr, default_pte);
614 put_pte(ctx, hop3_addr);
616 if (!(curr_pte & PAGE_PRESENT_MASK))
620 clear_pte(ctx, hop4_pte_addr);
622 clear_pte(ctx, hop3_pte_addr);
624 if (hop4_addr && !put_pte(ctx, hop4_addr))
630 clear_pte(ctx, hop3_pte_addr);
632 if (put_pte(ctx, hop3_addr))
635 clear_pte(ctx, hop2_pte_addr);
637 if (put_pte(ctx, hop2_addr))
640 clear_pte(ctx, hop1_pte_addr);
642 if (put_pte(ctx, hop1_addr))
645 clear_pte(ctx, hop0_pte_addr);
652 dev_err(hdev->dev, "virt addr 0x%llx is not mapped to phys addr\n",
658 static int _hl_mmu_v1_map(struct hl_ctx *ctx, u64 virt_addr, u64 phys_addr,
659 u32 page_size, bool is_dram_addr)
661 struct hl_device *hdev = ctx->hdev;
662 struct asic_fixed_properties *prop = &hdev->asic_prop;
663 struct hl_mmu_properties *mmu_prop;
664 u64 hop0_addr = 0, hop0_pte_addr = 0,
665 hop1_addr = 0, hop1_pte_addr = 0,
666 hop2_addr = 0, hop2_pte_addr = 0,
667 hop3_addr = 0, hop3_pte_addr = 0,
668 hop4_addr = 0, hop4_pte_addr = 0,
670 bool hop1_new = false, hop2_new = false, hop3_new = false,
671 hop4_new = false, is_huge;
675 * This mapping function can map a page or a huge page. For huge page
676 * there are only 3 hops rather than 4. Currently the DRAM allocation
677 * uses huge pages only but user memory could have been allocated with
678 * one of the two page sizes. Since this is a common code for all the
679 * three cases, we need this hugs page check.
682 mmu_prop = &prop->dmmu;
684 } else if (page_size == prop->pmmu_huge.page_size) {
685 mmu_prop = &prop->pmmu_huge;
688 mmu_prop = &prop->pmmu;
692 hop0_addr = get_hop0_addr(ctx);
693 hop0_pte_addr = get_hop0_pte_addr(ctx, mmu_prop, hop0_addr, virt_addr);
694 curr_pte = *(u64 *) (uintptr_t) hop0_pte_addr;
696 hop1_addr = get_alloc_next_hop_addr(ctx, curr_pte, &hop1_new);
697 if (hop1_addr == ULLONG_MAX)
700 hop1_pte_addr = get_hop1_pte_addr(ctx, mmu_prop, hop1_addr, virt_addr);
701 curr_pte = *(u64 *) (uintptr_t) hop1_pte_addr;
703 hop2_addr = get_alloc_next_hop_addr(ctx, curr_pte, &hop2_new);
704 if (hop2_addr == ULLONG_MAX)
707 hop2_pte_addr = get_hop2_pte_addr(ctx, mmu_prop, hop2_addr, virt_addr);
708 curr_pte = *(u64 *) (uintptr_t) hop2_pte_addr;
710 hop3_addr = get_alloc_next_hop_addr(ctx, curr_pte, &hop3_new);
711 if (hop3_addr == ULLONG_MAX)
714 hop3_pte_addr = get_hop3_pte_addr(ctx, mmu_prop, hop3_addr, virt_addr);
715 curr_pte = *(u64 *) (uintptr_t) hop3_pte_addr;
718 hop4_addr = get_alloc_next_hop_addr(ctx, curr_pte, &hop4_new);
719 if (hop4_addr == ULLONG_MAX)
722 hop4_pte_addr = get_hop4_pte_addr(ctx, mmu_prop, hop4_addr,
724 curr_pte = *(u64 *) (uintptr_t) hop4_pte_addr;
727 if (hdev->dram_default_page_mapping && is_dram_addr) {
728 u64 default_pte = (prop->mmu_dram_default_page_addr &
729 HOP_PHYS_ADDR_MASK) | LAST_MASK |
732 if (curr_pte != default_pte) {
734 "DRAM: mapping already exists for virt_addr 0x%llx\n",
740 if (hop1_new || hop2_new || hop3_new || hop4_new) {
742 "DRAM mapping should not allocate more hops\n");
746 } else if (curr_pte & PAGE_PRESENT_MASK) {
748 "mapping already exists for virt_addr 0x%llx\n",
751 dev_dbg(hdev->dev, "hop0 pte: 0x%llx (0x%llx)\n",
752 *(u64 *) (uintptr_t) hop0_pte_addr, hop0_pte_addr);
753 dev_dbg(hdev->dev, "hop1 pte: 0x%llx (0x%llx)\n",
754 *(u64 *) (uintptr_t) hop1_pte_addr, hop1_pte_addr);
755 dev_dbg(hdev->dev, "hop2 pte: 0x%llx (0x%llx)\n",
756 *(u64 *) (uintptr_t) hop2_pte_addr, hop2_pte_addr);
757 dev_dbg(hdev->dev, "hop3 pte: 0x%llx (0x%llx)\n",
758 *(u64 *) (uintptr_t) hop3_pte_addr, hop3_pte_addr);
761 dev_dbg(hdev->dev, "hop4 pte: 0x%llx (0x%llx)\n",
762 *(u64 *) (uintptr_t) hop4_pte_addr,
769 curr_pte = (phys_addr & HOP_PHYS_ADDR_MASK) | LAST_MASK
773 write_final_pte(ctx, hop3_pte_addr, curr_pte);
775 write_final_pte(ctx, hop4_pte_addr, curr_pte);
779 (hop1_addr & HOP_PHYS_ADDR_MASK) | PAGE_PRESENT_MASK;
780 write_pte(ctx, hop0_pte_addr, curr_pte);
784 (hop2_addr & HOP_PHYS_ADDR_MASK) | PAGE_PRESENT_MASK;
785 write_pte(ctx, hop1_pte_addr, curr_pte);
786 get_pte(ctx, hop1_addr);
790 (hop3_addr & HOP_PHYS_ADDR_MASK) | PAGE_PRESENT_MASK;
791 write_pte(ctx, hop2_pte_addr, curr_pte);
792 get_pte(ctx, hop2_addr);
797 curr_pte = (hop4_addr & HOP_PHYS_ADDR_MASK) |
799 write_pte(ctx, hop3_pte_addr, curr_pte);
800 get_pte(ctx, hop3_addr);
803 get_pte(ctx, hop4_addr);
805 get_pte(ctx, hop3_addr);
812 free_hop(ctx, hop4_addr);
814 free_hop(ctx, hop3_addr);
816 free_hop(ctx, hop2_addr);
818 free_hop(ctx, hop1_addr);
824 * hl_mmu_v1_swap_out - marks all mapping of the given ctx as swapped out
826 * @ctx: pointer to the context structure
829 static void hl_mmu_v1_swap_out(struct hl_ctx *ctx)
835 * hl_mmu_v1_swap_in - marks all mapping of the given ctx as swapped in
837 * @ctx: pointer to the context structure
840 static void hl_mmu_v1_swap_in(struct hl_ctx *ctx)
846 * hl_mmu_v1_prepare - prepare mmu for working with mmu v1
848 * @hdev: pointer to the device structure
850 void hl_mmu_v1_set_funcs(struct hl_device *hdev)
852 struct hl_mmu_funcs *mmu = &hdev->mmu_func;
854 mmu->init = hl_mmu_v1_init;
855 mmu->fini = hl_mmu_v1_fini;
856 mmu->ctx_init = hl_mmu_v1_ctx_init;
857 mmu->ctx_fini = hl_mmu_v1_ctx_fini;
858 mmu->map = _hl_mmu_v1_map;
859 mmu->unmap = _hl_mmu_v1_unmap;
861 mmu->swap_out = hl_mmu_v1_swap_out;
862 mmu->swap_in = hl_mmu_v1_swap_in;