drivers/misc/cxl/pci.c

   1 /*
   2  * Copyright 2014 IBM Corp.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * as published by the Free Software Foundation; either version
   7  * 2 of the License, or (at your option) any later version.
   8  */
   9
  10 #include <linux/pci_regs.h>
  11 #include <linux/pci_ids.h>
  12 #include <linux/device.h>
  13 #include <linux/module.h>
  14 #include <linux/kernel.h>
  15 #include <linux/slab.h>
  16 #include <linux/sort.h>
  17 #include <linux/pci.h>
  18 #include <linux/of.h>
  19 #include <linux/delay.h>
  20 #include <asm/opal.h>
  21 #include <asm/msi_bitmap.h>
  22 #include <asm/pnv-pci.h>
  23 #include <asm/io.h>
  24 #include <asm/reg.h>
  25
  26 #include "cxl.h"
  27 #include <misc/cxl.h>
  28
  29
  30 #define CXL_PCI_VSEC_ID 0x1280
  31 #define CXL_VSEC_MIN_SIZE 0x80
  32
  33 #define CXL_READ_VSEC_LENGTH(dev, vsec, dest)                   \
  34         {                                                       \
  35                 pci_read_config_word(dev, vsec + 0x6, dest);    \
  36                 *dest >>= 4;                                    \
  37         }
  38 #define CXL_READ_VSEC_NAFUS(dev, vsec, dest) \
  39         pci_read_config_byte(dev, vsec + 0x8, dest)
  40
  41 #define CXL_READ_VSEC_STATUS(dev, vsec, dest) \
  42         pci_read_config_byte(dev, vsec + 0x9, dest)
  43 #define CXL_STATUS_SECOND_PORT  0x80
  44 #define CXL_STATUS_MSI_X_FULL   0x40
  45 #define CXL_STATUS_MSI_X_SINGLE 0x20
  46 #define CXL_STATUS_FLASH_RW     0x08
  47 #define CXL_STATUS_FLASH_RO     0x04
  48 #define CXL_STATUS_LOADABLE_AFU 0x02
  49 #define CXL_STATUS_LOADABLE_PSL 0x01
  50 /* If we see these features we won't try to use the card */
  51 #define CXL_UNSUPPORTED_FEATURES \
  52         (CXL_STATUS_MSI_X_FULL | CXL_STATUS_MSI_X_SINGLE)
  53
  54 #define CXL_READ_VSEC_MODE_CONTROL(dev, vsec, dest) \
  55         pci_read_config_byte(dev, vsec + 0xa, dest)
  56 #define CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val) \
  57         pci_write_config_byte(dev, vsec + 0xa, val)
  58 #define CXL_WRITE_VSEC_MODE_CONTROL_BUS(bus, devfn, vsec, val) \
  59         pci_bus_write_config_byte(bus, devfn, vsec + 0xa, val)
  60 #define CXL_VSEC_PROTOCOL_MASK   0xe0
  61 #define CXL_VSEC_PROTOCOL_1024TB 0x80
  62 #define CXL_VSEC_PROTOCOL_512TB  0x40
  63 #define CXL_VSEC_PROTOCOL_256TB  0x20 /* Power 8/9 uses this */
  64 #define CXL_VSEC_PROTOCOL_ENABLE 0x01
  65
  66 #define CXL_READ_VSEC_PSL_REVISION(dev, vsec, dest) \
  67         pci_read_config_word(dev, vsec + 0xc, dest)
  68 #define CXL_READ_VSEC_CAIA_MINOR(dev, vsec, dest) \
  69         pci_read_config_byte(dev, vsec + 0xe, dest)
  70 #define CXL_READ_VSEC_CAIA_MAJOR(dev, vsec, dest) \
  71         pci_read_config_byte(dev, vsec + 0xf, dest)
  72 #define CXL_READ_VSEC_BASE_IMAGE(dev, vsec, dest) \
  73         pci_read_config_word(dev, vsec + 0x10, dest)
  74
  75 #define CXL_READ_VSEC_IMAGE_STATE(dev, vsec, dest) \
  76         pci_read_config_byte(dev, vsec + 0x13, dest)
  77 #define CXL_WRITE_VSEC_IMAGE_STATE(dev, vsec, val) \
  78         pci_write_config_byte(dev, vsec + 0x13, val)
  79 #define CXL_VSEC_USER_IMAGE_LOADED 0x80 /* RO */
  80 #define CXL_VSEC_PERST_LOADS_IMAGE 0x20 /* RW */
  81 #define CXL_VSEC_PERST_SELECT_USER 0x10 /* RW */
  82
  83 #define CXL_READ_VSEC_AFU_DESC_OFF(dev, vsec, dest) \
  84         pci_read_config_dword(dev, vsec + 0x20, dest)
  85 #define CXL_READ_VSEC_AFU_DESC_SIZE(dev, vsec, dest) \
  86         pci_read_config_dword(dev, vsec + 0x24, dest)
  87 #define CXL_READ_VSEC_PS_OFF(dev, vsec, dest) \
  88         pci_read_config_dword(dev, vsec + 0x28, dest)
  89 #define CXL_READ_VSEC_PS_SIZE(dev, vsec, dest) \
  90         pci_read_config_dword(dev, vsec + 0x2c, dest)
  91
  92
  93 /* This works a little different than the p1/p2 register accesses to make it
  94  * easier to pull out individual fields */
  95 #define AFUD_READ(afu, off)             in_be64(afu->native->afu_desc_mmio + off)
  96 #define AFUD_READ_LE(afu, off)          in_le64(afu->native->afu_desc_mmio + off)
  97 #define EXTRACT_PPC_BIT(val, bit)       (!!(val & PPC_BIT(bit)))
  98 #define EXTRACT_PPC_BITS(val, bs, be)   ((val & PPC_BITMASK(bs, be)) >> PPC_BITLSHIFT(be))
  99
 100 #define AFUD_READ_INFO(afu)             AFUD_READ(afu, 0x0)
 101 #define   AFUD_NUM_INTS_PER_PROC(val)   EXTRACT_PPC_BITS(val,  0, 15)
 102 #define   AFUD_NUM_PROCS(val)           EXTRACT_PPC_BITS(val, 16, 31)
 103 #define   AFUD_NUM_CRS(val)             EXTRACT_PPC_BITS(val, 32, 47)
 104 #define   AFUD_MULTIMODE(val)           EXTRACT_PPC_BIT(val, 48)
 105 #define   AFUD_PUSH_BLOCK_TRANSFER(val) EXTRACT_PPC_BIT(val, 55)
 106 #define   AFUD_DEDICATED_PROCESS(val)   EXTRACT_PPC_BIT(val, 59)
 107 #define   AFUD_AFU_DIRECTED(val)        EXTRACT_PPC_BIT(val, 61)
 108 #define   AFUD_TIME_SLICED(val)         EXTRACT_PPC_BIT(val, 63)
 109 #define AFUD_READ_CR(afu)               AFUD_READ(afu, 0x20)
 110 #define   AFUD_CR_LEN(val)              EXTRACT_PPC_BITS(val, 8, 63)
 111 #define AFUD_READ_CR_OFF(afu)           AFUD_READ(afu, 0x28)
 112 #define AFUD_READ_PPPSA(afu)            AFUD_READ(afu, 0x30)
 113 #define   AFUD_PPPSA_PP(val)            EXTRACT_PPC_BIT(val, 6)
 114 #define   AFUD_PPPSA_PSA(val)           EXTRACT_PPC_BIT(val, 7)
 115 #define   AFUD_PPPSA_LEN(val)           EXTRACT_PPC_BITS(val, 8, 63)
 116 #define AFUD_READ_PPPSA_OFF(afu)        AFUD_READ(afu, 0x38)
 117 #define AFUD_READ_EB(afu)               AFUD_READ(afu, 0x40)
 118 #define   AFUD_EB_LEN(val)              EXTRACT_PPC_BITS(val, 8, 63)
 119 #define AFUD_READ_EB_OFF(afu)           AFUD_READ(afu, 0x48)
 120
 121 static const struct pci_device_id cxl_pci_tbl[] = {
 122         { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0477), },
 123         { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x044b), },
 124         { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x04cf), },
 125         { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0601), },
 126         { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0623), },
 127         { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0628), },
 128         { PCI_DEVICE_CLASS(0x120000, ~0), },
 129
 130         { }
 131 };
 132 MODULE_DEVICE_TABLE(pci, cxl_pci_tbl);
 133
 134
 135 /*
 136  * Mostly using these wrappers to avoid confusion:
 137  * priv 1 is BAR2, while priv 2 is BAR0
 138  */
 139 static inline resource_size_t p1_base(struct pci_dev *dev)
 140 {
 141         return pci_resource_start(dev, 2);
 142 }
 143
 144 static inline resource_size_t p1_size(struct pci_dev *dev)
 145 {
 146         return pci_resource_len(dev, 2);
 147 }
 148
 149 static inline resource_size_t p2_base(struct pci_dev *dev)
 150 {
 151         return pci_resource_start(dev, 0);
 152 }
 153
 154 static inline resource_size_t p2_size(struct pci_dev *dev)
 155 {
 156         return pci_resource_len(dev, 0);
 157 }
 158
 159 static int find_cxl_vsec(struct pci_dev *dev)
 160 {
 161         int vsec = 0;
 162         u16 val;
 163
 164         while ((vsec = pci_find_next_ext_capability(dev, vsec, PCI_EXT_CAP_ID_VNDR))) {
 165                 pci_read_config_word(dev, vsec + 0x4, &val);
 166                 if (val == CXL_PCI_VSEC_ID)
 167                         return vsec;
 168         }
 169         return 0;
 170
 171 }
 172
 173 static void dump_cxl_config_space(struct pci_dev *dev)
 174 {
 175         int vsec;
 176         u32 val;
 177
 178         dev_info(&dev->dev, "dump_cxl_config_space\n");
 179
 180         pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &val);
 181         dev_info(&dev->dev, "BAR0: %#.8x\n", val);
 182         pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, &val);
 183         dev_info(&dev->dev, "BAR1: %#.8x\n", val);
 184         pci_read_config_dword(dev, PCI_BASE_ADDRESS_2, &val);
 185         dev_info(&dev->dev, "BAR2: %#.8x\n", val);
 186         pci_read_config_dword(dev, PCI_BASE_ADDRESS_3, &val);
 187         dev_info(&dev->dev, "BAR3: %#.8x\n", val);
 188         pci_read_config_dword(dev, PCI_BASE_ADDRESS_4, &val);
 189         dev_info(&dev->dev, "BAR4: %#.8x\n", val);
 190         pci_read_config_dword(dev, PCI_BASE_ADDRESS_5, &val);
 191         dev_info(&dev->dev, "BAR5: %#.8x\n", val);
 192
 193         dev_info(&dev->dev, "p1 regs: %#llx, len: %#llx\n",
 194                 p1_base(dev), p1_size(dev));
 195         dev_info(&dev->dev, "p2 regs: %#llx, len: %#llx\n",
 196                 p2_base(dev), p2_size(dev));
 197         dev_info(&dev->dev, "BAR 4/5: %#llx, len: %#llx\n",
 198                 pci_resource_start(dev, 4), pci_resource_len(dev, 4));
 199
 200         if (!(vsec = find_cxl_vsec(dev)))
 201                 return;
 202
 203 #define show_reg(name, what) \
 204         dev_info(&dev->dev, "cxl vsec: %30s: %#x\n", name, what)
 205
 206         pci_read_config_dword(dev, vsec + 0x0, &val);
 207         show_reg("Cap ID", (val >> 0) & 0xffff);
 208         show_reg("Cap Ver", (val >> 16) & 0xf);
 209         show_reg("Next Cap Ptr", (val >> 20) & 0xfff);
 210         pci_read_config_dword(dev, vsec + 0x4, &val);
 211         show_reg("VSEC ID", (val >> 0) & 0xffff);
 212         show_reg("VSEC Rev", (val >> 16) & 0xf);
 213         show_reg("VSEC Length", (val >> 20) & 0xfff);
 214         pci_read_config_dword(dev, vsec + 0x8, &val);
 215         show_reg("Num AFUs", (val >> 0) & 0xff);
 216         show_reg("Status", (val >> 8) & 0xff);
 217         show_reg("Mode Control", (val >> 16) & 0xff);
 218         show_reg("Reserved", (val >> 24) & 0xff);
 219         pci_read_config_dword(dev, vsec + 0xc, &val);
 220         show_reg("PSL Rev", (val >> 0) & 0xffff);
 221         show_reg("CAIA Ver", (val >> 16) & 0xffff);
 222         pci_read_config_dword(dev, vsec + 0x10, &val);
 223         show_reg("Base Image Rev", (val >> 0) & 0xffff);
 224         show_reg("Reserved", (val >> 16) & 0x0fff);
 225         show_reg("Image Control", (val >> 28) & 0x3);
 226         show_reg("Reserved", (val >> 30) & 0x1);
 227         show_reg("Image Loaded", (val >> 31) & 0x1);
 228
 229         pci_read_config_dword(dev, vsec + 0x14, &val);
 230         show_reg("Reserved", val);
 231         pci_read_config_dword(dev, vsec + 0x18, &val);
 232         show_reg("Reserved", val);
 233         pci_read_config_dword(dev, vsec + 0x1c, &val);
 234         show_reg("Reserved", val);
 235
 236         pci_read_config_dword(dev, vsec + 0x20, &val);
 237         show_reg("AFU Descriptor Offset", val);
 238         pci_read_config_dword(dev, vsec + 0x24, &val);
 239         show_reg("AFU Descriptor Size", val);
 240         pci_read_config_dword(dev, vsec + 0x28, &val);
 241         show_reg("Problem State Offset", val);
 242         pci_read_config_dword(dev, vsec + 0x2c, &val);
 243         show_reg("Problem State Size", val);
 244
 245         pci_read_config_dword(dev, vsec + 0x30, &val);
 246         show_reg("Reserved", val);
 247         pci_read_config_dword(dev, vsec + 0x34, &val);
 248         show_reg("Reserved", val);
 249         pci_read_config_dword(dev, vsec + 0x38, &val);
 250         show_reg("Reserved", val);
 251         pci_read_config_dword(dev, vsec + 0x3c, &val);
 252         show_reg("Reserved", val);
 253
 254         pci_read_config_dword(dev, vsec + 0x40, &val);
 255         show_reg("PSL Programming Port", val);
 256         pci_read_config_dword(dev, vsec + 0x44, &val);
 257         show_reg("PSL Programming Control", val);
 258
 259         pci_read_config_dword(dev, vsec + 0x48, &val);
 260         show_reg("Reserved", val);
 261         pci_read_config_dword(dev, vsec + 0x4c, &val);
 262         show_reg("Reserved", val);
 263
 264         pci_read_config_dword(dev, vsec + 0x50, &val);
 265         show_reg("Flash Address Register", val);
 266         pci_read_config_dword(dev, vsec + 0x54, &val);
 267         show_reg("Flash Size Register", val);
 268         pci_read_config_dword(dev, vsec + 0x58, &val);
 269         show_reg("Flash Status/Control Register", val);
 270         pci_read_config_dword(dev, vsec + 0x58, &val);
 271         show_reg("Flash Data Port", val);
 272
 273 #undef show_reg
 274 }
 275
 276 static void dump_afu_descriptor(struct cxl_afu *afu)
 277 {
 278         u64 val, afu_cr_num, afu_cr_off, afu_cr_len;
 279         int i;
 280
 281 #define show_reg(name, what) \
 282         dev_info(&afu->dev, "afu desc: %30s: %#llx\n", name, what)
 283
 284         val = AFUD_READ_INFO(afu);
 285         show_reg("num_ints_per_process", AFUD_NUM_INTS_PER_PROC(val));
 286         show_reg("num_of_processes", AFUD_NUM_PROCS(val));
 287         show_reg("num_of_afu_CRs", AFUD_NUM_CRS(val));
 288         show_reg("req_prog_mode", val & 0xffffULL);
 289         afu_cr_num = AFUD_NUM_CRS(val);
 290
 291         val = AFUD_READ(afu, 0x8);
 292         show_reg("Reserved", val);
 293         val = AFUD_READ(afu, 0x10);
 294         show_reg("Reserved", val);
 295         val = AFUD_READ(afu, 0x18);
 296         show_reg("Reserved", val);
 297
 298         val = AFUD_READ_CR(afu);
 299         show_reg("Reserved", (val >> (63-7)) & 0xff);
 300         show_reg("AFU_CR_len", AFUD_CR_LEN(val));
 301         afu_cr_len = AFUD_CR_LEN(val) * 256;
 302
 303         val = AFUD_READ_CR_OFF(afu);
 304         afu_cr_off = val;
 305         show_reg("AFU_CR_offset", val);
 306
 307         val = AFUD_READ_PPPSA(afu);
 308         show_reg("PerProcessPSA_control", (val >> (63-7)) & 0xff);
 309         show_reg("PerProcessPSA Length", AFUD_PPPSA_LEN(val));
 310
 311         val = AFUD_READ_PPPSA_OFF(afu);
 312         show_reg("PerProcessPSA_offset", val);
 313
 314         val = AFUD_READ_EB(afu);
 315         show_reg("Reserved", (val >> (63-7)) & 0xff);
 316         show_reg("AFU_EB_len", AFUD_EB_LEN(val));
 317
 318         val = AFUD_READ_EB_OFF(afu);
 319         show_reg("AFU_EB_offset", val);
 320
 321         for (i = 0; i < afu_cr_num; i++) {
 322                 val = AFUD_READ_LE(afu, afu_cr_off + i * afu_cr_len);
 323                 show_reg("CR Vendor", val & 0xffff);
 324                 show_reg("CR Device", (val >> 16) & 0xffff);
 325         }
 326 #undef show_reg
 327 }
 328
 329 #define P8_CAPP_UNIT0_ID 0xBA
 330 #define P8_CAPP_UNIT1_ID 0XBE
 331 #define P9_CAPP_UNIT0_ID 0xC0
 332 #define P9_CAPP_UNIT1_ID 0xE0
 333
 334 static int get_phb_index(struct device_node *np, u32 *phb_index)
 335 {
 336         if (of_property_read_u32(np, "ibm,phb-index", phb_index))
 337                 return -ENODEV;
 338         return 0;
 339 }
 340
 341 static u64 get_capp_unit_id(struct device_node *np, u32 phb_index)
 342 {
 343         /*
 344          * POWER 8:
 345          *  - For chips other than POWER8NVL, we only have CAPP 0,
 346          *    irrespective of which PHB is used.
 347          *  - For POWER8NVL, assume CAPP 0 is attached to PHB0 and
 348          *    CAPP 1 is attached to PHB1.
 349          */
 350         if (cxl_is_power8()) {
 351                 if (!pvr_version_is(PVR_POWER8NVL))
 352                         return P8_CAPP_UNIT0_ID;
 353
 354                 if (phb_index == 0)
 355                         return P8_CAPP_UNIT0_ID;
 356
 357                 if (phb_index == 1)
 358                         return P8_CAPP_UNIT1_ID;
 359         }
 360
 361         /*
 362          * POWER 9:
 363          *   PEC0 (PHB0). Capp ID = CAPP0 (0b1100_0000)
 364          *   PEC1 (PHB1 - PHB2). No capi mode
 365          *   PEC2 (PHB3 - PHB4 - PHB5): Capi mode on PHB3 only. Capp ID = CAPP1 (0b1110_0000)
 366          */
 367         if (cxl_is_power9()) {
 368                 if (phb_index == 0)
 369                         return P9_CAPP_UNIT0_ID;
 370
 371                 if (phb_index == 3)
 372                         return P9_CAPP_UNIT1_ID;
 373         }
 374
 375         return 0;
 376 }
 377
 378 int cxl_calc_capp_routing(struct pci_dev *dev, u64 *chipid,
 379                              u32 *phb_index, u64 *capp_unit_id)
 380 {
 381         int rc;
 382         struct device_node *np;
 383         const __be32 *prop;
 384
 385         if (!(np = pnv_pci_get_phb_node(dev)))
 386                 return -ENODEV;
 387
 388         while (np && !(prop = of_get_property(np, "ibm,chip-id", NULL)))
 389                 np = of_get_next_parent(np);
 390         if (!np)
 391                 return -ENODEV;
 392
 393         *chipid = be32_to_cpup(prop);
 394
 395         rc = get_phb_index(np, phb_index);
 396         if (rc) {
 397                 pr_err("cxl: invalid phb index\n");
 398                 of_node_put(np);
 399                 return rc;
 400         }
 401
 402         *capp_unit_id = get_capp_unit_id(np, *phb_index);
 403         of_node_put(np);
 404         if (!*capp_unit_id) {
 405                 pr_err("cxl: invalid capp unit id\n");
 406                 return -ENODEV;
 407         }
 408
 409         return 0;
 410 }
 411
 412 int cxl_get_xsl9_dsnctl(u64 capp_unit_id, u64 *reg)
 413 {
 414         u64 xsl_dsnctl;
 415
 416         /*
 417          * CAPI Identifier bits [0:7]
 418          * bit 61:60 MSI bits --> 0
 419          * bit 59 TVT selector --> 0
 420          */
 421
 422         /*
 423          * Tell XSL where to route data to.
 424          * The field chipid should match the PHB CAPI_CMPM register
 425          */
 426         xsl_dsnctl = ((u64)0x2 << (63-7)); /* Bit 57 */
 427         xsl_dsnctl |= (capp_unit_id << (63-15));
 428
 429         /* nMMU_ID Defaults to: b’000001001’*/
 430         xsl_dsnctl |= ((u64)0x09 << (63-28));
 431
 432         if (!(cxl_is_power9_dd1())) {
 433                 /*
 434                  * Used to identify CAPI packets which should be sorted into
 435                  * the Non-Blocking queues by the PHB. This field should match
 436                  * the PHB PBL_NBW_CMPM register
 437                  * nbwind=0x03, bits [57:58], must include capi indicator.
 438                  * Not supported on P9 DD1.
 439                  */
 440                 xsl_dsnctl |= ((u64)0x03 << (63-47));
 441
 442                 /*
 443                  * Upper 16b address bits of ASB_Notify messages sent to the
 444                  * system. Need to match the PHB’s ASN Compare/Mask Register.
 445                  * Not supported on P9 DD1.
 446                  */
 447                 xsl_dsnctl |= ((u64)0x04 << (63-55));
 448         }
 449
 450         *reg = xsl_dsnctl;
 451         return 0;
 452 }
 453
 454 static int init_implementation_adapter_regs_psl9(struct cxl *adapter,
 455                                                  struct pci_dev *dev)
 456 {
 457         u64 xsl_dsnctl, psl_fircntl;
 458         u64 chipid;
 459         u32 phb_index;
 460         u64 capp_unit_id;
 461         u64 psl_debug;
 462         int rc;
 463
 464         rc = cxl_calc_capp_routing(dev, &chipid, &phb_index, &capp_unit_id);
 465         if (rc)
 466                 return rc;
 467
 468         rc = cxl_get_xsl9_dsnctl(capp_unit_id, &xsl_dsnctl);
 469         if (rc)
 470                 return rc;
 471
 472         cxl_p1_write(adapter, CXL_XSL9_DSNCTL, xsl_dsnctl);
 473
 474         /* Set fir_cntl to recommended value for production env */
 475         psl_fircntl = (0x2ULL << (63-3)); /* ce_report */
 476         psl_fircntl |= (0x1ULL << (63-6)); /* FIR_report */
 477         psl_fircntl |= 0x1ULL; /* ce_thresh */
 478         cxl_p1_write(adapter, CXL_PSL9_FIR_CNTL, psl_fircntl);
 479
 480         /* vccredits=0x1  pcklat=0x4 */
 481         cxl_p1_write(adapter, CXL_PSL9_DSNDCTL, 0x0000000000001810ULL);
 482
 483         /*
 484          * For debugging with trace arrays.
 485          * Configure RX trace 0 segmented mode.
 486          * Configure CT trace 0 segmented mode.
 487          * Configure LA0 trace 0 segmented mode.
 488          * Configure LA1 trace 0 segmented mode.
 489          */
 490         cxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8040800080000000ULL);
 491         cxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8040800080000003ULL);
 492         cxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8040800080000005ULL);
 493         cxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8040800080000006ULL);
 494
 495         /*
 496          * A response to an ASB_Notify request is returned by the
 497          * system as an MMIO write to the address defined in
 498          * the PSL_TNR_ADDR register
 499          */
 500         /* PSL_TNR_ADDR */
 501
 502         /* NORST */
 503         cxl_p1_write(adapter, CXL_PSL9_DEBUG, 0x8000000000000000ULL);
 504
 505         /* allocate the apc machines */
 506         cxl_p1_write(adapter, CXL_PSL9_APCDEDTYPE, 0x40000003FFFF0000ULL);
 507
 508         /* Disable vc dd1 fix */
 509         if (cxl_is_power9_dd1())
 510                 cxl_p1_write(adapter, CXL_PSL9_GP_CT, 0x0400000000000001ULL);
 511
 512         /*
 513          * Check if PSL has data-cache. We need to flush adapter datacache
 514          * when as its about to be removed.
 515          */
 516         psl_debug = cxl_p1_read(adapter, CXL_PSL9_DEBUG);
 517         if (psl_debug & CXL_PSL_DEBUG_CDC) {
 518                 dev_dbg(&dev->dev, "No data-cache present\n");
 519                 adapter->native->no_data_cache = true;
 520         }
 521
 522         return 0;
 523 }
 524
 525 static int init_implementation_adapter_regs_psl8(struct cxl *adapter, struct pci_dev *dev)
 526 {
 527         u64 psl_dsnctl, psl_fircntl;
 528         u64 chipid;
 529         u32 phb_index;
 530         u64 capp_unit_id;
 531         int rc;
 532
 533         rc = cxl_calc_capp_routing(dev, &chipid, &phb_index, &capp_unit_id);
 534         if (rc)
 535                 return rc;
 536
 537         psl_dsnctl = 0x0000900000000000ULL; /* pteupd ttype, scdone */
 538         psl_dsnctl |= (0x2ULL << (63-38)); /* MMIO hang pulse: 256 us */
 539         /* Tell PSL where to route data to */
 540         psl_dsnctl |= (chipid << (63-5));
 541         psl_dsnctl |= (capp_unit_id << (63-13));
 542
 543         cxl_p1_write(adapter, CXL_PSL_DSNDCTL, psl_dsnctl);
 544         cxl_p1_write(adapter, CXL_PSL_RESLCKTO, 0x20000000200ULL);
 545         /* snoop write mask */
 546         cxl_p1_write(adapter, CXL_PSL_SNWRALLOC, 0x00000000FFFFFFFFULL);
 547         /* set fir_cntl to recommended value for production env */
 548         psl_fircntl = (0x2ULL << (63-3)); /* ce_report */
 549         psl_fircntl |= (0x1ULL << (63-6)); /* FIR_report */
 550         psl_fircntl |= 0x1ULL; /* ce_thresh */
 551         cxl_p1_write(adapter, CXL_PSL_FIR_CNTL, psl_fircntl);
 552         /* for debugging with trace arrays */
 553         cxl_p1_write(adapter, CXL_PSL_TRACE, 0x0000FF7C00000000ULL);
 554
 555         return 0;
 556 }
 557
 558 static int init_implementation_adapter_regs_xsl(struct cxl *adapter, struct pci_dev *dev)
 559 {
 560         u64 xsl_dsnctl;
 561         u64 chipid;
 562         u32 phb_index;
 563         u64 capp_unit_id;
 564         int rc;
 565
 566         rc = cxl_calc_capp_routing(dev, &chipid, &phb_index, &capp_unit_id);
 567         if (rc)
 568                 return rc;
 569
 570         /* Tell XSL where to route data to */
 571         xsl_dsnctl = 0x0000600000000000ULL | (chipid << (63-5));
 572         xsl_dsnctl |= (capp_unit_id << (63-13));
 573         cxl_p1_write(adapter, CXL_XSL_DSNCTL, xsl_dsnctl);
 574
 575         return 0;
 576 }
 577
 578 /* PSL & XSL */
 579 #define TBSYNC_CAL(n) (((u64)n & 0x7) << (63-3))
 580 #define TBSYNC_CNT(n) (((u64)n & 0x7) << (63-6))
 581 /* For the PSL this is a multiple for 0 < n <= 7: */
 582 #define PSL_2048_250MHZ_CYCLES 1
 583
 584 static void write_timebase_ctrl_psl9(struct cxl *adapter)
 585 {
 586         cxl_p1_write(adapter, CXL_PSL9_TB_CTLSTAT,
 587                      TBSYNC_CNT(2 * PSL_2048_250MHZ_CYCLES));
 588 }
 589
 590 static void write_timebase_ctrl_psl8(struct cxl *adapter)
 591 {
 592         cxl_p1_write(adapter, CXL_PSL_TB_CTLSTAT,
 593                      TBSYNC_CNT(2 * PSL_2048_250MHZ_CYCLES));
 594 }
 595
 596 /* XSL */
 597 #define TBSYNC_ENA (1ULL << 63)
 598 /* For the XSL this is 2**n * 2000 clocks for 0 < n <= 6: */
 599 #define XSL_2000_CLOCKS 1
 600 #define XSL_4000_CLOCKS 2
 601 #define XSL_8000_CLOCKS 3
 602
 603 static void write_timebase_ctrl_xsl(struct cxl *adapter)
 604 {
 605         cxl_p1_write(adapter, CXL_XSL_TB_CTLSTAT,
 606                      TBSYNC_ENA |
 607                      TBSYNC_CAL(3) |
 608                      TBSYNC_CNT(XSL_4000_CLOCKS));
 609 }
 610
 611 static u64 timebase_read_psl9(struct cxl *adapter)
 612 {
 613         return cxl_p1_read(adapter, CXL_PSL9_Timebase);
 614 }
 615
 616 static u64 timebase_read_psl8(struct cxl *adapter)
 617 {
 618         return cxl_p1_read(adapter, CXL_PSL_Timebase);
 619 }
 620
 621 static u64 timebase_read_xsl(struct cxl *adapter)
 622 {
 623         return cxl_p1_read(adapter, CXL_XSL_Timebase);
 624 }
 625
 626 static void cxl_setup_psl_timebase(struct cxl *adapter, struct pci_dev *dev)
 627 {
 628         u64 psl_tb;
 629         int delta;
 630         unsigned int retry = 0;
 631         struct device_node *np;
 632
 633         adapter->psl_timebase_synced = false;
 634
 635         if (!(np = pnv_pci_get_phb_node(dev)))
 636                 return;
 637
 638         /* Do not fail when CAPP timebase sync is not supported by OPAL */
 639         of_node_get(np);
 640         if (! of_get_property(np, "ibm,capp-timebase-sync", NULL)) {
 641                 of_node_put(np);
 642                 dev_info(&dev->dev, "PSL timebase inactive: OPAL support missing\n");
 643                 return;
 644         }
 645         of_node_put(np);
 646
 647         /*
 648          * Setup PSL Timebase Control and Status register
 649          * with the recommended Timebase Sync Count value
 650          */
 651         adapter->native->sl_ops->write_timebase_ctrl(adapter);
 652
 653         /* Enable PSL Timebase */
 654         cxl_p1_write(adapter, CXL_PSL_Control, 0x0000000000000000);
 655         cxl_p1_write(adapter, CXL_PSL_Control, CXL_PSL_Control_tb);
 656
 657         /* Wait until CORE TB and PSL TB difference <= 16usecs */
 658         do {
 659                 msleep(1);
 660                 if (retry++ > 5) {
 661                         dev_info(&dev->dev, "PSL timebase can't synchronize\n");
 662                         return;
 663                 }
 664                 psl_tb = adapter->native->sl_ops->timebase_read(adapter);
 665                 delta = mftb() - psl_tb;
 666                 if (delta < 0)
 667                         delta = -delta;
 668         } while (tb_to_ns(delta) > 16000);
 669
 670         adapter->psl_timebase_synced = true;
 671         return;
 672 }
 673
 674 static int init_implementation_afu_regs_psl9(struct cxl_afu *afu)
 675 {
 676         return 0;
 677 }
 678
 679 static int init_implementation_afu_regs_psl8(struct cxl_afu *afu)
 680 {
 681         /* read/write masks for this slice */
 682         cxl_p1n_write(afu, CXL_PSL_APCALLOC_A, 0xFFFFFFFEFEFEFEFEULL);
 683         /* APC read/write masks for this slice */
 684         cxl_p1n_write(afu, CXL_PSL_COALLOC_A, 0xFF000000FEFEFEFEULL);
 685         /* for debugging with trace arrays */
 686         cxl_p1n_write(afu, CXL_PSL_SLICE_TRACE, 0x0000FFFF00000000ULL);
 687         cxl_p1n_write(afu, CXL_PSL_RXCTL_A, CXL_PSL_RXCTL_AFUHP_4S);
 688
 689         return 0;
 690 }
 691
 692 int cxl_pci_setup_irq(struct cxl *adapter, unsigned int hwirq,
 693                 unsigned int virq)
 694 {
 695         struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
 696
 697         return pnv_cxl_ioda_msi_setup(dev, hwirq, virq);
 698 }
 699
 700 int cxl_update_image_control(struct cxl *adapter)
 701 {
 702         struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
 703         int rc;
 704         int vsec;
 705         u8 image_state;
 706
 707         if (!(vsec = find_cxl_vsec(dev))) {
 708                 dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n");
 709                 return -ENODEV;
 710         }
 711
 712         if ((rc = CXL_READ_VSEC_IMAGE_STATE(dev, vsec, &image_state))) {
 713                 dev_err(&dev->dev, "failed to read image state: %i\n", rc);
 714                 return rc;
 715         }
 716
 717         if (adapter->perst_loads_image)
 718                 image_state |= CXL_VSEC_PERST_LOADS_IMAGE;
 719         else
 720                 image_state &= ~CXL_VSEC_PERST_LOADS_IMAGE;
 721
 722         if (adapter->perst_select_user)
 723                 image_state |= CXL_VSEC_PERST_SELECT_USER;
 724         else
 725                 image_state &= ~CXL_VSEC_PERST_SELECT_USER;
 726
 727         if ((rc = CXL_WRITE_VSEC_IMAGE_STATE(dev, vsec, image_state))) {
 728                 dev_err(&dev->dev, "failed to update image control: %i\n", rc);
 729                 return rc;
 730         }
 731
 732         return 0;
 733 }
 734
 735 int cxl_pci_alloc_one_irq(struct cxl *adapter)
 736 {
 737         struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
 738
 739         return pnv_cxl_alloc_hwirqs(dev, 1);
 740 }
 741
 742 void cxl_pci_release_one_irq(struct cxl *adapter, int hwirq)
 743 {
 744         struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
 745
 746         return pnv_cxl_release_hwirqs(dev, hwirq, 1);
 747 }
 748
 749 int cxl_pci_alloc_irq_ranges(struct cxl_irq_ranges *irqs,
 750                         struct cxl *adapter, unsigned int num)
 751 {
 752         struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
 753
 754         return pnv_cxl_alloc_hwirq_ranges(irqs, dev, num);
 755 }
 756
 757 void cxl_pci_release_irq_ranges(struct cxl_irq_ranges *irqs,
 758                                 struct cxl *adapter)
 759 {
 760         struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
 761
 762         pnv_cxl_release_hwirq_ranges(irqs, dev);
 763 }
 764
 765 static int setup_cxl_bars(struct pci_dev *dev)
 766 {
 767         /* Safety check in case we get backported to < 3.17 without M64 */
 768         if ((p1_base(dev) < 0x100000000ULL) ||
 769             (p2_base(dev) < 0x100000000ULL)) {
 770                 dev_err(&dev->dev, "ABORTING: M32 BAR assignment incompatible with CXL\n");
 771                 return -ENODEV;
 772         }
 773
 774         /*
 775          * BAR 4/5 has a special meaning for CXL and must be programmed with a
 776          * special value corresponding to the CXL protocol address range.
 777          * For POWER 8/9 that means bits 48:49 must be set to 10
 778          */
 779         pci_write_config_dword(dev, PCI_BASE_ADDRESS_4, 0x00000000);
 780         pci_write_config_dword(dev, PCI_BASE_ADDRESS_5, 0x00020000);
 781
 782         return 0;
 783 }
 784
 785 #ifdef CONFIG_CXL_BIMODAL
 786
 787 struct cxl_switch_work {
 788         struct pci_dev *dev;
 789         struct work_struct work;
 790         int vsec;
 791         int mode;
 792 };
 793
 794 static void switch_card_to_cxl(struct work_struct *work)
 795 {
 796         struct cxl_switch_work *switch_work =
 797                 container_of(work, struct cxl_switch_work, work);
 798         struct pci_dev *dev = switch_work->dev;
 799         struct pci_bus *bus = dev->bus;
 800         struct pci_controller *hose = pci_bus_to_host(bus);
 801         struct pci_dev *bridge;
 802         struct pnv_php_slot *php_slot;
 803         unsigned int devfn;
 804         u8 val;
 805         int rc;
 806
 807         dev_info(&bus->dev, "cxl: Preparing for mode switch...\n");
 808         bridge = list_first_entry_or_null(&hose->bus->devices, struct pci_dev,
 809                                           bus_list);
 810         if (!bridge) {
 811                 dev_WARN(&bus->dev, "cxl: Couldn't find root port!\n");
 812                 goto err_dev_put;
 813         }
 814
 815         php_slot = pnv_php_find_slot(pci_device_to_OF_node(bridge));
 816         if (!php_slot) {
 817                 dev_err(&bus->dev, "cxl: Failed to find slot hotplug "
 818                                    "information. You may need to upgrade "
 819                                    "skiboot. Aborting.\n");
 820                 goto err_dev_put;
 821         }
 822
 823         rc = CXL_READ_VSEC_MODE_CONTROL(dev, switch_work->vsec, &val);
 824         if (rc) {
 825                 dev_err(&bus->dev, "cxl: Failed to read CAPI mode control: %i\n", rc);
 826                 goto err_dev_put;
 827         }
 828         devfn = dev->devfn;
 829
 830         /* Release the reference obtained in cxl_check_and_switch_mode() */
 831         pci_dev_put(dev);
 832
 833         dev_dbg(&bus->dev, "cxl: Removing PCI devices from kernel\n");
 834         pci_lock_rescan_remove();
 835         pci_hp_remove_devices(bridge->subordinate);
 836         pci_unlock_rescan_remove();
 837
 838         /* Switch the CXL protocol on the card */
 839         if (switch_work->mode == CXL_BIMODE_CXL) {
 840                 dev_info(&bus->dev, "cxl: Switching card to CXL mode\n");
 841                 val &= ~CXL_VSEC_PROTOCOL_MASK;
 842                 val |= CXL_VSEC_PROTOCOL_256TB | CXL_VSEC_PROTOCOL_ENABLE;
 843                 rc = pnv_cxl_enable_phb_kernel_api(hose, true);
 844                 if (rc) {
 845                         dev_err(&bus->dev, "cxl: Failed to enable kernel API"
 846                                            " on real PHB, aborting\n");
 847                         goto err_free_work;
 848                 }
 849         } else {
 850                 dev_WARN(&bus->dev, "cxl: Switching card to PCI mode not supported!\n");
 851                 goto err_free_work;
 852         }
 853
 854         rc = CXL_WRITE_VSEC_MODE_CONTROL_BUS(bus, devfn, switch_work->vsec, val);
 855         if (rc) {
 856                 dev_err(&bus->dev, "cxl: Failed to configure CXL protocol: %i\n", rc);
 857                 goto err_free_work;
 858         }
 859
 860         /*
 861          * The CAIA spec (v1.1, Section 10.6 Bi-modal Device Support) states
 862          * we must wait 100ms after this mode switch before touching PCIe config
 863          * space.
 864          */
 865         msleep(100);
 866
 867         /*
 868          * Hot reset to cause the card to come back in cxl mode. A
 869          * OPAL_RESET_PCI_LINK would be sufficient, but currently lacks support
 870          * in skiboot, so we use a hot reset instead.
 871          *
 872          * We call pci_set_pcie_reset_state() on the bridge, as a CAPI card is
 873          * guaranteed to sit directly under the root port, and setting the reset
 874          * state on a device directly under the root port is equivalent to doing
 875          * it on the root port iself.
 876          */
 877         dev_info(&bus->dev, "cxl: Configuration write complete, resetting card\n");
 878         pci_set_pcie_reset_state(bridge, pcie_hot_reset);
 879         pci_set_pcie_reset_state(bridge, pcie_deassert_reset);
 880
 881         dev_dbg(&bus->dev, "cxl: Offlining slot\n");
 882         rc = pnv_php_set_slot_power_state(&php_slot->slot, OPAL_PCI_SLOT_OFFLINE);
 883         if (rc) {
 884                 dev_err(&bus->dev, "cxl: OPAL offlining call failed: %i\n", rc);
 885                 goto err_free_work;
 886         }
 887
 888         dev_dbg(&bus->dev, "cxl: Onlining and probing slot\n");
 889         rc = pnv_php_set_slot_power_state(&php_slot->slot, OPAL_PCI_SLOT_ONLINE);
 890         if (rc) {
 891                 dev_err(&bus->dev, "cxl: OPAL onlining call failed: %i\n", rc);
 892                 goto err_free_work;
 893         }
 894
 895         pci_lock_rescan_remove();
 896         pci_hp_add_devices(bridge->subordinate);
 897         pci_unlock_rescan_remove();
 898
 899         dev_info(&bus->dev, "cxl: CAPI mode switch completed\n");
 900         kfree(switch_work);
 901         return;
 902
 903 err_dev_put:
 904         /* Release the reference obtained in cxl_check_and_switch_mode() */
 905         pci_dev_put(dev);
 906 err_free_work:
 907         kfree(switch_work);
 908 }
 909
 910 int cxl_check_and_switch_mode(struct pci_dev *dev, int mode, int vsec)
 911 {
 912         struct cxl_switch_work *work;
 913         u8 val;
 914         int rc;
 915
 916         if (!cpu_has_feature(CPU_FTR_HVMODE))
 917                 return -ENODEV;
 918
 919         if (!vsec) {
 920                 vsec = find_cxl_vsec(dev);
 921                 if (!vsec) {
 922                         dev_info(&dev->dev, "CXL VSEC not found\n");
 923                         return -ENODEV;
 924                 }
 925         }
 926
 927         rc = CXL_READ_VSEC_MODE_CONTROL(dev, vsec, &val);
 928         if (rc) {
 929                 dev_err(&dev->dev, "Failed to read current mode control: %i", rc);
 930                 return rc;
 931         }
 932
 933         if (mode == CXL_BIMODE_PCI) {
 934                 if (!(val & CXL_VSEC_PROTOCOL_ENABLE)) {
 935                         dev_info(&dev->dev, "Card is already in PCI mode\n");
 936                         return 0;
 937                 }
 938                 /*
 939                  * TODO: Before it's safe to switch the card back to PCI mode
 940                  * we need to disable the CAPP and make sure any cachelines the
 941                  * card holds have been flushed out. Needs skiboot support.
 942                  */
 943                 dev_WARN(&dev->dev, "CXL mode switch to PCI unsupported!\n");
 944                 return -EIO;
 945         }
 946
 947         if (val & CXL_VSEC_PROTOCOL_ENABLE) {
 948                 dev_info(&dev->dev, "Card is already in CXL mode\n");
 949                 return 0;
 950         }
 951
 952         dev_info(&dev->dev, "Card is in PCI mode, scheduling kernel thread "
 953                             "to switch to CXL mode\n");
 954
 955         work = kmalloc(sizeof(struct cxl_switch_work), GFP_KERNEL);
 956         if (!work)
 957                 return -ENOMEM;
 958
 959         pci_dev_get(dev);
 960         work->dev = dev;
 961         work->vsec = vsec;
 962         work->mode = mode;
 963         INIT_WORK(&work->work, switch_card_to_cxl);
 964
 965         schedule_work(&work->work);
 966
 967         /*
 968          * We return a failure now to abort the driver init. Once the
 969          * link has been cycled and the card is in cxl mode we will
 970          * come back (possibly using the generic cxl driver), but
 971          * return success as the card should then be in cxl mode.
 972          *
 973          * TODO: What if the card comes back in PCI mode even after
 974          *       the switch?  Don't want to spin endlessly.
 975          */
 976         return -EBUSY;
 977 }
 978 EXPORT_SYMBOL_GPL(cxl_check_and_switch_mode);
 979
 980 #endif /* CONFIG_CXL_BIMODAL */
 981
 982 static int setup_cxl_protocol_area(struct pci_dev *dev)
 983 {
 984         u8 val;
 985         int rc;
 986         int vsec = find_cxl_vsec(dev);
 987
 988         if (!vsec) {
 989                 dev_info(&dev->dev, "CXL VSEC not found\n");
 990                 return -ENODEV;
 991         }
 992
 993         rc = CXL_READ_VSEC_MODE_CONTROL(dev, vsec, &val);
 994         if (rc) {
 995                 dev_err(&dev->dev, "Failed to read current mode control: %i\n", rc);
 996                 return rc;
 997         }
 998
 999         if (!(val & CXL_VSEC_PROTOCOL_ENABLE)) {
1000                 dev_err(&dev->dev, "Card not in CAPI mode!\n");
1001                 return -EIO;
1002         }
1003
1004         if ((val & CXL_VSEC_PROTOCOL_MASK) != CXL_VSEC_PROTOCOL_256TB) {
1005                 val &= ~CXL_VSEC_PROTOCOL_MASK;
1006                 val |= CXL_VSEC_PROTOCOL_256TB;
1007                 rc = CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val);
1008                 if (rc) {
1009                         dev_err(&dev->dev, "Failed to set CXL protocol area: %i\n", rc);
1010                         return rc;
1011                 }
1012         }
1013
1014         return 0;
1015 }
1016
1017 static int pci_map_slice_regs(struct cxl_afu *afu, struct cxl *adapter, struct pci_dev *dev)
1018 {
1019         u64 p1n_base, p2n_base, afu_desc;
1020         const u64 p1n_size = 0x100;
1021         const u64 p2n_size = 0x1000;
1022
1023         p1n_base = p1_base(dev) + 0x10000 + (afu->slice * p1n_size);
1024         p2n_base = p2_base(dev) + (afu->slice * p2n_size);
1025         afu->psn_phys = p2_base(dev) + (adapter->native->ps_off + (afu->slice * adapter->ps_size));
1026         afu_desc = p2_base(dev) + adapter->native->afu_desc_off + (afu->slice * adapter->native->afu_desc_size);
1027
1028         if (!(afu->native->p1n_mmio = ioremap(p1n_base, p1n_size)))
1029                 goto err;
1030         if (!(afu->p2n_mmio = ioremap(p2n_base, p2n_size)))
1031                 goto err1;
1032         if (afu_desc) {
1033                 if (!(afu->native->afu_desc_mmio = ioremap(afu_desc, adapter->native->afu_desc_size)))
1034                         goto err2;
1035         }
1036
1037         return 0;
1038 err2:
1039         iounmap(afu->p2n_mmio);
1040 err1:
1041         iounmap(afu->native->p1n_mmio);
1042 err:
1043         dev_err(&afu->dev, "Error mapping AFU MMIO regions\n");
1044         return -ENOMEM;
1045 }
1046
1047 static void pci_unmap_slice_regs(struct cxl_afu *afu)
1048 {
1049         if (afu->p2n_mmio) {
1050                 iounmap(afu->p2n_mmio);
1051                 afu->p2n_mmio = NULL;
1052         }
1053         if (afu->native->p1n_mmio) {
1054                 iounmap(afu->native->p1n_mmio);
1055                 afu->native->p1n_mmio = NULL;
1056         }
1057         if (afu->native->afu_desc_mmio) {
1058                 iounmap(afu->native->afu_desc_mmio);
1059                 afu->native->afu_desc_mmio = NULL;
1060         }
1061 }
1062
1063 void cxl_pci_release_afu(struct device *dev)
1064 {
1065         struct cxl_afu *afu = to_cxl_afu(dev);
1066
1067         pr_devel("%s\n", __func__);
1068
1069         idr_destroy(&afu->contexts_idr);
1070         cxl_release_spa(afu);
1071
1072         kfree(afu->native);
1073         kfree(afu);
1074 }
1075
1076 /* Expects AFU struct to have recently been zeroed out */
1077 static int cxl_read_afu_descriptor(struct cxl_afu *afu)
1078 {
1079         u64 val;
1080
1081         val = AFUD_READ_INFO(afu);
1082         afu->pp_irqs = AFUD_NUM_INTS_PER_PROC(val);
1083         afu->max_procs_virtualised = AFUD_NUM_PROCS(val);
1084         afu->crs_num = AFUD_NUM_CRS(val);
1085
1086         if (AFUD_AFU_DIRECTED(val))
1087                 afu->modes_supported |= CXL_MODE_DIRECTED;
1088         if (AFUD_DEDICATED_PROCESS(val))
1089                 afu->modes_supported |= CXL_MODE_DEDICATED;
1090         if (AFUD_TIME_SLICED(val))
1091                 afu->modes_supported |= CXL_MODE_TIME_SLICED;
1092
1093         val = AFUD_READ_PPPSA(afu);
1094         afu->pp_size = AFUD_PPPSA_LEN(val) * 4096;
1095         afu->psa = AFUD_PPPSA_PSA(val);
1096         if ((afu->pp_psa = AFUD_PPPSA_PP(val)))
1097                 afu->native->pp_offset = AFUD_READ_PPPSA_OFF(afu);
1098
1099         val = AFUD_READ_CR(afu);
1100         afu->crs_len = AFUD_CR_LEN(val) * 256;
1101         afu->crs_offset = AFUD_READ_CR_OFF(afu);
1102
1103
1104         /* eb_len is in multiple of 4K */
1105         afu->eb_len = AFUD_EB_LEN(AFUD_READ_EB(afu)) * 4096;
1106         afu->eb_offset = AFUD_READ_EB_OFF(afu);
1107
1108         /* eb_off is 4K aligned so lower 12 bits are always zero */
1109         if (EXTRACT_PPC_BITS(afu->eb_offset, 0, 11) != 0) {
1110                 dev_warn(&afu->dev,
1111                          "Invalid AFU error buffer offset %Lx\n",
1112                          afu->eb_offset);
1113                 dev_info(&afu->dev,
1114                          "Ignoring AFU error buffer in the descriptor\n");
1115                 /* indicate that no afu buffer exists */
1116                 afu->eb_len = 0;
1117         }
1118
1119         return 0;
1120 }
1121
1122 static int cxl_afu_descriptor_looks_ok(struct cxl_afu *afu)
1123 {
1124         int i, rc;
1125         u32 val;
1126
1127         if (afu->psa && afu->adapter->ps_size <
1128                         (afu->native->pp_offset + afu->pp_size*afu->max_procs_virtualised)) {
1129                 dev_err(&afu->dev, "per-process PSA can't fit inside the PSA!\n");
1130                 return -ENODEV;
1131         }
1132
1133         if (afu->pp_psa && (afu->pp_size < PAGE_SIZE))
1134                 dev_warn(&afu->dev, "AFU uses pp_size(%#016llx) < PAGE_SIZE per-process PSA!\n", afu->pp_size);
1135
1136         for (i = 0; i < afu->crs_num; i++) {
1137                 rc = cxl_ops->afu_cr_read32(afu, i, 0, &val);
1138                 if (rc || val == 0) {
1139                         dev_err(&afu->dev, "ABORTING: AFU configuration record %i is invalid\n", i);
1140                         return -EINVAL;
1141                 }
1142         }
1143
1144         if ((afu->modes_supported & ~CXL_MODE_DEDICATED) && afu->max_procs_virtualised == 0) {
1145                 /*
1146                  * We could also check this for the dedicated process model
1147                  * since the architecture indicates it should be set to 1, but
1148                  * in that case we ignore the value and I'd rather not risk
1149                  * breaking any existing dedicated process AFUs that left it as
1150                  * 0 (not that I'm aware of any). It is clearly an error for an
1151                  * AFU directed AFU to set this to 0, and would have previously
1152                  * triggered a bug resulting in the maximum not being enforced
1153                  * at all since idr_alloc treats 0 as no maximum.
1154                  */
1155                 dev_err(&afu->dev, "AFU does not support any processes\n");
1156                 return -EINVAL;
1157         }
1158
1159         return 0;
1160 }
1161
1162 static int sanitise_afu_regs_psl9(struct cxl_afu *afu)
1163 {
1164         u64 reg;
1165
1166         /*
1167          * Clear out any regs that contain either an IVTE or address or may be
1168          * waiting on an acknowledgment to try to be a bit safer as we bring
1169          * it online
1170          */
1171         reg = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
1172         if ((reg & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) {
1173                 dev_warn(&afu->dev, "WARNING: AFU was not disabled: %#016llx\n", reg);
1174                 if (cxl_ops->afu_reset(afu))
1175                         return -EIO;
1176                 if (cxl_afu_disable(afu))
1177                         return -EIO;
1178                 if (cxl_psl_purge(afu))
1179                         return -EIO;
1180         }
1181         cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0x0000000000000000);
1182         cxl_p1n_write(afu, CXL_PSL_AMBAR_An, 0x0000000000000000);
1183         reg = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
1184         if (reg) {
1185                 dev_warn(&afu->dev, "AFU had pending DSISR: %#016llx\n", reg);
1186                 if (reg & CXL_PSL9_DSISR_An_TF)
1187                         cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);
1188                 else
1189                         cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A);
1190         }
1191         if (afu->adapter->native->sl_ops->register_serr_irq) {
1192                 reg = cxl_p1n_read(afu, CXL_PSL_SERR_An);
1193                 if (reg) {
1194                         if (reg & ~0x000000007fffffff)
1195                                 dev_warn(&afu->dev, "AFU had pending SERR: %#016llx\n", reg);
1196                         cxl_p1n_write(afu, CXL_PSL_SERR_An, reg & ~0xffff);
1197                 }
1198         }
1199         reg = cxl_p2n_read(afu, CXL_PSL_ErrStat_An);
1200         if (reg) {
1201                 dev_warn(&afu->dev, "AFU had pending error status: %#016llx\n", reg);
1202                 cxl_p2n_write(afu, CXL_PSL_ErrStat_An, reg);
1203         }
1204
1205         return 0;
1206 }
1207
1208 static int sanitise_afu_regs_psl8(struct cxl_afu *afu)
1209 {
1210         u64 reg;
1211
1212         /*
1213          * Clear out any regs that contain either an IVTE or address or may be
1214          * waiting on an acknowledgement to try to be a bit safer as we bring
1215          * it online
1216          */
1217         reg = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
1218         if ((reg & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) {
1219                 dev_warn(&afu->dev, "WARNING: AFU was not disabled: %#016llx\n", reg);
1220                 if (cxl_ops->afu_reset(afu))
1221                         return -EIO;
1222                 if (cxl_afu_disable(afu))
1223                         return -EIO;
1224                 if (cxl_psl_purge(afu))
1225                         return -EIO;
1226         }
1227         cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0x0000000000000000);
1228         cxl_p1n_write(afu, CXL_PSL_IVTE_Limit_An, 0x0000000000000000);
1229         cxl_p1n_write(afu, CXL_PSL_IVTE_Offset_An, 0x0000000000000000);
1230         cxl_p1n_write(afu, CXL_PSL_AMBAR_An, 0x0000000000000000);
1231         cxl_p1n_write(afu, CXL_PSL_SPOffset_An, 0x0000000000000000);
1232         cxl_p1n_write(afu, CXL_HAURP_An, 0x0000000000000000);
1233         cxl_p2n_write(afu, CXL_CSRP_An, 0x0000000000000000);
1234         cxl_p2n_write(afu, CXL_AURP1_An, 0x0000000000000000);
1235         cxl_p2n_write(afu, CXL_AURP0_An, 0x0000000000000000);
1236         cxl_p2n_write(afu, CXL_SSTP1_An, 0x0000000000000000);
1237         cxl_p2n_write(afu, CXL_SSTP0_An, 0x0000000000000000);
1238         reg = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
1239         if (reg) {
1240                 dev_warn(&afu->dev, "AFU had pending DSISR: %#016llx\n", reg);
1241                 if (reg & CXL_PSL_DSISR_TRANS)
1242                         cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);
1243                 else
1244                         cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A);
1245         }
1246         if (afu->adapter->native->sl_ops->register_serr_irq) {
1247                 reg = cxl_p1n_read(afu, CXL_PSL_SERR_An);
1248                 if (reg) {
1249                         if (reg & ~0xffff)
1250                                 dev_warn(&afu->dev, "AFU had pending SERR: %#016llx\n", reg);
1251                         cxl_p1n_write(afu, CXL_PSL_SERR_An, reg & ~0xffff);
1252                 }
1253         }
1254         reg = cxl_p2n_read(afu, CXL_PSL_ErrStat_An);
1255         if (reg) {
1256                 dev_warn(&afu->dev, "AFU had pending error status: %#016llx\n", reg);
1257                 cxl_p2n_write(afu, CXL_PSL_ErrStat_An, reg);
1258         }
1259
1260         return 0;
1261 }
1262
1263 #define ERR_BUFF_MAX_COPY_SIZE PAGE_SIZE
1264 /*
1265  * afu_eb_read:
1266  * Called from sysfs and reads the afu error info buffer. The h/w only supports
1267  * 4/8 bytes aligned access. So in case the requested offset/count arent 8 byte
1268  * aligned the function uses a bounce buffer which can be max PAGE_SIZE.
1269  */
1270 ssize_t cxl_pci_afu_read_err_buffer(struct cxl_afu *afu, char *buf,
1271                                 loff_t off, size_t count)
1272 {
1273         loff_t aligned_start, aligned_end;
1274         size_t aligned_length;
1275         void *tbuf;
1276         const void __iomem *ebuf = afu->native->afu_desc_mmio + afu->eb_offset;
1277
1278         if (count == 0 || off < 0 || (size_t)off >= afu->eb_len)
1279                 return 0;
1280
1281         /* calculate aligned read window */
1282         count = min((size_t)(afu->eb_len - off), count);
1283         aligned_start = round_down(off, 8);
1284         aligned_end = round_up(off + count, 8);
1285         aligned_length = aligned_end - aligned_start;
1286
1287         /* max we can copy in one read is PAGE_SIZE */
1288         if (aligned_length > ERR_BUFF_MAX_COPY_SIZE) {
1289                 aligned_length = ERR_BUFF_MAX_COPY_SIZE;
1290                 count = ERR_BUFF_MAX_COPY_SIZE - (off & 0x7);
1291         }
1292
1293         /* use bounce buffer for copy */
1294         tbuf = (void *)__get_free_page(GFP_KERNEL);
1295         if (!tbuf)
1296                 return -ENOMEM;
1297
1298         /* perform aligned read from the mmio region */
1299         memcpy_fromio(tbuf, ebuf + aligned_start, aligned_length);
1300         memcpy(buf, tbuf + (off & 0x7), count);
1301
1302         free_page((unsigned long)tbuf);
1303
1304         return count;
1305 }
1306
1307 static int pci_configure_afu(struct cxl_afu *afu, struct cxl *adapter, struct pci_dev *dev)
1308 {
1309         int rc;
1310
1311         if ((rc = pci_map_slice_regs(afu, adapter, dev)))
1312                 return rc;
1313
1314         if (adapter->native->sl_ops->sanitise_afu_regs) {
1315                 rc = adapter->native->sl_ops->sanitise_afu_regs(afu);
1316                 if (rc)
1317                         goto err1;
1318         }
1319
1320         /* We need to reset the AFU before we can read the AFU descriptor */
1321         if ((rc = cxl_ops->afu_reset(afu)))
1322                 goto err1;
1323
1324         if (cxl_verbose)
1325                 dump_afu_descriptor(afu);
1326
1327         if ((rc = cxl_read_afu_descriptor(afu)))
1328                 goto err1;
1329
1330         if ((rc = cxl_afu_descriptor_looks_ok(afu)))
1331                 goto err1;
1332
1333         if (adapter->native->sl_ops->afu_regs_init)
1334                 if ((rc = adapter->native->sl_ops->afu_regs_init(afu)))
1335                         goto err1;
1336
1337         if (adapter->native->sl_ops->register_serr_irq)
1338                 if ((rc = adapter->native->sl_ops->register_serr_irq(afu)))
1339                         goto err1;
1340
1341         if ((rc = cxl_native_register_psl_irq(afu)))
1342                 goto err2;
1343
1344         atomic_set(&afu->configured_state, 0);
1345         return 0;
1346
1347 err2:
1348         if (adapter->native->sl_ops->release_serr_irq)
1349                 adapter->native->sl_ops->release_serr_irq(afu);
1350 err1:
1351         pci_unmap_slice_regs(afu);
1352         return rc;
1353 }
1354
1355 static void pci_deconfigure_afu(struct cxl_afu *afu)
1356 {
1357         /*
1358          * It's okay to deconfigure when AFU is already locked, otherwise wait
1359          * until there are no readers
1360          */
1361         if (atomic_read(&afu->configured_state) != -1) {
1362                 while (atomic_cmpxchg(&afu->configured_state, 0, -1) != -1)
1363                         schedule();
1364         }
1365         cxl_native_release_psl_irq(afu);
1366         if (afu->adapter->native->sl_ops->release_serr_irq)
1367                 afu->adapter->native->sl_ops->release_serr_irq(afu);
1368         pci_unmap_slice_regs(afu);
1369 }
1370
1371 static int pci_init_afu(struct cxl *adapter, int slice, struct pci_dev *dev)
1372 {
1373         struct cxl_afu *afu;
1374         int rc = -ENOMEM;
1375
1376         afu = cxl_alloc_afu(adapter, slice);
1377         if (!afu)
1378                 return -ENOMEM;
1379
1380         afu->native = kzalloc(sizeof(struct cxl_afu_native), GFP_KERNEL);
1381         if (!afu->native)
1382                 goto err_free_afu;
1383
1384         mutex_init(&afu->native->spa_mutex);
1385
1386         rc = dev_set_name(&afu->dev, "afu%i.%i", adapter->adapter_num, slice);
1387         if (rc)
1388                 goto err_free_native;
1389
1390         rc = pci_configure_afu(afu, adapter, dev);
1391         if (rc)
1392                 goto err_free_native;
1393
1394         /* Don't care if this fails */
1395         cxl_debugfs_afu_add(afu);
1396
1397         /*
1398          * After we call this function we must not free the afu directly, even
1399          * if it returns an error!
1400          */
1401         if ((rc = cxl_register_afu(afu)))
1402                 goto err_put_dev;
1403
1404         if ((rc = cxl_sysfs_afu_add(afu)))
1405                 goto err_del_dev;
1406
1407         adapter->afu[afu->slice] = afu;
1408
1409         if ((rc = cxl_pci_vphb_add(afu)))
1410                 dev_info(&afu->dev, "Can't register vPHB\n");
1411
1412         return 0;
1413
1414 err_del_dev:
1415         device_del(&afu->dev);
1416 err_put_dev:
1417         pci_deconfigure_afu(afu);
1418         cxl_debugfs_afu_remove(afu);
1419         put_device(&afu->dev);
1420         return rc;
1421
1422 err_free_native:
1423         kfree(afu->native);
1424 err_free_afu:
1425         kfree(afu);
1426         return rc;
1427
1428 }
1429
1430 static void cxl_pci_remove_afu(struct cxl_afu *afu)
1431 {
1432         pr_devel("%s\n", __func__);
1433
1434         if (!afu)
1435                 return;
1436
1437         cxl_pci_vphb_remove(afu);
1438         cxl_sysfs_afu_remove(afu);
1439         cxl_debugfs_afu_remove(afu);
1440
1441         spin_lock(&afu->adapter->afu_list_lock);
1442         afu->adapter->afu[afu->slice] = NULL;
1443         spin_unlock(&afu->adapter->afu_list_lock);
1444
1445         cxl_context_detach_all(afu);
1446         cxl_ops->afu_deactivate_mode(afu, afu->current_mode);
1447
1448         pci_deconfigure_afu(afu);
1449         device_unregister(&afu->dev);
1450 }
1451
1452 int cxl_pci_reset(struct cxl *adapter)
1453 {
1454         struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
1455         int rc;
1456
1457         if (adapter->perst_same_image) {
1458                 dev_warn(&dev->dev,
1459                          "cxl: refusing to reset/reflash when perst_reloads_same_image is set.\n");
1460                 return -EINVAL;
1461         }
1462
1463         dev_info(&dev->dev, "CXL reset\n");
1464
1465         /*
1466          * The adapter is about to be reset, so ignore errors.
1467          */
1468         cxl_data_cache_flush(adapter);
1469
1470         /* pcie_warm_reset requests a fundamental pci reset which includes a
1471          * PERST assert/deassert.  PERST triggers a loading of the image
1472          * if "user" or "factory" is selected in sysfs */
1473         if ((rc = pci_set_pcie_reset_state(dev, pcie_warm_reset))) {
1474                 dev_err(&dev->dev, "cxl: pcie_warm_reset failed\n");
1475                 return rc;
1476         }
1477
1478         return rc;
1479 }
1480
1481 static int cxl_map_adapter_regs(struct cxl *adapter, struct pci_dev *dev)
1482 {
1483         if (pci_request_region(dev, 2, "priv 2 regs"))
1484                 goto err1;
1485         if (pci_request_region(dev, 0, "priv 1 regs"))
1486                 goto err2;
1487
1488         pr_devel("cxl_map_adapter_regs: p1: %#016llx %#llx, p2: %#016llx %#llx",
1489                         p1_base(dev), p1_size(dev), p2_base(dev), p2_size(dev));
1490
1491         if (!(adapter->native->p1_mmio = ioremap(p1_base(dev), p1_size(dev))))
1492                 goto err3;
1493
1494         if (!(adapter->native->p2_mmio = ioremap(p2_base(dev), p2_size(dev))))
1495                 goto err4;
1496
1497         return 0;
1498
1499 err4:
1500         iounmap(adapter->native->p1_mmio);
1501         adapter->native->p1_mmio = NULL;
1502 err3:
1503         pci_release_region(dev, 0);
1504 err2:
1505         pci_release_region(dev, 2);
1506 err1:
1507         return -ENOMEM;
1508 }
1509
1510 static void cxl_unmap_adapter_regs(struct cxl *adapter)
1511 {
1512         if (adapter->native->p1_mmio) {
1513                 iounmap(adapter->native->p1_mmio);
1514                 adapter->native->p1_mmio = NULL;
1515                 pci_release_region(to_pci_dev(adapter->dev.parent), 2);
1516         }
1517         if (adapter->native->p2_mmio) {
1518                 iounmap(adapter->native->p2_mmio);
1519                 adapter->native->p2_mmio = NULL;
1520                 pci_release_region(to_pci_dev(adapter->dev.parent), 0);
1521         }
1522 }
1523
1524 static int cxl_read_vsec(struct cxl *adapter, struct pci_dev *dev)
1525 {
1526         int vsec;
1527         u32 afu_desc_off, afu_desc_size;
1528         u32 ps_off, ps_size;
1529         u16 vseclen;
1530         u8 image_state;
1531
1532         if (!(vsec = find_cxl_vsec(dev))) {
1533                 dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n");
1534                 return -ENODEV;
1535         }
1536
1537         CXL_READ_VSEC_LENGTH(dev, vsec, &vseclen);
1538         if (vseclen < CXL_VSEC_MIN_SIZE) {
1539                 dev_err(&dev->dev, "ABORTING: CXL VSEC too short\n");
1540                 return -EINVAL;
1541         }
1542
1543         CXL_READ_VSEC_STATUS(dev, vsec, &adapter->vsec_status);
1544         CXL_READ_VSEC_PSL_REVISION(dev, vsec, &adapter->psl_rev);
1545         CXL_READ_VSEC_CAIA_MAJOR(dev, vsec, &adapter->caia_major);
1546         CXL_READ_VSEC_CAIA_MINOR(dev, vsec, &adapter->caia_minor);
1547         CXL_READ_VSEC_BASE_IMAGE(dev, vsec, &adapter->base_image);
1548         CXL_READ_VSEC_IMAGE_STATE(dev, vsec, &image_state);
1549         adapter->user_image_loaded = !!(image_state & CXL_VSEC_USER_IMAGE_LOADED);
1550         adapter->perst_select_user = !!(image_state & CXL_VSEC_USER_IMAGE_LOADED);
1551         adapter->perst_loads_image = !!(image_state & CXL_VSEC_PERST_LOADS_IMAGE);
1552
1553         CXL_READ_VSEC_NAFUS(dev, vsec, &adapter->slices);
1554         CXL_READ_VSEC_AFU_DESC_OFF(dev, vsec, &afu_desc_off);
1555         CXL_READ_VSEC_AFU_DESC_SIZE(dev, vsec, &afu_desc_size);
1556         CXL_READ_VSEC_PS_OFF(dev, vsec, &ps_off);
1557         CXL_READ_VSEC_PS_SIZE(dev, vsec, &ps_size);
1558
1559         /* Convert everything to bytes, because there is NO WAY I'd look at the
1560          * code a month later and forget what units these are in ;-) */
1561         adapter->native->ps_off = ps_off * 64 * 1024;
1562         adapter->ps_size = ps_size * 64 * 1024;
1563         adapter->native->afu_desc_off = afu_desc_off * 64 * 1024;
1564         adapter->native->afu_desc_size = afu_desc_size * 64 * 1024;
1565
1566         /* Total IRQs - 1 PSL ERROR - #AFU*(1 slice error + 1 DSI) */
1567         adapter->user_irqs = pnv_cxl_get_irq_count(dev) - 1 - 2*adapter->slices;
1568
1569         return 0;
1570 }
1571
1572 /*
1573  * Workaround a PCIe Host Bridge defect on some cards, that can cause
1574  * malformed Transaction Layer Packet (TLP) errors to be erroneously
1575  * reported. Mask this error in the Uncorrectable Error Mask Register.
1576  *
1577  * The upper nibble of the PSL revision is used to distinguish between
1578  * different cards. The affected ones have it set to 0.
1579  */
1580 static void cxl_fixup_malformed_tlp(struct cxl *adapter, struct pci_dev *dev)
1581 {
1582         int aer;
1583         u32 data;
1584
1585         if (adapter->psl_rev & 0xf000)
1586                 return;
1587         if (!(aer = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR)))
1588                 return;
1589         pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, &data);
1590         if (data & PCI_ERR_UNC_MALF_TLP)
1591                 if (data & PCI_ERR_UNC_INTN)
1592                         return;
1593         data |= PCI_ERR_UNC_MALF_TLP;
1594         data |= PCI_ERR_UNC_INTN;
1595         pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, data);
1596 }
1597
1598 static bool cxl_compatible_caia_version(struct cxl *adapter)
1599 {
1600         if (cxl_is_power8() && (adapter->caia_major == 1))
1601                 return true;
1602
1603         if (cxl_is_power9() && (adapter->caia_major == 2))
1604                 return true;
1605
1606         return false;
1607 }
1608
1609 static int cxl_vsec_looks_ok(struct cxl *adapter, struct pci_dev *dev)
1610 {
1611         if (adapter->vsec_status & CXL_STATUS_SECOND_PORT)
1612                 return -EBUSY;
1613
1614         if (adapter->vsec_status & CXL_UNSUPPORTED_FEATURES) {
1615                 dev_err(&dev->dev, "ABORTING: CXL requires unsupported features\n");
1616                 return -EINVAL;
1617         }
1618
1619         if (!cxl_compatible_caia_version(adapter)) {
1620                 dev_info(&dev->dev, "Ignoring card. PSL type is not supported (caia version: %d)\n",
1621                          adapter->caia_major);
1622                 return -ENODEV;
1623         }
1624
1625         if (!adapter->slices) {
1626                 /* Once we support dynamic reprogramming we can use the card if
1627                  * it supports loadable AFUs */
1628                 dev_err(&dev->dev, "ABORTING: Device has no AFUs\n");
1629                 return -EINVAL;
1630         }
1631
1632         if (!adapter->native->afu_desc_off || !adapter->native->afu_desc_size) {
1633                 dev_err(&dev->dev, "ABORTING: VSEC shows no AFU descriptors\n");
1634                 return -EINVAL;
1635         }
1636
1637         if (adapter->ps_size > p2_size(dev) - adapter->native->ps_off) {
1638                 dev_err(&dev->dev, "ABORTING: Problem state size larger than "
1639                                    "available in BAR2: 0x%llx > 0x%llx\n",
1640                          adapter->ps_size, p2_size(dev) - adapter->native->ps_off);
1641                 return -EINVAL;
1642         }
1643
1644         return 0;
1645 }
1646
1647 ssize_t cxl_pci_read_adapter_vpd(struct cxl *adapter, void *buf, size_t len)
1648 {
1649         return pci_read_vpd(to_pci_dev(adapter->dev.parent), 0, len, buf);
1650 }
1651
1652 static void cxl_release_adapter(struct device *dev)
1653 {
1654         struct cxl *adapter = to_cxl_adapter(dev);
1655
1656         pr_devel("cxl_release_adapter\n");
1657
1658         cxl_remove_adapter_nr(adapter);
1659
1660         kfree(adapter->native);
1661         kfree(adapter);
1662 }
1663
1664 #define CXL_PSL_ErrIVTE_tberror (0x1ull << (63-31))
1665
1666 static int sanitise_adapter_regs(struct cxl *adapter)
1667 {
1668         int rc = 0;
1669
1670         /* Clear PSL tberror bit by writing 1 to it */
1671         cxl_p1_write(adapter, CXL_PSL_ErrIVTE, CXL_PSL_ErrIVTE_tberror);
1672
1673         if (adapter->native->sl_ops->invalidate_all) {
1674                 /* do not invalidate ERAT entries when not reloading on PERST */
1675                 if (cxl_is_power9() && (adapter->perst_loads_image))
1676                         return 0;
1677                 rc = adapter->native->sl_ops->invalidate_all(adapter);
1678         }
1679
1680         return rc;
1681 }
1682
1683 /* This should contain *only* operations that can safely be done in
1684  * both creation and recovery.
1685  */
1686 static int cxl_configure_adapter(struct cxl *adapter, struct pci_dev *dev)
1687 {
1688         int rc;
1689
1690         adapter->dev.parent = &dev->dev;
1691         adapter->dev.release = cxl_release_adapter;
1692         pci_set_drvdata(dev, adapter);
1693
1694         rc = pci_enable_device(dev);
1695         if (rc) {
1696                 dev_err(&dev->dev, "pci_enable_device failed: %i\n", rc);
1697                 return rc;
1698         }
1699
1700         if ((rc = cxl_read_vsec(adapter, dev)))
1701                 return rc;
1702
1703         if ((rc = cxl_vsec_looks_ok(adapter, dev)))
1704                 return rc;
1705
1706         cxl_fixup_malformed_tlp(adapter, dev);
1707
1708         if ((rc = setup_cxl_bars(dev)))
1709                 return rc;
1710
1711         if ((rc = setup_cxl_protocol_area(dev)))
1712                 return rc;
1713
1714         if ((rc = cxl_update_image_control(adapter)))
1715                 return rc;
1716
1717         if ((rc = cxl_map_adapter_regs(adapter, dev)))
1718                 return rc;
1719
1720         if ((rc = sanitise_adapter_regs(adapter)))
1721                 goto err;
1722
1723         if ((rc = adapter->native->sl_ops->adapter_regs_init(adapter, dev)))
1724                 goto err;
1725
1726         /* Required for devices using CAPP DMA mode, harmless for others */
1727         pci_set_master(dev);
1728
1729         if ((rc = pnv_phb_to_cxl_mode(dev, adapter->native->sl_ops->capi_mode)))
1730                 goto err;
1731
1732         /* If recovery happened, the last step is to turn on snooping.
1733          * In the non-recovery case this has no effect */
1734         if ((rc = pnv_phb_to_cxl_mode(dev, OPAL_PHB_CAPI_MODE_SNOOP_ON)))
1735                 goto err;
1736
1737         /* Ignore error, adapter init is not dependant on timebase sync */
1738         cxl_setup_psl_timebase(adapter, dev);
1739
1740         if ((rc = cxl_native_register_psl_err_irq(adapter)))
1741                 goto err;
1742
1743         return 0;
1744
1745 err:
1746         cxl_unmap_adapter_regs(adapter);
1747         return rc;
1748
1749 }
1750
1751 static void cxl_deconfigure_adapter(struct cxl *adapter)
1752 {
1753         struct pci_dev *pdev = to_pci_dev(adapter->dev.parent);
1754
1755         cxl_native_release_psl_err_irq(adapter);
1756         cxl_unmap_adapter_regs(adapter);
1757
1758         pci_disable_device(pdev);
1759 }
1760
1761 static const struct cxl_service_layer_ops psl9_ops = {
1762         .adapter_regs_init = init_implementation_adapter_regs_psl9,
1763         .invalidate_all = cxl_invalidate_all_psl9,
1764         .afu_regs_init = init_implementation_afu_regs_psl9,
1765         .sanitise_afu_regs = sanitise_afu_regs_psl9,
1766         .register_serr_irq = cxl_native_register_serr_irq,
1767         .release_serr_irq = cxl_native_release_serr_irq,
1768         .handle_interrupt = cxl_irq_psl9,
1769         .fail_irq = cxl_fail_irq_psl,
1770         .activate_dedicated_process = cxl_activate_dedicated_process_psl9,
1771         .attach_afu_directed = cxl_attach_afu_directed_psl9,
1772         .attach_dedicated_process = cxl_attach_dedicated_process_psl9,
1773         .update_dedicated_ivtes = cxl_update_dedicated_ivtes_psl9,
1774         .debugfs_add_adapter_regs = cxl_debugfs_add_adapter_regs_psl9,
1775         .debugfs_add_afu_regs = cxl_debugfs_add_afu_regs_psl9,
1776         .psl_irq_dump_registers = cxl_native_irq_dump_regs_psl9,
1777         .debugfs_stop_trace = cxl_stop_trace_psl9,
1778         .write_timebase_ctrl = write_timebase_ctrl_psl9,
1779         .timebase_read = timebase_read_psl9,
1780         .capi_mode = OPAL_PHB_CAPI_MODE_CAPI,
1781         .needs_reset_before_disable = true,
1782 };
1783
1784 static const struct cxl_service_layer_ops psl8_ops = {
1785         .adapter_regs_init = init_implementation_adapter_regs_psl8,
1786         .invalidate_all = cxl_invalidate_all_psl8,
1787         .afu_regs_init = init_implementation_afu_regs_psl8,
1788         .sanitise_afu_regs = sanitise_afu_regs_psl8,
1789         .register_serr_irq = cxl_native_register_serr_irq,
1790         .release_serr_irq = cxl_native_release_serr_irq,
1791         .handle_interrupt = cxl_irq_psl8,
1792         .fail_irq = cxl_fail_irq_psl,
1793         .activate_dedicated_process = cxl_activate_dedicated_process_psl8,
1794         .attach_afu_directed = cxl_attach_afu_directed_psl8,
1795         .attach_dedicated_process = cxl_attach_dedicated_process_psl8,
1796         .update_dedicated_ivtes = cxl_update_dedicated_ivtes_psl8,
1797         .debugfs_add_adapter_regs = cxl_debugfs_add_adapter_regs_psl8,
1798         .debugfs_add_afu_regs = cxl_debugfs_add_afu_regs_psl8,
1799         .psl_irq_dump_registers = cxl_native_irq_dump_regs_psl8,
1800         .err_irq_dump_registers = cxl_native_err_irq_dump_regs,
1801         .debugfs_stop_trace = cxl_stop_trace_psl8,
1802         .write_timebase_ctrl = write_timebase_ctrl_psl8,
1803         .timebase_read = timebase_read_psl8,
1804         .capi_mode = OPAL_PHB_CAPI_MODE_CAPI,
1805         .needs_reset_before_disable = true,
1806 };
1807
1808 static const struct cxl_service_layer_ops xsl_ops = {
1809         .adapter_regs_init = init_implementation_adapter_regs_xsl,
1810         .invalidate_all = cxl_invalidate_all_psl8,
1811         .sanitise_afu_regs = sanitise_afu_regs_psl8,
1812         .handle_interrupt = cxl_irq_psl8,
1813         .fail_irq = cxl_fail_irq_psl,
1814         .activate_dedicated_process = cxl_activate_dedicated_process_psl8,
1815         .attach_afu_directed = cxl_attach_afu_directed_psl8,
1816         .attach_dedicated_process = cxl_attach_dedicated_process_psl8,
1817         .update_dedicated_ivtes = cxl_update_dedicated_ivtes_psl8,
1818         .debugfs_add_adapter_regs = cxl_debugfs_add_adapter_regs_xsl,
1819         .write_timebase_ctrl = write_timebase_ctrl_xsl,
1820         .timebase_read = timebase_read_xsl,
1821         .capi_mode = OPAL_PHB_CAPI_MODE_DMA,
1822 };
1823
1824 static void set_sl_ops(struct cxl *adapter, struct pci_dev *dev)
1825 {
1826         if (dev->vendor == PCI_VENDOR_ID_MELLANOX && dev->device == 0x1013) {
1827                 /* Mellanox CX-4 */
1828                 dev_info(&dev->dev, "Device uses an XSL\n");
1829                 adapter->native->sl_ops = &xsl_ops;
1830                 adapter->min_pe = 1; /* Workaround for CX-4 hardware bug */
1831         } else {
1832                 if (cxl_is_power8()) {
1833                         dev_info(&dev->dev, "Device uses a PSL8\n");
1834                         adapter->native->sl_ops = &psl8_ops;
1835                 } else {
1836                         dev_info(&dev->dev, "Device uses a PSL9\n");
1837                         adapter->native->sl_ops = &psl9_ops;
1838                 }
1839         }
1840 }
1841
1842
1843 static struct cxl *cxl_pci_init_adapter(struct pci_dev *dev)
1844 {
1845         struct cxl *adapter;
1846         int rc;
1847
1848         adapter = cxl_alloc_adapter();
1849         if (!adapter)
1850                 return ERR_PTR(-ENOMEM);
1851
1852         adapter->native = kzalloc(sizeof(struct cxl_native), GFP_KERNEL);
1853         if (!adapter->native) {
1854                 rc = -ENOMEM;
1855                 goto err_release;
1856         }
1857
1858         set_sl_ops(adapter, dev);
1859
1860         /* Set defaults for parameters which need to persist over
1861          * configure/reconfigure
1862          */
1863         adapter->perst_loads_image = true;
1864         adapter->perst_same_image = false;
1865
1866         rc = cxl_configure_adapter(adapter, dev);
1867         if (rc) {
1868                 pci_disable_device(dev);
1869                 goto err_release;
1870         }
1871
1872         /* Don't care if this one fails: */
1873         cxl_debugfs_adapter_add(adapter);
1874
1875         /*
1876          * After we call this function we must not free the adapter directly,
1877          * even if it returns an error!
1878          */
1879         if ((rc = cxl_register_adapter(adapter)))
1880                 goto err_put_dev;
1881
1882         if ((rc = cxl_sysfs_adapter_add(adapter)))
1883                 goto err_del_dev;
1884
1885         /* Release the context lock as adapter is configured */
1886         cxl_adapter_context_unlock(adapter);
1887
1888         return adapter;
1889
1890 err_del_dev:
1891         device_del(&adapter->dev);
1892 err_put_dev:
1893         /* This should mirror cxl_remove_adapter, except without the
1894          * sysfs parts
1895          */
1896         cxl_debugfs_adapter_remove(adapter);
1897         cxl_deconfigure_adapter(adapter);
1898         put_device(&adapter->dev);
1899         return ERR_PTR(rc);
1900
1901 err_release:
1902         cxl_release_adapter(&adapter->dev);
1903         return ERR_PTR(rc);
1904 }
1905
1906 static void cxl_pci_remove_adapter(struct cxl *adapter)
1907 {
1908         pr_devel("cxl_remove_adapter\n");
1909
1910         cxl_sysfs_adapter_remove(adapter);
1911         cxl_debugfs_adapter_remove(adapter);
1912
1913         /*
1914          * Flush adapter datacache as its about to be removed.
1915          */
1916         cxl_data_cache_flush(adapter);
1917
1918         cxl_deconfigure_adapter(adapter);
1919
1920         device_unregister(&adapter->dev);
1921 }
1922
1923 #define CXL_MAX_PCIEX_PARENT 2
1924
1925 int cxl_slot_is_switched(struct pci_dev *dev)
1926 {
1927         struct device_node *np;
1928         int depth = 0;
1929         const __be32 *prop;
1930
1931         if (!(np = pci_device_to_OF_node(dev))) {
1932                 pr_err("cxl: np = NULL\n");
1933                 return -ENODEV;
1934         }
1935         of_node_get(np);
1936         while (np) {
1937                 np = of_get_next_parent(np);
1938                 prop = of_get_property(np, "device_type", NULL);
1939                 if (!prop || strcmp((char *)prop, "pciex"))
1940                         break;
1941                 depth++;
1942         }
1943         of_node_put(np);
1944         return (depth > CXL_MAX_PCIEX_PARENT);
1945 }
1946
1947 bool cxl_slot_is_supported(struct pci_dev *dev, int flags)
1948 {
1949         if (!cpu_has_feature(CPU_FTR_HVMODE))
1950                 return false;
1951
1952         if ((flags & CXL_SLOT_FLAG_DMA) && (!pvr_version_is(PVR_POWER8NVL))) {
1953                 /*
1954                  * CAPP DMA mode is technically supported on regular P8, but
1955                  * will EEH if the card attempts to access memory < 4GB, which
1956                  * we cannot realistically avoid. We might be able to work
1957                  * around the issue, but until then return unsupported:
1958                  */
1959                 return false;
1960         }
1961
1962         if (cxl_slot_is_switched(dev))
1963                 return false;
1964
1965         /*
1966          * XXX: This gets a little tricky on regular P8 (not POWER8NVL) since
1967          * the CAPP can be connected to PHB 0, 1 or 2 on a first come first
1968          * served basis, which is racy to check from here. If we need to
1969          * support this in future we might need to consider having this
1970          * function effectively reserve it ahead of time.
1971          *
1972          * Currently, the only user of this API is the Mellanox CX4, which is
1973          * only supported on P8NVL due to the above mentioned limitation of
1974          * CAPP DMA mode and therefore does not need to worry about this. If the
1975          * issue with CAPP DMA mode is later worked around on P8 we might need
1976          * to revisit this.
1977          */
1978
1979         return true;
1980 }
1981 EXPORT_SYMBOL_GPL(cxl_slot_is_supported);
1982
1983
1984 static int cxl_probe(struct pci_dev *dev, const struct pci_device_id *id)
1985 {
1986         struct cxl *adapter;
1987         int slice;
1988         int rc;
1989
1990         if (cxl_pci_is_vphb_device(dev)) {
1991                 dev_dbg(&dev->dev, "cxl_init_adapter: Ignoring cxl vphb device\n");
1992                 return -ENODEV;
1993         }
1994
1995         if (cxl_slot_is_switched(dev)) {
1996                 dev_info(&dev->dev, "Ignoring card on incompatible PCI slot\n");
1997                 return -ENODEV;
1998         }
1999
2000         if (cxl_is_power9() && !radix_enabled()) {
2001                 dev_info(&dev->dev, "Only Radix mode supported\n");
2002                 return -ENODEV;
2003         }
2004
2005         if (cxl_verbose)
2006                 dump_cxl_config_space(dev);
2007
2008         adapter = cxl_pci_init_adapter(dev);
2009         if (IS_ERR(adapter)) {
2010                 dev_err(&dev->dev, "cxl_init_adapter failed: %li\n", PTR_ERR(adapter));
2011                 return PTR_ERR(adapter);
2012         }
2013
2014         for (slice = 0; slice < adapter->slices; slice++) {
2015                 if ((rc = pci_init_afu(adapter, slice, dev))) {
2016                         dev_err(&dev->dev, "AFU %i failed to initialise: %i\n", slice, rc);
2017                         continue;
2018                 }
2019
2020                 rc = cxl_afu_select_best_mode(adapter->afu[slice]);
2021                 if (rc)
2022                         dev_err(&dev->dev, "AFU %i failed to start: %i\n", slice, rc);
2023         }
2024
2025         if (pnv_pci_on_cxl_phb(dev) && adapter->slices >= 1)
2026                 pnv_cxl_phb_set_peer_afu(dev, adapter->afu[0]);
2027
2028         return 0;
2029 }
2030
2031 static void cxl_remove(struct pci_dev *dev)
2032 {
2033         struct cxl *adapter = pci_get_drvdata(dev);
2034         struct cxl_afu *afu;
2035         int i;
2036
2037         /*
2038          * Lock to prevent someone grabbing a ref through the adapter list as
2039          * we are removing it
2040          */
2041         for (i = 0; i < adapter->slices; i++) {
2042                 afu = adapter->afu[i];
2043                 cxl_pci_remove_afu(afu);
2044         }
2045         cxl_pci_remove_adapter(adapter);
2046 }
2047
2048 static pci_ers_result_t cxl_vphb_error_detected(struct cxl_afu *afu,
2049                                                 pci_channel_state_t state)
2050 {
2051         struct pci_dev *afu_dev;
2052         pci_ers_result_t result = PCI_ERS_RESULT_NEED_RESET;
2053         pci_ers_result_t afu_result = PCI_ERS_RESULT_NEED_RESET;
2054
2055         /* There should only be one entry, but go through the list
2056          * anyway
2057          */
2058         if (afu == NULL || afu->phb == NULL)
2059                 return result;
2060
2061         list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) {
2062                 if (!afu_dev->driver)
2063                         continue;
2064
2065                 afu_dev->error_state = state;
2066
2067                 if (afu_dev->driver->err_handler)
2068                         afu_result = afu_dev->driver->err_handler->error_detected(afu_dev,
2069                                                                                   state);
2070                 /* Disconnect trumps all, NONE trumps NEED_RESET */
2071                 if (afu_result == PCI_ERS_RESULT_DISCONNECT)
2072                         result = PCI_ERS_RESULT_DISCONNECT;
2073                 else if ((afu_result == PCI_ERS_RESULT_NONE) &&
2074                          (result == PCI_ERS_RESULT_NEED_RESET))
2075                         result = PCI_ERS_RESULT_NONE;
2076         }
2077         return result;
2078 }
2079
2080 static pci_ers_result_t cxl_pci_error_detected(struct pci_dev *pdev,
2081                                                pci_channel_state_t state)
2082 {
2083         struct cxl *adapter = pci_get_drvdata(pdev);
2084         struct cxl_afu *afu;
2085         pci_ers_result_t result = PCI_ERS_RESULT_NEED_RESET;
2086         pci_ers_result_t afu_result = PCI_ERS_RESULT_NEED_RESET;
2087         int i;
2088
2089         /* At this point, we could still have an interrupt pending.
2090          * Let's try to get them out of the way before they do
2091          * anything we don't like.
2092          */
2093         schedule();
2094
2095         /* If we're permanently dead, give up. */
2096         if (state == pci_channel_io_perm_failure) {
2097                 spin_lock(&adapter->afu_list_lock);
2098                 for (i = 0; i < adapter->slices; i++) {
2099                         afu = adapter->afu[i];
2100                         /*
2101                          * Tell the AFU drivers; but we don't care what they
2102                          * say, we're going away.
2103                          */
2104                         cxl_vphb_error_detected(afu, state);
2105                 }
2106                 spin_unlock(&adapter->afu_list_lock);
2107                 return PCI_ERS_RESULT_DISCONNECT;
2108         }
2109
2110         /* Are we reflashing?
2111          *
2112          * If we reflash, we could come back as something entirely
2113          * different, including a non-CAPI card. As such, by default
2114          * we don't participate in the process. We'll be unbound and
2115          * the slot re-probed. (TODO: check EEH doesn't blindly rebind
2116          * us!)
2117          *
2118          * However, this isn't the entire story: for reliablity
2119          * reasons, we usually want to reflash the FPGA on PERST in
2120          * order to get back to a more reliable known-good state.
2121          *
2122          * This causes us a bit of a problem: if we reflash we can't
2123          * trust that we'll come back the same - we could have a new
2124          * image and been PERSTed in order to load that
2125          * image. However, most of the time we actually *will* come
2126          * back the same - for example a regular EEH event.
2127          *
2128          * Therefore, we allow the user to assert that the image is
2129          * indeed the same and that we should continue on into EEH
2130          * anyway.
2131          */
2132         if (adapter->perst_loads_image && !adapter->perst_same_image) {
2133                 /* TODO take the PHB out of CXL mode */
2134                 dev_info(&pdev->dev, "reflashing, so opting out of EEH!\n");
2135                 return PCI_ERS_RESULT_NONE;
2136         }
2137
2138         /*
2139          * At this point, we want to try to recover.  We'll always
2140          * need a complete slot reset: we don't trust any other reset.
2141          *
2142          * Now, we go through each AFU:
2143          *  - We send the driver, if bound, an error_detected callback.
2144          *    We expect it to clean up, but it can also tell us to give
2145          *    up and permanently detach the card. To simplify things, if
2146          *    any bound AFU driver doesn't support EEH, we give up on EEH.
2147          *
2148          *  - We detach all contexts associated with the AFU. This
2149          *    does not free them, but puts them into a CLOSED state
2150          *    which causes any the associated files to return useful
2151          *    errors to userland. It also unmaps, but does not free,
2152          *    any IRQs.
2153          *
2154          *  - We clean up our side: releasing and unmapping resources we hold
2155          *    so we can wire them up again when the hardware comes back up.
2156          *
2157          * Driver authors should note:
2158          *
2159          *  - Any contexts you create in your kernel driver (except
2160          *    those associated with anonymous file descriptors) are
2161          *    your responsibility to free and recreate. Likewise with
2162          *    any attached resources.
2163          *
2164          *  - We will take responsibility for re-initialising the
2165          *    device context (the one set up for you in
2166          *    cxl_pci_enable_device_hook and accessed through
2167          *    cxl_get_context). If you've attached IRQs or other
2168          *    resources to it, they remains yours to free.
2169          *
2170          * You can call the same functions to release resources as you
2171          * normally would: we make sure that these functions continue
2172          * to work when the hardware is down.
2173          *
2174          * Two examples:
2175          *
2176          * 1) If you normally free all your resources at the end of
2177          *    each request, or if you use anonymous FDs, your
2178          *    error_detected callback can simply set a flag to tell
2179          *    your driver not to start any new calls. You can then
2180          *    clear the flag in the resume callback.
2181          *
2182          * 2) If you normally allocate your resources on startup:
2183          *     * Set a flag in error_detected as above.
2184          *     * Let CXL detach your contexts.
2185          *     * In slot_reset, free the old resources and allocate new ones.
2186          *     * In resume, clear the flag to allow things to start.
2187          */
2188
2189         /* Make sure no one else changes the afu list */
2190         spin_lock(&adapter->afu_list_lock);
2191
2192         for (i = 0; i < adapter->slices; i++) {
2193                 afu = adapter->afu[i];
2194
2195                 if (afu == NULL)
2196                         continue;
2197
2198                 afu_result = cxl_vphb_error_detected(afu, state);
2199                 cxl_context_detach_all(afu);
2200                 cxl_ops->afu_deactivate_mode(afu, afu->current_mode);
2201                 pci_deconfigure_afu(afu);
2202
2203                 /* Disconnect trumps all, NONE trumps NEED_RESET */
2204                 if (afu_result == PCI_ERS_RESULT_DISCONNECT)
2205                         result = PCI_ERS_RESULT_DISCONNECT;
2206                 else if ((afu_result == PCI_ERS_RESULT_NONE) &&
2207                          (result == PCI_ERS_RESULT_NEED_RESET))
2208                         result = PCI_ERS_RESULT_NONE;
2209         }
2210         spin_unlock(&adapter->afu_list_lock);
2211
2212         /* should take the context lock here */
2213         if (cxl_adapter_context_lock(adapter) != 0)
2214                 dev_warn(&adapter->dev,
2215                          "Couldn't take context lock with %d active-contexts\n",
2216                          atomic_read(&adapter->contexts_num));
2217
2218         cxl_deconfigure_adapter(adapter);
2219
2220         return result;
2221 }
2222
2223 static pci_ers_result_t cxl_pci_slot_reset(struct pci_dev *pdev)
2224 {
2225         struct cxl *adapter = pci_get_drvdata(pdev);
2226         struct cxl_afu *afu;
2227         struct cxl_context *ctx;
2228         struct pci_dev *afu_dev;
2229         pci_ers_result_t afu_result = PCI_ERS_RESULT_RECOVERED;
2230         pci_ers_result_t result = PCI_ERS_RESULT_RECOVERED;
2231         int i;
2232
2233         if (cxl_configure_adapter(adapter, pdev))
2234                 goto err;
2235
2236         /*
2237          * Unlock context activation for the adapter. Ideally this should be
2238          * done in cxl_pci_resume but cxlflash module tries to activate the
2239          * master context as part of slot_reset callback.
2240          */
2241         cxl_adapter_context_unlock(adapter);
2242
2243         spin_lock(&adapter->afu_list_lock);
2244         for (i = 0; i < adapter->slices; i++) {
2245                 afu = adapter->afu[i];
2246
2247                 if (afu == NULL)
2248                         continue;
2249
2250                 if (pci_configure_afu(afu, adapter, pdev))
2251                         goto err_unlock;
2252
2253                 if (cxl_afu_select_best_mode(afu))
2254                         goto err_unlock;
2255
2256                 if (afu->phb == NULL)
2257                         continue;
2258
2259                 list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) {
2260                         /* Reset the device context.
2261                          * TODO: make this less disruptive
2262                          */
2263                         ctx = cxl_get_context(afu_dev);
2264
2265                         if (ctx && cxl_release_context(ctx))
2266                                 goto err_unlock;
2267
2268                         ctx = cxl_dev_context_init(afu_dev);
2269                         if (IS_ERR(ctx))
2270                                 goto err_unlock;
2271
2272                         afu_dev->dev.archdata.cxl_ctx = ctx;
2273
2274                         if (cxl_ops->afu_check_and_enable(afu))
2275                                 goto err_unlock;
2276
2277                         afu_dev->error_state = pci_channel_io_normal;
2278
2279                         /* If there's a driver attached, allow it to
2280                          * chime in on recovery. Drivers should check
2281                          * if everything has come back OK, but
2282                          * shouldn't start new work until we call
2283                          * their resume function.
2284                          */
2285                         if (!afu_dev->driver)
2286                                 continue;
2287
2288                         if (afu_dev->driver->err_handler &&
2289                             afu_dev->driver->err_handler->slot_reset)
2290                                 afu_result = afu_dev->driver->err_handler->slot_reset(afu_dev);
2291
2292                         if (afu_result == PCI_ERS_RESULT_DISCONNECT)
2293                                 result = PCI_ERS_RESULT_DISCONNECT;
2294                 }
2295         }
2296
2297         spin_unlock(&adapter->afu_list_lock);
2298         return result;
2299
2300 err_unlock:
2301         spin_unlock(&adapter->afu_list_lock);
2302
2303 err:
2304         /* All the bits that happen in both error_detected and cxl_remove
2305          * should be idempotent, so we don't need to worry about leaving a mix
2306          * of unconfigured and reconfigured resources.
2307          */
2308         dev_err(&pdev->dev, "EEH recovery failed. Asking to be disconnected.\n");
2309         return PCI_ERS_RESULT_DISCONNECT;
2310 }
2311
2312 static void cxl_pci_resume(struct pci_dev *pdev)
2313 {
2314         struct cxl *adapter = pci_get_drvdata(pdev);
2315         struct cxl_afu *afu;
2316         struct pci_dev *afu_dev;
2317         int i;
2318
2319         /* Everything is back now. Drivers should restart work now.
2320          * This is not the place to be checking if everything came back up
2321          * properly, because there's no return value: do that in slot_reset.
2322          */
2323         spin_lock(&adapter->afu_list_lock);
2324         for (i = 0; i < adapter->slices; i++) {
2325                 afu = adapter->afu[i];
2326
2327                 if (afu == NULL || afu->phb == NULL)
2328                         continue;
2329
2330                 list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) {
2331                         if (afu_dev->driver && afu_dev->driver->err_handler &&
2332                             afu_dev->driver->err_handler->resume)
2333                                 afu_dev->driver->err_handler->resume(afu_dev);
2334                 }
2335         }
2336         spin_unlock(&adapter->afu_list_lock);
2337 }
2338
2339 static const struct pci_error_handlers cxl_err_handler = {
2340         .error_detected = cxl_pci_error_detected,
2341         .slot_reset = cxl_pci_slot_reset,
2342         .resume = cxl_pci_resume,
2343 };
2344
2345 struct pci_driver cxl_pci_driver = {
2346         .name = "cxl-pci",
2347         .id_table = cxl_pci_tbl,
2348         .probe = cxl_probe,
2349         .remove = cxl_remove,
2350         .shutdown = cxl_remove,
2351         .err_handler = &cxl_err_handler,
2352 };