1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2015 IBM Corp.
6 #include <linux/spinlock.h>
7 #include <linux/uaccess.h>
8 #include <linux/delay.h>
9 #include <linux/irqdomain.h>
10 #include <linux/platform_device.h>
16 #define CXL_ERROR_DETECTED_EVENT 1
17 #define CXL_SLOT_RESET_EVENT 2
18 #define CXL_RESUME_EVENT 3
20 static void pci_error_handlers(struct cxl_afu *afu,
22 pci_channel_state_t state)
24 struct pci_dev *afu_dev;
25 struct pci_driver *afu_drv;
26 const struct pci_error_handlers *err_handler;
31 list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) {
32 afu_drv = to_pci_driver(afu_dev->dev.driver);
36 err_handler = afu_drv->err_handler;
37 switch (bus_error_event) {
38 case CXL_ERROR_DETECTED_EVENT:
39 afu_dev->error_state = state;
42 err_handler->error_detected)
43 err_handler->error_detected(afu_dev, state);
45 case CXL_SLOT_RESET_EVENT:
46 afu_dev->error_state = state;
49 err_handler->slot_reset)
50 err_handler->slot_reset(afu_dev);
52 case CXL_RESUME_EVENT:
55 err_handler->resume(afu_dev);
61 static irqreturn_t guest_handle_psl_slice_error(struct cxl_context *ctx, u64 dsisr,
64 pr_devel("in %s\n", __func__);
65 dev_crit(&ctx->afu->dev, "PSL ERROR STATUS: 0x%.16llx\n", errstat);
67 return cxl_ops->ack_irq(ctx, 0, errstat);
70 static ssize_t guest_collect_vpd(struct cxl *adapter, struct cxl_afu *afu,
71 void *buf, size_t len)
73 unsigned int entries, mod;
74 unsigned long **vpd_buf = NULL;
76 int rc = 0, i, tocopy;
82 /* number of entries in the list */
83 entries = len / SG_BUFFER_SIZE;
84 mod = len % SG_BUFFER_SIZE;
88 if (entries > SG_MAX_ENTRIES) {
89 entries = SG_MAX_ENTRIES;
90 len = SG_MAX_ENTRIES * SG_BUFFER_SIZE;
94 vpd_buf = kcalloc(entries, sizeof(unsigned long *), GFP_KERNEL);
98 le = (struct sg_list *)get_zeroed_page(GFP_KERNEL);
104 for (i = 0; i < entries; i++) {
105 vpd_buf[i] = (unsigned long *)get_zeroed_page(GFP_KERNEL);
110 le[i].phys_addr = cpu_to_be64(virt_to_phys(vpd_buf[i]));
111 le[i].len = cpu_to_be64(SG_BUFFER_SIZE);
112 if ((i == (entries - 1)) && mod)
113 le[i].len = cpu_to_be64(mod);
117 rc = cxl_h_collect_vpd_adapter(adapter->guest->handle,
118 virt_to_phys(le), entries, &out);
120 rc = cxl_h_collect_vpd(afu->guest->handle, 0,
121 virt_to_phys(le), entries, &out);
122 pr_devel("length of available (entries: %i), vpd: %#llx\n",
127 * hcall returns in 'out' the size of available VPDs.
128 * It fills the buffer with as much data as possible.
134 for (i = 0; i < entries; i++) {
135 if (len < SG_BUFFER_SIZE)
138 tocopy = SG_BUFFER_SIZE;
139 memcpy(buf, vpd_buf[i], tocopy);
146 for (i = 0; i < entries; i++) {
148 free_page((unsigned long) vpd_buf[i]);
150 free_page((unsigned long) le);
156 static int guest_get_irq_info(struct cxl_context *ctx, struct cxl_irq_info *info)
158 return cxl_h_collect_int_info(ctx->afu->guest->handle, ctx->process_token, info);
161 static irqreturn_t guest_psl_irq(int irq, void *data)
163 struct cxl_context *ctx = data;
164 struct cxl_irq_info irq_info;
167 pr_devel("%d: received PSL interrupt %i\n", ctx->pe, irq);
168 rc = guest_get_irq_info(ctx, &irq_info);
170 WARN(1, "Unable to get IRQ info: %i\n", rc);
174 rc = cxl_irq_psl8(irq, ctx, &irq_info);
178 static int afu_read_error_state(struct cxl_afu *afu, int *state_out)
186 rc = cxl_h_read_error_state(afu->guest->handle, &state);
188 WARN_ON(state != H_STATE_NORMAL &&
189 state != H_STATE_DISABLE &&
190 state != H_STATE_TEMP_UNAVAILABLE &&
191 state != H_STATE_PERM_UNAVAILABLE);
192 *state_out = state & 0xffffffff;
197 static irqreturn_t guest_slice_irq_err(int irq, void *data)
199 struct cxl_afu *afu = data;
201 u64 serr, afu_error, dsisr;
203 rc = cxl_h_get_fn_error_interrupt(afu->guest->handle, &serr);
205 dev_crit(&afu->dev, "Couldn't read PSL_SERR_An: %d\n", rc);
208 afu_error = cxl_p2n_read(afu, CXL_AFU_ERR_An);
209 dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
210 cxl_afu_decode_psl_serr(afu, serr);
211 dev_crit(&afu->dev, "AFU_ERR_An: 0x%.16llx\n", afu_error);
212 dev_crit(&afu->dev, "PSL_DSISR_An: 0x%.16llx\n", dsisr);
214 rc = cxl_h_ack_fn_error_interrupt(afu->guest->handle, serr);
216 dev_crit(&afu->dev, "Couldn't ack slice error interrupt: %d\n",
223 static int irq_alloc_range(struct cxl *adapter, int len, int *irq)
226 struct irq_avail *cur;
228 for (i = 0; i < adapter->guest->irq_nranges; i++) {
229 cur = &adapter->guest->irq_avail[i];
230 n = bitmap_find_next_zero_area(cur->bitmap, cur->range,
232 if (n < cur->range) {
233 bitmap_set(cur->bitmap, n, len);
234 *irq = cur->offset + n;
235 pr_devel("guest: allocate IRQs %#x->%#x\n",
236 *irq, *irq + len - 1);
244 static int irq_free_range(struct cxl *adapter, int irq, int len)
247 struct irq_avail *cur;
252 for (i = 0; i < adapter->guest->irq_nranges; i++) {
253 cur = &adapter->guest->irq_avail[i];
254 if (irq >= cur->offset &&
255 (irq + len) <= (cur->offset + cur->range)) {
256 n = irq - cur->offset;
257 bitmap_clear(cur->bitmap, n, len);
258 pr_devel("guest: release IRQs %#x->%#x\n",
266 static int guest_reset(struct cxl *adapter)
268 struct cxl_afu *afu = NULL;
271 pr_devel("Adapter reset request\n");
272 spin_lock(&adapter->afu_list_lock);
273 for (i = 0; i < adapter->slices; i++) {
274 if ((afu = adapter->afu[i])) {
275 pci_error_handlers(afu, CXL_ERROR_DETECTED_EVENT,
276 pci_channel_io_frozen);
277 cxl_context_detach_all(afu);
281 rc = cxl_h_reset_adapter(adapter->guest->handle);
282 for (i = 0; i < adapter->slices; i++) {
283 if (!rc && (afu = adapter->afu[i])) {
284 pci_error_handlers(afu, CXL_SLOT_RESET_EVENT,
285 pci_channel_io_normal);
286 pci_error_handlers(afu, CXL_RESUME_EVENT, 0);
289 spin_unlock(&adapter->afu_list_lock);
293 static int guest_alloc_one_irq(struct cxl *adapter)
297 spin_lock(&adapter->guest->irq_alloc_lock);
298 if (irq_alloc_range(adapter, 1, &irq))
300 spin_unlock(&adapter->guest->irq_alloc_lock);
304 static void guest_release_one_irq(struct cxl *adapter, int irq)
306 spin_lock(&adapter->guest->irq_alloc_lock);
307 irq_free_range(adapter, irq, 1);
308 spin_unlock(&adapter->guest->irq_alloc_lock);
311 static int guest_alloc_irq_ranges(struct cxl_irq_ranges *irqs,
312 struct cxl *adapter, unsigned int num)
316 memset(irqs, 0, sizeof(struct cxl_irq_ranges));
318 spin_lock(&adapter->guest->irq_alloc_lock);
319 for (i = 0; i < CXL_IRQ_RANGES && num; i++) {
322 if (irq_alloc_range(adapter, try, &irq) == 0)
328 irqs->offset[i] = irq;
329 irqs->range[i] = try;
334 spin_unlock(&adapter->guest->irq_alloc_lock);
338 for (i = 0; i < CXL_IRQ_RANGES; i++)
339 irq_free_range(adapter, irqs->offset[i], irqs->range[i]);
340 spin_unlock(&adapter->guest->irq_alloc_lock);
344 static void guest_release_irq_ranges(struct cxl_irq_ranges *irqs,
349 spin_lock(&adapter->guest->irq_alloc_lock);
350 for (i = 0; i < CXL_IRQ_RANGES; i++)
351 irq_free_range(adapter, irqs->offset[i], irqs->range[i]);
352 spin_unlock(&adapter->guest->irq_alloc_lock);
355 static int guest_register_serr_irq(struct cxl_afu *afu)
357 afu->err_irq_name = kasprintf(GFP_KERNEL, "cxl-%s-err",
358 dev_name(&afu->dev));
359 if (!afu->err_irq_name)
362 if (!(afu->serr_virq = cxl_map_irq(afu->adapter, afu->serr_hwirq,
363 guest_slice_irq_err, afu, afu->err_irq_name))) {
364 kfree(afu->err_irq_name);
365 afu->err_irq_name = NULL;
372 static void guest_release_serr_irq(struct cxl_afu *afu)
374 cxl_unmap_irq(afu->serr_virq, afu);
375 cxl_ops->release_one_irq(afu->adapter, afu->serr_hwirq);
376 kfree(afu->err_irq_name);
379 static int guest_ack_irq(struct cxl_context *ctx, u64 tfc, u64 psl_reset_mask)
381 return cxl_h_control_faults(ctx->afu->guest->handle, ctx->process_token,
382 tfc >> 32, (psl_reset_mask != 0));
385 static void disable_afu_irqs(struct cxl_context *ctx)
387 irq_hw_number_t hwirq;
391 pr_devel("Disabling AFU(%d) interrupts\n", ctx->afu->slice);
392 for (r = 0; r < CXL_IRQ_RANGES; r++) {
393 hwirq = ctx->irqs.offset[r];
394 for (i = 0; i < ctx->irqs.range[r]; hwirq++, i++) {
395 virq = irq_find_mapping(NULL, hwirq);
401 static void enable_afu_irqs(struct cxl_context *ctx)
403 irq_hw_number_t hwirq;
407 pr_devel("Enabling AFU(%d) interrupts\n", ctx->afu->slice);
408 for (r = 0; r < CXL_IRQ_RANGES; r++) {
409 hwirq = ctx->irqs.offset[r];
410 for (i = 0; i < ctx->irqs.range[r]; hwirq++, i++) {
411 virq = irq_find_mapping(NULL, hwirq);
417 static int _guest_afu_cr_readXX(int sz, struct cxl_afu *afu, int cr_idx,
418 u64 offset, u64 *val)
424 if (afu->crs_len < sz)
427 if (unlikely(offset >= afu->crs_len))
430 cr = get_zeroed_page(GFP_KERNEL);
434 rc = cxl_h_get_config(afu->guest->handle, cr_idx, offset,
435 virt_to_phys((void *)cr), sz);
445 *val = in_le16((u16 *)cr);
448 *val = in_le32((unsigned *)cr);
451 *val = in_le64((u64 *)cr);
461 static int guest_afu_cr_read32(struct cxl_afu *afu, int cr_idx, u64 offset,
467 rc = _guest_afu_cr_readXX(4, afu, cr_idx, offset, &val);
473 static int guest_afu_cr_read16(struct cxl_afu *afu, int cr_idx, u64 offset,
479 rc = _guest_afu_cr_readXX(2, afu, cr_idx, offset, &val);
485 static int guest_afu_cr_read8(struct cxl_afu *afu, int cr_idx, u64 offset,
491 rc = _guest_afu_cr_readXX(1, afu, cr_idx, offset, &val);
497 static int guest_afu_cr_read64(struct cxl_afu *afu, int cr_idx, u64 offset,
500 return _guest_afu_cr_readXX(8, afu, cr_idx, offset, out);
503 static int guest_afu_cr_write32(struct cxl_afu *afu, int cr, u64 off, u32 in)
505 /* config record is not writable from guest */
509 static int guest_afu_cr_write16(struct cxl_afu *afu, int cr, u64 off, u16 in)
511 /* config record is not writable from guest */
515 static int guest_afu_cr_write8(struct cxl_afu *afu, int cr, u64 off, u8 in)
517 /* config record is not writable from guest */
521 static int attach_afu_directed(struct cxl_context *ctx, u64 wed, u64 amr)
523 struct cxl_process_element_hcall *elem;
524 struct cxl *adapter = ctx->afu->adapter;
525 const struct cred *cred;
528 u64 mmio_addr, mmio_size;
531 /* Must be 8 byte aligned and cannot cross a 4096 byte boundary */
532 if (!(elem = (struct cxl_process_element_hcall *)
533 get_zeroed_page(GFP_KERNEL)))
536 elem->version = cpu_to_be64(CXL_PROCESS_ELEMENT_VERSION);
539 flags |= CXL_PE_TRANSLATION_ENABLED;
540 flags |= CXL_PE_PRIVILEGED_PROCESS;
541 if (mfmsr() & MSR_SF)
542 flags |= CXL_PE_64_BIT;
545 flags |= CXL_PE_PROBLEM_STATE;
546 flags |= CXL_PE_TRANSLATION_ENABLED;
547 if (!test_tsk_thread_flag(current, TIF_32BIT))
548 flags |= CXL_PE_64_BIT;
549 cred = get_current_cred();
550 if (uid_eq(cred->euid, GLOBAL_ROOT_UID))
551 flags |= CXL_PE_PRIVILEGED_PROCESS;
554 elem->flags = cpu_to_be64(flags);
555 elem->common.tid = cpu_to_be32(0); /* Unused */
556 elem->common.pid = cpu_to_be32(pid);
557 elem->common.csrp = cpu_to_be64(0); /* disable */
558 elem->common.u.psl8.aurp0 = cpu_to_be64(0); /* disable */
559 elem->common.u.psl8.aurp1 = cpu_to_be64(0); /* disable */
561 cxl_prefault(ctx, wed);
563 elem->common.u.psl8.sstp0 = cpu_to_be64(ctx->sstp0);
564 elem->common.u.psl8.sstp1 = cpu_to_be64(ctx->sstp1);
567 * Ensure we have at least one interrupt allocated to take faults for
568 * kernel contexts that may not have allocated any AFU IRQs at all:
570 if (ctx->irqs.range[0] == 0) {
571 rc = afu_register_irqs(ctx, 0);
576 for (r = 0; r < CXL_IRQ_RANGES; r++) {
577 for (i = 0; i < ctx->irqs.range[r]; i++) {
578 if (r == 0 && i == 0) {
579 elem->pslVirtualIsn = cpu_to_be32(ctx->irqs.offset[0]);
581 idx = ctx->irqs.offset[r] + i - adapter->guest->irq_base_offset;
582 elem->applicationVirtualIsnBitmap[idx / 8] |= 0x80 >> (idx % 8);
586 elem->common.amr = cpu_to_be64(amr);
587 elem->common.wed = cpu_to_be64(wed);
589 disable_afu_irqs(ctx);
591 rc = cxl_h_attach_process(ctx->afu->guest->handle, elem,
592 &ctx->process_token, &mmio_addr, &mmio_size);
593 if (rc == H_SUCCESS) {
594 if (ctx->master || !ctx->afu->pp_psa) {
595 ctx->psn_phys = ctx->afu->psn_phys;
596 ctx->psn_size = ctx->afu->adapter->ps_size;
598 ctx->psn_phys = mmio_addr;
599 ctx->psn_size = mmio_size;
601 if (ctx->afu->pp_psa && mmio_size &&
602 ctx->afu->pp_size == 0) {
604 * There's no property in the device tree to read the
605 * pp_size. We only find out at the 1st attach.
606 * Compared to bare-metal, it is too late and we
607 * should really lock here. However, on powerVM,
608 * pp_size is really only used to display in /sys.
609 * Being discussed with pHyp for their next release.
611 ctx->afu->pp_size = mmio_size;
613 /* from PAPR: process element is bytes 4-7 of process token */
614 ctx->external_pe = ctx->process_token & 0xFFFFFFFF;
615 pr_devel("CXL pe=%i is known as %i for pHyp, mmio_size=%#llx",
616 ctx->pe, ctx->external_pe, ctx->psn_size);
617 ctx->pe_inserted = true;
618 enable_afu_irqs(ctx);
622 free_page((u64)elem);
626 static int guest_attach_process(struct cxl_context *ctx, bool kernel, u64 wed, u64 amr)
628 pr_devel("in %s\n", __func__);
630 ctx->kernel = kernel;
631 if (ctx->afu->current_mode == CXL_MODE_DIRECTED)
632 return attach_afu_directed(ctx, wed, amr);
634 /* dedicated mode not supported on FW840 */
639 static int detach_afu_directed(struct cxl_context *ctx)
641 if (!ctx->pe_inserted)
643 if (cxl_h_detach_process(ctx->afu->guest->handle, ctx->process_token))
648 static int guest_detach_process(struct cxl_context *ctx)
650 pr_devel("in %s\n", __func__);
651 trace_cxl_detach(ctx);
653 if (!cxl_ops->link_ok(ctx->afu->adapter, ctx->afu))
656 if (ctx->afu->current_mode == CXL_MODE_DIRECTED)
657 return detach_afu_directed(ctx);
662 static void guest_release_afu(struct device *dev)
664 struct cxl_afu *afu = to_cxl_afu(dev);
666 pr_devel("%s\n", __func__);
668 idr_destroy(&afu->contexts_idr);
674 ssize_t cxl_guest_read_afu_vpd(struct cxl_afu *afu, void *buf, size_t len)
676 return guest_collect_vpd(NULL, afu, buf, len);
679 #define ERR_BUFF_MAX_COPY_SIZE PAGE_SIZE
680 static ssize_t guest_afu_read_err_buffer(struct cxl_afu *afu, char *buf,
681 loff_t off, size_t count)
686 tbuf = (void *) get_zeroed_page(GFP_KERNEL);
690 rc = cxl_h_get_afu_err(afu->guest->handle,
697 if (count > ERR_BUFF_MAX_COPY_SIZE)
698 count = ERR_BUFF_MAX_COPY_SIZE - (off & 0x7);
699 memcpy(buf, tbuf, count);
701 free_page((u64)tbuf);
706 static int guest_afu_check_and_enable(struct cxl_afu *afu)
711 static bool guest_support_attributes(const char *attr_name,
715 case CXL_ADAPTER_ATTRS:
716 if ((strcmp(attr_name, "base_image") == 0) ||
717 (strcmp(attr_name, "load_image_on_perst") == 0) ||
718 (strcmp(attr_name, "perst_reloads_same_image") == 0) ||
719 (strcmp(attr_name, "image_loaded") == 0))
722 case CXL_AFU_MASTER_ATTRS:
723 if ((strcmp(attr_name, "pp_mmio_off") == 0))
735 static int activate_afu_directed(struct cxl_afu *afu)
739 dev_info(&afu->dev, "Activating AFU(%d) directed mode\n", afu->slice);
741 afu->current_mode = CXL_MODE_DIRECTED;
743 afu->num_procs = afu->max_procs_virtualised;
745 if ((rc = cxl_chardev_m_afu_add(afu)))
748 if ((rc = cxl_sysfs_afu_m_add(afu)))
751 if ((rc = cxl_chardev_s_afu_add(afu)))
756 cxl_sysfs_afu_m_remove(afu);
758 cxl_chardev_afu_remove(afu);
762 static int guest_afu_activate_mode(struct cxl_afu *afu, int mode)
766 if (!(mode & afu->modes_supported))
769 if (mode == CXL_MODE_DIRECTED)
770 return activate_afu_directed(afu);
772 if (mode == CXL_MODE_DEDICATED)
773 dev_err(&afu->dev, "Dedicated mode not supported\n");
778 static int deactivate_afu_directed(struct cxl_afu *afu)
780 dev_info(&afu->dev, "Deactivating AFU(%d) directed mode\n", afu->slice);
782 afu->current_mode = 0;
785 cxl_sysfs_afu_m_remove(afu);
786 cxl_chardev_afu_remove(afu);
788 cxl_ops->afu_reset(afu);
793 static int guest_afu_deactivate_mode(struct cxl_afu *afu, int mode)
797 if (!(mode & afu->modes_supported))
800 if (mode == CXL_MODE_DIRECTED)
801 return deactivate_afu_directed(afu);
805 static int guest_afu_reset(struct cxl_afu *afu)
807 pr_devel("AFU(%d) reset request\n", afu->slice);
808 return cxl_h_reset_afu(afu->guest->handle);
811 static int guest_map_slice_regs(struct cxl_afu *afu)
813 if (!(afu->p2n_mmio = ioremap(afu->guest->p2n_phys, afu->guest->p2n_size))) {
814 dev_err(&afu->dev, "Error mapping AFU(%d) MMIO regions\n",
821 static void guest_unmap_slice_regs(struct cxl_afu *afu)
824 iounmap(afu->p2n_mmio);
827 static int afu_update_state(struct cxl_afu *afu)
831 rc = afu_read_error_state(afu, &cur_state);
835 if (afu->guest->previous_state == cur_state)
838 pr_devel("AFU(%d) update state to %#x\n", afu->slice, cur_state);
842 afu->guest->previous_state = cur_state;
845 case H_STATE_DISABLE:
846 pci_error_handlers(afu, CXL_ERROR_DETECTED_EVENT,
847 pci_channel_io_frozen);
849 cxl_context_detach_all(afu);
850 if ((rc = cxl_ops->afu_reset(afu)))
851 pr_devel("reset hcall failed %d\n", rc);
853 rc = afu_read_error_state(afu, &cur_state);
854 if (!rc && cur_state == H_STATE_NORMAL) {
855 pci_error_handlers(afu, CXL_SLOT_RESET_EVENT,
856 pci_channel_io_normal);
857 pci_error_handlers(afu, CXL_RESUME_EVENT, 0);
859 afu->guest->previous_state = 0;
862 case H_STATE_TEMP_UNAVAILABLE:
863 afu->guest->previous_state = cur_state;
866 case H_STATE_PERM_UNAVAILABLE:
867 dev_err(&afu->dev, "AFU is in permanent error state\n");
868 pci_error_handlers(afu, CXL_ERROR_DETECTED_EVENT,
869 pci_channel_io_perm_failure);
870 afu->guest->previous_state = cur_state;
874 pr_err("Unexpected AFU(%d) error state: %#x\n",
875 afu->slice, cur_state);
882 static void afu_handle_errstate(struct work_struct *work)
884 struct cxl_afu_guest *afu_guest =
885 container_of(to_delayed_work(work), struct cxl_afu_guest, work_err);
887 if (!afu_update_state(afu_guest->parent) &&
888 afu_guest->previous_state == H_STATE_PERM_UNAVAILABLE)
891 if (afu_guest->handle_err)
892 schedule_delayed_work(&afu_guest->work_err,
893 msecs_to_jiffies(3000));
896 static bool guest_link_ok(struct cxl *cxl, struct cxl_afu *afu)
900 if (afu && (!afu_read_error_state(afu, &state))) {
901 if (state == H_STATE_NORMAL)
908 static int afu_properties_look_ok(struct cxl_afu *afu)
910 if (afu->pp_irqs < 0) {
911 dev_err(&afu->dev, "Unexpected per-process minimum interrupt value\n");
915 if (afu->max_procs_virtualised < 1) {
916 dev_err(&afu->dev, "Unexpected max number of processes virtualised value\n");
923 int cxl_guest_init_afu(struct cxl *adapter, int slice, struct device_node *afu_np)
929 pr_devel("in %s - AFU(%d)\n", __func__, slice);
930 if (!(afu = cxl_alloc_afu(adapter, slice)))
933 if (!(afu->guest = kzalloc(sizeof(struct cxl_afu_guest), GFP_KERNEL))) {
938 if ((rc = dev_set_name(&afu->dev, "afu%i.%i",
939 adapter->adapter_num,
945 if ((rc = cxl_of_read_afu_handle(afu, afu_np)))
948 if ((rc = cxl_ops->afu_reset(afu)))
951 if ((rc = cxl_of_read_afu_properties(afu, afu_np)))
954 if ((rc = afu_properties_look_ok(afu)))
957 if ((rc = guest_map_slice_regs(afu)))
960 if ((rc = guest_register_serr_irq(afu)))
964 * After we call this function we must not free the afu directly, even
965 * if it returns an error!
967 if ((rc = cxl_register_afu(afu)))
970 if ((rc = cxl_sysfs_afu_add(afu)))
974 * pHyp doesn't expose the programming models supported by the
975 * AFU. pHyp currently only supports directed mode. If it adds
976 * dedicated mode later, this version of cxl has no way to
977 * detect it. So we'll initialize the driver, but the first
979 * Being discussed with pHyp to do better (likely new property)
981 if (afu->max_procs_virtualised == 1)
982 afu->modes_supported = CXL_MODE_DEDICATED;
984 afu->modes_supported = CXL_MODE_DIRECTED;
986 if ((rc = cxl_afu_select_best_mode(afu)))
987 goto err_remove_sysfs;
989 adapter->afu[afu->slice] = afu;
994 * wake up the cpu periodically to check the state
995 * of the AFU using "afu" stored in the guest structure.
997 afu->guest->parent = afu;
998 afu->guest->handle_err = true;
999 INIT_DELAYED_WORK(&afu->guest->work_err, afu_handle_errstate);
1000 schedule_delayed_work(&afu->guest->work_err, msecs_to_jiffies(1000));
1002 if ((rc = cxl_pci_vphb_add(afu)))
1003 dev_info(&afu->dev, "Can't register vPHB\n");
1008 cxl_sysfs_afu_remove(afu);
1010 device_del(&afu->dev);
1012 put_device(&afu->dev);
1014 guest_release_serr_irq(afu);
1016 guest_unmap_slice_regs(afu);
1025 void cxl_guest_remove_afu(struct cxl_afu *afu)
1030 /* flush and stop pending job */
1031 afu->guest->handle_err = false;
1032 flush_delayed_work(&afu->guest->work_err);
1034 cxl_pci_vphb_remove(afu);
1035 cxl_sysfs_afu_remove(afu);
1037 spin_lock(&afu->adapter->afu_list_lock);
1038 afu->adapter->afu[afu->slice] = NULL;
1039 spin_unlock(&afu->adapter->afu_list_lock);
1041 cxl_context_detach_all(afu);
1042 cxl_ops->afu_deactivate_mode(afu, afu->current_mode);
1043 guest_release_serr_irq(afu);
1044 guest_unmap_slice_regs(afu);
1046 device_unregister(&afu->dev);
1049 static void free_adapter(struct cxl *adapter)
1051 struct irq_avail *cur;
1054 if (adapter->guest) {
1055 if (adapter->guest->irq_avail) {
1056 for (i = 0; i < adapter->guest->irq_nranges; i++) {
1057 cur = &adapter->guest->irq_avail[i];
1058 bitmap_free(cur->bitmap);
1060 kfree(adapter->guest->irq_avail);
1062 kfree(adapter->guest->status);
1063 kfree(adapter->guest);
1065 cxl_remove_adapter_nr(adapter);
1069 static int properties_look_ok(struct cxl *adapter)
1071 /* The absence of this property means that the operational
1072 * status is unknown or okay
1074 if (strlen(adapter->guest->status) &&
1075 strcmp(adapter->guest->status, "okay")) {
1076 pr_err("ABORTING:Bad operational status of the device\n");
1083 ssize_t cxl_guest_read_adapter_vpd(struct cxl *adapter, void *buf, size_t len)
1085 return guest_collect_vpd(adapter, NULL, buf, len);
1088 void cxl_guest_remove_adapter(struct cxl *adapter)
1090 pr_devel("in %s\n", __func__);
1092 cxl_sysfs_adapter_remove(adapter);
1094 cxl_guest_remove_chardev(adapter);
1095 device_unregister(&adapter->dev);
1098 static void release_adapter(struct device *dev)
1100 free_adapter(to_cxl_adapter(dev));
1103 struct cxl *cxl_guest_init_adapter(struct device_node *np, struct platform_device *pdev)
1105 struct cxl *adapter;
1109 if (!(adapter = cxl_alloc_adapter()))
1110 return ERR_PTR(-ENOMEM);
1112 if (!(adapter->guest = kzalloc(sizeof(struct cxl_guest), GFP_KERNEL))) {
1113 free_adapter(adapter);
1114 return ERR_PTR(-ENOMEM);
1117 adapter->slices = 0;
1118 adapter->guest->pdev = pdev;
1119 adapter->dev.parent = &pdev->dev;
1120 adapter->dev.release = release_adapter;
1121 dev_set_drvdata(&pdev->dev, adapter);
1124 * Hypervisor controls PSL timebase initialization (p1 register).
1125 * On FW840, PSL is initialized.
1127 adapter->psl_timebase_synced = true;
1129 if ((rc = cxl_of_read_adapter_handle(adapter, np)))
1132 if ((rc = cxl_of_read_adapter_properties(adapter, np)))
1135 if ((rc = properties_look_ok(adapter)))
1138 if ((rc = cxl_guest_add_chardev(adapter)))
1142 * After we call this function we must not free the adapter directly,
1143 * even if it returns an error!
1145 if ((rc = cxl_register_adapter(adapter)))
1148 if ((rc = cxl_sysfs_adapter_add(adapter)))
1151 /* release the context lock as the adapter is configured */
1152 cxl_adapter_context_unlock(adapter);
1157 device_del(&adapter->dev);
1159 put_device(&adapter->dev);
1161 cxl_guest_remove_chardev(adapter);
1164 free_adapter(adapter);
1168 void cxl_guest_reload_module(struct cxl *adapter)
1170 struct platform_device *pdev;
1172 pdev = adapter->guest->pdev;
1173 cxl_guest_remove_adapter(adapter);
1178 const struct cxl_backend_ops cxl_guest_ops = {
1179 .module = THIS_MODULE,
1180 .adapter_reset = guest_reset,
1181 .alloc_one_irq = guest_alloc_one_irq,
1182 .release_one_irq = guest_release_one_irq,
1183 .alloc_irq_ranges = guest_alloc_irq_ranges,
1184 .release_irq_ranges = guest_release_irq_ranges,
1186 .handle_psl_slice_error = guest_handle_psl_slice_error,
1187 .psl_interrupt = guest_psl_irq,
1188 .ack_irq = guest_ack_irq,
1189 .attach_process = guest_attach_process,
1190 .detach_process = guest_detach_process,
1191 .update_ivtes = NULL,
1192 .support_attributes = guest_support_attributes,
1193 .link_ok = guest_link_ok,
1194 .release_afu = guest_release_afu,
1195 .afu_read_err_buffer = guest_afu_read_err_buffer,
1196 .afu_check_and_enable = guest_afu_check_and_enable,
1197 .afu_activate_mode = guest_afu_activate_mode,
1198 .afu_deactivate_mode = guest_afu_deactivate_mode,
1199 .afu_reset = guest_afu_reset,
1200 .afu_cr_read8 = guest_afu_cr_read8,
1201 .afu_cr_read16 = guest_afu_cr_read16,
1202 .afu_cr_read32 = guest_afu_cr_read32,
1203 .afu_cr_read64 = guest_afu_cr_read64,
1204 .afu_cr_write8 = guest_afu_cr_write8,
1205 .afu_cr_write16 = guest_afu_cr_write16,
1206 .afu_cr_write32 = guest_afu_cr_write32,
1207 .read_adapter_vpd = cxl_guest_read_adapter_vpd,