1 /* Driver for Realtek PCI-Express card reader
3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 * Wei WANG <wei_wang@realsil.com.cn>
22 #include <linux/pci.h>
23 #include <linux/module.h>
24 #include <linux/slab.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/highmem.h>
27 #include <linux/interrupt.h>
28 #include <linux/delay.h>
29 #include <linux/idr.h>
30 #include <linux/platform_device.h>
31 #include <linux/mfd/core.h>
32 #include <linux/rtsx_pci.h>
33 #include <linux/mmc/card.h>
34 #include <asm/unaligned.h>
38 static bool msi_en = true;
39 module_param(msi_en, bool, S_IRUGO | S_IWUSR);
40 MODULE_PARM_DESC(msi_en, "Enable MSI");
42 static DEFINE_IDR(rtsx_pci_idr);
43 static DEFINE_SPINLOCK(rtsx_pci_lock);
45 static struct mfd_cell rtsx_pcr_cells[] = {
47 .name = DRV_NAME_RTSX_PCI_SDMMC,
50 .name = DRV_NAME_RTSX_PCI_MS,
54 static const struct pci_device_id rtsx_pci_ids[] = {
55 { PCI_DEVICE(0x10EC, 0x5209), PCI_CLASS_OTHERS << 16, 0xFF0000 },
56 { PCI_DEVICE(0x10EC, 0x5229), PCI_CLASS_OTHERS << 16, 0xFF0000 },
57 { PCI_DEVICE(0x10EC, 0x5289), PCI_CLASS_OTHERS << 16, 0xFF0000 },
58 { PCI_DEVICE(0x10EC, 0x5227), PCI_CLASS_OTHERS << 16, 0xFF0000 },
59 { PCI_DEVICE(0x10EC, 0x522A), PCI_CLASS_OTHERS << 16, 0xFF0000 },
60 { PCI_DEVICE(0x10EC, 0x5249), PCI_CLASS_OTHERS << 16, 0xFF0000 },
61 { PCI_DEVICE(0x10EC, 0x5287), PCI_CLASS_OTHERS << 16, 0xFF0000 },
62 { PCI_DEVICE(0x10EC, 0x5286), PCI_CLASS_OTHERS << 16, 0xFF0000 },
63 { PCI_DEVICE(0x10EC, 0x524A), PCI_CLASS_OTHERS << 16, 0xFF0000 },
64 { PCI_DEVICE(0x10EC, 0x525A), PCI_CLASS_OTHERS << 16, 0xFF0000 },
65 { PCI_DEVICE(0x10EC, 0x5260), PCI_CLASS_OTHERS << 16, 0xFF0000 },
69 MODULE_DEVICE_TABLE(pci, rtsx_pci_ids);
71 static inline void rtsx_pci_enable_aspm(struct rtsx_pcr *pcr)
73 rtsx_pci_update_cfg_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL,
77 static inline void rtsx_pci_disable_aspm(struct rtsx_pcr *pcr)
79 rtsx_pci_update_cfg_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL,
83 static int rtsx_comm_set_ltr_latency(struct rtsx_pcr *pcr, u32 latency)
85 rtsx_pci_write_register(pcr, MSGTXDATA0,
86 MASK_8_BIT_DEF, (u8) (latency & 0xFF));
87 rtsx_pci_write_register(pcr, MSGTXDATA1,
88 MASK_8_BIT_DEF, (u8)((latency >> 8) & 0xFF));
89 rtsx_pci_write_register(pcr, MSGTXDATA2,
90 MASK_8_BIT_DEF, (u8)((latency >> 16) & 0xFF));
91 rtsx_pci_write_register(pcr, MSGTXDATA3,
92 MASK_8_BIT_DEF, (u8)((latency >> 24) & 0xFF));
93 rtsx_pci_write_register(pcr, LTR_CTL, LTR_TX_EN_MASK |
94 LTR_LATENCY_MODE_MASK, LTR_TX_EN_1 | LTR_LATENCY_MODE_SW);
99 int rtsx_set_ltr_latency(struct rtsx_pcr *pcr, u32 latency)
101 if (pcr->ops->set_ltr_latency)
102 return pcr->ops->set_ltr_latency(pcr, latency);
104 return rtsx_comm_set_ltr_latency(pcr, latency);
107 static void rtsx_comm_set_aspm(struct rtsx_pcr *pcr, bool enable)
109 struct rtsx_cr_option *option = &pcr->option;
111 if (pcr->aspm_enabled == enable)
114 if (option->dev_aspm_mode == DEV_ASPM_DYNAMIC) {
116 rtsx_pci_enable_aspm(pcr);
118 rtsx_pci_disable_aspm(pcr);
119 } else if (option->dev_aspm_mode == DEV_ASPM_BACKDOOR) {
120 u8 mask = FORCE_ASPM_VAL_MASK;
125 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val);
128 pcr->aspm_enabled = enable;
131 static void rtsx_disable_aspm(struct rtsx_pcr *pcr)
133 if (pcr->ops->set_aspm)
134 pcr->ops->set_aspm(pcr, false);
136 rtsx_comm_set_aspm(pcr, false);
139 int rtsx_set_l1off_sub(struct rtsx_pcr *pcr, u8 val)
141 rtsx_pci_write_register(pcr, L1SUB_CONFIG3, 0xFF, val);
146 static void rtsx_set_l1off_sub_cfg_d0(struct rtsx_pcr *pcr, int active)
148 if (pcr->ops->set_l1off_cfg_sub_d0)
149 pcr->ops->set_l1off_cfg_sub_d0(pcr, active);
152 static void rtsx_comm_pm_full_on(struct rtsx_pcr *pcr)
154 struct rtsx_cr_option *option = &pcr->option;
156 rtsx_disable_aspm(pcr);
158 /* Fixes DMA transfer timout issue after disabling ASPM on RTS5260 */
161 if (option->ltr_enabled)
162 rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
164 if (rtsx_check_dev_flag(pcr, LTR_L1SS_PWR_GATE_EN))
165 rtsx_set_l1off_sub_cfg_d0(pcr, 1);
168 static void rtsx_pm_full_on(struct rtsx_pcr *pcr)
170 if (pcr->ops->full_on)
171 pcr->ops->full_on(pcr);
173 rtsx_comm_pm_full_on(pcr);
176 void rtsx_pci_start_run(struct rtsx_pcr *pcr)
178 /* If pci device removed, don't queue idle work any more */
182 if (pcr->state != PDEV_STAT_RUN) {
183 pcr->state = PDEV_STAT_RUN;
184 if (pcr->ops->enable_auto_blink)
185 pcr->ops->enable_auto_blink(pcr);
186 rtsx_pm_full_on(pcr);
189 mod_delayed_work(system_wq, &pcr->idle_work, msecs_to_jiffies(200));
191 EXPORT_SYMBOL_GPL(rtsx_pci_start_run);
193 int rtsx_pci_write_register(struct rtsx_pcr *pcr, u16 addr, u8 mask, u8 data)
196 u32 val = HAIMR_WRITE_START;
198 val |= (u32)(addr & 0x3FFF) << 16;
199 val |= (u32)mask << 8;
202 rtsx_pci_writel(pcr, RTSX_HAIMR, val);
204 for (i = 0; i < MAX_RW_REG_CNT; i++) {
205 val = rtsx_pci_readl(pcr, RTSX_HAIMR);
206 if ((val & HAIMR_TRANS_END) == 0) {
215 EXPORT_SYMBOL_GPL(rtsx_pci_write_register);
217 int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data)
219 u32 val = HAIMR_READ_START;
222 val |= (u32)(addr & 0x3FFF) << 16;
223 rtsx_pci_writel(pcr, RTSX_HAIMR, val);
225 for (i = 0; i < MAX_RW_REG_CNT; i++) {
226 val = rtsx_pci_readl(pcr, RTSX_HAIMR);
227 if ((val & HAIMR_TRANS_END) == 0)
231 if (i >= MAX_RW_REG_CNT)
235 *data = (u8)(val & 0xFF);
239 EXPORT_SYMBOL_GPL(rtsx_pci_read_register);
241 int __rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val)
243 int err, i, finished = 0;
246 rtsx_pci_init_cmd(pcr);
248 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYDATA0, 0xFF, (u8)val);
249 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYDATA1, 0xFF, (u8)(val >> 8));
250 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYADDR, 0xFF, addr);
251 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYRWCTL, 0xFF, 0x81);
253 err = rtsx_pci_send_cmd(pcr, 100);
257 for (i = 0; i < 100000; i++) {
258 err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
274 int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val)
276 if (pcr->ops->write_phy)
277 return pcr->ops->write_phy(pcr, addr, val);
279 return __rtsx_pci_write_phy_register(pcr, addr, val);
281 EXPORT_SYMBOL_GPL(rtsx_pci_write_phy_register);
283 int __rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val)
285 int err, i, finished = 0;
289 rtsx_pci_init_cmd(pcr);
291 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYADDR, 0xFF, addr);
292 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYRWCTL, 0xFF, 0x80);
294 err = rtsx_pci_send_cmd(pcr, 100);
298 for (i = 0; i < 100000; i++) {
299 err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
312 rtsx_pci_init_cmd(pcr);
314 rtsx_pci_add_cmd(pcr, READ_REG_CMD, PHYDATA0, 0, 0);
315 rtsx_pci_add_cmd(pcr, READ_REG_CMD, PHYDATA1, 0, 0);
317 err = rtsx_pci_send_cmd(pcr, 100);
321 ptr = rtsx_pci_get_cmd_data(pcr);
322 data = ((u16)ptr[1] << 8) | ptr[0];
330 int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val)
332 if (pcr->ops->read_phy)
333 return pcr->ops->read_phy(pcr, addr, val);
335 return __rtsx_pci_read_phy_register(pcr, addr, val);
337 EXPORT_SYMBOL_GPL(rtsx_pci_read_phy_register);
339 void rtsx_pci_stop_cmd(struct rtsx_pcr *pcr)
341 if (pcr->ops->stop_cmd)
342 return pcr->ops->stop_cmd(pcr);
344 rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD);
345 rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA);
347 rtsx_pci_write_register(pcr, DMACTL, 0x80, 0x80);
348 rtsx_pci_write_register(pcr, RBCTL, 0x80, 0x80);
350 EXPORT_SYMBOL_GPL(rtsx_pci_stop_cmd);
352 void rtsx_pci_add_cmd(struct rtsx_pcr *pcr,
353 u8 cmd_type, u16 reg_addr, u8 mask, u8 data)
357 u32 *ptr = (u32 *)(pcr->host_cmds_ptr);
359 val |= (u32)(cmd_type & 0x03) << 30;
360 val |= (u32)(reg_addr & 0x3FFF) << 16;
361 val |= (u32)mask << 8;
364 spin_lock_irqsave(&pcr->lock, flags);
366 if (pcr->ci < (HOST_CMDS_BUF_LEN / 4)) {
367 put_unaligned_le32(val, ptr);
371 spin_unlock_irqrestore(&pcr->lock, flags);
373 EXPORT_SYMBOL_GPL(rtsx_pci_add_cmd);
375 void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr *pcr)
379 rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
381 val |= (u32)(pcr->ci * 4) & 0x00FFFFFF;
382 /* Hardware Auto Response */
384 rtsx_pci_writel(pcr, RTSX_HCBCTLR, val);
386 EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd_no_wait);
388 int rtsx_pci_send_cmd(struct rtsx_pcr *pcr, int timeout)
390 struct completion trans_done;
396 spin_lock_irqsave(&pcr->lock, flags);
398 /* set up data structures for the wakeup system */
399 pcr->done = &trans_done;
400 pcr->trans_result = TRANS_NOT_READY;
401 init_completion(&trans_done);
403 rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
405 val |= (u32)(pcr->ci * 4) & 0x00FFFFFF;
406 /* Hardware Auto Response */
408 rtsx_pci_writel(pcr, RTSX_HCBCTLR, val);
410 spin_unlock_irqrestore(&pcr->lock, flags);
412 /* Wait for TRANS_OK_INT */
413 timeleft = wait_for_completion_interruptible_timeout(
414 &trans_done, msecs_to_jiffies(timeout));
416 pcr_dbg(pcr, "Timeout (%s %d)\n", __func__, __LINE__);
418 goto finish_send_cmd;
421 spin_lock_irqsave(&pcr->lock, flags);
422 if (pcr->trans_result == TRANS_RESULT_FAIL)
424 else if (pcr->trans_result == TRANS_RESULT_OK)
426 else if (pcr->trans_result == TRANS_NO_DEVICE)
428 spin_unlock_irqrestore(&pcr->lock, flags);
431 spin_lock_irqsave(&pcr->lock, flags);
433 spin_unlock_irqrestore(&pcr->lock, flags);
435 if ((err < 0) && (err != -ENODEV))
436 rtsx_pci_stop_cmd(pcr);
439 complete(pcr->finish_me);
443 EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd);
445 static void rtsx_pci_add_sg_tbl(struct rtsx_pcr *pcr,
446 dma_addr_t addr, unsigned int len, int end)
448 u64 *ptr = (u64 *)(pcr->host_sg_tbl_ptr) + pcr->sgi;
450 u8 option = RTSX_SG_VALID | RTSX_SG_TRANS_DATA;
452 pcr_dbg(pcr, "DMA addr: 0x%x, Len: 0x%x\n", (unsigned int)addr, len);
455 option |= RTSX_SG_END;
456 val = ((u64)addr << 32) | ((u64)len << 12) | option;
458 put_unaligned_le64(val, ptr);
462 int rtsx_pci_transfer_data(struct rtsx_pcr *pcr, struct scatterlist *sglist,
463 int num_sg, bool read, int timeout)
467 pcr_dbg(pcr, "--> %s: num_sg = %d\n", __func__, num_sg);
468 count = rtsx_pci_dma_map_sg(pcr, sglist, num_sg, read);
471 pcr_dbg(pcr, "DMA mapping count: %d\n", count);
473 err = rtsx_pci_dma_transfer(pcr, sglist, count, read, timeout);
475 rtsx_pci_dma_unmap_sg(pcr, sglist, num_sg, read);
479 EXPORT_SYMBOL_GPL(rtsx_pci_transfer_data);
481 int rtsx_pci_dma_map_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist,
482 int num_sg, bool read)
484 enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
489 if ((sglist == NULL) || (num_sg <= 0))
492 return dma_map_sg(&(pcr->pci->dev), sglist, num_sg, dir);
494 EXPORT_SYMBOL_GPL(rtsx_pci_dma_map_sg);
496 void rtsx_pci_dma_unmap_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist,
497 int num_sg, bool read)
499 enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
501 dma_unmap_sg(&(pcr->pci->dev), sglist, num_sg, dir);
503 EXPORT_SYMBOL_GPL(rtsx_pci_dma_unmap_sg);
505 int rtsx_pci_dma_transfer(struct rtsx_pcr *pcr, struct scatterlist *sglist,
506 int count, bool read, int timeout)
508 struct completion trans_done;
509 struct scatterlist *sg;
516 u8 dir = read ? DEVICE_TO_HOST : HOST_TO_DEVICE;
521 if ((sglist == NULL) || (count < 1))
524 val = ((u32)(dir & 0x01) << 29) | TRIG_DMA | ADMA_MODE;
526 for_each_sg(sglist, sg, count, i) {
527 addr = sg_dma_address(sg);
528 len = sg_dma_len(sg);
529 rtsx_pci_add_sg_tbl(pcr, addr, len, i == count - 1);
532 spin_lock_irqsave(&pcr->lock, flags);
534 pcr->done = &trans_done;
535 pcr->trans_result = TRANS_NOT_READY;
536 init_completion(&trans_done);
537 rtsx_pci_writel(pcr, RTSX_HDBAR, pcr->host_sg_tbl_addr);
538 rtsx_pci_writel(pcr, RTSX_HDBCTLR, val);
540 spin_unlock_irqrestore(&pcr->lock, flags);
542 timeleft = wait_for_completion_interruptible_timeout(
543 &trans_done, msecs_to_jiffies(timeout));
545 pcr_dbg(pcr, "Timeout (%s %d)\n", __func__, __LINE__);
550 spin_lock_irqsave(&pcr->lock, flags);
551 if (pcr->trans_result == TRANS_RESULT_FAIL) {
553 if (pcr->dma_error_count < RTS_MAX_TIMES_FREQ_REDUCTION)
554 pcr->dma_error_count++;
557 else if (pcr->trans_result == TRANS_NO_DEVICE)
559 spin_unlock_irqrestore(&pcr->lock, flags);
562 spin_lock_irqsave(&pcr->lock, flags);
564 spin_unlock_irqrestore(&pcr->lock, flags);
566 if ((err < 0) && (err != -ENODEV))
567 rtsx_pci_stop_cmd(pcr);
570 complete(pcr->finish_me);
574 EXPORT_SYMBOL_GPL(rtsx_pci_dma_transfer);
576 int rtsx_pci_read_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len)
588 for (i = 0; i < buf_len / 256; i++) {
589 rtsx_pci_init_cmd(pcr);
591 for (j = 0; j < 256; j++)
592 rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);
594 err = rtsx_pci_send_cmd(pcr, 250);
598 memcpy(ptr, rtsx_pci_get_cmd_data(pcr), 256);
603 rtsx_pci_init_cmd(pcr);
605 for (j = 0; j < buf_len % 256; j++)
606 rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);
608 err = rtsx_pci_send_cmd(pcr, 250);
613 memcpy(ptr, rtsx_pci_get_cmd_data(pcr), buf_len % 256);
617 EXPORT_SYMBOL_GPL(rtsx_pci_read_ppbuf);
619 int rtsx_pci_write_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len)
631 for (i = 0; i < buf_len / 256; i++) {
632 rtsx_pci_init_cmd(pcr);
634 for (j = 0; j < 256; j++) {
635 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
640 err = rtsx_pci_send_cmd(pcr, 250);
646 rtsx_pci_init_cmd(pcr);
648 for (j = 0; j < buf_len % 256; j++) {
649 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
654 err = rtsx_pci_send_cmd(pcr, 250);
661 EXPORT_SYMBOL_GPL(rtsx_pci_write_ppbuf);
663 static int rtsx_pci_set_pull_ctl(struct rtsx_pcr *pcr, const u32 *tbl)
665 rtsx_pci_init_cmd(pcr);
667 while (*tbl & 0xFFFF0000) {
668 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
669 (u16)(*tbl >> 16), 0xFF, (u8)(*tbl));
673 return rtsx_pci_send_cmd(pcr, 100);
676 int rtsx_pci_card_pull_ctl_enable(struct rtsx_pcr *pcr, int card)
680 if (card == RTSX_SD_CARD)
681 tbl = pcr->sd_pull_ctl_enable_tbl;
682 else if (card == RTSX_MS_CARD)
683 tbl = pcr->ms_pull_ctl_enable_tbl;
687 return rtsx_pci_set_pull_ctl(pcr, tbl);
689 EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_enable);
691 int rtsx_pci_card_pull_ctl_disable(struct rtsx_pcr *pcr, int card)
695 if (card == RTSX_SD_CARD)
696 tbl = pcr->sd_pull_ctl_disable_tbl;
697 else if (card == RTSX_MS_CARD)
698 tbl = pcr->ms_pull_ctl_disable_tbl;
703 return rtsx_pci_set_pull_ctl(pcr, tbl);
705 EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_disable);
707 static void rtsx_pci_enable_bus_int(struct rtsx_pcr *pcr)
709 pcr->bier = TRANS_OK_INT_EN | TRANS_FAIL_INT_EN | SD_INT_EN;
711 if (pcr->num_slots > 1)
712 pcr->bier |= MS_INT_EN;
714 /* Enable Bus Interrupt */
715 rtsx_pci_writel(pcr, RTSX_BIER, pcr->bier);
717 pcr_dbg(pcr, "RTSX_BIER: 0x%08x\n", pcr->bier);
720 static inline u8 double_ssc_depth(u8 depth)
722 return ((depth > 1) ? (depth - 1) : depth);
725 static u8 revise_ssc_depth(u8 ssc_depth, u8 div)
727 if (div > CLK_DIV_1) {
728 if (ssc_depth > (div - 1))
729 ssc_depth -= (div - 1);
731 ssc_depth = SSC_DEPTH_4M;
737 int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
738 u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk)
741 u8 n, clk_divider, mcu_cnt, div;
742 static const u8 depth[] = {
743 [RTSX_SSC_DEPTH_4M] = SSC_DEPTH_4M,
744 [RTSX_SSC_DEPTH_2M] = SSC_DEPTH_2M,
745 [RTSX_SSC_DEPTH_1M] = SSC_DEPTH_1M,
746 [RTSX_SSC_DEPTH_500K] = SSC_DEPTH_500K,
747 [RTSX_SSC_DEPTH_250K] = SSC_DEPTH_250K,
751 /* We use 250k(around) here, in initial stage */
752 clk_divider = SD_CLK_DIVIDE_128;
753 card_clock = 30000000;
755 clk_divider = SD_CLK_DIVIDE_0;
757 err = rtsx_pci_write_register(pcr, SD_CFG1,
758 SD_CLK_DIVIDE_MASK, clk_divider);
762 /* Reduce card clock by 20MHz each time a DMA transfer error occurs */
763 if (card_clock == UHS_SDR104_MAX_DTR &&
764 pcr->dma_error_count &&
765 PCI_PID(pcr) == RTS5227_DEVICE_ID)
766 card_clock = UHS_SDR104_MAX_DTR -
767 (pcr->dma_error_count * 20000000);
769 card_clock /= 1000000;
770 pcr_dbg(pcr, "Switch card clock to %dMHz\n", card_clock);
773 if (!initial_mode && double_clk)
774 clk = card_clock * 2;
775 pcr_dbg(pcr, "Internal SSC clock: %dMHz (cur_clock = %d)\n",
776 clk, pcr->cur_clock);
778 if (clk == pcr->cur_clock)
781 if (pcr->ops->conv_clk_and_div_n)
782 n = (u8)pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N);
785 if ((clk <= 2) || (n > MAX_DIV_N_PCR))
788 mcu_cnt = (u8)(125/clk + 3);
792 /* Make sure that the SSC clock div_n is not less than MIN_DIV_N_PCR */
794 while ((n < MIN_DIV_N_PCR) && (div < CLK_DIV_8)) {
795 if (pcr->ops->conv_clk_and_div_n) {
796 int dbl_clk = pcr->ops->conv_clk_and_div_n(n,
798 n = (u8)pcr->ops->conv_clk_and_div_n(dbl_clk,
805 pcr_dbg(pcr, "n = %d, div = %d\n", n, div);
807 ssc_depth = depth[ssc_depth];
809 ssc_depth = double_ssc_depth(ssc_depth);
811 ssc_depth = revise_ssc_depth(ssc_depth, div);
812 pcr_dbg(pcr, "ssc_depth = %d\n", ssc_depth);
814 rtsx_pci_init_cmd(pcr);
815 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
816 CLK_LOW_FREQ, CLK_LOW_FREQ);
817 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV,
818 0xFF, (div << 4) | mcu_cnt);
819 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
820 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2,
821 SSC_DEPTH_MASK, ssc_depth);
822 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n);
823 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB);
825 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
827 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
828 PHASE_NOT_RESET, PHASE_NOT_RESET);
831 err = rtsx_pci_send_cmd(pcr, 2000);
835 /* Wait SSC clock stable */
836 udelay(SSC_CLOCK_STABLE_WAIT);
837 err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
841 pcr->cur_clock = clk;
844 EXPORT_SYMBOL_GPL(rtsx_pci_switch_clock);
846 int rtsx_pci_card_power_on(struct rtsx_pcr *pcr, int card)
848 if (pcr->ops->card_power_on)
849 return pcr->ops->card_power_on(pcr, card);
853 EXPORT_SYMBOL_GPL(rtsx_pci_card_power_on);
855 int rtsx_pci_card_power_off(struct rtsx_pcr *pcr, int card)
857 if (pcr->ops->card_power_off)
858 return pcr->ops->card_power_off(pcr, card);
862 EXPORT_SYMBOL_GPL(rtsx_pci_card_power_off);
864 int rtsx_pci_card_exclusive_check(struct rtsx_pcr *pcr, int card)
866 static const unsigned int cd_mask[] = {
867 [RTSX_SD_CARD] = SD_EXIST,
868 [RTSX_MS_CARD] = MS_EXIST
871 if (!(pcr->flags & PCR_MS_PMOS)) {
872 /* When using single PMOS, accessing card is not permitted
873 * if the existing card is not the designated one.
875 if (pcr->card_exist & (~cd_mask[card]))
881 EXPORT_SYMBOL_GPL(rtsx_pci_card_exclusive_check);
883 int rtsx_pci_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
885 if (pcr->ops->switch_output_voltage)
886 return pcr->ops->switch_output_voltage(pcr, voltage);
890 EXPORT_SYMBOL_GPL(rtsx_pci_switch_output_voltage);
892 unsigned int rtsx_pci_card_exist(struct rtsx_pcr *pcr)
896 val = rtsx_pci_readl(pcr, RTSX_BIPR);
897 if (pcr->ops->cd_deglitch)
898 val = pcr->ops->cd_deglitch(pcr);
902 EXPORT_SYMBOL_GPL(rtsx_pci_card_exist);
904 void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr *pcr)
906 struct completion finish;
908 pcr->finish_me = &finish;
909 init_completion(&finish);
914 if (!pcr->remove_pci)
915 rtsx_pci_stop_cmd(pcr);
917 wait_for_completion_interruptible_timeout(&finish,
918 msecs_to_jiffies(2));
919 pcr->finish_me = NULL;
921 EXPORT_SYMBOL_GPL(rtsx_pci_complete_unfinished_transfer);
923 static void rtsx_pci_card_detect(struct work_struct *work)
925 struct delayed_work *dwork;
926 struct rtsx_pcr *pcr;
928 unsigned int card_detect = 0, card_inserted, card_removed;
931 dwork = to_delayed_work(work);
932 pcr = container_of(dwork, struct rtsx_pcr, carddet_work);
934 pcr_dbg(pcr, "--> %s\n", __func__);
936 mutex_lock(&pcr->pcr_mutex);
937 spin_lock_irqsave(&pcr->lock, flags);
939 irq_status = rtsx_pci_readl(pcr, RTSX_BIPR);
940 pcr_dbg(pcr, "irq_status: 0x%08x\n", irq_status);
942 irq_status &= CARD_EXIST;
943 card_inserted = pcr->card_inserted & irq_status;
944 card_removed = pcr->card_removed;
945 pcr->card_inserted = 0;
946 pcr->card_removed = 0;
948 spin_unlock_irqrestore(&pcr->lock, flags);
950 if (card_inserted || card_removed) {
951 pcr_dbg(pcr, "card_inserted: 0x%x, card_removed: 0x%x\n",
952 card_inserted, card_removed);
954 if (pcr->ops->cd_deglitch)
955 card_inserted = pcr->ops->cd_deglitch(pcr);
957 card_detect = card_inserted | card_removed;
959 pcr->card_exist |= card_inserted;
960 pcr->card_exist &= ~card_removed;
963 mutex_unlock(&pcr->pcr_mutex);
965 if ((card_detect & SD_EXIST) && pcr->slots[RTSX_SD_CARD].card_event)
966 pcr->slots[RTSX_SD_CARD].card_event(
967 pcr->slots[RTSX_SD_CARD].p_dev);
968 if ((card_detect & MS_EXIST) && pcr->slots[RTSX_MS_CARD].card_event)
969 pcr->slots[RTSX_MS_CARD].card_event(
970 pcr->slots[RTSX_MS_CARD].p_dev);
973 static void rtsx_pci_process_ocp(struct rtsx_pcr *pcr)
975 if (pcr->ops->process_ocp)
976 pcr->ops->process_ocp(pcr);
979 static int rtsx_pci_process_ocp_interrupt(struct rtsx_pcr *pcr)
981 if (pcr->option.ocp_en)
982 rtsx_pci_process_ocp(pcr);
987 static irqreturn_t rtsx_pci_isr(int irq, void *dev_id)
989 struct rtsx_pcr *pcr = dev_id;
995 spin_lock(&pcr->lock);
997 int_reg = rtsx_pci_readl(pcr, RTSX_BIPR);
998 /* Clear interrupt flag */
999 rtsx_pci_writel(pcr, RTSX_BIPR, int_reg);
1000 if ((int_reg & pcr->bier) == 0) {
1001 spin_unlock(&pcr->lock);
1004 if (int_reg == 0xFFFFFFFF) {
1005 spin_unlock(&pcr->lock);
1009 int_reg &= (pcr->bier | 0x7FFFFF);
1011 if (int_reg & SD_OC_INT)
1012 rtsx_pci_process_ocp_interrupt(pcr);
1014 if (int_reg & SD_INT) {
1015 if (int_reg & SD_EXIST) {
1016 pcr->card_inserted |= SD_EXIST;
1018 pcr->card_removed |= SD_EXIST;
1019 pcr->card_inserted &= ~SD_EXIST;
1021 pcr->dma_error_count = 0;
1024 if (int_reg & MS_INT) {
1025 if (int_reg & MS_EXIST) {
1026 pcr->card_inserted |= MS_EXIST;
1028 pcr->card_removed |= MS_EXIST;
1029 pcr->card_inserted &= ~MS_EXIST;
1033 if (int_reg & (NEED_COMPLETE_INT | DELINK_INT)) {
1034 if (int_reg & (TRANS_FAIL_INT | DELINK_INT)) {
1035 pcr->trans_result = TRANS_RESULT_FAIL;
1037 complete(pcr->done);
1038 } else if (int_reg & TRANS_OK_INT) {
1039 pcr->trans_result = TRANS_RESULT_OK;
1041 complete(pcr->done);
1045 if (pcr->card_inserted || pcr->card_removed)
1046 schedule_delayed_work(&pcr->carddet_work,
1047 msecs_to_jiffies(200));
1049 spin_unlock(&pcr->lock);
1053 static int rtsx_pci_acquire_irq(struct rtsx_pcr *pcr)
1055 pcr_dbg(pcr, "%s: pcr->msi_en = %d, pci->irq = %d\n",
1056 __func__, pcr->msi_en, pcr->pci->irq);
1058 if (request_irq(pcr->pci->irq, rtsx_pci_isr,
1059 pcr->msi_en ? 0 : IRQF_SHARED,
1060 DRV_NAME_RTSX_PCI, pcr)) {
1061 dev_err(&(pcr->pci->dev),
1062 "rtsx_sdmmc: unable to grab IRQ %d, disabling device\n",
1067 pcr->irq = pcr->pci->irq;
1068 pci_intx(pcr->pci, !pcr->msi_en);
1073 static void rtsx_enable_aspm(struct rtsx_pcr *pcr)
1075 if (pcr->ops->set_aspm)
1076 pcr->ops->set_aspm(pcr, true);
1078 rtsx_comm_set_aspm(pcr, true);
1081 static void rtsx_comm_pm_power_saving(struct rtsx_pcr *pcr)
1083 struct rtsx_cr_option *option = &pcr->option;
1085 if (option->ltr_enabled) {
1086 u32 latency = option->ltr_l1off_latency;
1088 if (rtsx_check_dev_flag(pcr, L1_SNOOZE_TEST_EN))
1089 mdelay(option->l1_snooze_delay);
1091 rtsx_set_ltr_latency(pcr, latency);
1094 if (rtsx_check_dev_flag(pcr, LTR_L1SS_PWR_GATE_EN))
1095 rtsx_set_l1off_sub_cfg_d0(pcr, 0);
1097 rtsx_enable_aspm(pcr);
1100 static void rtsx_pm_power_saving(struct rtsx_pcr *pcr)
1102 if (pcr->ops->power_saving)
1103 pcr->ops->power_saving(pcr);
1105 rtsx_comm_pm_power_saving(pcr);
1108 static void rtsx_pci_idle_work(struct work_struct *work)
1110 struct delayed_work *dwork = to_delayed_work(work);
1111 struct rtsx_pcr *pcr = container_of(dwork, struct rtsx_pcr, idle_work);
1113 pcr_dbg(pcr, "--> %s\n", __func__);
1115 mutex_lock(&pcr->pcr_mutex);
1117 pcr->state = PDEV_STAT_IDLE;
1119 if (pcr->ops->disable_auto_blink)
1120 pcr->ops->disable_auto_blink(pcr);
1121 if (pcr->ops->turn_off_led)
1122 pcr->ops->turn_off_led(pcr);
1124 rtsx_pm_power_saving(pcr);
1126 mutex_unlock(&pcr->pcr_mutex);
1130 static void rtsx_pci_power_off(struct rtsx_pcr *pcr, u8 pm_state)
1132 if (pcr->ops->turn_off_led)
1133 pcr->ops->turn_off_led(pcr);
1135 rtsx_pci_writel(pcr, RTSX_BIER, 0);
1138 rtsx_pci_write_register(pcr, PETXCFG, 0x08, 0x08);
1139 rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, pm_state);
1141 if (pcr->ops->force_power_down)
1142 pcr->ops->force_power_down(pcr, pm_state);
1146 void rtsx_pci_enable_ocp(struct rtsx_pcr *pcr)
1148 u8 val = SD_OCP_INT_EN | SD_DETECT_EN;
1150 if (pcr->ops->enable_ocp)
1151 pcr->ops->enable_ocp(pcr);
1153 rtsx_pci_write_register(pcr, REG_OCPCTL, 0xFF, val);
1157 void rtsx_pci_disable_ocp(struct rtsx_pcr *pcr)
1159 u8 mask = SD_OCP_INT_EN | SD_DETECT_EN;
1161 if (pcr->ops->disable_ocp)
1162 pcr->ops->disable_ocp(pcr);
1164 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
1167 void rtsx_pci_init_ocp(struct rtsx_pcr *pcr)
1169 if (pcr->ops->init_ocp) {
1170 pcr->ops->init_ocp(pcr);
1172 struct rtsx_cr_option *option = &(pcr->option);
1174 if (option->ocp_en) {
1175 u8 val = option->sd_400mA_ocp_thd;
1177 rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN, 0);
1178 rtsx_pci_write_register(pcr, REG_OCPPARA1,
1179 SD_OCP_TIME_MASK, SD_OCP_TIME_800);
1180 rtsx_pci_write_register(pcr, REG_OCPPARA2,
1181 SD_OCP_THD_MASK, val);
1182 rtsx_pci_write_register(pcr, REG_OCPGLITCH,
1183 SD_OCP_GLITCH_MASK, pcr->hw_param.ocp_glitch);
1184 rtsx_pci_enable_ocp(pcr);
1187 rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN,
1193 int rtsx_pci_get_ocpstat(struct rtsx_pcr *pcr, u8 *val)
1195 if (pcr->ops->get_ocpstat)
1196 return pcr->ops->get_ocpstat(pcr, val);
1198 return rtsx_pci_read_register(pcr, REG_OCPSTAT, val);
1201 void rtsx_pci_clear_ocpstat(struct rtsx_pcr *pcr)
1203 if (pcr->ops->clear_ocpstat) {
1204 pcr->ops->clear_ocpstat(pcr);
1206 u8 mask = SD_OCP_INT_CLR | SD_OC_CLR;
1207 u8 val = SD_OCP_INT_CLR | SD_OC_CLR;
1209 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, val);
1210 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
1214 int rtsx_sd_power_off_card3v3(struct rtsx_pcr *pcr)
1216 rtsx_pci_write_register(pcr, CARD_CLK_EN, SD_CLK_EN |
1217 MS_CLK_EN | SD40_CLK_EN, 0);
1218 rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0);
1220 rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);
1224 rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD);
1229 int rtsx_ms_power_off_card3v3(struct rtsx_pcr *pcr)
1231 rtsx_pci_write_register(pcr, CARD_CLK_EN, SD_CLK_EN |
1232 MS_CLK_EN | SD40_CLK_EN, 0);
1234 rtsx_pci_card_pull_ctl_disable(pcr, RTSX_MS_CARD);
1236 rtsx_pci_write_register(pcr, CARD_OE, MS_OUTPUT_EN, 0);
1237 rtsx_pci_card_power_off(pcr, RTSX_MS_CARD);
1242 static int rtsx_pci_init_hw(struct rtsx_pcr *pcr)
1246 pcr->pcie_cap = pci_find_capability(pcr->pci, PCI_CAP_ID_EXP);
1247 rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
1249 rtsx_pci_enable_bus_int(pcr);
1252 err = rtsx_pci_write_register(pcr, FPDCTL, SSC_POWER_DOWN, 0);
1256 /* Wait SSC power stable */
1259 rtsx_pci_disable_aspm(pcr);
1260 if (pcr->ops->optimize_phy) {
1261 err = pcr->ops->optimize_phy(pcr);
1266 rtsx_pci_init_cmd(pcr);
1268 /* Set mcu_cnt to 7 to ensure data can be sampled properly */
1269 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, 0x07, 0x07);
1271 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, HOST_SLEEP_STATE, 0x03, 0x00);
1272 /* Disable card clock */
1273 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, 0x1E, 0);
1274 /* Reset delink mode */
1275 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x0A, 0);
1276 /* Card driving select */
1277 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DRIVE_SEL,
1278 0xFF, pcr->card_drive_sel);
1279 /* Enable SSC Clock */
1280 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1,
1281 0xFF, SSC_8X_EN | SSC_SEL_4M);
1282 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF, 0x12);
1283 /* Disable cd_pwr_save */
1284 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x16, 0x10);
1285 /* Clear Link Ready Interrupt */
1286 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
1287 LINK_RDY_INT, LINK_RDY_INT);
1288 /* Enlarge the estimation window of PERST# glitch
1289 * to reduce the chance of invalid card interrupt
1291 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PERST_GLITCH_WIDTH, 0xFF, 0x80);
1292 /* Update RC oscillator to 400k
1293 * bit[0] F_HIGH: for RC oscillator, Rst_value is 1'b1
1296 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RCCTL, 0x01, 0x00);
1297 /* Set interrupt write clear
1298 * bit 1: U_elbi_if_rd_clr_en
1299 * 1: Enable ELBI interrupt[31:22] & [7:0] flag read clear
1300 * 0: ELBI interrupt flag[31:22] & [7:0] only can be write clear
1302 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, NFTS_TX_CTRL, 0x02, 0);
1304 err = rtsx_pci_send_cmd(pcr, 100);
1308 switch (PCI_PID(pcr)) {
1313 rtsx_pci_write_register(pcr, PM_CLK_FORCE_CTL, 1, 1);
1319 /* Enable clk_request_n to enable clock power management */
1320 rtsx_pci_write_config_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL + 1, 1);
1321 /* Enter L1 when host tx idle */
1322 rtsx_pci_write_config_byte(pcr, 0x70F, 0x5B);
1324 if (pcr->ops->extra_init_hw) {
1325 err = pcr->ops->extra_init_hw(pcr);
1330 /* No CD interrupt if probing driver with card inserted.
1331 * So we need to initialize pcr->card_exist here.
1333 if (pcr->ops->cd_deglitch)
1334 pcr->card_exist = pcr->ops->cd_deglitch(pcr);
1336 pcr->card_exist = rtsx_pci_readl(pcr, RTSX_BIPR) & CARD_EXIST;
1341 static int rtsx_pci_init_chip(struct rtsx_pcr *pcr)
1345 spin_lock_init(&pcr->lock);
1346 mutex_init(&pcr->pcr_mutex);
1348 switch (PCI_PID(pcr)) {
1351 rts5209_init_params(pcr);
1355 rts5229_init_params(pcr);
1359 rtl8411_init_params(pcr);
1363 rts5227_init_params(pcr);
1367 rts522a_init_params(pcr);
1371 rts5249_init_params(pcr);
1375 rts524a_init_params(pcr);
1379 rts525a_init_params(pcr);
1383 rtl8411b_init_params(pcr);
1387 rtl8402_init_params(pcr);
1390 rts5260_init_params(pcr);
1394 pcr_dbg(pcr, "PID: 0x%04x, IC version: 0x%02x\n",
1395 PCI_PID(pcr), pcr->ic_version);
1397 pcr->slots = kcalloc(pcr->num_slots, sizeof(struct rtsx_slot),
1402 if (pcr->ops->fetch_vendor_settings)
1403 pcr->ops->fetch_vendor_settings(pcr);
1405 pcr_dbg(pcr, "pcr->aspm_en = 0x%x\n", pcr->aspm_en);
1406 pcr_dbg(pcr, "pcr->sd30_drive_sel_1v8 = 0x%x\n",
1407 pcr->sd30_drive_sel_1v8);
1408 pcr_dbg(pcr, "pcr->sd30_drive_sel_3v3 = 0x%x\n",
1409 pcr->sd30_drive_sel_3v3);
1410 pcr_dbg(pcr, "pcr->card_drive_sel = 0x%x\n",
1411 pcr->card_drive_sel);
1412 pcr_dbg(pcr, "pcr->flags = 0x%x\n", pcr->flags);
1414 pcr->state = PDEV_STAT_IDLE;
1415 err = rtsx_pci_init_hw(pcr);
1424 static int rtsx_pci_probe(struct pci_dev *pcidev,
1425 const struct pci_device_id *id)
1427 struct rtsx_pcr *pcr;
1428 struct pcr_handle *handle;
1430 int ret, i, bar = 0;
1432 dev_dbg(&(pcidev->dev),
1433 ": Realtek PCI-E Card Reader found at %s [%04x:%04x] (rev %x)\n",
1434 pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device,
1435 (int)pcidev->revision);
1437 ret = pci_set_dma_mask(pcidev, DMA_BIT_MASK(32));
1441 ret = pci_enable_device(pcidev);
1445 ret = pci_request_regions(pcidev, DRV_NAME_RTSX_PCI);
1449 pcr = kzalloc(sizeof(*pcr), GFP_KERNEL);
1455 handle = kzalloc(sizeof(*handle), GFP_KERNEL);
1462 idr_preload(GFP_KERNEL);
1463 spin_lock(&rtsx_pci_lock);
1464 ret = idr_alloc(&rtsx_pci_idr, pcr, 0, 0, GFP_NOWAIT);
1467 spin_unlock(&rtsx_pci_lock);
1473 dev_set_drvdata(&pcidev->dev, handle);
1475 if (CHK_PCI_PID(pcr, 0x525A))
1477 len = pci_resource_len(pcidev, bar);
1478 base = pci_resource_start(pcidev, bar);
1479 pcr->remap_addr = ioremap_nocache(base, len);
1480 if (!pcr->remap_addr) {
1485 pcr->rtsx_resv_buf = dma_alloc_coherent(&(pcidev->dev),
1486 RTSX_RESV_BUF_LEN, &(pcr->rtsx_resv_buf_addr),
1488 if (pcr->rtsx_resv_buf == NULL) {
1492 pcr->host_cmds_ptr = pcr->rtsx_resv_buf;
1493 pcr->host_cmds_addr = pcr->rtsx_resv_buf_addr;
1494 pcr->host_sg_tbl_ptr = pcr->rtsx_resv_buf + HOST_CMDS_BUF_LEN;
1495 pcr->host_sg_tbl_addr = pcr->rtsx_resv_buf_addr + HOST_CMDS_BUF_LEN;
1497 pcr->card_inserted = 0;
1498 pcr->card_removed = 0;
1499 INIT_DELAYED_WORK(&pcr->carddet_work, rtsx_pci_card_detect);
1500 INIT_DELAYED_WORK(&pcr->idle_work, rtsx_pci_idle_work);
1502 pcr->msi_en = msi_en;
1504 ret = pci_enable_msi(pcidev);
1506 pcr->msi_en = false;
1509 ret = rtsx_pci_acquire_irq(pcr);
1513 pci_set_master(pcidev);
1514 synchronize_irq(pcr->irq);
1516 ret = rtsx_pci_init_chip(pcr);
1520 for (i = 0; i < ARRAY_SIZE(rtsx_pcr_cells); i++) {
1521 rtsx_pcr_cells[i].platform_data = handle;
1522 rtsx_pcr_cells[i].pdata_size = sizeof(*handle);
1524 ret = mfd_add_devices(&pcidev->dev, pcr->id, rtsx_pcr_cells,
1525 ARRAY_SIZE(rtsx_pcr_cells), NULL, 0, NULL);
1529 schedule_delayed_work(&pcr->idle_work, msecs_to_jiffies(200));
1536 free_irq(pcr->irq, (void *)pcr);
1539 pci_disable_msi(pcr->pci);
1540 dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN,
1541 pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr);
1543 iounmap(pcr->remap_addr);
1549 pci_release_regions(pcidev);
1551 pci_disable_device(pcidev);
1556 static void rtsx_pci_remove(struct pci_dev *pcidev)
1558 struct pcr_handle *handle = pci_get_drvdata(pcidev);
1559 struct rtsx_pcr *pcr = handle->pcr;
1561 pcr->remove_pci = true;
1563 /* Disable interrupts at the pcr level */
1564 spin_lock_irq(&pcr->lock);
1565 rtsx_pci_writel(pcr, RTSX_BIER, 0);
1567 spin_unlock_irq(&pcr->lock);
1569 cancel_delayed_work_sync(&pcr->carddet_work);
1570 cancel_delayed_work_sync(&pcr->idle_work);
1572 mfd_remove_devices(&pcidev->dev);
1574 dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN,
1575 pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr);
1576 free_irq(pcr->irq, (void *)pcr);
1578 pci_disable_msi(pcr->pci);
1579 iounmap(pcr->remap_addr);
1581 pci_release_regions(pcidev);
1582 pci_disable_device(pcidev);
1584 spin_lock(&rtsx_pci_lock);
1585 idr_remove(&rtsx_pci_idr, pcr->id);
1586 spin_unlock(&rtsx_pci_lock);
1592 dev_dbg(&(pcidev->dev),
1593 ": Realtek PCI-E Card Reader at %s [%04x:%04x] has been removed\n",
1594 pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device);
1599 static int rtsx_pci_suspend(struct pci_dev *pcidev, pm_message_t state)
1601 struct pcr_handle *handle;
1602 struct rtsx_pcr *pcr;
1604 dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
1606 handle = pci_get_drvdata(pcidev);
1609 cancel_delayed_work(&pcr->carddet_work);
1610 cancel_delayed_work(&pcr->idle_work);
1612 mutex_lock(&pcr->pcr_mutex);
1614 rtsx_pci_power_off(pcr, HOST_ENTER_S3);
1616 pci_save_state(pcidev);
1617 pci_enable_wake(pcidev, pci_choose_state(pcidev, state), 0);
1618 pci_disable_device(pcidev);
1619 pci_set_power_state(pcidev, pci_choose_state(pcidev, state));
1621 mutex_unlock(&pcr->pcr_mutex);
1625 static int rtsx_pci_resume(struct pci_dev *pcidev)
1627 struct pcr_handle *handle;
1628 struct rtsx_pcr *pcr;
1631 dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
1633 handle = pci_get_drvdata(pcidev);
1636 mutex_lock(&pcr->pcr_mutex);
1638 pci_set_power_state(pcidev, PCI_D0);
1639 pci_restore_state(pcidev);
1640 ret = pci_enable_device(pcidev);
1643 pci_set_master(pcidev);
1645 ret = rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, 0x00);
1649 ret = rtsx_pci_init_hw(pcr);
1653 schedule_delayed_work(&pcr->idle_work, msecs_to_jiffies(200));
1656 mutex_unlock(&pcr->pcr_mutex);
1660 static void rtsx_pci_shutdown(struct pci_dev *pcidev)
1662 struct pcr_handle *handle;
1663 struct rtsx_pcr *pcr;
1665 dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
1667 handle = pci_get_drvdata(pcidev);
1669 rtsx_pci_power_off(pcr, HOST_ENTER_S1);
1671 pci_disable_device(pcidev);
1672 free_irq(pcr->irq, (void *)pcr);
1674 pci_disable_msi(pcr->pci);
1677 #else /* CONFIG_PM */
1679 #define rtsx_pci_suspend NULL
1680 #define rtsx_pci_resume NULL
1681 #define rtsx_pci_shutdown NULL
1683 #endif /* CONFIG_PM */
1685 static struct pci_driver rtsx_pci_driver = {
1686 .name = DRV_NAME_RTSX_PCI,
1687 .id_table = rtsx_pci_ids,
1688 .probe = rtsx_pci_probe,
1689 .remove = rtsx_pci_remove,
1690 .suspend = rtsx_pci_suspend,
1691 .resume = rtsx_pci_resume,
1692 .shutdown = rtsx_pci_shutdown,
1694 module_pci_driver(rtsx_pci_driver);
1696 MODULE_LICENSE("GPL");
1697 MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
1698 MODULE_DESCRIPTION("Realtek PCI-E Card Reader Driver");