drivers/misc/cardreader/rtsx_pcr.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /* Driver for Realtek PCI-Express card reader
   3  *
   4  * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
   5  *
   6  * Author:
   7  *   Wei WANG <wei_wang@realsil.com.cn>
   8  */
   9
  10 #include <linux/pci.h>
  11 #include <linux/module.h>
  12 #include <linux/slab.h>
  13 #include <linux/dma-mapping.h>
  14 #include <linux/highmem.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/delay.h>
  17 #include <linux/idr.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/mfd/core.h>
  20 #include <linux/rtsx_pci.h>
  21 #include <linux/mmc/card.h>
  22 #include <asm/unaligned.h>
  23
  24 #include "rtsx_pcr.h"
  25 #include "rts5261.h"
  26 #include "rts5228.h"
  27
  28 static bool msi_en = true;
  29 module_param(msi_en, bool, S_IRUGO | S_IWUSR);
  30 MODULE_PARM_DESC(msi_en, "Enable MSI");
  31
  32 static DEFINE_IDR(rtsx_pci_idr);
  33 static DEFINE_SPINLOCK(rtsx_pci_lock);
  34
  35 static struct mfd_cell rtsx_pcr_cells[] = {
  36         [RTSX_SD_CARD] = {
  37                 .name = DRV_NAME_RTSX_PCI_SDMMC,
  38         },
  39 };
  40
  41 static const struct pci_device_id rtsx_pci_ids[] = {
  42         { PCI_DEVICE(0x10EC, 0x5209), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  43         { PCI_DEVICE(0x10EC, 0x5229), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  44         { PCI_DEVICE(0x10EC, 0x5289), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  45         { PCI_DEVICE(0x10EC, 0x5227), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  46         { PCI_DEVICE(0x10EC, 0x522A), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  47         { PCI_DEVICE(0x10EC, 0x5249), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  48         { PCI_DEVICE(0x10EC, 0x5287), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  49         { PCI_DEVICE(0x10EC, 0x5286), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  50         { PCI_DEVICE(0x10EC, 0x524A), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  51         { PCI_DEVICE(0x10EC, 0x525A), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  52         { PCI_DEVICE(0x10EC, 0x5260), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  53         { PCI_DEVICE(0x10EC, 0x5261), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  54         { PCI_DEVICE(0x10EC, 0x5228), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  55         { 0, }
  56 };
  57
  58 MODULE_DEVICE_TABLE(pci, rtsx_pci_ids);
  59
  60 static inline void rtsx_pci_disable_aspm(struct rtsx_pcr *pcr)
  61 {
  62         pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,
  63                                            PCI_EXP_LNKCTL_ASPMC, 0);
  64 }
  65
  66 static int rtsx_comm_set_ltr_latency(struct rtsx_pcr *pcr, u32 latency)
  67 {
  68         rtsx_pci_write_register(pcr, MSGTXDATA0,
  69                                 MASK_8_BIT_DEF, (u8) (latency & 0xFF));
  70         rtsx_pci_write_register(pcr, MSGTXDATA1,
  71                                 MASK_8_BIT_DEF, (u8)((latency >> 8) & 0xFF));
  72         rtsx_pci_write_register(pcr, MSGTXDATA2,
  73                                 MASK_8_BIT_DEF, (u8)((latency >> 16) & 0xFF));
  74         rtsx_pci_write_register(pcr, MSGTXDATA3,
  75                                 MASK_8_BIT_DEF, (u8)((latency >> 24) & 0xFF));
  76         rtsx_pci_write_register(pcr, LTR_CTL, LTR_TX_EN_MASK |
  77                 LTR_LATENCY_MODE_MASK, LTR_TX_EN_1 | LTR_LATENCY_MODE_SW);
  78
  79         return 0;
  80 }
  81
  82 int rtsx_set_ltr_latency(struct rtsx_pcr *pcr, u32 latency)
  83 {
  84         return rtsx_comm_set_ltr_latency(pcr, latency);
  85 }
  86
  87 static void rtsx_comm_set_aspm(struct rtsx_pcr *pcr, bool enable)
  88 {
  89         if (pcr->aspm_enabled == enable)
  90                 return;
  91
  92         pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,
  93                                            PCI_EXP_LNKCTL_ASPMC,
  94                                            enable ? pcr->aspm_en : 0);
  95
  96         pcr->aspm_enabled = enable;
  97 }
  98
  99 static void rtsx_disable_aspm(struct rtsx_pcr *pcr)
 100 {
 101         if (pcr->ops->set_aspm)
 102                 pcr->ops->set_aspm(pcr, false);
 103         else
 104                 rtsx_comm_set_aspm(pcr, false);
 105 }
 106
 107 int rtsx_set_l1off_sub(struct rtsx_pcr *pcr, u8 val)
 108 {
 109         rtsx_pci_write_register(pcr, L1SUB_CONFIG3, 0xFF, val);
 110
 111         return 0;
 112 }
 113
 114 static void rtsx_set_l1off_sub_cfg_d0(struct rtsx_pcr *pcr, int active)
 115 {
 116         if (pcr->ops->set_l1off_cfg_sub_d0)
 117                 pcr->ops->set_l1off_cfg_sub_d0(pcr, active);
 118 }
 119
 120 static void rtsx_comm_pm_full_on(struct rtsx_pcr *pcr)
 121 {
 122         struct rtsx_cr_option *option = &pcr->option;
 123
 124         rtsx_disable_aspm(pcr);
 125
 126         /* Fixes DMA transfer timout issue after disabling ASPM on RTS5260 */
 127         msleep(1);
 128
 129         if (option->ltr_enabled)
 130                 rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
 131
 132         if (rtsx_check_dev_flag(pcr, LTR_L1SS_PWR_GATE_EN))
 133                 rtsx_set_l1off_sub_cfg_d0(pcr, 1);
 134 }
 135
 136 static void rtsx_pm_full_on(struct rtsx_pcr *pcr)
 137 {
 138         rtsx_comm_pm_full_on(pcr);
 139 }
 140
 141 void rtsx_pci_start_run(struct rtsx_pcr *pcr)
 142 {
 143         /* If pci device removed, don't queue idle work any more */
 144         if (pcr->remove_pci)
 145                 return;
 146
 147         if (pcr->state != PDEV_STAT_RUN) {
 148                 pcr->state = PDEV_STAT_RUN;
 149                 if (pcr->ops->enable_auto_blink)
 150                         pcr->ops->enable_auto_blink(pcr);
 151                 rtsx_pm_full_on(pcr);
 152         }
 153
 154         mod_delayed_work(system_wq, &pcr->idle_work, msecs_to_jiffies(200));
 155 }
 156 EXPORT_SYMBOL_GPL(rtsx_pci_start_run);
 157
 158 int rtsx_pci_write_register(struct rtsx_pcr *pcr, u16 addr, u8 mask, u8 data)
 159 {
 160         int i;
 161         u32 val = HAIMR_WRITE_START;
 162
 163         val |= (u32)(addr & 0x3FFF) << 16;
 164         val |= (u32)mask << 8;
 165         val |= (u32)data;
 166
 167         rtsx_pci_writel(pcr, RTSX_HAIMR, val);
 168
 169         for (i = 0; i < MAX_RW_REG_CNT; i++) {
 170                 val = rtsx_pci_readl(pcr, RTSX_HAIMR);
 171                 if ((val & HAIMR_TRANS_END) == 0) {
 172                         if (data != (u8)val)
 173                                 return -EIO;
 174                         return 0;
 175                 }
 176         }
 177
 178         return -ETIMEDOUT;
 179 }
 180 EXPORT_SYMBOL_GPL(rtsx_pci_write_register);
 181
 182 int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data)
 183 {
 184         u32 val = HAIMR_READ_START;
 185         int i;
 186
 187         val |= (u32)(addr & 0x3FFF) << 16;
 188         rtsx_pci_writel(pcr, RTSX_HAIMR, val);
 189
 190         for (i = 0; i < MAX_RW_REG_CNT; i++) {
 191                 val = rtsx_pci_readl(pcr, RTSX_HAIMR);
 192                 if ((val & HAIMR_TRANS_END) == 0)
 193                         break;
 194         }
 195
 196         if (i >= MAX_RW_REG_CNT)
 197                 return -ETIMEDOUT;
 198
 199         if (data)
 200                 *data = (u8)(val & 0xFF);
 201
 202         return 0;
 203 }
 204 EXPORT_SYMBOL_GPL(rtsx_pci_read_register);
 205
 206 int __rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val)
 207 {
 208         int err, i, finished = 0;
 209         u8 tmp;
 210
 211         rtsx_pci_write_register(pcr, PHYDATA0, 0xFF, (u8)val);
 212         rtsx_pci_write_register(pcr, PHYDATA1, 0xFF, (u8)(val >> 8));
 213         rtsx_pci_write_register(pcr, PHYADDR, 0xFF, addr);
 214         rtsx_pci_write_register(pcr, PHYRWCTL, 0xFF, 0x81);
 215
 216         for (i = 0; i < 100000; i++) {
 217                 err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
 218                 if (err < 0)
 219                         return err;
 220
 221                 if (!(tmp & 0x80)) {
 222                         finished = 1;
 223                         break;
 224                 }
 225         }
 226
 227         if (!finished)
 228                 return -ETIMEDOUT;
 229
 230         return 0;
 231 }
 232
 233 int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val)
 234 {
 235         if (pcr->ops->write_phy)
 236                 return pcr->ops->write_phy(pcr, addr, val);
 237
 238         return __rtsx_pci_write_phy_register(pcr, addr, val);
 239 }
 240 EXPORT_SYMBOL_GPL(rtsx_pci_write_phy_register);
 241
 242 int __rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val)
 243 {
 244         int err, i, finished = 0;
 245         u16 data;
 246         u8 tmp, val1, val2;
 247
 248         rtsx_pci_write_register(pcr, PHYADDR, 0xFF, addr);
 249         rtsx_pci_write_register(pcr, PHYRWCTL, 0xFF, 0x80);
 250
 251         for (i = 0; i < 100000; i++) {
 252                 err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
 253                 if (err < 0)
 254                         return err;
 255
 256                 if (!(tmp & 0x80)) {
 257                         finished = 1;
 258                         break;
 259                 }
 260         }
 261
 262         if (!finished)
 263                 return -ETIMEDOUT;
 264
 265         rtsx_pci_read_register(pcr, PHYDATA0, &val1);
 266         rtsx_pci_read_register(pcr, PHYDATA1, &val2);
 267         data = val1 | (val2 << 8);
 268
 269         if (val)
 270                 *val = data;
 271
 272         return 0;
 273 }
 274
 275 int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val)
 276 {
 277         if (pcr->ops->read_phy)
 278                 return pcr->ops->read_phy(pcr, addr, val);
 279
 280         return __rtsx_pci_read_phy_register(pcr, addr, val);
 281 }
 282 EXPORT_SYMBOL_GPL(rtsx_pci_read_phy_register);
 283
 284 void rtsx_pci_stop_cmd(struct rtsx_pcr *pcr)
 285 {
 286         if (pcr->ops->stop_cmd)
 287                 return pcr->ops->stop_cmd(pcr);
 288
 289         rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD);
 290         rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA);
 291
 292         rtsx_pci_write_register(pcr, DMACTL, 0x80, 0x80);
 293         rtsx_pci_write_register(pcr, RBCTL, 0x80, 0x80);
 294 }
 295 EXPORT_SYMBOL_GPL(rtsx_pci_stop_cmd);
 296
 297 void rtsx_pci_add_cmd(struct rtsx_pcr *pcr,
 298                 u8 cmd_type, u16 reg_addr, u8 mask, u8 data)
 299 {
 300         unsigned long flags;
 301         u32 val = 0;
 302         u32 *ptr = (u32 *)(pcr->host_cmds_ptr);
 303
 304         val |= (u32)(cmd_type & 0x03) << 30;
 305         val |= (u32)(reg_addr & 0x3FFF) << 16;
 306         val |= (u32)mask << 8;
 307         val |= (u32)data;
 308
 309         spin_lock_irqsave(&pcr->lock, flags);
 310         ptr += pcr->ci;
 311         if (pcr->ci < (HOST_CMDS_BUF_LEN / 4)) {
 312                 put_unaligned_le32(val, ptr);
 313                 ptr++;
 314                 pcr->ci++;
 315         }
 316         spin_unlock_irqrestore(&pcr->lock, flags);
 317 }
 318 EXPORT_SYMBOL_GPL(rtsx_pci_add_cmd);
 319
 320 void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr *pcr)
 321 {
 322         u32 val = 1 << 31;
 323
 324         rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
 325
 326         val |= (u32)(pcr->ci * 4) & 0x00FFFFFF;
 327         /* Hardware Auto Response */
 328         val |= 0x40000000;
 329         rtsx_pci_writel(pcr, RTSX_HCBCTLR, val);
 330 }
 331 EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd_no_wait);
 332
 333 int rtsx_pci_send_cmd(struct rtsx_pcr *pcr, int timeout)
 334 {
 335         struct completion trans_done;
 336         u32 val = 1 << 31;
 337         long timeleft;
 338         unsigned long flags;
 339         int err = 0;
 340
 341         spin_lock_irqsave(&pcr->lock, flags);
 342
 343         /* set up data structures for the wakeup system */
 344         pcr->done = &trans_done;
 345         pcr->trans_result = TRANS_NOT_READY;
 346         init_completion(&trans_done);
 347
 348         rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
 349
 350         val |= (u32)(pcr->ci * 4) & 0x00FFFFFF;
 351         /* Hardware Auto Response */
 352         val |= 0x40000000;
 353         rtsx_pci_writel(pcr, RTSX_HCBCTLR, val);
 354
 355         spin_unlock_irqrestore(&pcr->lock, flags);
 356
 357         /* Wait for TRANS_OK_INT */
 358         timeleft = wait_for_completion_interruptible_timeout(
 359                         &trans_done, msecs_to_jiffies(timeout));
 360         if (timeleft <= 0) {
 361                 pcr_dbg(pcr, "Timeout (%s %d)\n", __func__, __LINE__);
 362                 err = -ETIMEDOUT;
 363                 goto finish_send_cmd;
 364         }
 365
 366         spin_lock_irqsave(&pcr->lock, flags);
 367         if (pcr->trans_result == TRANS_RESULT_FAIL)
 368                 err = -EINVAL;
 369         else if (pcr->trans_result == TRANS_RESULT_OK)
 370                 err = 0;
 371         else if (pcr->trans_result == TRANS_NO_DEVICE)
 372                 err = -ENODEV;
 373         spin_unlock_irqrestore(&pcr->lock, flags);
 374
 375 finish_send_cmd:
 376         spin_lock_irqsave(&pcr->lock, flags);
 377         pcr->done = NULL;
 378         spin_unlock_irqrestore(&pcr->lock, flags);
 379
 380         if ((err < 0) && (err != -ENODEV))
 381                 rtsx_pci_stop_cmd(pcr);
 382
 383         if (pcr->finish_me)
 384                 complete(pcr->finish_me);
 385
 386         return err;
 387 }
 388 EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd);
 389
 390 static void rtsx_pci_add_sg_tbl(struct rtsx_pcr *pcr,
 391                 dma_addr_t addr, unsigned int len, int end)
 392 {
 393         u64 *ptr = (u64 *)(pcr->host_sg_tbl_ptr) + pcr->sgi;
 394         u64 val;
 395         u8 option = RTSX_SG_VALID | RTSX_SG_TRANS_DATA;
 396
 397         pcr_dbg(pcr, "DMA addr: 0x%x, Len: 0x%x\n", (unsigned int)addr, len);
 398
 399         if (end)
 400                 option |= RTSX_SG_END;
 401
 402         if ((PCI_PID(pcr) == PID_5261) || (PCI_PID(pcr) == PID_5228)) {
 403                 if (len > 0xFFFF)
 404                         val = ((u64)addr << 32) | (((u64)len & 0xFFFF) << 16)
 405                                 | (((u64)len >> 16) << 6) | option;
 406                 else
 407                         val = ((u64)addr << 32) | ((u64)len << 16) | option;
 408         } else {
 409                 val = ((u64)addr << 32) | ((u64)len << 12) | option;
 410         }
 411         put_unaligned_le64(val, ptr);
 412         pcr->sgi++;
 413 }
 414
 415 int rtsx_pci_transfer_data(struct rtsx_pcr *pcr, struct scatterlist *sglist,
 416                 int num_sg, bool read, int timeout)
 417 {
 418         int err = 0, count;
 419
 420         pcr_dbg(pcr, "--> %s: num_sg = %d\n", __func__, num_sg);
 421         count = rtsx_pci_dma_map_sg(pcr, sglist, num_sg, read);
 422         if (count < 1)
 423                 return -EINVAL;
 424         pcr_dbg(pcr, "DMA mapping count: %d\n", count);
 425
 426         err = rtsx_pci_dma_transfer(pcr, sglist, count, read, timeout);
 427
 428         rtsx_pci_dma_unmap_sg(pcr, sglist, num_sg, read);
 429
 430         return err;
 431 }
 432 EXPORT_SYMBOL_GPL(rtsx_pci_transfer_data);
 433
 434 int rtsx_pci_dma_map_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist,
 435                 int num_sg, bool read)
 436 {
 437         enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
 438
 439         if (pcr->remove_pci)
 440                 return -EINVAL;
 441
 442         if ((sglist == NULL) || (num_sg <= 0))
 443                 return -EINVAL;
 444
 445         return dma_map_sg(&(pcr->pci->dev), sglist, num_sg, dir);
 446 }
 447 EXPORT_SYMBOL_GPL(rtsx_pci_dma_map_sg);
 448
 449 void rtsx_pci_dma_unmap_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist,
 450                 int num_sg, bool read)
 451 {
 452         enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
 453
 454         dma_unmap_sg(&(pcr->pci->dev), sglist, num_sg, dir);
 455 }
 456 EXPORT_SYMBOL_GPL(rtsx_pci_dma_unmap_sg);
 457
 458 int rtsx_pci_dma_transfer(struct rtsx_pcr *pcr, struct scatterlist *sglist,
 459                 int count, bool read, int timeout)
 460 {
 461         struct completion trans_done;
 462         struct scatterlist *sg;
 463         dma_addr_t addr;
 464         long timeleft;
 465         unsigned long flags;
 466         unsigned int len;
 467         int i, err = 0;
 468         u32 val;
 469         u8 dir = read ? DEVICE_TO_HOST : HOST_TO_DEVICE;
 470
 471         if (pcr->remove_pci)
 472                 return -ENODEV;
 473
 474         if ((sglist == NULL) || (count < 1))
 475                 return -EINVAL;
 476
 477         val = ((u32)(dir & 0x01) << 29) | TRIG_DMA | ADMA_MODE;
 478         pcr->sgi = 0;
 479         for_each_sg(sglist, sg, count, i) {
 480                 addr = sg_dma_address(sg);
 481                 len = sg_dma_len(sg);
 482                 rtsx_pci_add_sg_tbl(pcr, addr, len, i == count - 1);
 483         }
 484
 485         spin_lock_irqsave(&pcr->lock, flags);
 486
 487         pcr->done = &trans_done;
 488         pcr->trans_result = TRANS_NOT_READY;
 489         init_completion(&trans_done);
 490         rtsx_pci_writel(pcr, RTSX_HDBAR, pcr->host_sg_tbl_addr);
 491         rtsx_pci_writel(pcr, RTSX_HDBCTLR, val);
 492
 493         spin_unlock_irqrestore(&pcr->lock, flags);
 494
 495         timeleft = wait_for_completion_interruptible_timeout(
 496                         &trans_done, msecs_to_jiffies(timeout));
 497         if (timeleft <= 0) {
 498                 pcr_dbg(pcr, "Timeout (%s %d)\n", __func__, __LINE__);
 499                 err = -ETIMEDOUT;
 500                 goto out;
 501         }
 502
 503         spin_lock_irqsave(&pcr->lock, flags);
 504         if (pcr->trans_result == TRANS_RESULT_FAIL) {
 505                 err = -EILSEQ;
 506                 if (pcr->dma_error_count < RTS_MAX_TIMES_FREQ_REDUCTION)
 507                         pcr->dma_error_count++;
 508         }
 509
 510         else if (pcr->trans_result == TRANS_NO_DEVICE)
 511                 err = -ENODEV;
 512         spin_unlock_irqrestore(&pcr->lock, flags);
 513
 514 out:
 515         spin_lock_irqsave(&pcr->lock, flags);
 516         pcr->done = NULL;
 517         spin_unlock_irqrestore(&pcr->lock, flags);
 518
 519         if ((err < 0) && (err != -ENODEV))
 520                 rtsx_pci_stop_cmd(pcr);
 521
 522         if (pcr->finish_me)
 523                 complete(pcr->finish_me);
 524
 525         return err;
 526 }
 527 EXPORT_SYMBOL_GPL(rtsx_pci_dma_transfer);
 528
 529 int rtsx_pci_read_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len)
 530 {
 531         int err;
 532         int i, j;
 533         u16 reg;
 534         u8 *ptr;
 535
 536         if (buf_len > 512)
 537                 buf_len = 512;
 538
 539         ptr = buf;
 540         reg = PPBUF_BASE2;
 541         for (i = 0; i < buf_len / 256; i++) {
 542                 rtsx_pci_init_cmd(pcr);
 543
 544                 for (j = 0; j < 256; j++)
 545                         rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);
 546
 547                 err = rtsx_pci_send_cmd(pcr, 250);
 548                 if (err < 0)
 549                         return err;
 550
 551                 memcpy(ptr, rtsx_pci_get_cmd_data(pcr), 256);
 552                 ptr += 256;
 553         }
 554
 555         if (buf_len % 256) {
 556                 rtsx_pci_init_cmd(pcr);
 557
 558                 for (j = 0; j < buf_len % 256; j++)
 559                         rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);
 560
 561                 err = rtsx_pci_send_cmd(pcr, 250);
 562                 if (err < 0)
 563                         return err;
 564         }
 565
 566         memcpy(ptr, rtsx_pci_get_cmd_data(pcr), buf_len % 256);
 567
 568         return 0;
 569 }
 570 EXPORT_SYMBOL_GPL(rtsx_pci_read_ppbuf);
 571
 572 int rtsx_pci_write_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len)
 573 {
 574         int err;
 575         int i, j;
 576         u16 reg;
 577         u8 *ptr;
 578
 579         if (buf_len > 512)
 580                 buf_len = 512;
 581
 582         ptr = buf;
 583         reg = PPBUF_BASE2;
 584         for (i = 0; i < buf_len / 256; i++) {
 585                 rtsx_pci_init_cmd(pcr);
 586
 587                 for (j = 0; j < 256; j++) {
 588                         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
 589                                         reg++, 0xFF, *ptr);
 590                         ptr++;
 591                 }
 592
 593                 err = rtsx_pci_send_cmd(pcr, 250);
 594                 if (err < 0)
 595                         return err;
 596         }
 597
 598         if (buf_len % 256) {
 599                 rtsx_pci_init_cmd(pcr);
 600
 601                 for (j = 0; j < buf_len % 256; j++) {
 602                         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
 603                                         reg++, 0xFF, *ptr);
 604                         ptr++;
 605                 }
 606
 607                 err = rtsx_pci_send_cmd(pcr, 250);
 608                 if (err < 0)
 609                         return err;
 610         }
 611
 612         return 0;
 613 }
 614 EXPORT_SYMBOL_GPL(rtsx_pci_write_ppbuf);
 615
 616 static int rtsx_pci_set_pull_ctl(struct rtsx_pcr *pcr, const u32 *tbl)
 617 {
 618         rtsx_pci_init_cmd(pcr);
 619
 620         while (*tbl & 0xFFFF0000) {
 621                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
 622                                 (u16)(*tbl >> 16), 0xFF, (u8)(*tbl));
 623                 tbl++;
 624         }
 625
 626         return rtsx_pci_send_cmd(pcr, 100);
 627 }
 628
 629 int rtsx_pci_card_pull_ctl_enable(struct rtsx_pcr *pcr, int card)
 630 {
 631         const u32 *tbl;
 632
 633         if (card == RTSX_SD_CARD)
 634                 tbl = pcr->sd_pull_ctl_enable_tbl;
 635         else if (card == RTSX_MS_CARD)
 636                 tbl = pcr->ms_pull_ctl_enable_tbl;
 637         else
 638                 return -EINVAL;
 639
 640         return rtsx_pci_set_pull_ctl(pcr, tbl);
 641 }
 642 EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_enable);
 643
 644 int rtsx_pci_card_pull_ctl_disable(struct rtsx_pcr *pcr, int card)
 645 {
 646         const u32 *tbl;
 647
 648         if (card == RTSX_SD_CARD)
 649                 tbl = pcr->sd_pull_ctl_disable_tbl;
 650         else if (card == RTSX_MS_CARD)
 651                 tbl = pcr->ms_pull_ctl_disable_tbl;
 652         else
 653                 return -EINVAL;
 654
 655         return rtsx_pci_set_pull_ctl(pcr, tbl);
 656 }
 657 EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_disable);
 658
 659 static void rtsx_pci_enable_bus_int(struct rtsx_pcr *pcr)
 660 {
 661         struct rtsx_hw_param *hw_param = &pcr->hw_param;
 662
 663         pcr->bier = TRANS_OK_INT_EN | TRANS_FAIL_INT_EN | SD_INT_EN
 664                 | hw_param->interrupt_en;
 665
 666         if (pcr->num_slots > 1)
 667                 pcr->bier |= MS_INT_EN;
 668
 669         /* Enable Bus Interrupt */
 670         rtsx_pci_writel(pcr, RTSX_BIER, pcr->bier);
 671
 672         pcr_dbg(pcr, "RTSX_BIER: 0x%08x\n", pcr->bier);
 673 }
 674
 675 static inline u8 double_ssc_depth(u8 depth)
 676 {
 677         return ((depth > 1) ? (depth - 1) : depth);
 678 }
 679
 680 static u8 revise_ssc_depth(u8 ssc_depth, u8 div)
 681 {
 682         if (div > CLK_DIV_1) {
 683                 if (ssc_depth > (div - 1))
 684                         ssc_depth -= (div - 1);
 685                 else
 686                         ssc_depth = SSC_DEPTH_4M;
 687         }
 688
 689         return ssc_depth;
 690 }
 691
 692 int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
 693                 u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk)
 694 {
 695         int err, clk;
 696         u8 n, clk_divider, mcu_cnt, div;
 697         static const u8 depth[] = {
 698                 [RTSX_SSC_DEPTH_4M] = SSC_DEPTH_4M,
 699                 [RTSX_SSC_DEPTH_2M] = SSC_DEPTH_2M,
 700                 [RTSX_SSC_DEPTH_1M] = SSC_DEPTH_1M,
 701                 [RTSX_SSC_DEPTH_500K] = SSC_DEPTH_500K,
 702                 [RTSX_SSC_DEPTH_250K] = SSC_DEPTH_250K,
 703         };
 704
 705         if (PCI_PID(pcr) == PID_5261)
 706                 return rts5261_pci_switch_clock(pcr, card_clock,
 707                                 ssc_depth, initial_mode, double_clk, vpclk);
 708         if (PCI_PID(pcr) == PID_5228)
 709                 return rts5228_pci_switch_clock(pcr, card_clock,
 710                                 ssc_depth, initial_mode, double_clk, vpclk);
 711
 712         if (initial_mode) {
 713                 /* We use 250k(around) here, in initial stage */
 714                 clk_divider = SD_CLK_DIVIDE_128;
 715                 card_clock = 30000000;
 716         } else {
 717                 clk_divider = SD_CLK_DIVIDE_0;
 718         }
 719         err = rtsx_pci_write_register(pcr, SD_CFG1,
 720                         SD_CLK_DIVIDE_MASK, clk_divider);
 721         if (err < 0)
 722                 return err;
 723
 724         /* Reduce card clock by 20MHz each time a DMA transfer error occurs */
 725         if (card_clock == UHS_SDR104_MAX_DTR &&
 726             pcr->dma_error_count &&
 727             PCI_PID(pcr) == RTS5227_DEVICE_ID)
 728                 card_clock = UHS_SDR104_MAX_DTR -
 729                         (pcr->dma_error_count * 20000000);
 730
 731         card_clock /= 1000000;
 732         pcr_dbg(pcr, "Switch card clock to %dMHz\n", card_clock);
 733
 734         clk = card_clock;
 735         if (!initial_mode && double_clk)
 736                 clk = card_clock * 2;
 737         pcr_dbg(pcr, "Internal SSC clock: %dMHz (cur_clock = %d)\n",
 738                 clk, pcr->cur_clock);
 739
 740         if (clk == pcr->cur_clock)
 741                 return 0;
 742
 743         if (pcr->ops->conv_clk_and_div_n)
 744                 n = (u8)pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N);
 745         else
 746                 n = (u8)(clk - 2);
 747         if ((clk <= 2) || (n > MAX_DIV_N_PCR))
 748                 return -EINVAL;
 749
 750         mcu_cnt = (u8)(125/clk + 3);
 751         if (mcu_cnt > 15)
 752                 mcu_cnt = 15;
 753
 754         /* Make sure that the SSC clock div_n is not less than MIN_DIV_N_PCR */
 755         div = CLK_DIV_1;
 756         while ((n < MIN_DIV_N_PCR) && (div < CLK_DIV_8)) {
 757                 if (pcr->ops->conv_clk_and_div_n) {
 758                         int dbl_clk = pcr->ops->conv_clk_and_div_n(n,
 759                                         DIV_N_TO_CLK) * 2;
 760                         n = (u8)pcr->ops->conv_clk_and_div_n(dbl_clk,
 761                                         CLK_TO_DIV_N);
 762                 } else {
 763                         n = (n + 2) * 2 - 2;
 764                 }
 765                 div++;
 766         }
 767         pcr_dbg(pcr, "n = %d, div = %d\n", n, div);
 768
 769         ssc_depth = depth[ssc_depth];
 770         if (double_clk)
 771                 ssc_depth = double_ssc_depth(ssc_depth);
 772
 773         ssc_depth = revise_ssc_depth(ssc_depth, div);
 774         pcr_dbg(pcr, "ssc_depth = %d\n", ssc_depth);
 775
 776         rtsx_pci_init_cmd(pcr);
 777         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
 778                         CLK_LOW_FREQ, CLK_LOW_FREQ);
 779         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV,
 780                         0xFF, (div << 4) | mcu_cnt);
 781         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
 782         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2,
 783                         SSC_DEPTH_MASK, ssc_depth);
 784         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n);
 785         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB);
 786         if (vpclk) {
 787                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
 788                                 PHASE_NOT_RESET, 0);
 789                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
 790                                 PHASE_NOT_RESET, PHASE_NOT_RESET);
 791         }
 792
 793         err = rtsx_pci_send_cmd(pcr, 2000);
 794         if (err < 0)
 795                 return err;
 796
 797         /* Wait SSC clock stable */
 798         udelay(SSC_CLOCK_STABLE_WAIT);
 799         err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
 800         if (err < 0)
 801                 return err;
 802
 803         pcr->cur_clock = clk;
 804         return 0;
 805 }
 806 EXPORT_SYMBOL_GPL(rtsx_pci_switch_clock);
 807
 808 int rtsx_pci_card_power_on(struct rtsx_pcr *pcr, int card)
 809 {
 810         if (pcr->ops->card_power_on)
 811                 return pcr->ops->card_power_on(pcr, card);
 812
 813         return 0;
 814 }
 815 EXPORT_SYMBOL_GPL(rtsx_pci_card_power_on);
 816
 817 int rtsx_pci_card_power_off(struct rtsx_pcr *pcr, int card)
 818 {
 819         if (pcr->ops->card_power_off)
 820                 return pcr->ops->card_power_off(pcr, card);
 821
 822         return 0;
 823 }
 824 EXPORT_SYMBOL_GPL(rtsx_pci_card_power_off);
 825
 826 int rtsx_pci_card_exclusive_check(struct rtsx_pcr *pcr, int card)
 827 {
 828         static const unsigned int cd_mask[] = {
 829                 [RTSX_SD_CARD] = SD_EXIST,
 830                 [RTSX_MS_CARD] = MS_EXIST
 831         };
 832
 833         if (!(pcr->flags & PCR_MS_PMOS)) {
 834                 /* When using single PMOS, accessing card is not permitted
 835                  * if the existing card is not the designated one.
 836                  */
 837                 if (pcr->card_exist & (~cd_mask[card]))
 838                         return -EIO;
 839         }
 840
 841         return 0;
 842 }
 843 EXPORT_SYMBOL_GPL(rtsx_pci_card_exclusive_check);
 844
 845 int rtsx_pci_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
 846 {
 847         if (pcr->ops->switch_output_voltage)
 848                 return pcr->ops->switch_output_voltage(pcr, voltage);
 849
 850         return 0;
 851 }
 852 EXPORT_SYMBOL_GPL(rtsx_pci_switch_output_voltage);
 853
 854 unsigned int rtsx_pci_card_exist(struct rtsx_pcr *pcr)
 855 {
 856         unsigned int val;
 857
 858         val = rtsx_pci_readl(pcr, RTSX_BIPR);
 859         if (pcr->ops->cd_deglitch)
 860                 val = pcr->ops->cd_deglitch(pcr);
 861
 862         return val;
 863 }
 864 EXPORT_SYMBOL_GPL(rtsx_pci_card_exist);
 865
 866 void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr *pcr)
 867 {
 868         struct completion finish;
 869
 870         pcr->finish_me = &finish;
 871         init_completion(&finish);
 872
 873         if (pcr->done)
 874                 complete(pcr->done);
 875
 876         if (!pcr->remove_pci)
 877                 rtsx_pci_stop_cmd(pcr);
 878
 879         wait_for_completion_interruptible_timeout(&finish,
 880                         msecs_to_jiffies(2));
 881         pcr->finish_me = NULL;
 882 }
 883 EXPORT_SYMBOL_GPL(rtsx_pci_complete_unfinished_transfer);
 884
 885 static void rtsx_pci_card_detect(struct work_struct *work)
 886 {
 887         struct delayed_work *dwork;
 888         struct rtsx_pcr *pcr;
 889         unsigned long flags;
 890         unsigned int card_detect = 0, card_inserted, card_removed;
 891         u32 irq_status;
 892
 893         dwork = to_delayed_work(work);
 894         pcr = container_of(dwork, struct rtsx_pcr, carddet_work);
 895
 896         pcr_dbg(pcr, "--> %s\n", __func__);
 897
 898         mutex_lock(&pcr->pcr_mutex);
 899         spin_lock_irqsave(&pcr->lock, flags);
 900
 901         irq_status = rtsx_pci_readl(pcr, RTSX_BIPR);
 902         pcr_dbg(pcr, "irq_status: 0x%08x\n", irq_status);
 903
 904         irq_status &= CARD_EXIST;
 905         card_inserted = pcr->card_inserted & irq_status;
 906         card_removed = pcr->card_removed;
 907         pcr->card_inserted = 0;
 908         pcr->card_removed = 0;
 909
 910         spin_unlock_irqrestore(&pcr->lock, flags);
 911
 912         if (card_inserted || card_removed) {
 913                 pcr_dbg(pcr, "card_inserted: 0x%x, card_removed: 0x%x\n",
 914                         card_inserted, card_removed);
 915
 916                 if (pcr->ops->cd_deglitch)
 917                         card_inserted = pcr->ops->cd_deglitch(pcr);
 918
 919                 card_detect = card_inserted | card_removed;
 920
 921                 pcr->card_exist |= card_inserted;
 922                 pcr->card_exist &= ~card_removed;
 923         }
 924
 925         mutex_unlock(&pcr->pcr_mutex);
 926
 927         if ((card_detect & SD_EXIST) && pcr->slots[RTSX_SD_CARD].card_event)
 928                 pcr->slots[RTSX_SD_CARD].card_event(
 929                                 pcr->slots[RTSX_SD_CARD].p_dev);
 930         if ((card_detect & MS_EXIST) && pcr->slots[RTSX_MS_CARD].card_event)
 931                 pcr->slots[RTSX_MS_CARD].card_event(
 932                                 pcr->slots[RTSX_MS_CARD].p_dev);
 933 }
 934
 935 static void rtsx_pci_process_ocp(struct rtsx_pcr *pcr)
 936 {
 937         if (pcr->ops->process_ocp) {
 938                 pcr->ops->process_ocp(pcr);
 939         } else {
 940                 if (!pcr->option.ocp_en)
 941                         return;
 942                 rtsx_pci_get_ocpstat(pcr, &pcr->ocp_stat);
 943                 if (pcr->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
 944                         rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);
 945                         rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0);
 946                         rtsx_pci_clear_ocpstat(pcr);
 947                         pcr->ocp_stat = 0;
 948                 }
 949         }
 950 }
 951
 952 static int rtsx_pci_process_ocp_interrupt(struct rtsx_pcr *pcr)
 953 {
 954         if (pcr->option.ocp_en)
 955                 rtsx_pci_process_ocp(pcr);
 956
 957         return 0;
 958 }
 959
 960 static irqreturn_t rtsx_pci_isr(int irq, void *dev_id)
 961 {
 962         struct rtsx_pcr *pcr = dev_id;
 963         u32 int_reg;
 964
 965         if (!pcr)
 966                 return IRQ_NONE;
 967
 968         spin_lock(&pcr->lock);
 969
 970         int_reg = rtsx_pci_readl(pcr, RTSX_BIPR);
 971         /* Clear interrupt flag */
 972         rtsx_pci_writel(pcr, RTSX_BIPR, int_reg);
 973         if ((int_reg & pcr->bier) == 0) {
 974                 spin_unlock(&pcr->lock);
 975                 return IRQ_NONE;
 976         }
 977         if (int_reg == 0xFFFFFFFF) {
 978                 spin_unlock(&pcr->lock);
 979                 return IRQ_HANDLED;
 980         }
 981
 982         int_reg &= (pcr->bier | 0x7FFFFF);
 983
 984         if (int_reg & SD_OC_INT)
 985                 rtsx_pci_process_ocp_interrupt(pcr);
 986
 987         if (int_reg & SD_INT) {
 988                 if (int_reg & SD_EXIST) {
 989                         pcr->card_inserted |= SD_EXIST;
 990                 } else {
 991                         pcr->card_removed |= SD_EXIST;
 992                         pcr->card_inserted &= ~SD_EXIST;
 993                 }
 994                 pcr->dma_error_count = 0;
 995         }
 996
 997         if (int_reg & MS_INT) {
 998                 if (int_reg & MS_EXIST) {
 999                         pcr->card_inserted |= MS_EXIST;
1000                 } else {
1001                         pcr->card_removed |= MS_EXIST;
1002                         pcr->card_inserted &= ~MS_EXIST;
1003                 }
1004         }
1005
1006         if (int_reg & (NEED_COMPLETE_INT | DELINK_INT)) {
1007                 if (int_reg & (TRANS_FAIL_INT | DELINK_INT)) {
1008                         pcr->trans_result = TRANS_RESULT_FAIL;
1009                         if (pcr->done)
1010                                 complete(pcr->done);
1011                 } else if (int_reg & TRANS_OK_INT) {
1012                         pcr->trans_result = TRANS_RESULT_OK;
1013                         if (pcr->done)
1014                                 complete(pcr->done);
1015                 }
1016         }
1017
1018         if ((pcr->card_inserted || pcr->card_removed) && !(int_reg & SD_OC_INT))
1019                 schedule_delayed_work(&pcr->carddet_work,
1020                                 msecs_to_jiffies(200));
1021
1022         spin_unlock(&pcr->lock);
1023         return IRQ_HANDLED;
1024 }
1025
1026 static int rtsx_pci_acquire_irq(struct rtsx_pcr *pcr)
1027 {
1028         pcr_dbg(pcr, "%s: pcr->msi_en = %d, pci->irq = %d\n",
1029                         __func__, pcr->msi_en, pcr->pci->irq);
1030
1031         if (request_irq(pcr->pci->irq, rtsx_pci_isr,
1032                         pcr->msi_en ? 0 : IRQF_SHARED,
1033                         DRV_NAME_RTSX_PCI, pcr)) {
1034                 dev_err(&(pcr->pci->dev),
1035                         "rtsx_sdmmc: unable to grab IRQ %d, disabling device\n",
1036                         pcr->pci->irq);
1037                 return -1;
1038         }
1039
1040         pcr->irq = pcr->pci->irq;
1041         pci_intx(pcr->pci, !pcr->msi_en);
1042
1043         return 0;
1044 }
1045
1046 static void rtsx_enable_aspm(struct rtsx_pcr *pcr)
1047 {
1048         if (pcr->ops->set_aspm)
1049                 pcr->ops->set_aspm(pcr, true);
1050         else
1051                 rtsx_comm_set_aspm(pcr, true);
1052 }
1053
1054 static void rtsx_comm_pm_power_saving(struct rtsx_pcr *pcr)
1055 {
1056         struct rtsx_cr_option *option = &pcr->option;
1057
1058         if (option->ltr_enabled) {
1059                 u32 latency = option->ltr_l1off_latency;
1060
1061                 if (rtsx_check_dev_flag(pcr, L1_SNOOZE_TEST_EN))
1062                         mdelay(option->l1_snooze_delay);
1063
1064                 rtsx_set_ltr_latency(pcr, latency);
1065         }
1066
1067         if (rtsx_check_dev_flag(pcr, LTR_L1SS_PWR_GATE_EN))
1068                 rtsx_set_l1off_sub_cfg_d0(pcr, 0);
1069
1070         rtsx_enable_aspm(pcr);
1071 }
1072
1073 static void rtsx_pm_power_saving(struct rtsx_pcr *pcr)
1074 {
1075         rtsx_comm_pm_power_saving(pcr);
1076 }
1077
1078 static void rtsx_pci_idle_work(struct work_struct *work)
1079 {
1080         struct delayed_work *dwork = to_delayed_work(work);
1081         struct rtsx_pcr *pcr = container_of(dwork, struct rtsx_pcr, idle_work);
1082
1083         pcr_dbg(pcr, "--> %s\n", __func__);
1084
1085         mutex_lock(&pcr->pcr_mutex);
1086
1087         pcr->state = PDEV_STAT_IDLE;
1088
1089         if (pcr->ops->disable_auto_blink)
1090                 pcr->ops->disable_auto_blink(pcr);
1091         if (pcr->ops->turn_off_led)
1092                 pcr->ops->turn_off_led(pcr);
1093
1094         rtsx_pm_power_saving(pcr);
1095
1096         mutex_unlock(&pcr->pcr_mutex);
1097 }
1098
1099 static void rtsx_base_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
1100 {
1101         /* Set relink_time to 0 */
1102         rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, MASK_8_BIT_DEF, 0);
1103         rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, MASK_8_BIT_DEF, 0);
1104         rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3,
1105                         RELINK_TIME_MASK, 0);
1106
1107         rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3,
1108                         D3_DELINK_MODE_EN, D3_DELINK_MODE_EN);
1109
1110         rtsx_pci_write_register(pcr, FPDCTL, ALL_POWER_DOWN, ALL_POWER_DOWN);
1111 }
1112
1113 static void __maybe_unused rtsx_pci_power_off(struct rtsx_pcr *pcr, u8 pm_state)
1114 {
1115         if (pcr->ops->turn_off_led)
1116                 pcr->ops->turn_off_led(pcr);
1117
1118         rtsx_pci_writel(pcr, RTSX_BIER, 0);
1119         pcr->bier = 0;
1120
1121         rtsx_pci_write_register(pcr, PETXCFG, 0x08, 0x08);
1122         rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, pm_state);
1123
1124         if (pcr->ops->force_power_down)
1125                 pcr->ops->force_power_down(pcr, pm_state);
1126         else
1127                 rtsx_base_force_power_down(pcr, pm_state);
1128 }
1129
1130 void rtsx_pci_enable_ocp(struct rtsx_pcr *pcr)
1131 {
1132         u8 val = SD_OCP_INT_EN | SD_DETECT_EN;
1133
1134         if (pcr->ops->enable_ocp) {
1135                 pcr->ops->enable_ocp(pcr);
1136         } else {
1137                 rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN, 0);
1138                 rtsx_pci_write_register(pcr, REG_OCPCTL, 0xFF, val);
1139         }
1140
1141 }
1142
1143 void rtsx_pci_disable_ocp(struct rtsx_pcr *pcr)
1144 {
1145         u8 mask = SD_OCP_INT_EN | SD_DETECT_EN;
1146
1147         if (pcr->ops->disable_ocp) {
1148                 pcr->ops->disable_ocp(pcr);
1149         } else {
1150                 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
1151                 rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN,
1152                                 OC_POWER_DOWN);
1153         }
1154 }
1155
1156 void rtsx_pci_init_ocp(struct rtsx_pcr *pcr)
1157 {
1158         if (pcr->ops->init_ocp) {
1159                 pcr->ops->init_ocp(pcr);
1160         } else {
1161                 struct rtsx_cr_option *option = &(pcr->option);
1162
1163                 if (option->ocp_en) {
1164                         u8 val = option->sd_800mA_ocp_thd;
1165
1166                         rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN, 0);
1167                         rtsx_pci_write_register(pcr, REG_OCPPARA1,
1168                                 SD_OCP_TIME_MASK, SD_OCP_TIME_800);
1169                         rtsx_pci_write_register(pcr, REG_OCPPARA2,
1170                                 SD_OCP_THD_MASK, val);
1171                         rtsx_pci_write_register(pcr, REG_OCPGLITCH,
1172                                 SD_OCP_GLITCH_MASK, pcr->hw_param.ocp_glitch);
1173                         rtsx_pci_enable_ocp(pcr);
1174                 }
1175         }
1176 }
1177
1178 int rtsx_pci_get_ocpstat(struct rtsx_pcr *pcr, u8 *val)
1179 {
1180         if (pcr->ops->get_ocpstat)
1181                 return pcr->ops->get_ocpstat(pcr, val);
1182         else
1183                 return rtsx_pci_read_register(pcr, REG_OCPSTAT, val);
1184 }
1185
1186 void rtsx_pci_clear_ocpstat(struct rtsx_pcr *pcr)
1187 {
1188         if (pcr->ops->clear_ocpstat) {
1189                 pcr->ops->clear_ocpstat(pcr);
1190         } else {
1191                 u8 mask = SD_OCP_INT_CLR | SD_OC_CLR;
1192                 u8 val = SD_OCP_INT_CLR | SD_OC_CLR;
1193
1194                 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, val);
1195                 udelay(100);
1196                 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
1197         }
1198 }
1199
1200 void rtsx_pci_enable_oobs_polling(struct rtsx_pcr *pcr)
1201 {
1202         u16 val;
1203
1204         if ((PCI_PID(pcr) != PID_525A) && (PCI_PID(pcr) != PID_5260)) {
1205                 rtsx_pci_read_phy_register(pcr, 0x01, &val);
1206                 val |= 1<<9;
1207                 rtsx_pci_write_phy_register(pcr, 0x01, val);
1208         }
1209         rtsx_pci_write_register(pcr, REG_CFG_OOBS_OFF_TIMER, 0xFF, 0x32);
1210         rtsx_pci_write_register(pcr, REG_CFG_OOBS_ON_TIMER, 0xFF, 0x05);
1211         rtsx_pci_write_register(pcr, REG_CFG_VCM_ON_TIMER, 0xFF, 0x83);
1212         rtsx_pci_write_register(pcr, REG_CFG_OOBS_POLLING, 0xFF, 0xDE);
1213
1214 }
1215
1216 void rtsx_pci_disable_oobs_polling(struct rtsx_pcr *pcr)
1217 {
1218         u16 val;
1219
1220         if ((PCI_PID(pcr) != PID_525A) && (PCI_PID(pcr) != PID_5260)) {
1221                 rtsx_pci_read_phy_register(pcr, 0x01, &val);
1222                 val &= ~(1<<9);
1223                 rtsx_pci_write_phy_register(pcr, 0x01, val);
1224         }
1225         rtsx_pci_write_register(pcr, REG_CFG_VCM_ON_TIMER, 0xFF, 0x03);
1226         rtsx_pci_write_register(pcr, REG_CFG_OOBS_POLLING, 0xFF, 0x00);
1227
1228 }
1229
1230 int rtsx_sd_power_off_card3v3(struct rtsx_pcr *pcr)
1231 {
1232         rtsx_pci_write_register(pcr, CARD_CLK_EN, SD_CLK_EN |
1233                 MS_CLK_EN | SD40_CLK_EN, 0);
1234         rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0);
1235         rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);
1236
1237         msleep(50);
1238
1239         rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD);
1240
1241         return 0;
1242 }
1243
1244 int rtsx_ms_power_off_card3v3(struct rtsx_pcr *pcr)
1245 {
1246         rtsx_pci_write_register(pcr, CARD_CLK_EN, SD_CLK_EN |
1247                 MS_CLK_EN | SD40_CLK_EN, 0);
1248
1249         rtsx_pci_card_pull_ctl_disable(pcr, RTSX_MS_CARD);
1250
1251         rtsx_pci_write_register(pcr, CARD_OE, MS_OUTPUT_EN, 0);
1252         rtsx_pci_card_power_off(pcr, RTSX_MS_CARD);
1253
1254         return 0;
1255 }
1256
1257 static int rtsx_pci_init_hw(struct rtsx_pcr *pcr)
1258 {
1259         struct pci_dev *pdev = pcr->pci;
1260         int err;
1261
1262         if (PCI_PID(pcr) == PID_5228)
1263                 rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG1, RTS5228_LDO1_SR_TIME_MASK,
1264                                 RTS5228_LDO1_SR_0_5);
1265
1266         rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
1267
1268         rtsx_pci_enable_bus_int(pcr);
1269
1270         /* Power on SSC */
1271         if (PCI_PID(pcr) == PID_5261) {
1272                 /* Gating real mcu clock */
1273                 err = rtsx_pci_write_register(pcr, RTS5261_FW_CFG1,
1274                         RTS5261_MCU_CLOCK_GATING, 0);
1275                 err = rtsx_pci_write_register(pcr, RTS5261_REG_FPDCTL,
1276                         SSC_POWER_DOWN, 0);
1277         } else {
1278                 err = rtsx_pci_write_register(pcr, FPDCTL, SSC_POWER_DOWN, 0);
1279         }
1280         if (err < 0)
1281                 return err;
1282
1283         /* Wait SSC power stable */
1284         udelay(200);
1285
1286         rtsx_pci_disable_aspm(pcr);
1287         if (pcr->ops->optimize_phy) {
1288                 err = pcr->ops->optimize_phy(pcr);
1289                 if (err < 0)
1290                         return err;
1291         }
1292
1293         rtsx_pci_init_cmd(pcr);
1294
1295         /* Set mcu_cnt to 7 to ensure data can be sampled properly */
1296         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, 0x07, 0x07);
1297
1298         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, HOST_SLEEP_STATE, 0x03, 0x00);
1299         /* Disable card clock */
1300         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, 0x1E, 0);
1301         /* Reset delink mode */
1302         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x0A, 0);
1303         /* Card driving select */
1304         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DRIVE_SEL,
1305                         0xFF, pcr->card_drive_sel);
1306         /* Enable SSC Clock */
1307         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1,
1308                         0xFF, SSC_8X_EN | SSC_SEL_4M);
1309         if (PCI_PID(pcr) == PID_5261)
1310                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF,
1311                         RTS5261_SSC_DEPTH_2M);
1312         else if (PCI_PID(pcr) == PID_5228)
1313                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF,
1314                         RTS5228_SSC_DEPTH_2M);
1315         else
1316                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF, 0x12);
1317
1318         /* Disable cd_pwr_save */
1319         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x16, 0x10);
1320         /* Clear Link Ready Interrupt */
1321         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
1322                         LINK_RDY_INT, LINK_RDY_INT);
1323         /* Enlarge the estimation window of PERST# glitch
1324          * to reduce the chance of invalid card interrupt
1325          */
1326         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PERST_GLITCH_WIDTH, 0xFF, 0x80);
1327         /* Update RC oscillator to 400k
1328          * bit[0] F_HIGH: for RC oscillator, Rst_value is 1'b1
1329          *                1: 2M  0: 400k
1330          */
1331         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RCCTL, 0x01, 0x00);
1332         /* Set interrupt write clear
1333          * bit 1: U_elbi_if_rd_clr_en
1334          *      1: Enable ELBI interrupt[31:22] & [7:0] flag read clear
1335          *      0: ELBI interrupt flag[31:22] & [7:0] only can be write clear
1336          */
1337         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, NFTS_TX_CTRL, 0x02, 0);
1338
1339         err = rtsx_pci_send_cmd(pcr, 100);
1340         if (err < 0)
1341                 return err;
1342
1343         switch (PCI_PID(pcr)) {
1344         case PID_5250:
1345         case PID_524A:
1346         case PID_525A:
1347         case PID_5260:
1348         case PID_5261:
1349         case PID_5228:
1350                 rtsx_pci_write_register(pcr, PM_CLK_FORCE_CTL, 1, 1);
1351                 break;
1352         default:
1353                 break;
1354         }
1355
1356         /*init ocp*/
1357         rtsx_pci_init_ocp(pcr);
1358
1359         /* Enable clk_request_n to enable clock power management */
1360         pcie_capability_write_word(pdev, PCI_EXP_LNKCTL,
1361                                    PCI_EXP_LNKCTL_CLKREQ_EN);
1362         /* Enter L1 when host tx idle */
1363         pci_write_config_byte(pdev, 0x70F, 0x5B);
1364
1365         if (pcr->ops->extra_init_hw) {
1366                 err = pcr->ops->extra_init_hw(pcr);
1367                 if (err < 0)
1368                         return err;
1369         }
1370
1371         /* No CD interrupt if probing driver with card inserted.
1372          * So we need to initialize pcr->card_exist here.
1373          */
1374         if (pcr->ops->cd_deglitch)
1375                 pcr->card_exist = pcr->ops->cd_deglitch(pcr);
1376         else
1377                 pcr->card_exist = rtsx_pci_readl(pcr, RTSX_BIPR) & CARD_EXIST;
1378
1379         return 0;
1380 }
1381
1382 static int rtsx_pci_init_chip(struct rtsx_pcr *pcr)
1383 {
1384         int err;
1385
1386         spin_lock_init(&pcr->lock);
1387         mutex_init(&pcr->pcr_mutex);
1388
1389         switch (PCI_PID(pcr)) {
1390         default:
1391         case 0x5209:
1392                 rts5209_init_params(pcr);
1393                 break;
1394
1395         case 0x5229:
1396                 rts5229_init_params(pcr);
1397                 break;
1398
1399         case 0x5289:
1400                 rtl8411_init_params(pcr);
1401                 break;
1402
1403         case 0x5227:
1404                 rts5227_init_params(pcr);
1405                 break;
1406
1407         case 0x522A:
1408                 rts522a_init_params(pcr);
1409                 break;
1410
1411         case 0x5249:
1412                 rts5249_init_params(pcr);
1413                 break;
1414
1415         case 0x524A:
1416                 rts524a_init_params(pcr);
1417                 break;
1418
1419         case 0x525A:
1420                 rts525a_init_params(pcr);
1421                 break;
1422
1423         case 0x5287:
1424                 rtl8411b_init_params(pcr);
1425                 break;
1426
1427         case 0x5286:
1428                 rtl8402_init_params(pcr);
1429                 break;
1430
1431         case 0x5260:
1432                 rts5260_init_params(pcr);
1433                 break;
1434
1435         case 0x5261:
1436                 rts5261_init_params(pcr);
1437                 break;
1438
1439         case 0x5228:
1440                 rts5228_init_params(pcr);
1441                 break;
1442         }
1443
1444         pcr_dbg(pcr, "PID: 0x%04x, IC version: 0x%02x\n",
1445                         PCI_PID(pcr), pcr->ic_version);
1446
1447         pcr->slots = kcalloc(pcr->num_slots, sizeof(struct rtsx_slot),
1448                         GFP_KERNEL);
1449         if (!pcr->slots)
1450                 return -ENOMEM;
1451
1452         if (pcr->ops->fetch_vendor_settings)
1453                 pcr->ops->fetch_vendor_settings(pcr);
1454
1455         pcr_dbg(pcr, "pcr->aspm_en = 0x%x\n", pcr->aspm_en);
1456         pcr_dbg(pcr, "pcr->sd30_drive_sel_1v8 = 0x%x\n",
1457                         pcr->sd30_drive_sel_1v8);
1458         pcr_dbg(pcr, "pcr->sd30_drive_sel_3v3 = 0x%x\n",
1459                         pcr->sd30_drive_sel_3v3);
1460         pcr_dbg(pcr, "pcr->card_drive_sel = 0x%x\n",
1461                         pcr->card_drive_sel);
1462         pcr_dbg(pcr, "pcr->flags = 0x%x\n", pcr->flags);
1463
1464         pcr->state = PDEV_STAT_IDLE;
1465         err = rtsx_pci_init_hw(pcr);
1466         if (err < 0) {
1467                 kfree(pcr->slots);
1468                 return err;
1469         }
1470
1471         return 0;
1472 }
1473
1474 static int rtsx_pci_probe(struct pci_dev *pcidev,
1475                           const struct pci_device_id *id)
1476 {
1477         struct rtsx_pcr *pcr;
1478         struct pcr_handle *handle;
1479         u32 base, len;
1480         int ret, i, bar = 0;
1481
1482         dev_dbg(&(pcidev->dev),
1483                 ": Realtek PCI-E Card Reader found at %s [%04x:%04x] (rev %x)\n",
1484                 pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device,
1485                 (int)pcidev->revision);
1486
1487         ret = pci_set_dma_mask(pcidev, DMA_BIT_MASK(32));
1488         if (ret < 0)
1489                 return ret;
1490
1491         ret = pci_enable_device(pcidev);
1492         if (ret)
1493                 return ret;
1494
1495         ret = pci_request_regions(pcidev, DRV_NAME_RTSX_PCI);
1496         if (ret)
1497                 goto disable;
1498
1499         pcr = kzalloc(sizeof(*pcr), GFP_KERNEL);
1500         if (!pcr) {
1501                 ret = -ENOMEM;
1502                 goto release_pci;
1503         }
1504
1505         handle = kzalloc(sizeof(*handle), GFP_KERNEL);
1506         if (!handle) {
1507                 ret = -ENOMEM;
1508                 goto free_pcr;
1509         }
1510         handle->pcr = pcr;
1511
1512         idr_preload(GFP_KERNEL);
1513         spin_lock(&rtsx_pci_lock);
1514         ret = idr_alloc(&rtsx_pci_idr, pcr, 0, 0, GFP_NOWAIT);
1515         if (ret >= 0)
1516                 pcr->id = ret;
1517         spin_unlock(&rtsx_pci_lock);
1518         idr_preload_end();
1519         if (ret < 0)
1520                 goto free_handle;
1521
1522         pcr->pci = pcidev;
1523         dev_set_drvdata(&pcidev->dev, handle);
1524
1525         if (CHK_PCI_PID(pcr, 0x525A))
1526                 bar = 1;
1527         len = pci_resource_len(pcidev, bar);
1528         base = pci_resource_start(pcidev, bar);
1529         pcr->remap_addr = ioremap(base, len);
1530         if (!pcr->remap_addr) {
1531                 ret = -ENOMEM;
1532                 goto free_idr;
1533         }
1534
1535         pcr->rtsx_resv_buf = dma_alloc_coherent(&(pcidev->dev),
1536                         RTSX_RESV_BUF_LEN, &(pcr->rtsx_resv_buf_addr),
1537                         GFP_KERNEL);
1538         if (pcr->rtsx_resv_buf == NULL) {
1539                 ret = -ENXIO;
1540                 goto unmap;
1541         }
1542         pcr->host_cmds_ptr = pcr->rtsx_resv_buf;
1543         pcr->host_cmds_addr = pcr->rtsx_resv_buf_addr;
1544         pcr->host_sg_tbl_ptr = pcr->rtsx_resv_buf + HOST_CMDS_BUF_LEN;
1545         pcr->host_sg_tbl_addr = pcr->rtsx_resv_buf_addr + HOST_CMDS_BUF_LEN;
1546
1547         pcr->card_inserted = 0;
1548         pcr->card_removed = 0;
1549         INIT_DELAYED_WORK(&pcr->carddet_work, rtsx_pci_card_detect);
1550         INIT_DELAYED_WORK(&pcr->idle_work, rtsx_pci_idle_work);
1551
1552         pcr->msi_en = msi_en;
1553         if (pcr->msi_en) {
1554                 ret = pci_enable_msi(pcidev);
1555                 if (ret)
1556                         pcr->msi_en = false;
1557         }
1558
1559         ret = rtsx_pci_acquire_irq(pcr);
1560         if (ret < 0)
1561                 goto disable_msi;
1562
1563         pci_set_master(pcidev);
1564         synchronize_irq(pcr->irq);
1565
1566         ret = rtsx_pci_init_chip(pcr);
1567         if (ret < 0)
1568                 goto disable_irq;
1569
1570         for (i = 0; i < ARRAY_SIZE(rtsx_pcr_cells); i++) {
1571                 rtsx_pcr_cells[i].platform_data = handle;
1572                 rtsx_pcr_cells[i].pdata_size = sizeof(*handle);
1573         }
1574         ret = mfd_add_devices(&pcidev->dev, pcr->id, rtsx_pcr_cells,
1575                         ARRAY_SIZE(rtsx_pcr_cells), NULL, 0, NULL);
1576         if (ret < 0)
1577                 goto free_slots;
1578
1579         schedule_delayed_work(&pcr->idle_work, msecs_to_jiffies(200));
1580
1581         return 0;
1582
1583 free_slots:
1584         kfree(pcr->slots);
1585 disable_irq:
1586         free_irq(pcr->irq, (void *)pcr);
1587 disable_msi:
1588         if (pcr->msi_en)
1589                 pci_disable_msi(pcr->pci);
1590         dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN,
1591                         pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr);
1592 unmap:
1593         iounmap(pcr->remap_addr);
1594 free_idr:
1595         spin_lock(&rtsx_pci_lock);
1596         idr_remove(&rtsx_pci_idr, pcr->id);
1597         spin_unlock(&rtsx_pci_lock);
1598 free_handle:
1599         kfree(handle);
1600 free_pcr:
1601         kfree(pcr);
1602 release_pci:
1603         pci_release_regions(pcidev);
1604 disable:
1605         pci_disable_device(pcidev);
1606
1607         return ret;
1608 }
1609
1610 static void rtsx_pci_remove(struct pci_dev *pcidev)
1611 {
1612         struct pcr_handle *handle = pci_get_drvdata(pcidev);
1613         struct rtsx_pcr *pcr = handle->pcr;
1614
1615         pcr->remove_pci = true;
1616
1617         /* Disable interrupts at the pcr level */
1618         spin_lock_irq(&pcr->lock);
1619         rtsx_pci_writel(pcr, RTSX_BIER, 0);
1620         pcr->bier = 0;
1621         spin_unlock_irq(&pcr->lock);
1622
1623         cancel_delayed_work_sync(&pcr->carddet_work);
1624         cancel_delayed_work_sync(&pcr->idle_work);
1625
1626         mfd_remove_devices(&pcidev->dev);
1627
1628         dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN,
1629                         pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr);
1630         free_irq(pcr->irq, (void *)pcr);
1631         if (pcr->msi_en)
1632                 pci_disable_msi(pcr->pci);
1633         iounmap(pcr->remap_addr);
1634
1635         pci_release_regions(pcidev);
1636         pci_disable_device(pcidev);
1637
1638         spin_lock(&rtsx_pci_lock);
1639         idr_remove(&rtsx_pci_idr, pcr->id);
1640         spin_unlock(&rtsx_pci_lock);
1641
1642         kfree(pcr->slots);
1643         kfree(pcr);
1644         kfree(handle);
1645
1646         dev_dbg(&(pcidev->dev),
1647                 ": Realtek PCI-E Card Reader at %s [%04x:%04x] has been removed\n",
1648                 pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device);
1649 }
1650
1651 static int __maybe_unused rtsx_pci_suspend(struct device *dev_d)
1652 {
1653         struct pci_dev *pcidev = to_pci_dev(dev_d);
1654         struct pcr_handle *handle;
1655         struct rtsx_pcr *pcr;
1656
1657         dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
1658
1659         handle = pci_get_drvdata(pcidev);
1660         pcr = handle->pcr;
1661
1662         cancel_delayed_work(&pcr->carddet_work);
1663         cancel_delayed_work(&pcr->idle_work);
1664
1665         mutex_lock(&pcr->pcr_mutex);
1666
1667         rtsx_pci_power_off(pcr, HOST_ENTER_S3);
1668
1669         device_wakeup_disable(dev_d);
1670
1671         mutex_unlock(&pcr->pcr_mutex);
1672         return 0;
1673 }
1674
1675 static int __maybe_unused rtsx_pci_resume(struct device *dev_d)
1676 {
1677         struct pci_dev *pcidev = to_pci_dev(dev_d);
1678         struct pcr_handle *handle;
1679         struct rtsx_pcr *pcr;
1680         int ret = 0;
1681
1682         dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
1683
1684         handle = pci_get_drvdata(pcidev);
1685         pcr = handle->pcr;
1686
1687         mutex_lock(&pcr->pcr_mutex);
1688
1689         ret = rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, 0x00);
1690         if (ret)
1691                 goto out;
1692
1693         ret = rtsx_pci_init_hw(pcr);
1694         if (ret)
1695                 goto out;
1696
1697         schedule_delayed_work(&pcr->idle_work, msecs_to_jiffies(200));
1698
1699 out:
1700         mutex_unlock(&pcr->pcr_mutex);
1701         return ret;
1702 }
1703
1704 #ifdef CONFIG_PM
1705
1706 static void rtsx_pci_shutdown(struct pci_dev *pcidev)
1707 {
1708         struct pcr_handle *handle;
1709         struct rtsx_pcr *pcr;
1710
1711         dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
1712
1713         handle = pci_get_drvdata(pcidev);
1714         pcr = handle->pcr;
1715         rtsx_pci_power_off(pcr, HOST_ENTER_S1);
1716
1717         pci_disable_device(pcidev);
1718         free_irq(pcr->irq, (void *)pcr);
1719         if (pcr->msi_en)
1720                 pci_disable_msi(pcr->pci);
1721 }
1722
1723 #else /* CONFIG_PM */
1724
1725 #define rtsx_pci_shutdown NULL
1726
1727 #endif /* CONFIG_PM */
1728
1729 static SIMPLE_DEV_PM_OPS(rtsx_pci_pm_ops, rtsx_pci_suspend, rtsx_pci_resume);
1730
1731 static struct pci_driver rtsx_pci_driver = {
1732         .name = DRV_NAME_RTSX_PCI,
1733         .id_table = rtsx_pci_ids,
1734         .probe = rtsx_pci_probe,
1735         .remove = rtsx_pci_remove,
1736         .driver.pm = &rtsx_pci_pm_ops,
1737         .shutdown = rtsx_pci_shutdown,
1738 };
1739 module_pci_driver(rtsx_pci_driver);
1740
1741 MODULE_LICENSE("GPL");
1742 MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
1743 MODULE_DESCRIPTION("Realtek PCI-E Card Reader Driver");