drivers/mfd/stmpe.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * ST Microelectronics MFD: stmpe's driver
   4  *
   5  * Copyright (C) ST-Ericsson SA 2010
   6  *
   7  * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
   8  */
   9
  10 #include <linux/err.h>
  11 #include <linux/gpio.h>
  12 #include <linux/export.h>
  13 #include <linux/kernel.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/irq.h>
  16 #include <linux/irqdomain.h>
  17 #include <linux/of.h>
  18 #include <linux/of_gpio.h>
  19 #include <linux/pm.h>
  20 #include <linux/slab.h>
  21 #include <linux/mfd/core.h>
  22 #include <linux/delay.h>
  23 #include <linux/regulator/consumer.h>
  24 #include "stmpe.h"
  25
  26 /**
  27  * struct stmpe_platform_data - STMPE platform data
  28  * @id: device id to distinguish between multiple STMPEs on the same board
  29  * @blocks: bitmask of blocks to enable (use STMPE_BLOCK_*)
  30  * @irq_trigger: IRQ trigger to use for the interrupt to the host
  31  * @autosleep: bool to enable/disable stmpe autosleep
  32  * @autosleep_timeout: inactivity timeout in milliseconds for autosleep
  33  * @irq_over_gpio: true if gpio is used to get irq
  34  * @irq_gpio: gpio number over which irq will be requested (significant only if
  35  *            irq_over_gpio is true)
  36  */
  37 struct stmpe_platform_data {
  38         int id;
  39         unsigned int blocks;
  40         unsigned int irq_trigger;
  41         bool autosleep;
  42         bool irq_over_gpio;
  43         int irq_gpio;
  44         int autosleep_timeout;
  45 };
  46
  47 static int __stmpe_enable(struct stmpe *stmpe, unsigned int blocks)
  48 {
  49         return stmpe->variant->enable(stmpe, blocks, true);
  50 }
  51
  52 static int __stmpe_disable(struct stmpe *stmpe, unsigned int blocks)
  53 {
  54         return stmpe->variant->enable(stmpe, blocks, false);
  55 }
  56
  57 static int __stmpe_reg_read(struct stmpe *stmpe, u8 reg)
  58 {
  59         int ret;
  60
  61         ret = stmpe->ci->read_byte(stmpe, reg);
  62         if (ret < 0)
  63                 dev_err(stmpe->dev, "failed to read reg %#x: %d\n", reg, ret);
  64
  65         dev_vdbg(stmpe->dev, "rd: reg %#x => data %#x\n", reg, ret);
  66
  67         return ret;
  68 }
  69
  70 static int __stmpe_reg_write(struct stmpe *stmpe, u8 reg, u8 val)
  71 {
  72         int ret;
  73
  74         dev_vdbg(stmpe->dev, "wr: reg %#x <= %#x\n", reg, val);
  75
  76         ret = stmpe->ci->write_byte(stmpe, reg, val);
  77         if (ret < 0)
  78                 dev_err(stmpe->dev, "failed to write reg %#x: %d\n", reg, ret);
  79
  80         return ret;
  81 }
  82
  83 static int __stmpe_set_bits(struct stmpe *stmpe, u8 reg, u8 mask, u8 val)
  84 {
  85         int ret;
  86
  87         ret = __stmpe_reg_read(stmpe, reg);
  88         if (ret < 0)
  89                 return ret;
  90
  91         ret &= ~mask;
  92         ret |= val;
  93
  94         return __stmpe_reg_write(stmpe, reg, ret);
  95 }
  96
  97 static int __stmpe_block_read(struct stmpe *stmpe, u8 reg, u8 length,
  98                               u8 *values)
  99 {
 100         int ret;
 101
 102         ret = stmpe->ci->read_block(stmpe, reg, length, values);
 103         if (ret < 0)
 104                 dev_err(stmpe->dev, "failed to read regs %#x: %d\n", reg, ret);
 105
 106         dev_vdbg(stmpe->dev, "rd: reg %#x (%d) => ret %#x\n", reg, length, ret);
 107         stmpe_dump_bytes("stmpe rd: ", values, length);
 108
 109         return ret;
 110 }
 111
 112 static int __stmpe_block_write(struct stmpe *stmpe, u8 reg, u8 length,
 113                         const u8 *values)
 114 {
 115         int ret;
 116
 117         dev_vdbg(stmpe->dev, "wr: regs %#x (%d)\n", reg, length);
 118         stmpe_dump_bytes("stmpe wr: ", values, length);
 119
 120         ret = stmpe->ci->write_block(stmpe, reg, length, values);
 121         if (ret < 0)
 122                 dev_err(stmpe->dev, "failed to write regs %#x: %d\n", reg, ret);
 123
 124         return ret;
 125 }
 126
 127 /**
 128  * stmpe_enable - enable blocks on an STMPE device
 129  * @stmpe:      Device to work on
 130  * @blocks:     Mask of blocks (enum stmpe_block values) to enable
 131  */
 132 int stmpe_enable(struct stmpe *stmpe, unsigned int blocks)
 133 {
 134         int ret;
 135
 136         mutex_lock(&stmpe->lock);
 137         ret = __stmpe_enable(stmpe, blocks);
 138         mutex_unlock(&stmpe->lock);
 139
 140         return ret;
 141 }
 142 EXPORT_SYMBOL_GPL(stmpe_enable);
 143
 144 /**
 145  * stmpe_disable - disable blocks on an STMPE device
 146  * @stmpe:      Device to work on
 147  * @blocks:     Mask of blocks (enum stmpe_block values) to enable
 148  */
 149 int stmpe_disable(struct stmpe *stmpe, unsigned int blocks)
 150 {
 151         int ret;
 152
 153         mutex_lock(&stmpe->lock);
 154         ret = __stmpe_disable(stmpe, blocks);
 155         mutex_unlock(&stmpe->lock);
 156
 157         return ret;
 158 }
 159 EXPORT_SYMBOL_GPL(stmpe_disable);
 160
 161 /**
 162  * stmpe_reg_read() - read a single STMPE register
 163  * @stmpe:      Device to read from
 164  * @reg:        Register to read
 165  */
 166 int stmpe_reg_read(struct stmpe *stmpe, u8 reg)
 167 {
 168         int ret;
 169
 170         mutex_lock(&stmpe->lock);
 171         ret = __stmpe_reg_read(stmpe, reg);
 172         mutex_unlock(&stmpe->lock);
 173
 174         return ret;
 175 }
 176 EXPORT_SYMBOL_GPL(stmpe_reg_read);
 177
 178 /**
 179  * stmpe_reg_write() - write a single STMPE register
 180  * @stmpe:      Device to write to
 181  * @reg:        Register to write
 182  * @val:        Value to write
 183  */
 184 int stmpe_reg_write(struct stmpe *stmpe, u8 reg, u8 val)
 185 {
 186         int ret;
 187
 188         mutex_lock(&stmpe->lock);
 189         ret = __stmpe_reg_write(stmpe, reg, val);
 190         mutex_unlock(&stmpe->lock);
 191
 192         return ret;
 193 }
 194 EXPORT_SYMBOL_GPL(stmpe_reg_write);
 195
 196 /**
 197  * stmpe_set_bits() - set the value of a bitfield in a STMPE register
 198  * @stmpe:      Device to write to
 199  * @reg:        Register to write
 200  * @mask:       Mask of bits to set
 201  * @val:        Value to set
 202  */
 203 int stmpe_set_bits(struct stmpe *stmpe, u8 reg, u8 mask, u8 val)
 204 {
 205         int ret;
 206
 207         mutex_lock(&stmpe->lock);
 208         ret = __stmpe_set_bits(stmpe, reg, mask, val);
 209         mutex_unlock(&stmpe->lock);
 210
 211         return ret;
 212 }
 213 EXPORT_SYMBOL_GPL(stmpe_set_bits);
 214
 215 /**
 216  * stmpe_block_read() - read multiple STMPE registers
 217  * @stmpe:      Device to read from
 218  * @reg:        First register
 219  * @length:     Number of registers
 220  * @values:     Buffer to write to
 221  */
 222 int stmpe_block_read(struct stmpe *stmpe, u8 reg, u8 length, u8 *values)
 223 {
 224         int ret;
 225
 226         mutex_lock(&stmpe->lock);
 227         ret = __stmpe_block_read(stmpe, reg, length, values);
 228         mutex_unlock(&stmpe->lock);
 229
 230         return ret;
 231 }
 232 EXPORT_SYMBOL_GPL(stmpe_block_read);
 233
 234 /**
 235  * stmpe_block_write() - write multiple STMPE registers
 236  * @stmpe:      Device to write to
 237  * @reg:        First register
 238  * @length:     Number of registers
 239  * @values:     Values to write
 240  */
 241 int stmpe_block_write(struct stmpe *stmpe, u8 reg, u8 length,
 242                       const u8 *values)
 243 {
 244         int ret;
 245
 246         mutex_lock(&stmpe->lock);
 247         ret = __stmpe_block_write(stmpe, reg, length, values);
 248         mutex_unlock(&stmpe->lock);
 249
 250         return ret;
 251 }
 252 EXPORT_SYMBOL_GPL(stmpe_block_write);
 253
 254 /**
 255  * stmpe_set_altfunc()- set the alternate function for STMPE pins
 256  * @stmpe:      Device to configure
 257  * @pins:       Bitmask of pins to affect
 258  * @block:      block to enable alternate functions for
 259  *
 260  * @pins is assumed to have a bit set for each of the bits whose alternate
 261  * function is to be changed, numbered according to the GPIOXY numbers.
 262  *
 263  * If the GPIO module is not enabled, this function automatically enables it in
 264  * order to perform the change.
 265  */
 266 int stmpe_set_altfunc(struct stmpe *stmpe, u32 pins, enum stmpe_block block)
 267 {
 268         struct stmpe_variant_info *variant = stmpe->variant;
 269         u8 regaddr = stmpe->regs[STMPE_IDX_GPAFR_U_MSB];
 270         int af_bits = variant->af_bits;
 271         int numregs = DIV_ROUND_UP(stmpe->num_gpios * af_bits, 8);
 272         int mask = (1 << af_bits) - 1;
 273         u8 regs[8];
 274         int af, afperreg, ret;
 275
 276         if (!variant->get_altfunc)
 277                 return 0;
 278
 279         afperreg = 8 / af_bits;
 280         mutex_lock(&stmpe->lock);
 281
 282         ret = __stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
 283         if (ret < 0)
 284                 goto out;
 285
 286         ret = __stmpe_block_read(stmpe, regaddr, numregs, regs);
 287         if (ret < 0)
 288                 goto out;
 289
 290         af = variant->get_altfunc(stmpe, block);
 291
 292         while (pins) {
 293                 int pin = __ffs(pins);
 294                 int regoffset = numregs - (pin / afperreg) - 1;
 295                 int pos = (pin % afperreg) * (8 / afperreg);
 296
 297                 regs[regoffset] &= ~(mask << pos);
 298                 regs[regoffset] |= af << pos;
 299
 300                 pins &= ~(1 << pin);
 301         }
 302
 303         ret = __stmpe_block_write(stmpe, regaddr, numregs, regs);
 304
 305 out:
 306         mutex_unlock(&stmpe->lock);
 307         return ret;
 308 }
 309 EXPORT_SYMBOL_GPL(stmpe_set_altfunc);
 310
 311 /*
 312  * GPIO (all variants)
 313  */
 314
 315 static struct resource stmpe_gpio_resources[] = {
 316         /* Start and end filled dynamically */
 317         {
 318                 .flags  = IORESOURCE_IRQ,
 319         },
 320 };
 321
 322 static const struct mfd_cell stmpe_gpio_cell = {
 323         .name           = "stmpe-gpio",
 324         .of_compatible  = "st,stmpe-gpio",
 325         .resources      = stmpe_gpio_resources,
 326         .num_resources  = ARRAY_SIZE(stmpe_gpio_resources),
 327 };
 328
 329 static const struct mfd_cell stmpe_gpio_cell_noirq = {
 330         .name           = "stmpe-gpio",
 331         .of_compatible  = "st,stmpe-gpio",
 332         /* gpio cell resources consist of an irq only so no resources here */
 333 };
 334
 335 /*
 336  * Keypad (1601, 2401, 2403)
 337  */
 338
 339 static struct resource stmpe_keypad_resources[] = {
 340         /* Start and end filled dynamically */
 341         {
 342                 .name   = "KEYPAD",
 343                 .flags  = IORESOURCE_IRQ,
 344         },
 345         {
 346                 .name   = "KEYPAD_OVER",
 347                 .flags  = IORESOURCE_IRQ,
 348         },
 349 };
 350
 351 static const struct mfd_cell stmpe_keypad_cell = {
 352         .name           = "stmpe-keypad",
 353         .of_compatible  = "st,stmpe-keypad",
 354         .resources      = stmpe_keypad_resources,
 355         .num_resources  = ARRAY_SIZE(stmpe_keypad_resources),
 356 };
 357
 358 /*
 359  * PWM (1601, 2401, 2403)
 360  */
 361 static struct resource stmpe_pwm_resources[] = {
 362         /* Start and end filled dynamically */
 363         {
 364                 .name   = "PWM0",
 365                 .flags  = IORESOURCE_IRQ,
 366         },
 367         {
 368                 .name   = "PWM1",
 369                 .flags  = IORESOURCE_IRQ,
 370         },
 371         {
 372                 .name   = "PWM2",
 373                 .flags  = IORESOURCE_IRQ,
 374         },
 375 };
 376
 377 static const struct mfd_cell stmpe_pwm_cell = {
 378         .name           = "stmpe-pwm",
 379         .of_compatible  = "st,stmpe-pwm",
 380         .resources      = stmpe_pwm_resources,
 381         .num_resources  = ARRAY_SIZE(stmpe_pwm_resources),
 382 };
 383
 384 /*
 385  * STMPE801
 386  */
 387 static const u8 stmpe801_regs[] = {
 388         [STMPE_IDX_CHIP_ID]     = STMPE801_REG_CHIP_ID,
 389         [STMPE_IDX_ICR_LSB]     = STMPE801_REG_SYS_CTRL,
 390         [STMPE_IDX_GPMR_LSB]    = STMPE801_REG_GPIO_MP_STA,
 391         [STMPE_IDX_GPSR_LSB]    = STMPE801_REG_GPIO_SET_PIN,
 392         [STMPE_IDX_GPCR_LSB]    = STMPE801_REG_GPIO_SET_PIN,
 393         [STMPE_IDX_GPDR_LSB]    = STMPE801_REG_GPIO_DIR,
 394         [STMPE_IDX_IEGPIOR_LSB] = STMPE801_REG_GPIO_INT_EN,
 395         [STMPE_IDX_ISGPIOR_MSB] = STMPE801_REG_GPIO_INT_STA,
 396
 397 };
 398
 399 static struct stmpe_variant_block stmpe801_blocks[] = {
 400         {
 401                 .cell   = &stmpe_gpio_cell,
 402                 .irq    = 0,
 403                 .block  = STMPE_BLOCK_GPIO,
 404         },
 405 };
 406
 407 static struct stmpe_variant_block stmpe801_blocks_noirq[] = {
 408         {
 409                 .cell   = &stmpe_gpio_cell_noirq,
 410                 .block  = STMPE_BLOCK_GPIO,
 411         },
 412 };
 413
 414 static int stmpe801_enable(struct stmpe *stmpe, unsigned int blocks,
 415                            bool enable)
 416 {
 417         if (blocks & STMPE_BLOCK_GPIO)
 418                 return 0;
 419         else
 420                 return -EINVAL;
 421 }
 422
 423 static struct stmpe_variant_info stmpe801 = {
 424         .name           = "stmpe801",
 425         .id_val         = STMPE801_ID,
 426         .id_mask        = 0xffff,
 427         .num_gpios      = 8,
 428         .regs           = stmpe801_regs,
 429         .blocks         = stmpe801_blocks,
 430         .num_blocks     = ARRAY_SIZE(stmpe801_blocks),
 431         .num_irqs       = STMPE801_NR_INTERNAL_IRQS,
 432         .enable         = stmpe801_enable,
 433 };
 434
 435 static struct stmpe_variant_info stmpe801_noirq = {
 436         .name           = "stmpe801",
 437         .id_val         = STMPE801_ID,
 438         .id_mask        = 0xffff,
 439         .num_gpios      = 8,
 440         .regs           = stmpe801_regs,
 441         .blocks         = stmpe801_blocks_noirq,
 442         .num_blocks     = ARRAY_SIZE(stmpe801_blocks_noirq),
 443         .enable         = stmpe801_enable,
 444 };
 445
 446 /*
 447  * Touchscreen (STMPE811 or STMPE610)
 448  */
 449
 450 static struct resource stmpe_ts_resources[] = {
 451         /* Start and end filled dynamically */
 452         {
 453                 .name   = "TOUCH_DET",
 454                 .flags  = IORESOURCE_IRQ,
 455         },
 456         {
 457                 .name   = "FIFO_TH",
 458                 .flags  = IORESOURCE_IRQ,
 459         },
 460 };
 461
 462 static const struct mfd_cell stmpe_ts_cell = {
 463         .name           = "stmpe-ts",
 464         .of_compatible  = "st,stmpe-ts",
 465         .resources      = stmpe_ts_resources,
 466         .num_resources  = ARRAY_SIZE(stmpe_ts_resources),
 467 };
 468
 469 /*
 470  * ADC (STMPE811)
 471  */
 472
 473 static struct resource stmpe_adc_resources[] = {
 474         /* Start and end filled dynamically */
 475         {
 476                 .name   = "STMPE_TEMP_SENS",
 477                 .flags  = IORESOURCE_IRQ,
 478         },
 479         {
 480                 .name   = "STMPE_ADC",
 481                 .flags  = IORESOURCE_IRQ,
 482         },
 483 };
 484
 485 static const struct mfd_cell stmpe_adc_cell = {
 486         .name           = "stmpe-adc",
 487         .of_compatible  = "st,stmpe-adc",
 488         .resources      = stmpe_adc_resources,
 489         .num_resources  = ARRAY_SIZE(stmpe_adc_resources),
 490 };
 491
 492 /*
 493  * STMPE811 or STMPE610
 494  */
 495
 496 static const u8 stmpe811_regs[] = {
 497         [STMPE_IDX_CHIP_ID]     = STMPE811_REG_CHIP_ID,
 498         [STMPE_IDX_SYS_CTRL]    = STMPE811_REG_SYS_CTRL,
 499         [STMPE_IDX_SYS_CTRL2]   = STMPE811_REG_SYS_CTRL2,
 500         [STMPE_IDX_ICR_LSB]     = STMPE811_REG_INT_CTRL,
 501         [STMPE_IDX_IER_LSB]     = STMPE811_REG_INT_EN,
 502         [STMPE_IDX_ISR_MSB]     = STMPE811_REG_INT_STA,
 503         [STMPE_IDX_GPMR_LSB]    = STMPE811_REG_GPIO_MP_STA,
 504         [STMPE_IDX_GPSR_LSB]    = STMPE811_REG_GPIO_SET_PIN,
 505         [STMPE_IDX_GPCR_LSB]    = STMPE811_REG_GPIO_CLR_PIN,
 506         [STMPE_IDX_GPDR_LSB]    = STMPE811_REG_GPIO_DIR,
 507         [STMPE_IDX_GPRER_LSB]   = STMPE811_REG_GPIO_RE,
 508         [STMPE_IDX_GPFER_LSB]   = STMPE811_REG_GPIO_FE,
 509         [STMPE_IDX_GPAFR_U_MSB] = STMPE811_REG_GPIO_AF,
 510         [STMPE_IDX_IEGPIOR_LSB] = STMPE811_REG_GPIO_INT_EN,
 511         [STMPE_IDX_ISGPIOR_MSB] = STMPE811_REG_GPIO_INT_STA,
 512         [STMPE_IDX_GPEDR_LSB]   = STMPE811_REG_GPIO_ED,
 513 };
 514
 515 static struct stmpe_variant_block stmpe811_blocks[] = {
 516         {
 517                 .cell   = &stmpe_gpio_cell,
 518                 .irq    = STMPE811_IRQ_GPIOC,
 519                 .block  = STMPE_BLOCK_GPIO,
 520         },
 521         {
 522                 .cell   = &stmpe_ts_cell,
 523                 .irq    = STMPE811_IRQ_TOUCH_DET,
 524                 .block  = STMPE_BLOCK_TOUCHSCREEN,
 525         },
 526         {
 527                 .cell   = &stmpe_adc_cell,
 528                 .irq    = STMPE811_IRQ_TEMP_SENS,
 529                 .block  = STMPE_BLOCK_ADC,
 530         },
 531 };
 532
 533 static int stmpe811_enable(struct stmpe *stmpe, unsigned int blocks,
 534                            bool enable)
 535 {
 536         unsigned int mask = 0;
 537
 538         if (blocks & STMPE_BLOCK_GPIO)
 539                 mask |= STMPE811_SYS_CTRL2_GPIO_OFF;
 540
 541         if (blocks & STMPE_BLOCK_ADC)
 542                 mask |= STMPE811_SYS_CTRL2_ADC_OFF;
 543
 544         if (blocks & STMPE_BLOCK_TOUCHSCREEN)
 545                 mask |= STMPE811_SYS_CTRL2_TSC_OFF;
 546
 547         return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL2], mask,
 548                                 enable ? 0 : mask);
 549 }
 550
 551 int stmpe811_adc_common_init(struct stmpe *stmpe)
 552 {
 553         int ret;
 554         u8 adc_ctrl1, adc_ctrl1_mask;
 555
 556         adc_ctrl1 = STMPE_SAMPLE_TIME(stmpe->sample_time) |
 557                     STMPE_MOD_12B(stmpe->mod_12b) |
 558                     STMPE_REF_SEL(stmpe->ref_sel);
 559         adc_ctrl1_mask = STMPE_SAMPLE_TIME(0xff) | STMPE_MOD_12B(0xff) |
 560                          STMPE_REF_SEL(0xff);
 561
 562         ret = stmpe_set_bits(stmpe, STMPE811_REG_ADC_CTRL1,
 563                         adc_ctrl1_mask, adc_ctrl1);
 564         if (ret) {
 565                 dev_err(stmpe->dev, "Could not setup ADC\n");
 566                 return ret;
 567         }
 568
 569         ret = stmpe_set_bits(stmpe, STMPE811_REG_ADC_CTRL2,
 570                         STMPE_ADC_FREQ(0xff), STMPE_ADC_FREQ(stmpe->adc_freq));
 571         if (ret) {
 572                 dev_err(stmpe->dev, "Could not setup ADC\n");
 573                 return ret;
 574         }
 575
 576         return 0;
 577 }
 578 EXPORT_SYMBOL_GPL(stmpe811_adc_common_init);
 579
 580 static int stmpe811_get_altfunc(struct stmpe *stmpe, enum stmpe_block block)
 581 {
 582         /* 0 for touchscreen, 1 for GPIO */
 583         return block != STMPE_BLOCK_TOUCHSCREEN;
 584 }
 585
 586 static struct stmpe_variant_info stmpe811 = {
 587         .name           = "stmpe811",
 588         .id_val         = 0x0811,
 589         .id_mask        = 0xffff,
 590         .num_gpios      = 8,
 591         .af_bits        = 1,
 592         .regs           = stmpe811_regs,
 593         .blocks         = stmpe811_blocks,
 594         .num_blocks     = ARRAY_SIZE(stmpe811_blocks),
 595         .num_irqs       = STMPE811_NR_INTERNAL_IRQS,
 596         .enable         = stmpe811_enable,
 597         .get_altfunc    = stmpe811_get_altfunc,
 598 };
 599
 600 /* Similar to 811, except number of gpios */
 601 static struct stmpe_variant_info stmpe610 = {
 602         .name           = "stmpe610",
 603         .id_val         = 0x0811,
 604         .id_mask        = 0xffff,
 605         .num_gpios      = 6,
 606         .af_bits        = 1,
 607         .regs           = stmpe811_regs,
 608         .blocks         = stmpe811_blocks,
 609         .num_blocks     = ARRAY_SIZE(stmpe811_blocks),
 610         .num_irqs       = STMPE811_NR_INTERNAL_IRQS,
 611         .enable         = stmpe811_enable,
 612         .get_altfunc    = stmpe811_get_altfunc,
 613 };
 614
 615 /*
 616  * STMPE1600
 617  * Compared to all others STMPE variant, LSB and MSB regs are located in this
 618  * order :      LSB   addr
 619  *              MSB   addr + 1
 620  * As there is only 2 * 8bits registers for GPMR/GPSR/IEGPIOPR, CSB index is MSB registers
 621  */
 622
 623 static const u8 stmpe1600_regs[] = {
 624         [STMPE_IDX_CHIP_ID]     = STMPE1600_REG_CHIP_ID,
 625         [STMPE_IDX_SYS_CTRL]    = STMPE1600_REG_SYS_CTRL,
 626         [STMPE_IDX_ICR_LSB]     = STMPE1600_REG_SYS_CTRL,
 627         [STMPE_IDX_GPMR_LSB]    = STMPE1600_REG_GPMR_LSB,
 628         [STMPE_IDX_GPMR_CSB]    = STMPE1600_REG_GPMR_MSB,
 629         [STMPE_IDX_GPSR_LSB]    = STMPE1600_REG_GPSR_LSB,
 630         [STMPE_IDX_GPSR_CSB]    = STMPE1600_REG_GPSR_MSB,
 631         [STMPE_IDX_GPCR_LSB]    = STMPE1600_REG_GPSR_LSB,
 632         [STMPE_IDX_GPCR_CSB]    = STMPE1600_REG_GPSR_MSB,
 633         [STMPE_IDX_GPDR_LSB]    = STMPE1600_REG_GPDR_LSB,
 634         [STMPE_IDX_GPDR_CSB]    = STMPE1600_REG_GPDR_MSB,
 635         [STMPE_IDX_IEGPIOR_LSB] = STMPE1600_REG_IEGPIOR_LSB,
 636         [STMPE_IDX_IEGPIOR_CSB] = STMPE1600_REG_IEGPIOR_MSB,
 637         [STMPE_IDX_ISGPIOR_LSB] = STMPE1600_REG_ISGPIOR_LSB,
 638 };
 639
 640 static struct stmpe_variant_block stmpe1600_blocks[] = {
 641         {
 642                 .cell   = &stmpe_gpio_cell,
 643                 .irq    = 0,
 644                 .block  = STMPE_BLOCK_GPIO,
 645         },
 646 };
 647
 648 static int stmpe1600_enable(struct stmpe *stmpe, unsigned int blocks,
 649                            bool enable)
 650 {
 651         if (blocks & STMPE_BLOCK_GPIO)
 652                 return 0;
 653         else
 654                 return -EINVAL;
 655 }
 656
 657 static struct stmpe_variant_info stmpe1600 = {
 658         .name           = "stmpe1600",
 659         .id_val         = STMPE1600_ID,
 660         .id_mask        = 0xffff,
 661         .num_gpios      = 16,
 662         .af_bits        = 0,
 663         .regs           = stmpe1600_regs,
 664         .blocks         = stmpe1600_blocks,
 665         .num_blocks     = ARRAY_SIZE(stmpe1600_blocks),
 666         .num_irqs       = STMPE1600_NR_INTERNAL_IRQS,
 667         .enable         = stmpe1600_enable,
 668 };
 669
 670 /*
 671  * STMPE1601
 672  */
 673
 674 static const u8 stmpe1601_regs[] = {
 675         [STMPE_IDX_CHIP_ID]     = STMPE1601_REG_CHIP_ID,
 676         [STMPE_IDX_SYS_CTRL]    = STMPE1601_REG_SYS_CTRL,
 677         [STMPE_IDX_SYS_CTRL2]   = STMPE1601_REG_SYS_CTRL2,
 678         [STMPE_IDX_ICR_LSB]     = STMPE1601_REG_ICR_LSB,
 679         [STMPE_IDX_IER_MSB]     = STMPE1601_REG_IER_MSB,
 680         [STMPE_IDX_IER_LSB]     = STMPE1601_REG_IER_LSB,
 681         [STMPE_IDX_ISR_MSB]     = STMPE1601_REG_ISR_MSB,
 682         [STMPE_IDX_GPMR_LSB]    = STMPE1601_REG_GPIO_MP_LSB,
 683         [STMPE_IDX_GPMR_CSB]    = STMPE1601_REG_GPIO_MP_MSB,
 684         [STMPE_IDX_GPSR_LSB]    = STMPE1601_REG_GPIO_SET_LSB,
 685         [STMPE_IDX_GPSR_CSB]    = STMPE1601_REG_GPIO_SET_MSB,
 686         [STMPE_IDX_GPCR_LSB]    = STMPE1601_REG_GPIO_CLR_LSB,
 687         [STMPE_IDX_GPCR_CSB]    = STMPE1601_REG_GPIO_CLR_MSB,
 688         [STMPE_IDX_GPDR_LSB]    = STMPE1601_REG_GPIO_SET_DIR_LSB,
 689         [STMPE_IDX_GPDR_CSB]    = STMPE1601_REG_GPIO_SET_DIR_MSB,
 690         [STMPE_IDX_GPEDR_LSB]   = STMPE1601_REG_GPIO_ED_LSB,
 691         [STMPE_IDX_GPEDR_CSB]   = STMPE1601_REG_GPIO_ED_MSB,
 692         [STMPE_IDX_GPRER_LSB]   = STMPE1601_REG_GPIO_RE_LSB,
 693         [STMPE_IDX_GPRER_CSB]   = STMPE1601_REG_GPIO_RE_MSB,
 694         [STMPE_IDX_GPFER_LSB]   = STMPE1601_REG_GPIO_FE_LSB,
 695         [STMPE_IDX_GPFER_CSB]   = STMPE1601_REG_GPIO_FE_MSB,
 696         [STMPE_IDX_GPPUR_LSB]   = STMPE1601_REG_GPIO_PU_LSB,
 697         [STMPE_IDX_GPAFR_U_MSB] = STMPE1601_REG_GPIO_AF_U_MSB,
 698         [STMPE_IDX_IEGPIOR_LSB] = STMPE1601_REG_INT_EN_GPIO_MASK_LSB,
 699         [STMPE_IDX_IEGPIOR_CSB] = STMPE1601_REG_INT_EN_GPIO_MASK_MSB,
 700         [STMPE_IDX_ISGPIOR_MSB] = STMPE1601_REG_INT_STA_GPIO_MSB,
 701 };
 702
 703 static struct stmpe_variant_block stmpe1601_blocks[] = {
 704         {
 705                 .cell   = &stmpe_gpio_cell,
 706                 .irq    = STMPE1601_IRQ_GPIOC,
 707                 .block  = STMPE_BLOCK_GPIO,
 708         },
 709         {
 710                 .cell   = &stmpe_keypad_cell,
 711                 .irq    = STMPE1601_IRQ_KEYPAD,
 712                 .block  = STMPE_BLOCK_KEYPAD,
 713         },
 714         {
 715                 .cell   = &stmpe_pwm_cell,
 716                 .irq    = STMPE1601_IRQ_PWM0,
 717                 .block  = STMPE_BLOCK_PWM,
 718         },
 719 };
 720
 721 /* supported autosleep timeout delay (in msecs) */
 722 static const int stmpe_autosleep_delay[] = {
 723         4, 16, 32, 64, 128, 256, 512, 1024,
 724 };
 725
 726 static int stmpe_round_timeout(int timeout)
 727 {
 728         int i;
 729
 730         for (i = 0; i < ARRAY_SIZE(stmpe_autosleep_delay); i++) {
 731                 if (stmpe_autosleep_delay[i] >= timeout)
 732                         return i;
 733         }
 734
 735         /*
 736          * requests for delays longer than supported should not return the
 737          * longest supported delay
 738          */
 739         return -EINVAL;
 740 }
 741
 742 static int stmpe_autosleep(struct stmpe *stmpe, int autosleep_timeout)
 743 {
 744         int ret;
 745
 746         if (!stmpe->variant->enable_autosleep)
 747                 return -ENOSYS;
 748
 749         mutex_lock(&stmpe->lock);
 750         ret = stmpe->variant->enable_autosleep(stmpe, autosleep_timeout);
 751         mutex_unlock(&stmpe->lock);
 752
 753         return ret;
 754 }
 755
 756 /*
 757  * Both stmpe 1601/2403 support same layout for autosleep
 758  */
 759 static int stmpe1601_autosleep(struct stmpe *stmpe,
 760                 int autosleep_timeout)
 761 {
 762         int ret, timeout;
 763
 764         /* choose the best available timeout */
 765         timeout = stmpe_round_timeout(autosleep_timeout);
 766         if (timeout < 0) {
 767                 dev_err(stmpe->dev, "invalid timeout\n");
 768                 return timeout;
 769         }
 770
 771         ret = __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL2],
 772                         STMPE1601_AUTOSLEEP_TIMEOUT_MASK,
 773                         timeout);
 774         if (ret < 0)
 775                 return ret;
 776
 777         return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL2],
 778                         STPME1601_AUTOSLEEP_ENABLE,
 779                         STPME1601_AUTOSLEEP_ENABLE);
 780 }
 781
 782 static int stmpe1601_enable(struct stmpe *stmpe, unsigned int blocks,
 783                             bool enable)
 784 {
 785         unsigned int mask = 0;
 786
 787         if (blocks & STMPE_BLOCK_GPIO)
 788                 mask |= STMPE1601_SYS_CTRL_ENABLE_GPIO;
 789         else
 790                 mask &= ~STMPE1601_SYS_CTRL_ENABLE_GPIO;
 791
 792         if (blocks & STMPE_BLOCK_KEYPAD)
 793                 mask |= STMPE1601_SYS_CTRL_ENABLE_KPC;
 794         else
 795                 mask &= ~STMPE1601_SYS_CTRL_ENABLE_KPC;
 796
 797         if (blocks & STMPE_BLOCK_PWM)
 798                 mask |= STMPE1601_SYS_CTRL_ENABLE_SPWM;
 799         else
 800                 mask &= ~STMPE1601_SYS_CTRL_ENABLE_SPWM;
 801
 802         return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL], mask,
 803                                 enable ? mask : 0);
 804 }
 805
 806 static int stmpe1601_get_altfunc(struct stmpe *stmpe, enum stmpe_block block)
 807 {
 808         switch (block) {
 809         case STMPE_BLOCK_PWM:
 810                 return 2;
 811
 812         case STMPE_BLOCK_KEYPAD:
 813                 return 1;
 814
 815         case STMPE_BLOCK_GPIO:
 816         default:
 817                 return 0;
 818         }
 819 }
 820
 821 static struct stmpe_variant_info stmpe1601 = {
 822         .name           = "stmpe1601",
 823         .id_val         = 0x0210,
 824         .id_mask        = 0xfff0,       /* at least 0x0210 and 0x0212 */
 825         .num_gpios      = 16,
 826         .af_bits        = 2,
 827         .regs           = stmpe1601_regs,
 828         .blocks         = stmpe1601_blocks,
 829         .num_blocks     = ARRAY_SIZE(stmpe1601_blocks),
 830         .num_irqs       = STMPE1601_NR_INTERNAL_IRQS,
 831         .enable         = stmpe1601_enable,
 832         .get_altfunc    = stmpe1601_get_altfunc,
 833         .enable_autosleep       = stmpe1601_autosleep,
 834 };
 835
 836 /*
 837  * STMPE1801
 838  */
 839 static const u8 stmpe1801_regs[] = {
 840         [STMPE_IDX_CHIP_ID]     = STMPE1801_REG_CHIP_ID,
 841         [STMPE_IDX_SYS_CTRL]    = STMPE1801_REG_SYS_CTRL,
 842         [STMPE_IDX_ICR_LSB]     = STMPE1801_REG_INT_CTRL_LOW,
 843         [STMPE_IDX_IER_LSB]     = STMPE1801_REG_INT_EN_MASK_LOW,
 844         [STMPE_IDX_ISR_LSB]     = STMPE1801_REG_INT_STA_LOW,
 845         [STMPE_IDX_GPMR_LSB]    = STMPE1801_REG_GPIO_MP_LOW,
 846         [STMPE_IDX_GPMR_CSB]    = STMPE1801_REG_GPIO_MP_MID,
 847         [STMPE_IDX_GPMR_MSB]    = STMPE1801_REG_GPIO_MP_HIGH,
 848         [STMPE_IDX_GPSR_LSB]    = STMPE1801_REG_GPIO_SET_LOW,
 849         [STMPE_IDX_GPSR_CSB]    = STMPE1801_REG_GPIO_SET_MID,
 850         [STMPE_IDX_GPSR_MSB]    = STMPE1801_REG_GPIO_SET_HIGH,
 851         [STMPE_IDX_GPCR_LSB]    = STMPE1801_REG_GPIO_CLR_LOW,
 852         [STMPE_IDX_GPCR_CSB]    = STMPE1801_REG_GPIO_CLR_MID,
 853         [STMPE_IDX_GPCR_MSB]    = STMPE1801_REG_GPIO_CLR_HIGH,
 854         [STMPE_IDX_GPDR_LSB]    = STMPE1801_REG_GPIO_SET_DIR_LOW,
 855         [STMPE_IDX_GPDR_CSB]    = STMPE1801_REG_GPIO_SET_DIR_MID,
 856         [STMPE_IDX_GPDR_MSB]    = STMPE1801_REG_GPIO_SET_DIR_HIGH,
 857         [STMPE_IDX_GPRER_LSB]   = STMPE1801_REG_GPIO_RE_LOW,
 858         [STMPE_IDX_GPRER_CSB]   = STMPE1801_REG_GPIO_RE_MID,
 859         [STMPE_IDX_GPRER_MSB]   = STMPE1801_REG_GPIO_RE_HIGH,
 860         [STMPE_IDX_GPFER_LSB]   = STMPE1801_REG_GPIO_FE_LOW,
 861         [STMPE_IDX_GPFER_CSB]   = STMPE1801_REG_GPIO_FE_MID,
 862         [STMPE_IDX_GPFER_MSB]   = STMPE1801_REG_GPIO_FE_HIGH,
 863         [STMPE_IDX_GPPUR_LSB]   = STMPE1801_REG_GPIO_PULL_UP_LOW,
 864         [STMPE_IDX_IEGPIOR_LSB] = STMPE1801_REG_INT_EN_GPIO_MASK_LOW,
 865         [STMPE_IDX_IEGPIOR_CSB] = STMPE1801_REG_INT_EN_GPIO_MASK_MID,
 866         [STMPE_IDX_IEGPIOR_MSB] = STMPE1801_REG_INT_EN_GPIO_MASK_HIGH,
 867         [STMPE_IDX_ISGPIOR_MSB] = STMPE1801_REG_INT_STA_GPIO_HIGH,
 868 };
 869
 870 static struct stmpe_variant_block stmpe1801_blocks[] = {
 871         {
 872                 .cell   = &stmpe_gpio_cell,
 873                 .irq    = STMPE1801_IRQ_GPIOC,
 874                 .block  = STMPE_BLOCK_GPIO,
 875         },
 876         {
 877                 .cell   = &stmpe_keypad_cell,
 878                 .irq    = STMPE1801_IRQ_KEYPAD,
 879                 .block  = STMPE_BLOCK_KEYPAD,
 880         },
 881 };
 882
 883 static int stmpe1801_enable(struct stmpe *stmpe, unsigned int blocks,
 884                             bool enable)
 885 {
 886         unsigned int mask = 0;
 887         if (blocks & STMPE_BLOCK_GPIO)
 888                 mask |= STMPE1801_MSK_INT_EN_GPIO;
 889
 890         if (blocks & STMPE_BLOCK_KEYPAD)
 891                 mask |= STMPE1801_MSK_INT_EN_KPC;
 892
 893         return __stmpe_set_bits(stmpe, STMPE1801_REG_INT_EN_MASK_LOW, mask,
 894                                 enable ? mask : 0);
 895 }
 896
 897 static int stmpe_reset(struct stmpe *stmpe)
 898 {
 899         u16 id_val = stmpe->variant->id_val;
 900         unsigned long timeout;
 901         int ret = 0;
 902         u8 reset_bit;
 903
 904         if (id_val == STMPE811_ID)
 905                 /* STMPE801 and STMPE610 use bit 1 of SYS_CTRL register */
 906                 reset_bit = STMPE811_SYS_CTRL_RESET;
 907         else
 908                 /* all other STMPE variant use bit 7 of SYS_CTRL register */
 909                 reset_bit = STMPE_SYS_CTRL_RESET;
 910
 911         ret = __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL],
 912                                reset_bit, reset_bit);
 913         if (ret < 0)
 914                 return ret;
 915
 916         msleep(10);
 917
 918         timeout = jiffies + msecs_to_jiffies(100);
 919         while (time_before(jiffies, timeout)) {
 920                 ret = __stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL]);
 921                 if (ret < 0)
 922                         return ret;
 923                 if (!(ret & reset_bit))
 924                         return 0;
 925                 usleep_range(100, 200);
 926         }
 927         return -EIO;
 928 }
 929
 930 static struct stmpe_variant_info stmpe1801 = {
 931         .name           = "stmpe1801",
 932         .id_val         = STMPE1801_ID,
 933         .id_mask        = 0xfff0,
 934         .num_gpios      = 18,
 935         .af_bits        = 0,
 936         .regs           = stmpe1801_regs,
 937         .blocks         = stmpe1801_blocks,
 938         .num_blocks     = ARRAY_SIZE(stmpe1801_blocks),
 939         .num_irqs       = STMPE1801_NR_INTERNAL_IRQS,
 940         .enable         = stmpe1801_enable,
 941         /* stmpe1801 do not have any gpio alternate function */
 942         .get_altfunc    = NULL,
 943 };
 944
 945 /*
 946  * STMPE24XX
 947  */
 948
 949 static const u8 stmpe24xx_regs[] = {
 950         [STMPE_IDX_CHIP_ID]     = STMPE24XX_REG_CHIP_ID,
 951         [STMPE_IDX_SYS_CTRL]    = STMPE24XX_REG_SYS_CTRL,
 952         [STMPE_IDX_SYS_CTRL2]   = STMPE24XX_REG_SYS_CTRL2,
 953         [STMPE_IDX_ICR_LSB]     = STMPE24XX_REG_ICR_LSB,
 954         [STMPE_IDX_IER_MSB]     = STMPE24XX_REG_IER_MSB,
 955         [STMPE_IDX_IER_LSB]     = STMPE24XX_REG_IER_LSB,
 956         [STMPE_IDX_ISR_MSB]     = STMPE24XX_REG_ISR_MSB,
 957         [STMPE_IDX_GPMR_LSB]    = STMPE24XX_REG_GPMR_LSB,
 958         [STMPE_IDX_GPMR_CSB]    = STMPE24XX_REG_GPMR_CSB,
 959         [STMPE_IDX_GPMR_MSB]    = STMPE24XX_REG_GPMR_MSB,
 960         [STMPE_IDX_GPSR_LSB]    = STMPE24XX_REG_GPSR_LSB,
 961         [STMPE_IDX_GPSR_CSB]    = STMPE24XX_REG_GPSR_CSB,
 962         [STMPE_IDX_GPSR_MSB]    = STMPE24XX_REG_GPSR_MSB,
 963         [STMPE_IDX_GPCR_LSB]    = STMPE24XX_REG_GPCR_LSB,
 964         [STMPE_IDX_GPCR_CSB]    = STMPE24XX_REG_GPCR_CSB,
 965         [STMPE_IDX_GPCR_MSB]    = STMPE24XX_REG_GPCR_MSB,
 966         [STMPE_IDX_GPDR_LSB]    = STMPE24XX_REG_GPDR_LSB,
 967         [STMPE_IDX_GPDR_CSB]    = STMPE24XX_REG_GPDR_CSB,
 968         [STMPE_IDX_GPDR_MSB]    = STMPE24XX_REG_GPDR_MSB,
 969         [STMPE_IDX_GPRER_LSB]   = STMPE24XX_REG_GPRER_LSB,
 970         [STMPE_IDX_GPRER_CSB]   = STMPE24XX_REG_GPRER_CSB,
 971         [STMPE_IDX_GPRER_MSB]   = STMPE24XX_REG_GPRER_MSB,
 972         [STMPE_IDX_GPFER_LSB]   = STMPE24XX_REG_GPFER_LSB,
 973         [STMPE_IDX_GPFER_CSB]   = STMPE24XX_REG_GPFER_CSB,
 974         [STMPE_IDX_GPFER_MSB]   = STMPE24XX_REG_GPFER_MSB,
 975         [STMPE_IDX_GPPUR_LSB]   = STMPE24XX_REG_GPPUR_LSB,
 976         [STMPE_IDX_GPPDR_LSB]   = STMPE24XX_REG_GPPDR_LSB,
 977         [STMPE_IDX_GPAFR_U_MSB] = STMPE24XX_REG_GPAFR_U_MSB,
 978         [STMPE_IDX_IEGPIOR_LSB] = STMPE24XX_REG_IEGPIOR_LSB,
 979         [STMPE_IDX_IEGPIOR_CSB] = STMPE24XX_REG_IEGPIOR_CSB,
 980         [STMPE_IDX_IEGPIOR_MSB] = STMPE24XX_REG_IEGPIOR_MSB,
 981         [STMPE_IDX_ISGPIOR_MSB] = STMPE24XX_REG_ISGPIOR_MSB,
 982         [STMPE_IDX_GPEDR_LSB]   = STMPE24XX_REG_GPEDR_LSB,
 983         [STMPE_IDX_GPEDR_CSB]   = STMPE24XX_REG_GPEDR_CSB,
 984         [STMPE_IDX_GPEDR_MSB]   = STMPE24XX_REG_GPEDR_MSB,
 985 };
 986
 987 static struct stmpe_variant_block stmpe24xx_blocks[] = {
 988         {
 989                 .cell   = &stmpe_gpio_cell,
 990                 .irq    = STMPE24XX_IRQ_GPIOC,
 991                 .block  = STMPE_BLOCK_GPIO,
 992         },
 993         {
 994                 .cell   = &stmpe_keypad_cell,
 995                 .irq    = STMPE24XX_IRQ_KEYPAD,
 996                 .block  = STMPE_BLOCK_KEYPAD,
 997         },
 998         {
 999                 .cell   = &stmpe_pwm_cell,
1000                 .irq    = STMPE24XX_IRQ_PWM0,
1001                 .block  = STMPE_BLOCK_PWM,
1002         },
1003 };
1004
1005 static int stmpe24xx_enable(struct stmpe *stmpe, unsigned int blocks,
1006                             bool enable)
1007 {
1008         unsigned int mask = 0;
1009
1010         if (blocks & STMPE_BLOCK_GPIO)
1011                 mask |= STMPE24XX_SYS_CTRL_ENABLE_GPIO;
1012
1013         if (blocks & STMPE_BLOCK_KEYPAD)
1014                 mask |= STMPE24XX_SYS_CTRL_ENABLE_KPC;
1015
1016         return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL], mask,
1017                                 enable ? mask : 0);
1018 }
1019
1020 static int stmpe24xx_get_altfunc(struct stmpe *stmpe, enum stmpe_block block)
1021 {
1022         switch (block) {
1023         case STMPE_BLOCK_ROTATOR:
1024                 return 2;
1025
1026         case STMPE_BLOCK_KEYPAD:
1027         case STMPE_BLOCK_PWM:
1028                 return 1;
1029
1030         case STMPE_BLOCK_GPIO:
1031         default:
1032                 return 0;
1033         }
1034 }
1035
1036 static struct stmpe_variant_info stmpe2401 = {
1037         .name           = "stmpe2401",
1038         .id_val         = 0x0101,
1039         .id_mask        = 0xffff,
1040         .num_gpios      = 24,
1041         .af_bits        = 2,
1042         .regs           = stmpe24xx_regs,
1043         .blocks         = stmpe24xx_blocks,
1044         .num_blocks     = ARRAY_SIZE(stmpe24xx_blocks),
1045         .num_irqs       = STMPE24XX_NR_INTERNAL_IRQS,
1046         .enable         = stmpe24xx_enable,
1047         .get_altfunc    = stmpe24xx_get_altfunc,
1048 };
1049
1050 static struct stmpe_variant_info stmpe2403 = {
1051         .name           = "stmpe2403",
1052         .id_val         = 0x0120,
1053         .id_mask        = 0xffff,
1054         .num_gpios      = 24,
1055         .af_bits        = 2,
1056         .regs           = stmpe24xx_regs,
1057         .blocks         = stmpe24xx_blocks,
1058         .num_blocks     = ARRAY_SIZE(stmpe24xx_blocks),
1059         .num_irqs       = STMPE24XX_NR_INTERNAL_IRQS,
1060         .enable         = stmpe24xx_enable,
1061         .get_altfunc    = stmpe24xx_get_altfunc,
1062         .enable_autosleep       = stmpe1601_autosleep, /* same as stmpe1601 */
1063 };
1064
1065 static struct stmpe_variant_info *stmpe_variant_info[STMPE_NBR_PARTS] = {
1066         [STMPE610]      = &stmpe610,
1067         [STMPE801]      = &stmpe801,
1068         [STMPE811]      = &stmpe811,
1069         [STMPE1600]     = &stmpe1600,
1070         [STMPE1601]     = &stmpe1601,
1071         [STMPE1801]     = &stmpe1801,
1072         [STMPE2401]     = &stmpe2401,
1073         [STMPE2403]     = &stmpe2403,
1074 };
1075
1076 /*
1077  * These devices can be connected in a 'no-irq' configuration - the irq pin
1078  * is not used and the device cannot interrupt the CPU. Here we only list
1079  * devices which support this configuration - the driver will fail probing
1080  * for any devices not listed here which are configured in this way.
1081  */
1082 static struct stmpe_variant_info *stmpe_noirq_variant_info[STMPE_NBR_PARTS] = {
1083         [STMPE801]      = &stmpe801_noirq,
1084 };
1085
1086 static irqreturn_t stmpe_irq(int irq, void *data)
1087 {
1088         struct stmpe *stmpe = data;
1089         struct stmpe_variant_info *variant = stmpe->variant;
1090         int num = DIV_ROUND_UP(variant->num_irqs, 8);
1091         u8 israddr;
1092         u8 isr[3];
1093         int ret;
1094         int i;
1095
1096         if (variant->id_val == STMPE801_ID ||
1097             variant->id_val == STMPE1600_ID) {
1098                 int base = irq_find_mapping(stmpe->domain, 0);
1099
1100                 handle_nested_irq(base);
1101                 return IRQ_HANDLED;
1102         }
1103
1104         if (variant->id_val == STMPE1801_ID)
1105                 israddr = stmpe->regs[STMPE_IDX_ISR_LSB];
1106         else
1107                 israddr = stmpe->regs[STMPE_IDX_ISR_MSB];
1108
1109         ret = stmpe_block_read(stmpe, israddr, num, isr);
1110         if (ret < 0)
1111                 return IRQ_NONE;
1112
1113         for (i = 0; i < num; i++) {
1114                 int bank = num - i - 1;
1115                 u8 status = isr[i];
1116                 u8 clear;
1117
1118                 status &= stmpe->ier[bank];
1119                 if (!status)
1120                         continue;
1121
1122                 clear = status;
1123                 while (status) {
1124                         int bit = __ffs(status);
1125                         int line = bank * 8 + bit;
1126                         int nestedirq = irq_find_mapping(stmpe->domain, line);
1127
1128                         handle_nested_irq(nestedirq);
1129                         status &= ~(1 << bit);
1130                 }
1131
1132                 stmpe_reg_write(stmpe, israddr + i, clear);
1133         }
1134
1135         return IRQ_HANDLED;
1136 }
1137
1138 static void stmpe_irq_lock(struct irq_data *data)
1139 {
1140         struct stmpe *stmpe = irq_data_get_irq_chip_data(data);
1141
1142         mutex_lock(&stmpe->irq_lock);
1143 }
1144
1145 static void stmpe_irq_sync_unlock(struct irq_data *data)
1146 {
1147         struct stmpe *stmpe = irq_data_get_irq_chip_data(data);
1148         struct stmpe_variant_info *variant = stmpe->variant;
1149         int num = DIV_ROUND_UP(variant->num_irqs, 8);
1150         int i;
1151
1152         for (i = 0; i < num; i++) {
1153                 u8 new = stmpe->ier[i];
1154                 u8 old = stmpe->oldier[i];
1155
1156                 if (new == old)
1157                         continue;
1158
1159                 stmpe->oldier[i] = new;
1160                 stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_IER_LSB + i], new);
1161         }
1162
1163         mutex_unlock(&stmpe->irq_lock);
1164 }
1165
1166 static void stmpe_irq_mask(struct irq_data *data)
1167 {
1168         struct stmpe *stmpe = irq_data_get_irq_chip_data(data);
1169         int offset = data->hwirq;
1170         int regoffset = offset / 8;
1171         int mask = 1 << (offset % 8);
1172
1173         stmpe->ier[regoffset] &= ~mask;
1174 }
1175
1176 static void stmpe_irq_unmask(struct irq_data *data)
1177 {
1178         struct stmpe *stmpe = irq_data_get_irq_chip_data(data);
1179         int offset = data->hwirq;
1180         int regoffset = offset / 8;
1181         int mask = 1 << (offset % 8);
1182
1183         stmpe->ier[regoffset] |= mask;
1184 }
1185
1186 static struct irq_chip stmpe_irq_chip = {
1187         .name                   = "stmpe",
1188         .irq_bus_lock           = stmpe_irq_lock,
1189         .irq_bus_sync_unlock    = stmpe_irq_sync_unlock,
1190         .irq_mask               = stmpe_irq_mask,
1191         .irq_unmask             = stmpe_irq_unmask,
1192 };
1193
1194 static int stmpe_irq_map(struct irq_domain *d, unsigned int virq,
1195                                 irq_hw_number_t hwirq)
1196 {
1197         struct stmpe *stmpe = d->host_data;
1198         struct irq_chip *chip = NULL;
1199
1200         if (stmpe->variant->id_val != STMPE801_ID)
1201                 chip = &stmpe_irq_chip;
1202
1203         irq_set_chip_data(virq, stmpe);
1204         irq_set_chip_and_handler(virq, chip, handle_edge_irq);
1205         irq_set_nested_thread(virq, 1);
1206         irq_set_noprobe(virq);
1207
1208         return 0;
1209 }
1210
1211 static void stmpe_irq_unmap(struct irq_domain *d, unsigned int virq)
1212 {
1213                 irq_set_chip_and_handler(virq, NULL, NULL);
1214                 irq_set_chip_data(virq, NULL);
1215 }
1216
1217 static const struct irq_domain_ops stmpe_irq_ops = {
1218         .map    = stmpe_irq_map,
1219         .unmap  = stmpe_irq_unmap,
1220         .xlate  = irq_domain_xlate_twocell,
1221 };
1222
1223 static int stmpe_irq_init(struct stmpe *stmpe, struct device_node *np)
1224 {
1225         int base = 0;
1226         int num_irqs = stmpe->variant->num_irqs;
1227
1228         stmpe->domain = irq_domain_add_simple(np, num_irqs, base,
1229                                               &stmpe_irq_ops, stmpe);
1230         if (!stmpe->domain) {
1231                 dev_err(stmpe->dev, "Failed to create irqdomain\n");
1232                 return -ENOSYS;
1233         }
1234
1235         return 0;
1236 }
1237
1238 static int stmpe_chip_init(struct stmpe *stmpe)
1239 {
1240         unsigned int irq_trigger = stmpe->pdata->irq_trigger;
1241         int autosleep_timeout = stmpe->pdata->autosleep_timeout;
1242         struct stmpe_variant_info *variant = stmpe->variant;
1243         u8 icr = 0;
1244         unsigned int id;
1245         u8 data[2];
1246         int ret;
1247
1248         ret = stmpe_block_read(stmpe, stmpe->regs[STMPE_IDX_CHIP_ID],
1249                                ARRAY_SIZE(data), data);
1250         if (ret < 0)
1251                 return ret;
1252
1253         id = (data[0] << 8) | data[1];
1254         if ((id & variant->id_mask) != variant->id_val) {
1255                 dev_err(stmpe->dev, "unknown chip id: %#x\n", id);
1256                 return -EINVAL;
1257         }
1258
1259         dev_info(stmpe->dev, "%s detected, chip id: %#x\n", variant->name, id);
1260
1261         /* Disable all modules -- subdrivers should enable what they need. */
1262         ret = stmpe_disable(stmpe, ~0);
1263         if (ret)
1264                 return ret;
1265
1266         ret =  stmpe_reset(stmpe);
1267         if (ret < 0)
1268                 return ret;
1269
1270         if (stmpe->irq >= 0) {
1271                 if (id == STMPE801_ID || id == STMPE1600_ID)
1272                         icr = STMPE_SYS_CTRL_INT_EN;
1273                 else
1274                         icr = STMPE_ICR_LSB_GIM;
1275
1276                 /* STMPE801 and STMPE1600 don't support Edge interrupts */
1277                 if (id != STMPE801_ID && id != STMPE1600_ID) {
1278                         if (irq_trigger == IRQF_TRIGGER_FALLING ||
1279                                         irq_trigger == IRQF_TRIGGER_RISING)
1280                                 icr |= STMPE_ICR_LSB_EDGE;
1281                 }
1282
1283                 if (irq_trigger == IRQF_TRIGGER_RISING ||
1284                                 irq_trigger == IRQF_TRIGGER_HIGH) {
1285                         if (id == STMPE801_ID || id == STMPE1600_ID)
1286                                 icr |= STMPE_SYS_CTRL_INT_HI;
1287                         else
1288                                 icr |= STMPE_ICR_LSB_HIGH;
1289                 }
1290         }
1291
1292         if (stmpe->pdata->autosleep) {
1293                 ret = stmpe_autosleep(stmpe, autosleep_timeout);
1294                 if (ret)
1295                         return ret;
1296         }
1297
1298         return stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_ICR_LSB], icr);
1299 }
1300
1301 static int stmpe_add_device(struct stmpe *stmpe, const struct mfd_cell *cell)
1302 {
1303         return mfd_add_devices(stmpe->dev, stmpe->pdata->id, cell, 1,
1304                                NULL, 0, stmpe->domain);
1305 }
1306
1307 static int stmpe_devices_init(struct stmpe *stmpe)
1308 {
1309         struct stmpe_variant_info *variant = stmpe->variant;
1310         unsigned int platform_blocks = stmpe->pdata->blocks;
1311         int ret = -EINVAL;
1312         int i, j;
1313
1314         for (i = 0; i < variant->num_blocks; i++) {
1315                 struct stmpe_variant_block *block = &variant->blocks[i];
1316
1317                 if (!(platform_blocks & block->block))
1318                         continue;
1319
1320                 for (j = 0; j < block->cell->num_resources; j++) {
1321                         struct resource *res =
1322                                 (struct resource *) &block->cell->resources[j];
1323
1324                         /* Dynamically fill in a variant's IRQ. */
1325                         if (res->flags & IORESOURCE_IRQ)
1326                                 res->start = res->end = block->irq + j;
1327                 }
1328
1329                 platform_blocks &= ~block->block;
1330                 ret = stmpe_add_device(stmpe, block->cell);
1331                 if (ret)
1332                         return ret;
1333         }
1334
1335         if (platform_blocks)
1336                 dev_warn(stmpe->dev,
1337                          "platform wants blocks (%#x) not present on variant",
1338                          platform_blocks);
1339
1340         return ret;
1341 }
1342
1343 static void stmpe_of_probe(struct stmpe_platform_data *pdata,
1344                            struct device_node *np)
1345 {
1346         struct device_node *child;
1347
1348         pdata->id = of_alias_get_id(np, "stmpe-i2c");
1349         if (pdata->id < 0)
1350                 pdata->id = -1;
1351
1352         pdata->irq_gpio = of_get_named_gpio_flags(np, "irq-gpio", 0,
1353                                 &pdata->irq_trigger);
1354         if (gpio_is_valid(pdata->irq_gpio))
1355                 pdata->irq_over_gpio = 1;
1356         else
1357                 pdata->irq_trigger = IRQF_TRIGGER_NONE;
1358
1359         of_property_read_u32(np, "st,autosleep-timeout",
1360                         &pdata->autosleep_timeout);
1361
1362         pdata->autosleep = (pdata->autosleep_timeout) ? true : false;
1363
1364         for_each_available_child_of_node(np, child) {
1365                 if (of_node_name_eq(child, "stmpe_gpio")) {
1366                         pdata->blocks |= STMPE_BLOCK_GPIO;
1367                 } else if (of_node_name_eq(child, "stmpe_keypad")) {
1368                         pdata->blocks |= STMPE_BLOCK_KEYPAD;
1369                 } else if (of_node_name_eq(child, "stmpe_touchscreen")) {
1370                         pdata->blocks |= STMPE_BLOCK_TOUCHSCREEN;
1371                 } else if (of_node_name_eq(child, "stmpe_adc")) {
1372                         pdata->blocks |= STMPE_BLOCK_ADC;
1373                 } else if (of_node_name_eq(child, "stmpe_pwm")) {
1374                         pdata->blocks |= STMPE_BLOCK_PWM;
1375                 } else if (of_node_name_eq(child, "stmpe_rotator")) {
1376                         pdata->blocks |= STMPE_BLOCK_ROTATOR;
1377                 }
1378         }
1379 }
1380
1381 /* Called from client specific probe routines */
1382 int stmpe_probe(struct stmpe_client_info *ci, enum stmpe_partnum partnum)
1383 {
1384         struct stmpe_platform_data *pdata;
1385         struct device_node *np = ci->dev->of_node;
1386         struct stmpe *stmpe;
1387         int ret;
1388         u32 val;
1389
1390         pdata = devm_kzalloc(ci->dev, sizeof(*pdata), GFP_KERNEL);
1391         if (!pdata)
1392                 return -ENOMEM;
1393
1394         stmpe_of_probe(pdata, np);
1395
1396         if (of_find_property(np, "interrupts", NULL) == NULL)
1397                 ci->irq = -1;
1398
1399         stmpe = devm_kzalloc(ci->dev, sizeof(struct stmpe), GFP_KERNEL);
1400         if (!stmpe)
1401                 return -ENOMEM;
1402
1403         mutex_init(&stmpe->irq_lock);
1404         mutex_init(&stmpe->lock);
1405
1406         if (!of_property_read_u32(np, "st,sample-time", &val))
1407                 stmpe->sample_time = val;
1408         if (!of_property_read_u32(np, "st,mod-12b", &val))
1409                 stmpe->mod_12b = val;
1410         if (!of_property_read_u32(np, "st,ref-sel", &val))
1411                 stmpe->ref_sel = val;
1412         if (!of_property_read_u32(np, "st,adc-freq", &val))
1413                 stmpe->adc_freq = val;
1414
1415         stmpe->dev = ci->dev;
1416         stmpe->client = ci->client;
1417         stmpe->pdata = pdata;
1418         stmpe->ci = ci;
1419         stmpe->partnum = partnum;
1420         stmpe->variant = stmpe_variant_info[partnum];
1421         stmpe->regs = stmpe->variant->regs;
1422         stmpe->num_gpios = stmpe->variant->num_gpios;
1423         stmpe->vcc = devm_regulator_get_optional(ci->dev, "vcc");
1424         if (!IS_ERR(stmpe->vcc)) {
1425                 ret = regulator_enable(stmpe->vcc);
1426                 if (ret)
1427                         dev_warn(ci->dev, "failed to enable VCC supply\n");
1428         }
1429         stmpe->vio = devm_regulator_get_optional(ci->dev, "vio");
1430         if (!IS_ERR(stmpe->vio)) {
1431                 ret = regulator_enable(stmpe->vio);
1432                 if (ret)
1433                         dev_warn(ci->dev, "failed to enable VIO supply\n");
1434         }
1435         dev_set_drvdata(stmpe->dev, stmpe);
1436
1437         if (ci->init)
1438                 ci->init(stmpe);
1439
1440         if (pdata->irq_over_gpio) {
1441                 ret = devm_gpio_request_one(ci->dev, pdata->irq_gpio,
1442                                 GPIOF_DIR_IN, "stmpe");
1443                 if (ret) {
1444                         dev_err(stmpe->dev, "failed to request IRQ GPIO: %d\n",
1445                                         ret);
1446                         return ret;
1447                 }
1448
1449                 stmpe->irq = gpio_to_irq(pdata->irq_gpio);
1450         } else {
1451                 stmpe->irq = ci->irq;
1452         }
1453
1454         if (stmpe->irq < 0) {
1455                 /* use alternate variant info for no-irq mode, if supported */
1456                 dev_info(stmpe->dev,
1457                         "%s configured in no-irq mode by platform data\n",
1458                         stmpe->variant->name);
1459                 if (!stmpe_noirq_variant_info[stmpe->partnum]) {
1460                         dev_err(stmpe->dev,
1461                                 "%s does not support no-irq mode!\n",
1462                                 stmpe->variant->name);
1463                         return -ENODEV;
1464                 }
1465                 stmpe->variant = stmpe_noirq_variant_info[stmpe->partnum];
1466         } else if (pdata->irq_trigger == IRQF_TRIGGER_NONE) {
1467                 pdata->irq_trigger = irq_get_trigger_type(stmpe->irq);
1468         }
1469
1470         ret = stmpe_chip_init(stmpe);
1471         if (ret)
1472                 return ret;
1473
1474         if (stmpe->irq >= 0) {
1475                 ret = stmpe_irq_init(stmpe, np);
1476                 if (ret)
1477                         return ret;
1478
1479                 ret = devm_request_threaded_irq(ci->dev, stmpe->irq, NULL,
1480                                 stmpe_irq, pdata->irq_trigger | IRQF_ONESHOT,
1481                                 "stmpe", stmpe);
1482                 if (ret) {
1483                         dev_err(stmpe->dev, "failed to request IRQ: %d\n",
1484                                         ret);
1485                         return ret;
1486                 }
1487         }
1488
1489         ret = stmpe_devices_init(stmpe);
1490         if (!ret)
1491                 return 0;
1492
1493         dev_err(stmpe->dev, "failed to add children\n");
1494         mfd_remove_devices(stmpe->dev);
1495
1496         return ret;
1497 }
1498
1499 void stmpe_remove(struct stmpe *stmpe)
1500 {
1501         if (!IS_ERR(stmpe->vio))
1502                 regulator_disable(stmpe->vio);
1503         if (!IS_ERR(stmpe->vcc))
1504                 regulator_disable(stmpe->vcc);
1505
1506         __stmpe_disable(stmpe, STMPE_BLOCK_ADC);
1507
1508         mfd_remove_devices(stmpe->dev);
1509 }
1510
1511 #ifdef CONFIG_PM
1512 static int stmpe_suspend(struct device *dev)
1513 {
1514         struct stmpe *stmpe = dev_get_drvdata(dev);
1515
1516         if (stmpe->irq >= 0 && device_may_wakeup(dev))
1517                 enable_irq_wake(stmpe->irq);
1518
1519         return 0;
1520 }
1521
1522 static int stmpe_resume(struct device *dev)
1523 {
1524         struct stmpe *stmpe = dev_get_drvdata(dev);
1525
1526         if (stmpe->irq >= 0 && device_may_wakeup(dev))
1527                 disable_irq_wake(stmpe->irq);
1528
1529         return 0;
1530 }
1531
1532 const struct dev_pm_ops stmpe_dev_pm_ops = {
1533         .suspend        = stmpe_suspend,
1534         .resume         = stmpe_resume,
1535 };
1536 #endif