drivers/mfd/sm501.c

   1 /* linux/drivers/mfd/sm501.c
   2  *
   3  * Copyright (C) 2006 Simtec Electronics
   4  *      Ben Dooks <ben@simtec.co.uk>
   5  *      Vincent Sanders <vince@simtec.co.uk>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * SM501 MFD driver
  12 */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/delay.h>
  17 #include <linux/init.h>
  18 #include <linux/list.h>
  19 #include <linux/device.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pci.h>
  22 #include <linux/i2c-gpio.h>
  23 #include <linux/slab.h>
  24
  25 #include <linux/sm501.h>
  26 #include <linux/sm501-regs.h>
  27 #include <linux/serial_8250.h>
  28
  29 #include <linux/io.h>
  30
  31 struct sm501_device {
  32         struct list_head                list;
  33         struct platform_device          pdev;
  34 };
  35
  36 struct sm501_gpio;
  37
  38 #ifdef CONFIG_MFD_SM501_GPIO
  39 #include <linux/gpio.h>
  40
  41 struct sm501_gpio_chip {
  42         struct gpio_chip        gpio;
  43         struct sm501_gpio       *ourgpio;       /* to get back to parent. */
  44         void __iomem            *regbase;
  45         void __iomem            *control;       /* address of control reg. */
  46 };
  47
  48 struct sm501_gpio {
  49         struct sm501_gpio_chip  low;
  50         struct sm501_gpio_chip  high;
  51         spinlock_t              lock;
  52
  53         unsigned int             registered : 1;
  54         void __iomem            *regs;
  55         struct resource         *regs_res;
  56 };
  57 #else
  58 struct sm501_gpio {
  59         /* no gpio support, empty definition for sm501_devdata. */
  60 };
  61 #endif
  62
  63 struct sm501_devdata {
  64         spinlock_t                       reg_lock;
  65         struct mutex                     clock_lock;
  66         struct list_head                 devices;
  67         struct sm501_gpio                gpio;
  68
  69         struct device                   *dev;
  70         struct resource                 *io_res;
  71         struct resource                 *mem_res;
  72         struct resource                 *regs_claim;
  73         struct sm501_platdata           *platdata;
  74
  75
  76         unsigned int                     in_suspend;
  77         unsigned long                    pm_misc;
  78
  79         int                              unit_power[20];
  80         unsigned int                     pdev_id;
  81         unsigned int                     irq;
  82         void __iomem                    *regs;
  83         unsigned int                     rev;
  84 };
  85
  86
  87 #define MHZ (1000 * 1000)
  88
  89 #ifdef DEBUG
  90 static const unsigned int div_tab[] = {
  91         [0]             = 1,
  92         [1]             = 2,
  93         [2]             = 4,
  94         [3]             = 8,
  95         [4]             = 16,
  96         [5]             = 32,
  97         [6]             = 64,
  98         [7]             = 128,
  99         [8]             = 3,
 100         [9]             = 6,
 101         [10]            = 12,
 102         [11]            = 24,
 103         [12]            = 48,
 104         [13]            = 96,
 105         [14]            = 192,
 106         [15]            = 384,
 107         [16]            = 5,
 108         [17]            = 10,
 109         [18]            = 20,
 110         [19]            = 40,
 111         [20]            = 80,
 112         [21]            = 160,
 113         [22]            = 320,
 114         [23]            = 604,
 115 };
 116
 117 static unsigned long decode_div(unsigned long pll2, unsigned long val,
 118                                 unsigned int lshft, unsigned int selbit,
 119                                 unsigned long mask)
 120 {
 121         if (val & selbit)
 122                 pll2 = 288 * MHZ;
 123
 124         return pll2 / div_tab[(val >> lshft) & mask];
 125 }
 126
 127 #define fmt_freq(x) ((x) / MHZ), ((x) % MHZ), (x)
 128
 129 /* sm501_dump_clk
 130  *
 131  * Print out the current clock configuration for the device
 132 */
 133
 134 static void sm501_dump_clk(struct sm501_devdata *sm)
 135 {
 136         unsigned long misct = smc501_readl(sm->regs + SM501_MISC_TIMING);
 137         unsigned long pm0 = smc501_readl(sm->regs + SM501_POWER_MODE_0_CLOCK);
 138         unsigned long pm1 = smc501_readl(sm->regs + SM501_POWER_MODE_1_CLOCK);
 139         unsigned long pmc = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL);
 140         unsigned long sdclk0, sdclk1;
 141         unsigned long pll2 = 0;
 142
 143         switch (misct & 0x30) {
 144         case 0x00:
 145                 pll2 = 336 * MHZ;
 146                 break;
 147         case 0x10:
 148                 pll2 = 288 * MHZ;
 149                 break;
 150         case 0x20:
 151                 pll2 = 240 * MHZ;
 152                 break;
 153         case 0x30:
 154                 pll2 = 192 * MHZ;
 155                 break;
 156         }
 157
 158         sdclk0 = (misct & (1<<12)) ? pll2 : 288 * MHZ;
 159         sdclk0 /= div_tab[((misct >> 8) & 0xf)];
 160
 161         sdclk1 = (misct & (1<<20)) ? pll2 : 288 * MHZ;
 162         sdclk1 /= div_tab[((misct >> 16) & 0xf)];
 163
 164         dev_dbg(sm->dev, "MISCT=%08lx, PM0=%08lx, PM1=%08lx\n",
 165                 misct, pm0, pm1);
 166
 167         dev_dbg(sm->dev, "PLL2 = %ld.%ld MHz (%ld), SDCLK0=%08lx, SDCLK1=%08lx\n",
 168                 fmt_freq(pll2), sdclk0, sdclk1);
 169
 170         dev_dbg(sm->dev, "SDRAM: PM0=%ld, PM1=%ld\n", sdclk0, sdclk1);
 171
 172         dev_dbg(sm->dev, "PM0[%c]: "
 173                  "P2 %ld.%ld MHz (%ld), V2 %ld.%ld (%ld), "
 174                  "M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n",
 175                  (pmc & 3 ) == 0 ? '*' : '-',
 176                  fmt_freq(decode_div(pll2, pm0, 24, 1<<29, 31)),
 177                  fmt_freq(decode_div(pll2, pm0, 16, 1<<20, 15)),
 178                  fmt_freq(decode_div(pll2, pm0, 8,  1<<12, 15)),
 179                  fmt_freq(decode_div(pll2, pm0, 0,  1<<4,  15)));
 180
 181         dev_dbg(sm->dev, "PM1[%c]: "
 182                 "P2 %ld.%ld MHz (%ld), V2 %ld.%ld (%ld), "
 183                 "M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n",
 184                 (pmc & 3 ) == 1 ? '*' : '-',
 185                 fmt_freq(decode_div(pll2, pm1, 24, 1<<29, 31)),
 186                 fmt_freq(decode_div(pll2, pm1, 16, 1<<20, 15)),
 187                 fmt_freq(decode_div(pll2, pm1, 8,  1<<12, 15)),
 188                 fmt_freq(decode_div(pll2, pm1, 0,  1<<4,  15)));
 189 }
 190
 191 static void sm501_dump_regs(struct sm501_devdata *sm)
 192 {
 193         void __iomem *regs = sm->regs;
 194
 195         dev_info(sm->dev, "System Control   %08x\n",
 196                         smc501_readl(regs + SM501_SYSTEM_CONTROL));
 197         dev_info(sm->dev, "Misc Control     %08x\n",
 198                         smc501_readl(regs + SM501_MISC_CONTROL));
 199         dev_info(sm->dev, "GPIO Control Low %08x\n",
 200                         smc501_readl(regs + SM501_GPIO31_0_CONTROL));
 201         dev_info(sm->dev, "GPIO Control Hi  %08x\n",
 202                         smc501_readl(regs + SM501_GPIO63_32_CONTROL));
 203         dev_info(sm->dev, "DRAM Control     %08x\n",
 204                         smc501_readl(regs + SM501_DRAM_CONTROL));
 205         dev_info(sm->dev, "Arbitration Ctrl %08x\n",
 206                         smc501_readl(regs + SM501_ARBTRTN_CONTROL));
 207         dev_info(sm->dev, "Misc Timing      %08x\n",
 208                         smc501_readl(regs + SM501_MISC_TIMING));
 209 }
 210
 211 static void sm501_dump_gate(struct sm501_devdata *sm)
 212 {
 213         dev_info(sm->dev, "CurrentGate      %08x\n",
 214                         smc501_readl(sm->regs + SM501_CURRENT_GATE));
 215         dev_info(sm->dev, "CurrentClock     %08x\n",
 216                         smc501_readl(sm->regs + SM501_CURRENT_CLOCK));
 217         dev_info(sm->dev, "PowerModeControl %08x\n",
 218                         smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL));
 219 }
 220
 221 #else
 222 static inline void sm501_dump_gate(struct sm501_devdata *sm) { }
 223 static inline void sm501_dump_regs(struct sm501_devdata *sm) { }
 224 static inline void sm501_dump_clk(struct sm501_devdata *sm) { }
 225 #endif
 226
 227 /* sm501_sync_regs
 228  *
 229  * ensure the
 230 */
 231
 232 static void sm501_sync_regs(struct sm501_devdata *sm)
 233 {
 234         smc501_readl(sm->regs);
 235 }
 236
 237 static inline void sm501_mdelay(struct sm501_devdata *sm, unsigned int delay)
 238 {
 239         /* during suspend/resume, we are currently not allowed to sleep,
 240          * so change to using mdelay() instead of msleep() if we
 241          * are in one of these paths */
 242
 243         if (sm->in_suspend)
 244                 mdelay(delay);
 245         else
 246                 msleep(delay);
 247 }
 248
 249 /* sm501_misc_control
 250  *
 251  * alters the miscellaneous control parameters
 252 */
 253
 254 int sm501_misc_control(struct device *dev,
 255                        unsigned long set, unsigned long clear)
 256 {
 257         struct sm501_devdata *sm = dev_get_drvdata(dev);
 258         unsigned long misc;
 259         unsigned long save;
 260         unsigned long to;
 261
 262         spin_lock_irqsave(&sm->reg_lock, save);
 263
 264         misc = smc501_readl(sm->regs + SM501_MISC_CONTROL);
 265         to = (misc & ~clear) | set;
 266
 267         if (to != misc) {
 268                 smc501_writel(to, sm->regs + SM501_MISC_CONTROL);
 269                 sm501_sync_regs(sm);
 270
 271                 dev_dbg(sm->dev, "MISC_CONTROL %08lx\n", misc);
 272         }
 273
 274         spin_unlock_irqrestore(&sm->reg_lock, save);
 275         return to;
 276 }
 277
 278 EXPORT_SYMBOL_GPL(sm501_misc_control);
 279
 280 /* sm501_modify_reg
 281  *
 282  * Modify a register in the SM501 which may be shared with other
 283  * drivers.
 284 */
 285
 286 unsigned long sm501_modify_reg(struct device *dev,
 287                                unsigned long reg,
 288                                unsigned long set,
 289                                unsigned long clear)
 290 {
 291         struct sm501_devdata *sm = dev_get_drvdata(dev);
 292         unsigned long data;
 293         unsigned long save;
 294
 295         spin_lock_irqsave(&sm->reg_lock, save);
 296
 297         data = smc501_readl(sm->regs + reg);
 298         data |= set;
 299         data &= ~clear;
 300
 301         smc501_writel(data, sm->regs + reg);
 302         sm501_sync_regs(sm);
 303
 304         spin_unlock_irqrestore(&sm->reg_lock, save);
 305
 306         return data;
 307 }
 308
 309 EXPORT_SYMBOL_GPL(sm501_modify_reg);
 310
 311 /* sm501_unit_power
 312  *
 313  * alters the power active gate to set specific units on or off
 314  */
 315
 316 int sm501_unit_power(struct device *dev, unsigned int unit, unsigned int to)
 317 {
 318         struct sm501_devdata *sm = dev_get_drvdata(dev);
 319         unsigned long mode;
 320         unsigned long gate;
 321         unsigned long clock;
 322
 323         mutex_lock(&sm->clock_lock);
 324
 325         mode = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL);
 326         gate = smc501_readl(sm->regs + SM501_CURRENT_GATE);
 327         clock = smc501_readl(sm->regs + SM501_CURRENT_CLOCK);
 328
 329         mode &= 3;              /* get current power mode */
 330
 331         if (unit >= ARRAY_SIZE(sm->unit_power)) {
 332                 dev_err(dev, "%s: bad unit %d\n", __func__, unit);
 333                 goto already;
 334         }
 335
 336         dev_dbg(sm->dev, "%s: unit %d, cur %d, to %d\n", __func__, unit,
 337                 sm->unit_power[unit], to);
 338
 339         if (to == 0 && sm->unit_power[unit] == 0) {
 340                 dev_err(sm->dev, "unit %d is already shutdown\n", unit);
 341                 goto already;
 342         }
 343
 344         sm->unit_power[unit] += to ? 1 : -1;
 345         to = sm->unit_power[unit] ? 1 : 0;
 346
 347         if (to) {
 348                 if (gate & (1 << unit))
 349                         goto already;
 350                 gate |= (1 << unit);
 351         } else {
 352                 if (!(gate & (1 << unit)))
 353                         goto already;
 354                 gate &= ~(1 << unit);
 355         }
 356
 357         switch (mode) {
 358         case 1:
 359                 smc501_writel(gate, sm->regs + SM501_POWER_MODE_0_GATE);
 360                 smc501_writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK);
 361                 mode = 0;
 362                 break;
 363         case 2:
 364         case 0:
 365                 smc501_writel(gate, sm->regs + SM501_POWER_MODE_1_GATE);
 366                 smc501_writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK);
 367                 mode = 1;
 368                 break;
 369
 370         default:
 371                 gate = -1;
 372                 goto already;
 373         }
 374
 375         smc501_writel(mode, sm->regs + SM501_POWER_MODE_CONTROL);
 376         sm501_sync_regs(sm);
 377
 378         dev_dbg(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n",
 379                 gate, clock, mode);
 380
 381         sm501_mdelay(sm, 16);
 382
 383  already:
 384         mutex_unlock(&sm->clock_lock);
 385         return gate;
 386 }
 387
 388 EXPORT_SYMBOL_GPL(sm501_unit_power);
 389
 390 /* clock value structure. */
 391 struct sm501_clock {
 392         unsigned long mclk;
 393         int divider;
 394         int shift;
 395         unsigned int m, n, k;
 396 };
 397
 398 /* sm501_calc_clock
 399  *
 400  * Calculates the nearest discrete clock frequency that
 401  * can be achieved with the specified input clock.
 402  *   the maximum divisor is 3 or 5
 403  */
 404
 405 static int sm501_calc_clock(unsigned long freq,
 406                             struct sm501_clock *clock,
 407                             int max_div,
 408                             unsigned long mclk,
 409                             long *best_diff)
 410 {
 411         int ret = 0;
 412         int divider;
 413         int shift;
 414         long diff;
 415
 416         /* try dividers 1 and 3 for CRT and for panel,
 417            try divider 5 for panel only.*/
 418
 419         for (divider = 1; divider <= max_div; divider += 2) {
 420                 /* try all 8 shift values.*/
 421                 for (shift = 0; shift < 8; shift++) {
 422                         /* Calculate difference to requested clock */
 423                         diff = DIV_ROUND_CLOSEST(mclk, divider << shift) - freq;
 424                         if (diff < 0)
 425                                 diff = -diff;
 426
 427                         /* If it is less than the current, use it */
 428                         if (diff < *best_diff) {
 429                                 *best_diff = diff;
 430
 431                                 clock->mclk = mclk;
 432                                 clock->divider = divider;
 433                                 clock->shift = shift;
 434                                 ret = 1;
 435                         }
 436                 }
 437         }
 438
 439         return ret;
 440 }
 441
 442 /* sm501_calc_pll
 443  *
 444  * Calculates the nearest discrete clock frequency that can be
 445  * achieved using the programmable PLL.
 446  *   the maximum divisor is 3 or 5
 447  */
 448
 449 static unsigned long sm501_calc_pll(unsigned long freq,
 450                                         struct sm501_clock *clock,
 451                                         int max_div)
 452 {
 453         unsigned long mclk;
 454         unsigned int m, n, k;
 455         long best_diff = 999999999;
 456
 457         /*
 458          * The SM502 datasheet doesn't specify the min/max values for M and N.
 459          * N = 1 at least doesn't work in practice.
 460          */
 461         for (m = 2; m <= 255; m++) {
 462                 for (n = 2; n <= 127; n++) {
 463                         for (k = 0; k <= 1; k++) {
 464                                 mclk = (24000000UL * m / n) >> k;
 465
 466                                 if (sm501_calc_clock(freq, clock, max_div,
 467                                                      mclk, &best_diff)) {
 468                                         clock->m = m;
 469                                         clock->n = n;
 470                                         clock->k = k;
 471                                 }
 472                         }
 473                 }
 474         }
 475
 476         /* Return best clock. */
 477         return clock->mclk / (clock->divider << clock->shift);
 478 }
 479
 480 /* sm501_select_clock
 481  *
 482  * Calculates the nearest discrete clock frequency that can be
 483  * achieved using the 288MHz and 336MHz PLLs.
 484  *   the maximum divisor is 3 or 5
 485  */
 486
 487 static unsigned long sm501_select_clock(unsigned long freq,
 488                                         struct sm501_clock *clock,
 489                                         int max_div)
 490 {
 491         unsigned long mclk;
 492         long best_diff = 999999999;
 493
 494         /* Try 288MHz and 336MHz clocks. */
 495         for (mclk = 288000000; mclk <= 336000000; mclk += 48000000) {
 496                 sm501_calc_clock(freq, clock, max_div, mclk, &best_diff);
 497         }
 498
 499         /* Return best clock. */
 500         return clock->mclk / (clock->divider << clock->shift);
 501 }
 502
 503 /* sm501_set_clock
 504  *
 505  * set one of the four clock sources to the closest available frequency to
 506  *  the one specified
 507 */
 508
 509 unsigned long sm501_set_clock(struct device *dev,
 510                               int clksrc,
 511                               unsigned long req_freq)
 512 {
 513         struct sm501_devdata *sm = dev_get_drvdata(dev);
 514         unsigned long mode = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL);
 515         unsigned long gate = smc501_readl(sm->regs + SM501_CURRENT_GATE);
 516         unsigned long clock = smc501_readl(sm->regs + SM501_CURRENT_CLOCK);
 517         unsigned int pll_reg = 0;
 518         unsigned long sm501_freq; /* the actual frequency achieved */
 519         u64 reg;
 520
 521         struct sm501_clock to;
 522
 523         /* find achivable discrete frequency and setup register value
 524          * accordingly, V2XCLK, MCLK and M1XCLK are the same P2XCLK
 525          * has an extra bit for the divider */
 526
 527         switch (clksrc) {
 528         case SM501_CLOCK_P2XCLK:
 529                 /* This clock is divided in half so to achieve the
 530                  * requested frequency the value must be multiplied by
 531                  * 2. This clock also has an additional pre divisor */
 532
 533                 if (sm->rev >= 0xC0) {
 534                         /* SM502 -> use the programmable PLL */
 535                         sm501_freq = (sm501_calc_pll(2 * req_freq,
 536                                                      &to, 5) / 2);
 537                         reg = to.shift & 0x07;/* bottom 3 bits are shift */
 538                         if (to.divider == 3)
 539                                 reg |= 0x08; /* /3 divider required */
 540                         else if (to.divider == 5)
 541                                 reg |= 0x10; /* /5 divider required */
 542                         reg |= 0x40; /* select the programmable PLL */
 543                         pll_reg = 0x20000 | (to.k << 15) | (to.n << 8) | to.m;
 544                 } else {
 545                         sm501_freq = (sm501_select_clock(2 * req_freq,
 546                                                          &to, 5) / 2);
 547                         reg = to.shift & 0x07;/* bottom 3 bits are shift */
 548                         if (to.divider == 3)
 549                                 reg |= 0x08; /* /3 divider required */
 550                         else if (to.divider == 5)
 551                                 reg |= 0x10; /* /5 divider required */
 552                         if (to.mclk != 288000000)
 553                                 reg |= 0x20; /* which mclk pll is source */
 554                 }
 555                 break;
 556
 557         case SM501_CLOCK_V2XCLK:
 558                 /* This clock is divided in half so to achieve the
 559                  * requested frequency the value must be multiplied by 2. */
 560
 561                 sm501_freq = (sm501_select_clock(2 * req_freq, &to, 3) / 2);
 562                 reg=to.shift & 0x07;    /* bottom 3 bits are shift */
 563                 if (to.divider == 3)
 564                         reg |= 0x08;    /* /3 divider required */
 565                 if (to.mclk != 288000000)
 566                         reg |= 0x10;    /* which mclk pll is source */
 567                 break;
 568
 569         case SM501_CLOCK_MCLK:
 570         case SM501_CLOCK_M1XCLK:
 571                 /* These clocks are the same and not further divided */
 572
 573                 sm501_freq = sm501_select_clock( req_freq, &to, 3);
 574                 reg=to.shift & 0x07;    /* bottom 3 bits are shift */
 575                 if (to.divider == 3)
 576                         reg |= 0x08;    /* /3 divider required */
 577                 if (to.mclk != 288000000)
 578                         reg |= 0x10;    /* which mclk pll is source */
 579                 break;
 580
 581         default:
 582                 return 0; /* this is bad */
 583         }
 584
 585         mutex_lock(&sm->clock_lock);
 586
 587         mode = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL);
 588         gate = smc501_readl(sm->regs + SM501_CURRENT_GATE);
 589         clock = smc501_readl(sm->regs + SM501_CURRENT_CLOCK);
 590
 591         clock = clock & ~(0xFF << clksrc);
 592         clock |= reg<<clksrc;
 593
 594         mode &= 3;      /* find current mode */
 595
 596         switch (mode) {
 597         case 1:
 598                 smc501_writel(gate, sm->regs + SM501_POWER_MODE_0_GATE);
 599                 smc501_writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK);
 600                 mode = 0;
 601                 break;
 602         case 2:
 603         case 0:
 604                 smc501_writel(gate, sm->regs + SM501_POWER_MODE_1_GATE);
 605                 smc501_writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK);
 606                 mode = 1;
 607                 break;
 608
 609         default:
 610                 mutex_unlock(&sm->clock_lock);
 611                 return -1;
 612         }
 613
 614         smc501_writel(mode, sm->regs + SM501_POWER_MODE_CONTROL);
 615
 616         if (pll_reg)
 617                 smc501_writel(pll_reg,
 618                                 sm->regs + SM501_PROGRAMMABLE_PLL_CONTROL);
 619
 620         sm501_sync_regs(sm);
 621
 622         dev_dbg(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n",
 623                 gate, clock, mode);
 624
 625         sm501_mdelay(sm, 16);
 626         mutex_unlock(&sm->clock_lock);
 627
 628         sm501_dump_clk(sm);
 629
 630         return sm501_freq;
 631 }
 632
 633 EXPORT_SYMBOL_GPL(sm501_set_clock);
 634
 635 /* sm501_find_clock
 636  *
 637  * finds the closest available frequency for a given clock
 638 */
 639
 640 unsigned long sm501_find_clock(struct device *dev,
 641                                int clksrc,
 642                                unsigned long req_freq)
 643 {
 644         struct sm501_devdata *sm = dev_get_drvdata(dev);
 645         unsigned long sm501_freq; /* the frequency achieveable by the 501 */
 646         struct sm501_clock to;
 647
 648         switch (clksrc) {
 649         case SM501_CLOCK_P2XCLK:
 650                 if (sm->rev >= 0xC0) {
 651                         /* SM502 -> use the programmable PLL */
 652                         sm501_freq = (sm501_calc_pll(2 * req_freq,
 653                                                      &to, 5) / 2);
 654                 } else {
 655                         sm501_freq = (sm501_select_clock(2 * req_freq,
 656                                                          &to, 5) / 2);
 657                 }
 658                 break;
 659
 660         case SM501_CLOCK_V2XCLK:
 661                 sm501_freq = (sm501_select_clock(2 * req_freq, &to, 3) / 2);
 662                 break;
 663
 664         case SM501_CLOCK_MCLK:
 665         case SM501_CLOCK_M1XCLK:
 666                 sm501_freq = sm501_select_clock(req_freq, &to, 3);
 667                 break;
 668
 669         default:
 670                 sm501_freq = 0;         /* error */
 671         }
 672
 673         return sm501_freq;
 674 }
 675
 676 EXPORT_SYMBOL_GPL(sm501_find_clock);
 677
 678 static struct sm501_device *to_sm_device(struct platform_device *pdev)
 679 {
 680         return container_of(pdev, struct sm501_device, pdev);
 681 }
 682
 683 /* sm501_device_release
 684  *
 685  * A release function for the platform devices we create to allow us to
 686  * free any items we allocated
 687 */
 688
 689 static void sm501_device_release(struct device *dev)
 690 {
 691         kfree(to_sm_device(to_platform_device(dev)));
 692 }
 693
 694 /* sm501_create_subdev
 695  *
 696  * Create a skeleton platform device with resources for passing to a
 697  * sub-driver
 698 */
 699
 700 static struct platform_device *
 701 sm501_create_subdev(struct sm501_devdata *sm, char *name,
 702                     unsigned int res_count, unsigned int platform_data_size)
 703 {
 704         struct sm501_device *smdev;
 705
 706         smdev = kzalloc(sizeof(struct sm501_device) +
 707                         (sizeof(struct resource) * res_count) +
 708                         platform_data_size, GFP_KERNEL);
 709         if (!smdev)
 710                 return NULL;
 711
 712         smdev->pdev.dev.release = sm501_device_release;
 713
 714         smdev->pdev.name = name;
 715         smdev->pdev.id = sm->pdev_id;
 716         smdev->pdev.dev.parent = sm->dev;
 717         smdev->pdev.dev.coherent_dma_mask = 0xffffffff;
 718
 719         if (res_count) {
 720                 smdev->pdev.resource = (struct resource *)(smdev+1);
 721                 smdev->pdev.num_resources = res_count;
 722         }
 723         if (platform_data_size)
 724                 smdev->pdev.dev.platform_data = (void *)(smdev+1);
 725
 726         return &smdev->pdev;
 727 }
 728
 729 /* sm501_register_device
 730  *
 731  * Register a platform device created with sm501_create_subdev()
 732 */
 733
 734 static int sm501_register_device(struct sm501_devdata *sm,
 735                                  struct platform_device *pdev)
 736 {
 737         struct sm501_device *smdev = to_sm_device(pdev);
 738         int ptr;
 739         int ret;
 740
 741         for (ptr = 0; ptr < pdev->num_resources; ptr++) {
 742                 printk(KERN_DEBUG "%s[%d] %pR\n",
 743                        pdev->name, ptr, &pdev->resource[ptr]);
 744         }
 745
 746         ret = platform_device_register(pdev);
 747
 748         if (ret >= 0) {
 749                 dev_dbg(sm->dev, "registered %s\n", pdev->name);
 750                 list_add_tail(&smdev->list, &sm->devices);
 751         } else
 752                 dev_err(sm->dev, "error registering %s (%d)\n",
 753                         pdev->name, ret);
 754
 755         return ret;
 756 }
 757
 758 /* sm501_create_subio
 759  *
 760  * Fill in an IO resource for a sub device
 761 */
 762
 763 static void sm501_create_subio(struct sm501_devdata *sm,
 764                                struct resource *res,
 765                                resource_size_t offs,
 766                                resource_size_t size)
 767 {
 768         res->flags = IORESOURCE_MEM;
 769         res->parent = sm->io_res;
 770         res->start = sm->io_res->start + offs;
 771         res->end = res->start + size - 1;
 772 }
 773
 774 /* sm501_create_mem
 775  *
 776  * Fill in an MEM resource for a sub device
 777 */
 778
 779 static void sm501_create_mem(struct sm501_devdata *sm,
 780                              struct resource *res,
 781                              resource_size_t *offs,
 782                              resource_size_t size)
 783 {
 784         *offs -= size;          /* adjust memory size */
 785
 786         res->flags = IORESOURCE_MEM;
 787         res->parent = sm->mem_res;
 788         res->start = sm->mem_res->start + *offs;
 789         res->end = res->start + size - 1;
 790 }
 791
 792 /* sm501_create_irq
 793  *
 794  * Fill in an IRQ resource for a sub device
 795 */
 796
 797 static void sm501_create_irq(struct sm501_devdata *sm,
 798                              struct resource *res)
 799 {
 800         res->flags = IORESOURCE_IRQ;
 801         res->parent = NULL;
 802         res->start = res->end = sm->irq;
 803 }
 804
 805 static int sm501_register_usbhost(struct sm501_devdata *sm,
 806                                   resource_size_t *mem_avail)
 807 {
 808         struct platform_device *pdev;
 809
 810         pdev = sm501_create_subdev(sm, "sm501-usb", 3, 0);
 811         if (!pdev)
 812                 return -ENOMEM;
 813
 814         sm501_create_subio(sm, &pdev->resource[0], 0x40000, 0x20000);
 815         sm501_create_mem(sm, &pdev->resource[1], mem_avail, 256*1024);
 816         sm501_create_irq(sm, &pdev->resource[2]);
 817
 818         return sm501_register_device(sm, pdev);
 819 }
 820
 821 static void sm501_setup_uart_data(struct sm501_devdata *sm,
 822                                   struct plat_serial8250_port *uart_data,
 823                                   unsigned int offset)
 824 {
 825         uart_data->membase = sm->regs + offset;
 826         uart_data->mapbase = sm->io_res->start + offset;
 827         uart_data->iotype = UPIO_MEM;
 828         uart_data->irq = sm->irq;
 829         uart_data->flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ;
 830         uart_data->regshift = 2;
 831         uart_data->uartclk = (9600 * 16);
 832 }
 833
 834 static int sm501_register_uart(struct sm501_devdata *sm, int devices)
 835 {
 836         struct platform_device *pdev;
 837         struct plat_serial8250_port *uart_data;
 838
 839         pdev = sm501_create_subdev(sm, "serial8250", 0,
 840                                    sizeof(struct plat_serial8250_port) * 3);
 841         if (!pdev)
 842                 return -ENOMEM;
 843
 844         uart_data = dev_get_platdata(&pdev->dev);
 845
 846         if (devices & SM501_USE_UART0) {
 847                 sm501_setup_uart_data(sm, uart_data++, 0x30000);
 848                 sm501_unit_power(sm->dev, SM501_GATE_UART0, 1);
 849                 sm501_modify_reg(sm->dev, SM501_IRQ_MASK, 1 << 12, 0);
 850                 sm501_modify_reg(sm->dev, SM501_GPIO63_32_CONTROL, 0x01e0, 0);
 851         }
 852         if (devices & SM501_USE_UART1) {
 853                 sm501_setup_uart_data(sm, uart_data++, 0x30020);
 854                 sm501_unit_power(sm->dev, SM501_GATE_UART1, 1);
 855                 sm501_modify_reg(sm->dev, SM501_IRQ_MASK, 1 << 13, 0);
 856                 sm501_modify_reg(sm->dev, SM501_GPIO63_32_CONTROL, 0x1e00, 0);
 857         }
 858
 859         pdev->id = PLAT8250_DEV_SM501;
 860
 861         return sm501_register_device(sm, pdev);
 862 }
 863
 864 static int sm501_register_display(struct sm501_devdata *sm,
 865                                   resource_size_t *mem_avail)
 866 {
 867         struct platform_device *pdev;
 868
 869         pdev = sm501_create_subdev(sm, "sm501-fb", 4, 0);
 870         if (!pdev)
 871                 return -ENOMEM;
 872
 873         sm501_create_subio(sm, &pdev->resource[0], 0x80000, 0x10000);
 874         sm501_create_subio(sm, &pdev->resource[1], 0x100000, 0x50000);
 875         sm501_create_mem(sm, &pdev->resource[2], mem_avail, *mem_avail);
 876         sm501_create_irq(sm, &pdev->resource[3]);
 877
 878         return sm501_register_device(sm, pdev);
 879 }
 880
 881 #ifdef CONFIG_MFD_SM501_GPIO
 882
 883 static inline struct sm501_devdata *sm501_gpio_to_dev(struct sm501_gpio *gpio)
 884 {
 885         return container_of(gpio, struct sm501_devdata, gpio);
 886 }
 887
 888 static int sm501_gpio_get(struct gpio_chip *chip, unsigned offset)
 889
 890 {
 891         struct sm501_gpio_chip *smgpio = gpiochip_get_data(chip);
 892         unsigned long result;
 893
 894         result = smc501_readl(smgpio->regbase + SM501_GPIO_DATA_LOW);
 895         result >>= offset;
 896
 897         return result & 1UL;
 898 }
 899
 900 static void sm501_gpio_ensure_gpio(struct sm501_gpio_chip *smchip,
 901                                    unsigned long bit)
 902 {
 903         unsigned long ctrl;
 904
 905         /* check and modify if this pin is not set as gpio. */
 906
 907         if (smc501_readl(smchip->control) & bit) {
 908                 dev_info(sm501_gpio_to_dev(smchip->ourgpio)->dev,
 909                          "changing mode of gpio, bit %08lx\n", bit);
 910
 911                 ctrl = smc501_readl(smchip->control);
 912                 ctrl &= ~bit;
 913                 smc501_writel(ctrl, smchip->control);
 914
 915                 sm501_sync_regs(sm501_gpio_to_dev(smchip->ourgpio));
 916         }
 917 }
 918
 919 static void sm501_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 920
 921 {
 922         struct sm501_gpio_chip *smchip = gpiochip_get_data(chip);
 923         struct sm501_gpio *smgpio = smchip->ourgpio;
 924         unsigned long bit = 1 << offset;
 925         void __iomem *regs = smchip->regbase;
 926         unsigned long save;
 927         unsigned long val;
 928
 929         dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d)\n",
 930                 __func__, chip, offset);
 931
 932         spin_lock_irqsave(&smgpio->lock, save);
 933
 934         val = smc501_readl(regs + SM501_GPIO_DATA_LOW) & ~bit;
 935         if (value)
 936                 val |= bit;
 937         smc501_writel(val, regs);
 938
 939         sm501_sync_regs(sm501_gpio_to_dev(smgpio));
 940         sm501_gpio_ensure_gpio(smchip, bit);
 941
 942         spin_unlock_irqrestore(&smgpio->lock, save);
 943 }
 944
 945 static int sm501_gpio_input(struct gpio_chip *chip, unsigned offset)
 946 {
 947         struct sm501_gpio_chip *smchip = gpiochip_get_data(chip);
 948         struct sm501_gpio *smgpio = smchip->ourgpio;
 949         void __iomem *regs = smchip->regbase;
 950         unsigned long bit = 1 << offset;
 951         unsigned long save;
 952         unsigned long ddr;
 953
 954         dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d)\n",
 955                 __func__, chip, offset);
 956
 957         spin_lock_irqsave(&smgpio->lock, save);
 958
 959         ddr = smc501_readl(regs + SM501_GPIO_DDR_LOW);
 960         smc501_writel(ddr & ~bit, regs + SM501_GPIO_DDR_LOW);
 961
 962         sm501_sync_regs(sm501_gpio_to_dev(smgpio));
 963         sm501_gpio_ensure_gpio(smchip, bit);
 964
 965         spin_unlock_irqrestore(&smgpio->lock, save);
 966
 967         return 0;
 968 }
 969
 970 static int sm501_gpio_output(struct gpio_chip *chip,
 971                              unsigned offset, int value)
 972 {
 973         struct sm501_gpio_chip *smchip = gpiochip_get_data(chip);
 974         struct sm501_gpio *smgpio = smchip->ourgpio;
 975         unsigned long bit = 1 << offset;
 976         void __iomem *regs = smchip->regbase;
 977         unsigned long save;
 978         unsigned long val;
 979         unsigned long ddr;
 980
 981         dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d,%d)\n",
 982                 __func__, chip, offset, value);
 983
 984         spin_lock_irqsave(&smgpio->lock, save);
 985
 986         val = smc501_readl(regs + SM501_GPIO_DATA_LOW);
 987         if (value)
 988                 val |= bit;
 989         else
 990                 val &= ~bit;
 991         smc501_writel(val, regs);
 992
 993         ddr = smc501_readl(regs + SM501_GPIO_DDR_LOW);
 994         smc501_writel(ddr | bit, regs + SM501_GPIO_DDR_LOW);
 995
 996         sm501_sync_regs(sm501_gpio_to_dev(smgpio));
 997         smc501_writel(val, regs + SM501_GPIO_DATA_LOW);
 998
 999         sm501_sync_regs(sm501_gpio_to_dev(smgpio));
1000         spin_unlock_irqrestore(&smgpio->lock, save);
1001
1002         return 0;
1003 }
1004
1005 static const struct gpio_chip gpio_chip_template = {
1006         .ngpio                  = 32,
1007         .direction_input        = sm501_gpio_input,
1008         .direction_output       = sm501_gpio_output,
1009         .set                    = sm501_gpio_set,
1010         .get                    = sm501_gpio_get,
1011 };
1012
1013 static int sm501_gpio_register_chip(struct sm501_devdata *sm,
1014                                               struct sm501_gpio *gpio,
1015                                               struct sm501_gpio_chip *chip)
1016 {
1017         struct sm501_platdata *pdata = sm->platdata;
1018         struct gpio_chip *gchip = &chip->gpio;
1019         int base = pdata->gpio_base;
1020
1021         chip->gpio = gpio_chip_template;
1022
1023         if (chip == &gpio->high) {
1024                 if (base > 0)
1025                         base += 32;
1026                 chip->regbase = gpio->regs + SM501_GPIO_DATA_HIGH;
1027                 chip->control = sm->regs + SM501_GPIO63_32_CONTROL;
1028                 gchip->label  = "SM501-HIGH";
1029         } else {
1030                 chip->regbase = gpio->regs + SM501_GPIO_DATA_LOW;
1031                 chip->control = sm->regs + SM501_GPIO31_0_CONTROL;
1032                 gchip->label  = "SM501-LOW";
1033         }
1034
1035         gchip->base   = base;
1036         chip->ourgpio = gpio;
1037
1038         return gpiochip_add_data(gchip, chip);
1039 }
1040
1041 static int sm501_register_gpio(struct sm501_devdata *sm)
1042 {
1043         struct sm501_gpio *gpio = &sm->gpio;
1044         resource_size_t iobase = sm->io_res->start + SM501_GPIO;
1045         int ret;
1046
1047         dev_dbg(sm->dev, "registering gpio block %08llx\n",
1048                 (unsigned long long)iobase);
1049
1050         spin_lock_init(&gpio->lock);
1051
1052         gpio->regs_res = request_mem_region(iobase, 0x20, "sm501-gpio");
1053         if (gpio->regs_res == NULL) {
1054                 dev_err(sm->dev, "gpio: failed to request region\n");
1055                 return -ENXIO;
1056         }
1057
1058         gpio->regs = ioremap(iobase, 0x20);
1059         if (gpio->regs == NULL) {
1060                 dev_err(sm->dev, "gpio: failed to remap registers\n");
1061                 ret = -ENXIO;
1062                 goto err_claimed;
1063         }
1064
1065         /* Register both our chips. */
1066
1067         ret = sm501_gpio_register_chip(sm, gpio, &gpio->low);
1068         if (ret) {
1069                 dev_err(sm->dev, "failed to add low chip\n");
1070                 goto err_mapped;
1071         }
1072
1073         ret = sm501_gpio_register_chip(sm, gpio, &gpio->high);
1074         if (ret) {
1075                 dev_err(sm->dev, "failed to add high chip\n");
1076                 goto err_low_chip;
1077         }
1078
1079         gpio->registered = 1;
1080
1081         return 0;
1082
1083  err_low_chip:
1084         gpiochip_remove(&gpio->low.gpio);
1085
1086  err_mapped:
1087         iounmap(gpio->regs);
1088
1089  err_claimed:
1090         release_resource(gpio->regs_res);
1091         kfree(gpio->regs_res);
1092
1093         return ret;
1094 }
1095
1096 static void sm501_gpio_remove(struct sm501_devdata *sm)
1097 {
1098         struct sm501_gpio *gpio = &sm->gpio;
1099
1100         if (!sm->gpio.registered)
1101                 return;
1102
1103         gpiochip_remove(&gpio->low.gpio);
1104         gpiochip_remove(&gpio->high.gpio);
1105
1106         iounmap(gpio->regs);
1107         release_resource(gpio->regs_res);
1108         kfree(gpio->regs_res);
1109 }
1110
1111 static inline int sm501_gpio_pin2nr(struct sm501_devdata *sm, unsigned int pin)
1112 {
1113         struct sm501_gpio *gpio = &sm->gpio;
1114         int base = (pin < 32) ? gpio->low.gpio.base : gpio->high.gpio.base;
1115
1116         return (pin % 32) + base;
1117 }
1118
1119 static inline int sm501_gpio_isregistered(struct sm501_devdata *sm)
1120 {
1121         return sm->gpio.registered;
1122 }
1123 #else
1124 static inline int sm501_register_gpio(struct sm501_devdata *sm)
1125 {
1126         return 0;
1127 }
1128
1129 static inline void sm501_gpio_remove(struct sm501_devdata *sm)
1130 {
1131 }
1132
1133 static inline int sm501_gpio_pin2nr(struct sm501_devdata *sm, unsigned int pin)
1134 {
1135         return -1;
1136 }
1137
1138 static inline int sm501_gpio_isregistered(struct sm501_devdata *sm)
1139 {
1140         return 0;
1141 }
1142 #endif
1143
1144 static int sm501_register_gpio_i2c_instance(struct sm501_devdata *sm,
1145                                             struct sm501_platdata_gpio_i2c *iic)
1146 {
1147         struct i2c_gpio_platform_data *icd;
1148         struct platform_device *pdev;
1149
1150         pdev = sm501_create_subdev(sm, "i2c-gpio", 0,
1151                                    sizeof(struct i2c_gpio_platform_data));
1152         if (!pdev)
1153                 return -ENOMEM;
1154
1155         icd = dev_get_platdata(&pdev->dev);
1156
1157         /* We keep the pin_sda and pin_scl fields relative in case the
1158          * same platform data is passed to >1 SM501.
1159          */
1160
1161         icd->sda_pin = sm501_gpio_pin2nr(sm, iic->pin_sda);
1162         icd->scl_pin = sm501_gpio_pin2nr(sm, iic->pin_scl);
1163         icd->timeout = iic->timeout;
1164         icd->udelay = iic->udelay;
1165
1166         /* note, we can't use either of the pin numbers, as the i2c-gpio
1167          * driver uses the platform.id field to generate the bus number
1168          * to register with the i2c core; The i2c core doesn't have enough
1169          * entries to deal with anything we currently use.
1170         */
1171
1172         pdev->id = iic->bus_num;
1173
1174         dev_info(sm->dev, "registering i2c-%d: sda=%d (%d), scl=%d (%d)\n",
1175                  iic->bus_num,
1176                  icd->sda_pin, iic->pin_sda, icd->scl_pin, iic->pin_scl);
1177
1178         return sm501_register_device(sm, pdev);
1179 }
1180
1181 static int sm501_register_gpio_i2c(struct sm501_devdata *sm,
1182                                    struct sm501_platdata *pdata)
1183 {
1184         struct sm501_platdata_gpio_i2c *iic = pdata->gpio_i2c;
1185         int index;
1186         int ret;
1187
1188         for (index = 0; index < pdata->gpio_i2c_nr; index++, iic++) {
1189                 ret = sm501_register_gpio_i2c_instance(sm, iic);
1190                 if (ret < 0)
1191                         return ret;
1192         }
1193
1194         return 0;
1195 }
1196
1197 /* sm501_dbg_regs
1198  *
1199  * Debug attribute to attach to parent device to show core registers
1200 */
1201
1202 static ssize_t sm501_dbg_regs(struct device *dev,
1203                               struct device_attribute *attr, char *buff)
1204 {
1205         struct sm501_devdata *sm = dev_get_drvdata(dev) ;
1206         unsigned int reg;
1207         char *ptr = buff;
1208         int ret;
1209
1210         for (reg = 0x00; reg < 0x70; reg += 4) {
1211                 ret = sprintf(ptr, "%08x = %08x\n",
1212                               reg, smc501_readl(sm->regs + reg));
1213                 ptr += ret;
1214         }
1215
1216         return ptr - buff;
1217 }
1218
1219
1220 static DEVICE_ATTR(dbg_regs, 0444, sm501_dbg_regs, NULL);
1221
1222 /* sm501_init_reg
1223  *
1224  * Helper function for the init code to setup a register
1225  *
1226  * clear the bits which are set in r->mask, and then set
1227  * the bits set in r->set.
1228 */
1229
1230 static inline void sm501_init_reg(struct sm501_devdata *sm,
1231                                   unsigned long reg,
1232                                   struct sm501_reg_init *r)
1233 {
1234         unsigned long tmp;
1235
1236         tmp = smc501_readl(sm->regs + reg);
1237         tmp &= ~r->mask;
1238         tmp |= r->set;
1239         smc501_writel(tmp, sm->regs + reg);
1240 }
1241
1242 /* sm501_init_regs
1243  *
1244  * Setup core register values
1245 */
1246
1247 static void sm501_init_regs(struct sm501_devdata *sm,
1248                             struct sm501_initdata *init)
1249 {
1250         sm501_misc_control(sm->dev,
1251                            init->misc_control.set,
1252                            init->misc_control.mask);
1253
1254         sm501_init_reg(sm, SM501_MISC_TIMING, &init->misc_timing);
1255         sm501_init_reg(sm, SM501_GPIO31_0_CONTROL, &init->gpio_low);
1256         sm501_init_reg(sm, SM501_GPIO63_32_CONTROL, &init->gpio_high);
1257
1258         if (init->m1xclk) {
1259                 dev_info(sm->dev, "setting M1XCLK to %ld\n", init->m1xclk);
1260                 sm501_set_clock(sm->dev, SM501_CLOCK_M1XCLK, init->m1xclk);
1261         }
1262
1263         if (init->mclk) {
1264                 dev_info(sm->dev, "setting MCLK to %ld\n", init->mclk);
1265                 sm501_set_clock(sm->dev, SM501_CLOCK_MCLK, init->mclk);
1266         }
1267
1268 }
1269
1270 /* Check the PLL sources for the M1CLK and M1XCLK
1271  *
1272  * If the M1CLK and M1XCLKs are not sourced from the same PLL, then
1273  * there is a risk (see errata AB-5) that the SM501 will cease proper
1274  * function. If this happens, then it is likely the SM501 will
1275  * hang the system.
1276 */
1277
1278 static int sm501_check_clocks(struct sm501_devdata *sm)
1279 {
1280         unsigned long pwrmode = smc501_readl(sm->regs + SM501_CURRENT_CLOCK);
1281         unsigned long msrc = (pwrmode & SM501_POWERMODE_M_SRC);
1282         unsigned long m1src = (pwrmode & SM501_POWERMODE_M1_SRC);
1283
1284         return ((msrc == 0 && m1src != 0) || (msrc != 0 && m1src == 0));
1285 }
1286
1287 static unsigned int sm501_mem_local[] = {
1288         [0]     = 4*1024*1024,
1289         [1]     = 8*1024*1024,
1290         [2]     = 16*1024*1024,
1291         [3]     = 32*1024*1024,
1292         [4]     = 64*1024*1024,
1293         [5]     = 2*1024*1024,
1294 };
1295
1296 /* sm501_init_dev
1297  *
1298  * Common init code for an SM501
1299 */
1300
1301 static int sm501_init_dev(struct sm501_devdata *sm)
1302 {
1303         struct sm501_initdata *idata;
1304         struct sm501_platdata *pdata;
1305         resource_size_t mem_avail;
1306         unsigned long dramctrl;
1307         unsigned long devid;
1308         int ret;
1309
1310         mutex_init(&sm->clock_lock);
1311         spin_lock_init(&sm->reg_lock);
1312
1313         INIT_LIST_HEAD(&sm->devices);
1314
1315         devid = smc501_readl(sm->regs + SM501_DEVICEID);
1316
1317         if ((devid & SM501_DEVICEID_IDMASK) != SM501_DEVICEID_SM501) {
1318                 dev_err(sm->dev, "incorrect device id %08lx\n", devid);
1319                 return -EINVAL;
1320         }
1321
1322         /* disable irqs */
1323         smc501_writel(0, sm->regs + SM501_IRQ_MASK);
1324
1325         dramctrl = smc501_readl(sm->regs + SM501_DRAM_CONTROL);
1326         mem_avail = sm501_mem_local[(dramctrl >> 13) & 0x7];
1327
1328         dev_info(sm->dev, "SM501 At %p: Version %08lx, %ld Mb, IRQ %d\n",
1329                  sm->regs, devid, (unsigned long)mem_avail >> 20, sm->irq);
1330
1331         sm->rev = devid & SM501_DEVICEID_REVMASK;
1332
1333         sm501_dump_gate(sm);
1334
1335         ret = device_create_file(sm->dev, &dev_attr_dbg_regs);
1336         if (ret)
1337                 dev_err(sm->dev, "failed to create debug regs file\n");
1338
1339         sm501_dump_clk(sm);
1340
1341         /* check to see if we have some device initialisation */
1342
1343         pdata = sm->platdata;
1344         idata = pdata ? pdata->init : NULL;
1345
1346         if (idata) {
1347                 sm501_init_regs(sm, idata);
1348
1349                 if (idata->devices & SM501_USE_USB_HOST)
1350                         sm501_register_usbhost(sm, &mem_avail);
1351                 if (idata->devices & (SM501_USE_UART0 | SM501_USE_UART1))
1352                         sm501_register_uart(sm, idata->devices);
1353                 if (idata->devices & SM501_USE_GPIO)
1354                         sm501_register_gpio(sm);
1355         }
1356
1357         if (pdata && pdata->gpio_i2c != NULL && pdata->gpio_i2c_nr > 0) {
1358                 if (!sm501_gpio_isregistered(sm))
1359                         dev_err(sm->dev, "no gpio available for i2c gpio.\n");
1360                 else
1361                         sm501_register_gpio_i2c(sm, pdata);
1362         }
1363
1364         ret = sm501_check_clocks(sm);
1365         if (ret) {
1366                 dev_err(sm->dev, "M1X and M clocks sourced from different "
1367                                         "PLLs\n");
1368                 return -EINVAL;
1369         }
1370
1371         /* always create a framebuffer */
1372         sm501_register_display(sm, &mem_avail);
1373
1374         return 0;
1375 }
1376
1377 static int sm501_plat_probe(struct platform_device *dev)
1378 {
1379         struct sm501_devdata *sm;
1380         int ret;
1381
1382         sm = kzalloc(sizeof(struct sm501_devdata), GFP_KERNEL);
1383         if (sm == NULL) {
1384                 dev_err(&dev->dev, "no memory for device data\n");
1385                 ret = -ENOMEM;
1386                 goto err1;
1387         }
1388
1389         sm->dev = &dev->dev;
1390         sm->pdev_id = dev->id;
1391         sm->platdata = dev_get_platdata(&dev->dev);
1392
1393         ret = platform_get_irq(dev, 0);
1394         if (ret < 0) {
1395                 dev_err(&dev->dev, "failed to get irq resource\n");
1396                 goto err_res;
1397         }
1398         sm->irq = ret;
1399
1400         sm->io_res = platform_get_resource(dev, IORESOURCE_MEM, 1);
1401         sm->mem_res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1402
1403         if (sm->io_res == NULL || sm->mem_res == NULL) {
1404                 dev_err(&dev->dev, "failed to get IO resource\n");
1405                 ret = -ENOENT;
1406                 goto err_res;
1407         }
1408
1409         sm->regs_claim = request_mem_region(sm->io_res->start,
1410                                             0x100, "sm501");
1411
1412         if (sm->regs_claim == NULL) {
1413                 dev_err(&dev->dev, "cannot claim registers\n");
1414                 ret = -EBUSY;
1415                 goto err_res;
1416         }
1417
1418         platform_set_drvdata(dev, sm);
1419
1420         sm->regs = ioremap(sm->io_res->start, resource_size(sm->io_res));
1421
1422         if (sm->regs == NULL) {
1423                 dev_err(&dev->dev, "cannot remap registers\n");
1424                 ret = -EIO;
1425                 goto err_claim;
1426         }
1427
1428         ret = sm501_init_dev(sm);
1429         if (ret)
1430                 goto err_unmap;
1431
1432         return 0;
1433
1434  err_unmap:
1435         iounmap(sm->regs);
1436  err_claim:
1437         release_resource(sm->regs_claim);
1438         kfree(sm->regs_claim);
1439  err_res:
1440         kfree(sm);
1441  err1:
1442         return ret;
1443
1444 }
1445
1446 #ifdef CONFIG_PM
1447
1448 /* power management support */
1449
1450 static void sm501_set_power(struct sm501_devdata *sm, int on)
1451 {
1452         struct sm501_platdata *pd = sm->platdata;
1453
1454         if (pd == NULL)
1455                 return;
1456
1457         if (pd->get_power) {
1458                 if (pd->get_power(sm->dev) == on) {
1459                         dev_dbg(sm->dev, "is already %d\n", on);
1460                         return;
1461                 }
1462         }
1463
1464         if (pd->set_power) {
1465                 dev_dbg(sm->dev, "setting power to %d\n", on);
1466
1467                 pd->set_power(sm->dev, on);
1468                 sm501_mdelay(sm, 10);
1469         }
1470 }
1471
1472 static int sm501_plat_suspend(struct platform_device *pdev, pm_message_t state)
1473 {
1474         struct sm501_devdata *sm = platform_get_drvdata(pdev);
1475
1476         sm->in_suspend = 1;
1477         sm->pm_misc = smc501_readl(sm->regs + SM501_MISC_CONTROL);
1478
1479         sm501_dump_regs(sm);
1480
1481         if (sm->platdata) {
1482                 if (sm->platdata->flags & SM501_FLAG_SUSPEND_OFF)
1483                         sm501_set_power(sm, 0);
1484         }
1485
1486         return 0;
1487 }
1488
1489 static int sm501_plat_resume(struct platform_device *pdev)
1490 {
1491         struct sm501_devdata *sm = platform_get_drvdata(pdev);
1492
1493         sm501_set_power(sm, 1);
1494
1495         sm501_dump_regs(sm);
1496         sm501_dump_gate(sm);
1497         sm501_dump_clk(sm);
1498
1499         /* check to see if we are in the same state as when suspended */
1500
1501         if (smc501_readl(sm->regs + SM501_MISC_CONTROL) != sm->pm_misc) {
1502                 dev_info(sm->dev, "SM501_MISC_CONTROL changed over sleep\n");
1503                 smc501_writel(sm->pm_misc, sm->regs + SM501_MISC_CONTROL);
1504
1505                 /* our suspend causes the controller state to change,
1506                  * either by something attempting setup, power loss,
1507                  * or an external reset event on power change */
1508
1509                 if (sm->platdata && sm->platdata->init) {
1510                         sm501_init_regs(sm, sm->platdata->init);
1511                 }
1512         }
1513
1514         /* dump our state from resume */
1515
1516         sm501_dump_regs(sm);
1517         sm501_dump_clk(sm);
1518
1519         sm->in_suspend = 0;
1520
1521         return 0;
1522 }
1523 #else
1524 #define sm501_plat_suspend NULL
1525 #define sm501_plat_resume NULL
1526 #endif
1527
1528 /* Initialisation data for PCI devices */
1529
1530 static struct sm501_initdata sm501_pci_initdata = {
1531         .gpio_high      = {
1532                 .set    = 0x3F000000,           /* 24bit panel */
1533                 .mask   = 0x0,
1534         },
1535         .misc_timing    = {
1536                 .set    = 0x010100,             /* SDRAM timing */
1537                 .mask   = 0x1F1F00,
1538         },
1539         .misc_control   = {
1540                 .set    = SM501_MISC_PNL_24BIT,
1541                 .mask   = 0,
1542         },
1543
1544         .devices        = SM501_USE_ALL,
1545
1546         /* Errata AB-3 says that 72MHz is the fastest available
1547          * for 33MHZ PCI with proper bus-mastering operation */
1548
1549         .mclk           = 72 * MHZ,
1550         .m1xclk         = 144 * MHZ,
1551 };
1552
1553 static struct sm501_platdata_fbsub sm501_pdata_fbsub = {
1554         .flags          = (SM501FB_FLAG_USE_INIT_MODE |
1555                            SM501FB_FLAG_USE_HWCURSOR |
1556                            SM501FB_FLAG_USE_HWACCEL |
1557                            SM501FB_FLAG_DISABLE_AT_EXIT),
1558 };
1559
1560 static struct sm501_platdata_fb sm501_fb_pdata = {
1561         .fb_route       = SM501_FB_OWN,
1562         .fb_crt         = &sm501_pdata_fbsub,
1563         .fb_pnl         = &sm501_pdata_fbsub,
1564 };
1565
1566 static struct sm501_platdata sm501_pci_platdata = {
1567         .init           = &sm501_pci_initdata,
1568         .fb             = &sm501_fb_pdata,
1569         .gpio_base      = -1,
1570 };
1571
1572 static int sm501_pci_probe(struct pci_dev *dev,
1573                                      const struct pci_device_id *id)
1574 {
1575         struct sm501_devdata *sm;
1576         int err;
1577
1578         sm = kzalloc(sizeof(struct sm501_devdata), GFP_KERNEL);
1579         if (sm == NULL) {
1580                 dev_err(&dev->dev, "no memory for device data\n");
1581                 err = -ENOMEM;
1582                 goto err1;
1583         }
1584
1585         /* set a default set of platform data */
1586         dev->dev.platform_data = sm->platdata = &sm501_pci_platdata;
1587
1588         /* set a hopefully unique id for our child platform devices */
1589         sm->pdev_id = 32 + dev->devfn;
1590
1591         pci_set_drvdata(dev, sm);
1592
1593         err = pci_enable_device(dev);
1594         if (err) {
1595                 dev_err(&dev->dev, "cannot enable device\n");
1596                 goto err2;
1597         }
1598
1599         sm->dev = &dev->dev;
1600         sm->irq = dev->irq;
1601
1602 #ifdef __BIG_ENDIAN
1603         /* if the system is big-endian, we most probably have a
1604          * translation in the IO layer making the PCI bus little endian
1605          * so make the framebuffer swapped pixels */
1606
1607         sm501_fb_pdata.flags |= SM501_FBPD_SWAP_FB_ENDIAN;
1608 #endif
1609
1610         /* check our resources */
1611
1612         if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM)) {
1613                 dev_err(&dev->dev, "region #0 is not memory?\n");
1614                 err = -EINVAL;
1615                 goto err3;
1616         }
1617
1618         if (!(pci_resource_flags(dev, 1) & IORESOURCE_MEM)) {
1619                 dev_err(&dev->dev, "region #1 is not memory?\n");
1620                 err = -EINVAL;
1621                 goto err3;
1622         }
1623
1624         /* make our resources ready for sharing */
1625
1626         sm->io_res = &dev->resource[1];
1627         sm->mem_res = &dev->resource[0];
1628
1629         sm->regs_claim = request_mem_region(sm->io_res->start,
1630                                             0x100, "sm501");
1631         if (sm->regs_claim == NULL) {
1632                 dev_err(&dev->dev, "cannot claim registers\n");
1633                 err= -EBUSY;
1634                 goto err3;
1635         }
1636
1637         sm->regs = pci_ioremap_bar(dev, 1);
1638
1639         if (sm->regs == NULL) {
1640                 dev_err(&dev->dev, "cannot remap registers\n");
1641                 err = -EIO;
1642                 goto err4;
1643         }
1644
1645         sm501_init_dev(sm);
1646         return 0;
1647
1648  err4:
1649         release_resource(sm->regs_claim);
1650         kfree(sm->regs_claim);
1651  err3:
1652         pci_disable_device(dev);
1653  err2:
1654         kfree(sm);
1655  err1:
1656         return err;
1657 }
1658
1659 static void sm501_remove_sub(struct sm501_devdata *sm,
1660                              struct sm501_device *smdev)
1661 {
1662         list_del(&smdev->list);
1663         platform_device_unregister(&smdev->pdev);
1664 }
1665
1666 static void sm501_dev_remove(struct sm501_devdata *sm)
1667 {
1668         struct sm501_device *smdev, *tmp;
1669
1670         list_for_each_entry_safe(smdev, tmp, &sm->devices, list)
1671                 sm501_remove_sub(sm, smdev);
1672
1673         device_remove_file(sm->dev, &dev_attr_dbg_regs);
1674
1675         sm501_gpio_remove(sm);
1676 }
1677
1678 static void sm501_pci_remove(struct pci_dev *dev)
1679 {
1680         struct sm501_devdata *sm = pci_get_drvdata(dev);
1681
1682         sm501_dev_remove(sm);
1683         iounmap(sm->regs);
1684
1685         release_resource(sm->regs_claim);
1686         kfree(sm->regs_claim);
1687
1688         pci_disable_device(dev);
1689 }
1690
1691 static int sm501_plat_remove(struct platform_device *dev)
1692 {
1693         struct sm501_devdata *sm = platform_get_drvdata(dev);
1694
1695         sm501_dev_remove(sm);
1696         iounmap(sm->regs);
1697
1698         release_resource(sm->regs_claim);
1699         kfree(sm->regs_claim);
1700
1701         return 0;
1702 }
1703
1704 static const struct pci_device_id sm501_pci_tbl[] = {
1705         { 0x126f, 0x0501, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
1706         { 0, },
1707 };
1708
1709 MODULE_DEVICE_TABLE(pci, sm501_pci_tbl);
1710
1711 static struct pci_driver sm501_pci_driver = {
1712         .name           = "sm501",
1713         .id_table       = sm501_pci_tbl,
1714         .probe          = sm501_pci_probe,
1715         .remove         = sm501_pci_remove,
1716 };
1717
1718 MODULE_ALIAS("platform:sm501");
1719
1720 static const struct of_device_id of_sm501_match_tbl[] = {
1721         { .compatible = "smi,sm501", },
1722         { /* end */ }
1723 };
1724 MODULE_DEVICE_TABLE(of, of_sm501_match_tbl);
1725
1726 static struct platform_driver sm501_plat_driver = {
1727         .driver         = {
1728                 .name   = "sm501",
1729                 .of_match_table = of_sm501_match_tbl,
1730         },
1731         .probe          = sm501_plat_probe,
1732         .remove         = sm501_plat_remove,
1733         .suspend        = sm501_plat_suspend,
1734         .resume         = sm501_plat_resume,
1735 };
1736
1737 static int __init sm501_base_init(void)
1738 {
1739         int ret;
1740
1741         ret = platform_driver_register(&sm501_plat_driver);
1742         if (ret < 0)
1743                 return ret;
1744
1745         return pci_register_driver(&sm501_pci_driver);
1746 }
1747
1748 static void __exit sm501_base_exit(void)
1749 {
1750         platform_driver_unregister(&sm501_plat_driver);
1751         pci_unregister_driver(&sm501_pci_driver);
1752 }
1753
1754 module_init(sm501_base_init);
1755 module_exit(sm501_base_exit);
1756
1757 MODULE_DESCRIPTION("SM501 Core Driver");
1758 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, Vincent Sanders");
1759 MODULE_LICENSE("GPL v2");