drivers/mfd/rts5249.c

   1 /* Driver for Realtek PCI-Express card reader
   2  *
   3  * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2, or (at your option) any
   8  * later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program; if not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * Author:
  19  *   Wei WANG <wei_wang@realsil.com.cn>
  20  */
  21
  22 #include <linux/module.h>
  23 #include <linux/delay.h>
  24 #include <linux/mfd/rtsx_pci.h>
  25
  26 #include "rtsx_pcr.h"
  27
  28 static u8 rts5249_get_ic_version(struct rtsx_pcr *pcr)
  29 {
  30         u8 val;
  31
  32         rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
  33         return val & 0x0F;
  34 }
  35
  36 static void rts5249_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
  37 {
  38         u8 driving_3v3[4][3] = {
  39                 {0x11, 0x11, 0x18},
  40                 {0x55, 0x55, 0x5C},
  41                 {0xFF, 0xFF, 0xFF},
  42                 {0x96, 0x96, 0x96},
  43         };
  44         u8 driving_1v8[4][3] = {
  45                 {0xC4, 0xC4, 0xC4},
  46                 {0x3C, 0x3C, 0x3C},
  47                 {0xFE, 0xFE, 0xFE},
  48                 {0xB3, 0xB3, 0xB3},
  49         };
  50         u8 (*driving)[3], drive_sel;
  51
  52         if (voltage == OUTPUT_3V3) {
  53                 driving = driving_3v3;
  54                 drive_sel = pcr->sd30_drive_sel_3v3;
  55         } else {
  56                 driving = driving_1v8;
  57                 drive_sel = pcr->sd30_drive_sel_1v8;
  58         }
  59
  60         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL,
  61                         0xFF, driving[drive_sel][0]);
  62         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL,
  63                         0xFF, driving[drive_sel][1]);
  64         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL,
  65                         0xFF, driving[drive_sel][2]);
  66 }
  67
  68 static void rtsx_base_fetch_vendor_settings(struct rtsx_pcr *pcr)
  69 {
  70         u32 reg;
  71
  72         rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, &reg);
  73         pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
  74
  75         if (!rtsx_vendor_setting_valid(reg)) {
  76                 pcr_dbg(pcr, "skip fetch vendor setting\n");
  77                 return;
  78         }
  79
  80         pcr->aspm_en = rtsx_reg_to_aspm(reg);
  81         pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
  82         pcr->card_drive_sel &= 0x3F;
  83         pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
  84
  85         rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG2, &reg);
  86         pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
  87         pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
  88         if (rtsx_reg_check_reverse_socket(reg))
  89                 pcr->flags |= PCR_REVERSE_SOCKET;
  90 }
  91
  92 static void rtsx_base_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
  93 {
  94         /* Set relink_time to 0 */
  95         rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, 0xFF, 0);
  96         rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, 0xFF, 0);
  97         rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3, 0x01, 0);
  98
  99         if (pm_state == HOST_ENTER_S3)
 100                 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3,
 101                         D3_DELINK_MODE_EN, D3_DELINK_MODE_EN);
 102
 103         rtsx_pci_write_register(pcr, FPDCTL, 0x03, 0x03);
 104 }
 105
 106 static int rts5249_extra_init_hw(struct rtsx_pcr *pcr)
 107 {
 108         rtsx_pci_init_cmd(pcr);
 109
 110         /* Rest L1SUB Config */
 111         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, L1SUB_CONFIG3, 0xFF, 0x00);
 112         /* Configure GPIO as output */
 113         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);
 114         /* Reset ASPM state to default value */
 115         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
 116         /* Switch LDO3318 source from DV33 to card_3v3 */
 117         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00);
 118         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01);
 119         /* LED shine disabled, set initial shine cycle period */
 120         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02);
 121         /* Configure driving */
 122         rts5249_fill_driving(pcr, OUTPUT_3V3);
 123         if (pcr->flags & PCR_REVERSE_SOCKET)
 124                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0xB0);
 125         else
 126                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0x80);
 127
 128         return rtsx_pci_send_cmd(pcr, 100);
 129 }
 130
 131 static int rts5249_optimize_phy(struct rtsx_pcr *pcr)
 132 {
 133         int err;
 134
 135         err = rtsx_pci_write_register(pcr, PM_CTRL3, D3_DELINK_MODE_EN, 0x00);
 136         if (err < 0)
 137                 return err;
 138
 139         err = rtsx_pci_write_phy_register(pcr, PHY_REV,
 140                         PHY_REV_RESV | PHY_REV_RXIDLE_LATCHED |
 141                         PHY_REV_P1_EN | PHY_REV_RXIDLE_EN |
 142                         PHY_REV_CLKREQ_TX_EN | PHY_REV_RX_PWST |
 143                         PHY_REV_CLKREQ_DT_1_0 | PHY_REV_STOP_CLKRD |
 144                         PHY_REV_STOP_CLKWR);
 145         if (err < 0)
 146                 return err;
 147
 148         msleep(1);
 149
 150         err = rtsx_pci_write_phy_register(pcr, PHY_BPCR,
 151                         PHY_BPCR_IBRXSEL | PHY_BPCR_IBTXSEL |
 152                         PHY_BPCR_IB_FILTER | PHY_BPCR_CMIRROR_EN);
 153         if (err < 0)
 154                 return err;
 155
 156         err = rtsx_pci_write_phy_register(pcr, PHY_PCR,
 157                         PHY_PCR_FORCE_CODE | PHY_PCR_OOBS_CALI_50 |
 158                         PHY_PCR_OOBS_VCM_08 | PHY_PCR_OOBS_SEN_90 |
 159                         PHY_PCR_RSSI_EN | PHY_PCR_RX10K);
 160         if (err < 0)
 161                 return err;
 162
 163         err = rtsx_pci_write_phy_register(pcr, PHY_RCR2,
 164                         PHY_RCR2_EMPHASE_EN | PHY_RCR2_NADJR |
 165                         PHY_RCR2_CDR_SR_2 | PHY_RCR2_FREQSEL_12 |
 166                         PHY_RCR2_CDR_SC_12P | PHY_RCR2_CALIB_LATE);
 167         if (err < 0)
 168                 return err;
 169
 170         err = rtsx_pci_write_phy_register(pcr, PHY_FLD4,
 171                         PHY_FLD4_FLDEN_SEL | PHY_FLD4_REQ_REF |
 172                         PHY_FLD4_RXAMP_OFF | PHY_FLD4_REQ_ADDA |
 173                         PHY_FLD4_BER_COUNT | PHY_FLD4_BER_TIMER |
 174                         PHY_FLD4_BER_CHK_EN);
 175         if (err < 0)
 176                 return err;
 177         err = rtsx_pci_write_phy_register(pcr, PHY_RDR,
 178                         PHY_RDR_RXDSEL_1_9 | PHY_SSC_AUTO_PWD);
 179         if (err < 0)
 180                 return err;
 181         err = rtsx_pci_write_phy_register(pcr, PHY_RCR1,
 182                         PHY_RCR1_ADP_TIME_4 | PHY_RCR1_VCO_COARSE);
 183         if (err < 0)
 184                 return err;
 185         err = rtsx_pci_write_phy_register(pcr, PHY_FLD3,
 186                         PHY_FLD3_TIMER_4 | PHY_FLD3_TIMER_6 |
 187                         PHY_FLD3_RXDELINK);
 188         if (err < 0)
 189                 return err;
 190
 191         return rtsx_pci_write_phy_register(pcr, PHY_TUNE,
 192                         PHY_TUNE_TUNEREF_1_0 | PHY_TUNE_VBGSEL_1252 |
 193                         PHY_TUNE_SDBUS_33 | PHY_TUNE_TUNED18 |
 194                         PHY_TUNE_TUNED12 | PHY_TUNE_TUNEA12);
 195 }
 196
 197 static int rtsx_base_turn_on_led(struct rtsx_pcr *pcr)
 198 {
 199         return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02);
 200 }
 201
 202 static int rtsx_base_turn_off_led(struct rtsx_pcr *pcr)
 203 {
 204         return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00);
 205 }
 206
 207 static int rtsx_base_enable_auto_blink(struct rtsx_pcr *pcr)
 208 {
 209         return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08);
 210 }
 211
 212 static int rtsx_base_disable_auto_blink(struct rtsx_pcr *pcr)
 213 {
 214         return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00);
 215 }
 216
 217 static int rtsx_base_card_power_on(struct rtsx_pcr *pcr, int card)
 218 {
 219         int err;
 220
 221         rtsx_pci_init_cmd(pcr);
 222         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
 223                         SD_POWER_MASK, SD_VCC_PARTIAL_POWER_ON);
 224         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
 225                         LDO3318_PWR_MASK, 0x02);
 226         err = rtsx_pci_send_cmd(pcr, 100);
 227         if (err < 0)
 228                 return err;
 229
 230         msleep(5);
 231
 232         rtsx_pci_init_cmd(pcr);
 233         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
 234                         SD_POWER_MASK, SD_VCC_POWER_ON);
 235         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
 236                         LDO3318_PWR_MASK, 0x06);
 237         return rtsx_pci_send_cmd(pcr, 100);
 238 }
 239
 240 static int rtsx_base_card_power_off(struct rtsx_pcr *pcr, int card)
 241 {
 242         rtsx_pci_init_cmd(pcr);
 243         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
 244                         SD_POWER_MASK, SD_POWER_OFF);
 245         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
 246                         LDO3318_PWR_MASK, 0x00);
 247         return rtsx_pci_send_cmd(pcr, 100);
 248 }
 249
 250 static int rtsx_base_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
 251 {
 252         int err;
 253         u16 append;
 254
 255         switch (voltage) {
 256         case OUTPUT_3V3:
 257                 err = rtsx_pci_update_phy(pcr, PHY_TUNE, PHY_TUNE_VOLTAGE_MASK,
 258                         PHY_TUNE_VOLTAGE_3V3);
 259                 if (err < 0)
 260                         return err;
 261                 break;
 262         case OUTPUT_1V8:
 263                 append = PHY_TUNE_D18_1V8;
 264                 if (CHK_PCI_PID(pcr, 0x5249)) {
 265                         err = rtsx_pci_update_phy(pcr, PHY_BACR,
 266                                 PHY_BACR_BASIC_MASK, 0);
 267                         if (err < 0)
 268                                 return err;
 269                         append = PHY_TUNE_D18_1V7;
 270                 }
 271
 272                 err = rtsx_pci_update_phy(pcr, PHY_TUNE, PHY_TUNE_VOLTAGE_MASK,
 273                         append);
 274                 if (err < 0)
 275                         return err;
 276                 break;
 277         default:
 278                 pcr_dbg(pcr, "unknown output voltage %d\n", voltage);
 279                 return -EINVAL;
 280         }
 281
 282         /* set pad drive */
 283         rtsx_pci_init_cmd(pcr);
 284         rts5249_fill_driving(pcr, voltage);
 285         return rtsx_pci_send_cmd(pcr, 100);
 286 }
 287
 288 static const struct pcr_ops rts5249_pcr_ops = {
 289         .fetch_vendor_settings = rtsx_base_fetch_vendor_settings,
 290         .extra_init_hw = rts5249_extra_init_hw,
 291         .optimize_phy = rts5249_optimize_phy,
 292         .turn_on_led = rtsx_base_turn_on_led,
 293         .turn_off_led = rtsx_base_turn_off_led,
 294         .enable_auto_blink = rtsx_base_enable_auto_blink,
 295         .disable_auto_blink = rtsx_base_disable_auto_blink,
 296         .card_power_on = rtsx_base_card_power_on,
 297         .card_power_off = rtsx_base_card_power_off,
 298         .switch_output_voltage = rtsx_base_switch_output_voltage,
 299         .force_power_down = rtsx_base_force_power_down,
 300 };
 301
 302 /* SD Pull Control Enable:
 303  *     SD_DAT[3:0] ==> pull up
 304  *     SD_CD       ==> pull up
 305  *     SD_WP       ==> pull up
 306  *     SD_CMD      ==> pull up
 307  *     SD_CLK      ==> pull down
 308  */
 309 static const u32 rts5249_sd_pull_ctl_enable_tbl[] = {
 310         RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
 311         RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
 312         RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
 313         RTSX_REG_PAIR(CARD_PULL_CTL4, 0xAA),
 314         0,
 315 };
 316
 317 /* SD Pull Control Disable:
 318  *     SD_DAT[3:0] ==> pull down
 319  *     SD_CD       ==> pull up
 320  *     SD_WP       ==> pull down
 321  *     SD_CMD      ==> pull down
 322  *     SD_CLK      ==> pull down
 323  */
 324 static const u32 rts5249_sd_pull_ctl_disable_tbl[] = {
 325         RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
 326         RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
 327         RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
 328         RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
 329         0,
 330 };
 331
 332 /* MS Pull Control Enable:
 333  *     MS CD       ==> pull up
 334  *     others      ==> pull down
 335  */
 336 static const u32 rts5249_ms_pull_ctl_enable_tbl[] = {
 337         RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
 338         RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
 339         RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
 340         0,
 341 };
 342
 343 /* MS Pull Control Disable:
 344  *     MS CD       ==> pull up
 345  *     others      ==> pull down
 346  */
 347 static const u32 rts5249_ms_pull_ctl_disable_tbl[] = {
 348         RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
 349         RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
 350         RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
 351         0,
 352 };
 353
 354 void rts5249_init_params(struct rtsx_pcr *pcr)
 355 {
 356         pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
 357         pcr->num_slots = 2;
 358         pcr->ops = &rts5249_pcr_ops;
 359
 360         pcr->flags = 0;
 361         pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
 362         pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
 363         pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
 364         pcr->aspm_en = ASPM_L1_EN;
 365         pcr->tx_initial_phase = SET_CLOCK_PHASE(1, 29, 16);
 366         pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);
 367
 368         pcr->ic_version = rts5249_get_ic_version(pcr);
 369         pcr->sd_pull_ctl_enable_tbl = rts5249_sd_pull_ctl_enable_tbl;
 370         pcr->sd_pull_ctl_disable_tbl = rts5249_sd_pull_ctl_disable_tbl;
 371         pcr->ms_pull_ctl_enable_tbl = rts5249_ms_pull_ctl_enable_tbl;
 372         pcr->ms_pull_ctl_disable_tbl = rts5249_ms_pull_ctl_disable_tbl;
 373
 374         pcr->reg_pm_ctrl3 = PM_CTRL3;
 375 }
 376
 377 static int rts524a_write_phy(struct rtsx_pcr *pcr, u8 addr, u16 val)
 378 {
 379         addr = addr & 0x80 ? (addr & 0x7F) | 0x40 : addr;
 380
 381         return __rtsx_pci_write_phy_register(pcr, addr, val);
 382 }
 383
 384 static int rts524a_read_phy(struct rtsx_pcr *pcr, u8 addr, u16 *val)
 385 {
 386         addr = addr & 0x80 ? (addr & 0x7F) | 0x40 : addr;
 387
 388         return __rtsx_pci_read_phy_register(pcr, addr, val);
 389 }
 390
 391 static int rts524a_optimize_phy(struct rtsx_pcr *pcr)
 392 {
 393         int err;
 394
 395         err = rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3,
 396                 D3_DELINK_MODE_EN, 0x00);
 397         if (err < 0)
 398                 return err;
 399
 400         rtsx_pci_write_phy_register(pcr, PHY_PCR,
 401                 PHY_PCR_FORCE_CODE | PHY_PCR_OOBS_CALI_50 |
 402                 PHY_PCR_OOBS_VCM_08 | PHY_PCR_OOBS_SEN_90 | PHY_PCR_RSSI_EN);
 403         rtsx_pci_write_phy_register(pcr, PHY_SSCCR3,
 404                 PHY_SSCCR3_STEP_IN | PHY_SSCCR3_CHECK_DELAY);
 405
 406         if (is_version(pcr, 0x524A, IC_VER_A)) {
 407                 rtsx_pci_write_phy_register(pcr, PHY_SSCCR3,
 408                         PHY_SSCCR3_STEP_IN | PHY_SSCCR3_CHECK_DELAY);
 409                 rtsx_pci_write_phy_register(pcr, PHY_SSCCR2,
 410                         PHY_SSCCR2_PLL_NCODE | PHY_SSCCR2_TIME0 |
 411                         PHY_SSCCR2_TIME2_WIDTH);
 412                 rtsx_pci_write_phy_register(pcr, PHY_ANA1A,
 413                         PHY_ANA1A_TXR_LOOPBACK | PHY_ANA1A_RXT_BIST |
 414                         PHY_ANA1A_TXR_BIST | PHY_ANA1A_REV);
 415                 rtsx_pci_write_phy_register(pcr, PHY_ANA1D,
 416                         PHY_ANA1D_DEBUG_ADDR);
 417                 rtsx_pci_write_phy_register(pcr, PHY_DIG1E,
 418                         PHY_DIG1E_REV | PHY_DIG1E_D0_X_D1 |
 419                         PHY_DIG1E_RX_ON_HOST | PHY_DIG1E_RCLK_REF_HOST |
 420                         PHY_DIG1E_RCLK_TX_EN_KEEP |
 421                         PHY_DIG1E_RCLK_TX_TERM_KEEP |
 422                         PHY_DIG1E_RCLK_RX_EIDLE_ON | PHY_DIG1E_TX_TERM_KEEP |
 423                         PHY_DIG1E_RX_TERM_KEEP | PHY_DIG1E_TX_EN_KEEP |
 424                         PHY_DIG1E_RX_EN_KEEP);
 425         }
 426
 427         rtsx_pci_write_phy_register(pcr, PHY_ANA08,
 428                 PHY_ANA08_RX_EQ_DCGAIN | PHY_ANA08_SEL_RX_EN |
 429                 PHY_ANA08_RX_EQ_VAL | PHY_ANA08_SCP | PHY_ANA08_SEL_IPI);
 430
 431         return 0;
 432 }
 433
 434 static int rts524a_extra_init_hw(struct rtsx_pcr *pcr)
 435 {
 436         rts5249_extra_init_hw(pcr);
 437
 438         rtsx_pci_write_register(pcr, FUNC_FORCE_CTL,
 439                 FORCE_ASPM_L1_EN, FORCE_ASPM_L1_EN);
 440         rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0);
 441         rtsx_pci_write_register(pcr, LDO_VCC_CFG1, LDO_VCC_LMT_EN,
 442                 LDO_VCC_LMT_EN);
 443         rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL);
 444         if (is_version(pcr, 0x524A, IC_VER_A)) {
 445                 rtsx_pci_write_register(pcr, LDO_DV18_CFG,
 446                         LDO_DV18_SR_MASK, LDO_DV18_SR_DF);
 447                 rtsx_pci_write_register(pcr, LDO_VCC_CFG1,
 448                         LDO_VCC_REF_TUNE_MASK, LDO_VCC_REF_1V2);
 449                 rtsx_pci_write_register(pcr, LDO_VIO_CFG,
 450                         LDO_VIO_REF_TUNE_MASK, LDO_VIO_REF_1V2);
 451                 rtsx_pci_write_register(pcr, LDO_VIO_CFG,
 452                         LDO_VIO_SR_MASK, LDO_VIO_SR_DF);
 453                 rtsx_pci_write_register(pcr, LDO_DV12S_CFG,
 454                         LDO_REF12_TUNE_MASK, LDO_REF12_TUNE_DF);
 455                 rtsx_pci_write_register(pcr, SD40_LDO_CTL1,
 456                         SD40_VIO_TUNE_MASK, SD40_VIO_TUNE_1V7);
 457         }
 458
 459         return 0;
 460 }
 461
 462 static const struct pcr_ops rts524a_pcr_ops = {
 463         .write_phy = rts524a_write_phy,
 464         .read_phy = rts524a_read_phy,
 465         .fetch_vendor_settings = rtsx_base_fetch_vendor_settings,
 466         .extra_init_hw = rts524a_extra_init_hw,
 467         .optimize_phy = rts524a_optimize_phy,
 468         .turn_on_led = rtsx_base_turn_on_led,
 469         .turn_off_led = rtsx_base_turn_off_led,
 470         .enable_auto_blink = rtsx_base_enable_auto_blink,
 471         .disable_auto_blink = rtsx_base_disable_auto_blink,
 472         .card_power_on = rtsx_base_card_power_on,
 473         .card_power_off = rtsx_base_card_power_off,
 474         .switch_output_voltage = rtsx_base_switch_output_voltage,
 475         .force_power_down = rtsx_base_force_power_down,
 476 };
 477
 478 void rts524a_init_params(struct rtsx_pcr *pcr)
 479 {
 480         rts5249_init_params(pcr);
 481
 482         pcr->reg_pm_ctrl3 = RTS524A_PM_CTRL3;
 483         pcr->ops = &rts524a_pcr_ops;
 484 }
 485
 486 static int rts525a_card_power_on(struct rtsx_pcr *pcr, int card)
 487 {
 488         rtsx_pci_write_register(pcr, LDO_VCC_CFG1,
 489                 LDO_VCC_TUNE_MASK, LDO_VCC_3V3);
 490         return rtsx_base_card_power_on(pcr, card);
 491 }
 492
 493 static int rts525a_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
 494 {
 495         switch (voltage) {
 496         case OUTPUT_3V3:
 497                 rtsx_pci_write_register(pcr, LDO_CONFIG2,
 498                         LDO_D3318_MASK, LDO_D3318_33V);
 499                 rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8, 0);
 500                 break;
 501         case OUTPUT_1V8:
 502                 rtsx_pci_write_register(pcr, LDO_CONFIG2,
 503                         LDO_D3318_MASK, LDO_D3318_18V);
 504                 rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8,
 505                         SD_IO_USING_1V8);
 506                 break;
 507         default:
 508                 return -EINVAL;
 509         }
 510
 511         rtsx_pci_init_cmd(pcr);
 512         rts5249_fill_driving(pcr, voltage);
 513         return rtsx_pci_send_cmd(pcr, 100);
 514 }
 515
 516 static int rts525a_optimize_phy(struct rtsx_pcr *pcr)
 517 {
 518         int err;
 519
 520         err = rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3,
 521                 D3_DELINK_MODE_EN, 0x00);
 522         if (err < 0)
 523                 return err;
 524
 525         rtsx_pci_write_phy_register(pcr, _PHY_FLD0,
 526                 _PHY_FLD0_CLK_REQ_20C | _PHY_FLD0_RX_IDLE_EN |
 527                 _PHY_FLD0_BIT_ERR_RSTN | _PHY_FLD0_BER_COUNT |
 528                 _PHY_FLD0_BER_TIMER | _PHY_FLD0_CHECK_EN);
 529
 530         rtsx_pci_write_phy_register(pcr, _PHY_ANA03,
 531                 _PHY_ANA03_TIMER_MAX | _PHY_ANA03_OOBS_DEB_EN |
 532                 _PHY_CMU_DEBUG_EN);
 533
 534         if (is_version(pcr, 0x525A, IC_VER_A))
 535                 rtsx_pci_write_phy_register(pcr, _PHY_REV0,
 536                         _PHY_REV0_FILTER_OUT | _PHY_REV0_CDR_BYPASS_PFD |
 537                         _PHY_REV0_CDR_RX_IDLE_BYPASS);
 538
 539         return 0;
 540 }
 541
 542 static int rts525a_extra_init_hw(struct rtsx_pcr *pcr)
 543 {
 544         rts5249_extra_init_hw(pcr);
 545
 546         rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL);
 547         if (is_version(pcr, 0x525A, IC_VER_A)) {
 548                 rtsx_pci_write_register(pcr, L1SUB_CONFIG2,
 549                         L1SUB_AUTO_CFG, L1SUB_AUTO_CFG);
 550                 rtsx_pci_write_register(pcr, RREF_CFG,
 551                         RREF_VBGSEL_MASK, RREF_VBGSEL_1V25);
 552                 rtsx_pci_write_register(pcr, LDO_VIO_CFG,
 553                         LDO_VIO_TUNE_MASK, LDO_VIO_1V7);
 554                 rtsx_pci_write_register(pcr, LDO_DV12S_CFG,
 555                         LDO_D12_TUNE_MASK, LDO_D12_TUNE_DF);
 556                 rtsx_pci_write_register(pcr, LDO_AV12S_CFG,
 557                         LDO_AV12S_TUNE_MASK, LDO_AV12S_TUNE_DF);
 558                 rtsx_pci_write_register(pcr, LDO_VCC_CFG0,
 559                         LDO_VCC_LMTVTH_MASK, LDO_VCC_LMTVTH_2A);
 560                 rtsx_pci_write_register(pcr, OOBS_CONFIG,
 561                         OOBS_AUTOK_DIS | OOBS_VAL_MASK, 0x89);
 562         }
 563
 564         return 0;
 565 }
 566
 567 static const struct pcr_ops rts525a_pcr_ops = {
 568         .fetch_vendor_settings = rtsx_base_fetch_vendor_settings,
 569         .extra_init_hw = rts525a_extra_init_hw,
 570         .optimize_phy = rts525a_optimize_phy,
 571         .turn_on_led = rtsx_base_turn_on_led,
 572         .turn_off_led = rtsx_base_turn_off_led,
 573         .enable_auto_blink = rtsx_base_enable_auto_blink,
 574         .disable_auto_blink = rtsx_base_disable_auto_blink,
 575         .card_power_on = rts525a_card_power_on,
 576         .card_power_off = rtsx_base_card_power_off,
 577         .switch_output_voltage = rts525a_switch_output_voltage,
 578         .force_power_down = rtsx_base_force_power_down,
 579 };
 580
 581 void rts525a_init_params(struct rtsx_pcr *pcr)
 582 {
 583         rts5249_init_params(pcr);
 584
 585         pcr->reg_pm_ctrl3 = RTS524A_PM_CTRL3;
 586         pcr->ops = &rts525a_pcr_ops;
 587 }
 588