GNU Linux-libre 4.4.289-gnu1
[releases.git] / drivers / mfd / rc5t583-irq.c
1 /*
2  * Interrupt driver for RICOH583 power management chip.
3  *
4  * Copyright (c) 2011-2012, NVIDIA CORPORATION.  All rights reserved.
5  * Author: Laxman dewangan <ldewangan@nvidia.com>
6  *
7  * based on code
8  *      Copyright (C) 2011 RICOH COMPANY,LTD
9  *
10  * This program is free software; you can redistribute it and/or modify it
11  * under the terms and conditions of the GNU General Public License,
12  * version 2, as published by the Free Software Foundation.
13  *
14  * This program is distributed in the hope it will be useful, but WITHOUT
15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
17  * more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
21  *
22  */
23 #include <linux/interrupt.h>
24 #include <linux/irq.h>
25 #include <linux/i2c.h>
26 #include <linux/mfd/rc5t583.h>
27
28 enum int_type {
29         SYS_INT  = 0x1,
30         DCDC_INT = 0x2,
31         RTC_INT  = 0x4,
32         ADC_INT  = 0x8,
33         GPIO_INT = 0x10,
34 };
35
36 static int gpedge_add[] = {
37         RC5T583_GPIO_GPEDGE2,
38         RC5T583_GPIO_GPEDGE2
39 };
40
41 static int irq_en_add[] = {
42         RC5T583_INT_EN_SYS1,
43         RC5T583_INT_EN_SYS2,
44         RC5T583_INT_EN_DCDC,
45         RC5T583_INT_EN_RTC,
46         RC5T583_INT_EN_ADC1,
47         RC5T583_INT_EN_ADC2,
48         RC5T583_INT_EN_ADC3,
49         RC5T583_GPIO_EN_INT
50 };
51
52 static int irq_mon_add[] = {
53         RC5T583_INT_MON_SYS1,
54         RC5T583_INT_MON_SYS2,
55         RC5T583_INT_MON_DCDC,
56         RC5T583_INT_MON_RTC,
57         RC5T583_INT_IR_ADCL,
58         RC5T583_INT_IR_ADCH,
59         RC5T583_INT_IR_ADCEND,
60         RC5T583_INT_IR_GPIOF,
61         RC5T583_INT_IR_GPIOR
62 };
63
64 static int irq_clr_add[] = {
65         RC5T583_INT_IR_SYS1,
66         RC5T583_INT_IR_SYS2,
67         RC5T583_INT_IR_DCDC,
68         RC5T583_INT_IR_RTC,
69         RC5T583_INT_IR_ADCL,
70         RC5T583_INT_IR_ADCH,
71         RC5T583_INT_IR_ADCEND,
72         RC5T583_INT_IR_GPIOF,
73         RC5T583_INT_IR_GPIOR
74 };
75
76 static int main_int_type[] = {
77         SYS_INT,
78         SYS_INT,
79         DCDC_INT,
80         RTC_INT,
81         ADC_INT,
82         ADC_INT,
83         ADC_INT,
84         GPIO_INT,
85         GPIO_INT,
86 };
87
88 struct rc5t583_irq_data {
89         u8      int_type;
90         u8      master_bit;
91         u8      int_en_bit;
92         u8      mask_reg_index;
93         int     grp_index;
94 };
95
96 #define RC5T583_IRQ(_int_type, _master_bit, _grp_index, \
97                         _int_bit, _mask_ind)            \
98         {                                               \
99                 .int_type       = _int_type,            \
100                 .master_bit     = _master_bit,          \
101                 .grp_index      = _grp_index,           \
102                 .int_en_bit     = _int_bit,             \
103                 .mask_reg_index = _mask_ind,            \
104         }
105
106 static const struct rc5t583_irq_data rc5t583_irqs[RC5T583_MAX_IRQS] = {
107         [RC5T583_IRQ_ONKEY]             = RC5T583_IRQ(SYS_INT,  0, 0, 0, 0),
108         [RC5T583_IRQ_ACOK]              = RC5T583_IRQ(SYS_INT,  0, 1, 1, 0),
109         [RC5T583_IRQ_LIDOPEN]           = RC5T583_IRQ(SYS_INT,  0, 2, 2, 0),
110         [RC5T583_IRQ_PREOT]             = RC5T583_IRQ(SYS_INT,  0, 3, 3, 0),
111         [RC5T583_IRQ_CLKSTP]            = RC5T583_IRQ(SYS_INT,  0, 4, 4, 0),
112         [RC5T583_IRQ_ONKEY_OFF]         = RC5T583_IRQ(SYS_INT,  0, 5, 5, 0),
113         [RC5T583_IRQ_WD]                = RC5T583_IRQ(SYS_INT,  0, 7, 7, 0),
114         [RC5T583_IRQ_EN_PWRREQ1]        = RC5T583_IRQ(SYS_INT,  0, 8, 0, 1),
115         [RC5T583_IRQ_EN_PWRREQ2]        = RC5T583_IRQ(SYS_INT,  0, 9, 1, 1),
116         [RC5T583_IRQ_PRE_VINDET]        = RC5T583_IRQ(SYS_INT,  0, 10, 2, 1),
117
118         [RC5T583_IRQ_DC0LIM]            = RC5T583_IRQ(DCDC_INT, 1, 0, 0, 2),
119         [RC5T583_IRQ_DC1LIM]            = RC5T583_IRQ(DCDC_INT, 1, 1, 1, 2),
120         [RC5T583_IRQ_DC2LIM]            = RC5T583_IRQ(DCDC_INT, 1, 2, 2, 2),
121         [RC5T583_IRQ_DC3LIM]            = RC5T583_IRQ(DCDC_INT, 1, 3, 3, 2),
122
123         [RC5T583_IRQ_CTC]               = RC5T583_IRQ(RTC_INT,  2, 0, 0, 3),
124         [RC5T583_IRQ_YALE]              = RC5T583_IRQ(RTC_INT,  2, 5, 5, 3),
125         [RC5T583_IRQ_DALE]              = RC5T583_IRQ(RTC_INT,  2, 6, 6, 3),
126         [RC5T583_IRQ_WALE]              = RC5T583_IRQ(RTC_INT,  2, 7, 7, 3),
127
128         [RC5T583_IRQ_AIN1L]             = RC5T583_IRQ(ADC_INT,  3, 0, 0, 4),
129         [RC5T583_IRQ_AIN2L]             = RC5T583_IRQ(ADC_INT,  3, 1, 1, 4),
130         [RC5T583_IRQ_AIN3L]             = RC5T583_IRQ(ADC_INT,  3, 2, 2, 4),
131         [RC5T583_IRQ_VBATL]             = RC5T583_IRQ(ADC_INT,  3, 3, 3, 4),
132         [RC5T583_IRQ_VIN3L]             = RC5T583_IRQ(ADC_INT,  3, 4, 4, 4),
133         [RC5T583_IRQ_VIN8L]             = RC5T583_IRQ(ADC_INT,  3, 5, 5, 4),
134         [RC5T583_IRQ_AIN1H]             = RC5T583_IRQ(ADC_INT,  3, 6, 0, 5),
135         [RC5T583_IRQ_AIN2H]             = RC5T583_IRQ(ADC_INT,  3, 7, 1, 5),
136         [RC5T583_IRQ_AIN3H]             = RC5T583_IRQ(ADC_INT,  3, 8, 2, 5),
137         [RC5T583_IRQ_VBATH]             = RC5T583_IRQ(ADC_INT,  3, 9, 3, 5),
138         [RC5T583_IRQ_VIN3H]             = RC5T583_IRQ(ADC_INT,  3, 10, 4, 5),
139         [RC5T583_IRQ_VIN8H]             = RC5T583_IRQ(ADC_INT,  3, 11, 5, 5),
140         [RC5T583_IRQ_ADCEND]            = RC5T583_IRQ(ADC_INT,  3, 12, 0, 6),
141
142         [RC5T583_IRQ_GPIO0]             = RC5T583_IRQ(GPIO_INT, 4, 0, 0, 7),
143         [RC5T583_IRQ_GPIO1]             = RC5T583_IRQ(GPIO_INT, 4, 1, 1, 7),
144         [RC5T583_IRQ_GPIO2]             = RC5T583_IRQ(GPIO_INT, 4, 2, 2, 7),
145         [RC5T583_IRQ_GPIO3]             = RC5T583_IRQ(GPIO_INT, 4, 3, 3, 7),
146         [RC5T583_IRQ_GPIO4]             = RC5T583_IRQ(GPIO_INT, 4, 4, 4, 7),
147         [RC5T583_IRQ_GPIO5]             = RC5T583_IRQ(GPIO_INT, 4, 5, 5, 7),
148         [RC5T583_IRQ_GPIO6]             = RC5T583_IRQ(GPIO_INT, 4, 6, 6, 7),
149         [RC5T583_IRQ_GPIO7]             = RC5T583_IRQ(GPIO_INT, 4, 7, 7, 7),
150 };
151
152 static void rc5t583_irq_lock(struct irq_data *irq_data)
153 {
154         struct rc5t583 *rc5t583 = irq_data_get_irq_chip_data(irq_data);
155         mutex_lock(&rc5t583->irq_lock);
156 }
157
158 static void rc5t583_irq_unmask(struct irq_data *irq_data)
159 {
160         struct rc5t583 *rc5t583 = irq_data_get_irq_chip_data(irq_data);
161         unsigned int __irq = irq_data->irq - rc5t583->irq_base;
162         const struct rc5t583_irq_data *data = &rc5t583_irqs[__irq];
163
164         rc5t583->group_irq_en[data->grp_index] |= 1 << data->grp_index;
165         rc5t583->intc_inten_reg |= 1 << data->master_bit;
166         rc5t583->irq_en_reg[data->mask_reg_index] |= 1 << data->int_en_bit;
167 }
168
169 static void rc5t583_irq_mask(struct irq_data *irq_data)
170 {
171         struct rc5t583 *rc5t583 = irq_data_get_irq_chip_data(irq_data);
172         unsigned int __irq = irq_data->irq - rc5t583->irq_base;
173         const struct rc5t583_irq_data *data = &rc5t583_irqs[__irq];
174
175         rc5t583->group_irq_en[data->grp_index] &= ~(1 << data->grp_index);
176         if (!rc5t583->group_irq_en[data->grp_index])
177                 rc5t583->intc_inten_reg &= ~(1 << data->master_bit);
178
179         rc5t583->irq_en_reg[data->mask_reg_index] &= ~(1 << data->int_en_bit);
180 }
181
182 static int rc5t583_irq_set_type(struct irq_data *irq_data, unsigned int type)
183 {
184         struct rc5t583 *rc5t583 = irq_data_get_irq_chip_data(irq_data);
185         unsigned int __irq = irq_data->irq - rc5t583->irq_base;
186         const struct rc5t583_irq_data *data = &rc5t583_irqs[__irq];
187         int val = 0;
188         int gpedge_index;
189         int gpedge_bit_pos;
190
191         /* Supporting only trigger level inetrrupt */
192         if ((data->int_type & GPIO_INT) && (type & IRQ_TYPE_EDGE_BOTH)) {
193                 gpedge_index = data->int_en_bit / 4;
194                 gpedge_bit_pos = data->int_en_bit % 4;
195
196                 if (type & IRQ_TYPE_EDGE_FALLING)
197                         val |= 0x2;
198
199                 if (type & IRQ_TYPE_EDGE_RISING)
200                         val |= 0x1;
201
202                 rc5t583->gpedge_reg[gpedge_index] &= ~(3 << gpedge_bit_pos);
203                 rc5t583->gpedge_reg[gpedge_index] |= (val << gpedge_bit_pos);
204                 rc5t583_irq_unmask(irq_data);
205                 return 0;
206         }
207         return -EINVAL;
208 }
209
210 static void rc5t583_irq_sync_unlock(struct irq_data *irq_data)
211 {
212         struct rc5t583 *rc5t583 = irq_data_get_irq_chip_data(irq_data);
213         int i;
214         int ret;
215
216         for (i = 0; i < ARRAY_SIZE(rc5t583->gpedge_reg); i++) {
217                 ret = rc5t583_write(rc5t583->dev, gpedge_add[i],
218                                 rc5t583->gpedge_reg[i]);
219                 if (ret < 0)
220                         dev_warn(rc5t583->dev,
221                                 "Error in writing reg 0x%02x error: %d\n",
222                                 gpedge_add[i], ret);
223         }
224
225         for (i = 0; i < ARRAY_SIZE(rc5t583->irq_en_reg); i++) {
226                 ret = rc5t583_write(rc5t583->dev, irq_en_add[i],
227                                         rc5t583->irq_en_reg[i]);
228                 if (ret < 0)
229                         dev_warn(rc5t583->dev,
230                                 "Error in writing reg 0x%02x error: %d\n",
231                                 irq_en_add[i], ret);
232         }
233
234         ret = rc5t583_write(rc5t583->dev, RC5T583_INTC_INTEN,
235                                 rc5t583->intc_inten_reg);
236         if (ret < 0)
237                 dev_warn(rc5t583->dev,
238                         "Error in writing reg 0x%02x error: %d\n",
239                         RC5T583_INTC_INTEN, ret);
240
241         mutex_unlock(&rc5t583->irq_lock);
242 }
243 #ifdef CONFIG_PM_SLEEP
244 static int rc5t583_irq_set_wake(struct irq_data *irq_data, unsigned int on)
245 {
246         struct rc5t583 *rc5t583 = irq_data_get_irq_chip_data(irq_data);
247         return irq_set_irq_wake(rc5t583->chip_irq, on);
248 }
249 #else
250 #define rc5t583_irq_set_wake NULL
251 #endif
252
253 static irqreturn_t rc5t583_irq(int irq, void *data)
254 {
255         struct rc5t583 *rc5t583 = data;
256         uint8_t int_sts[RC5T583_MAX_INTERRUPT_MASK_REGS];
257         uint8_t master_int = 0;
258         int i;
259         int ret;
260         unsigned int rtc_int_sts = 0;
261
262         /* Clear the status */
263         for (i = 0; i < RC5T583_MAX_INTERRUPT_MASK_REGS; i++)
264                 int_sts[i] = 0;
265
266         ret  = rc5t583_read(rc5t583->dev, RC5T583_INTC_INTMON, &master_int);
267         if (ret < 0) {
268                 dev_err(rc5t583->dev,
269                         "Error in reading reg 0x%02x error: %d\n",
270                         RC5T583_INTC_INTMON, ret);
271                 return IRQ_HANDLED;
272         }
273
274         for (i = 0; i < RC5T583_MAX_INTERRUPT_MASK_REGS; ++i) {
275                 if (!(master_int & main_int_type[i]))
276                         continue;
277
278                 ret = rc5t583_read(rc5t583->dev, irq_mon_add[i], &int_sts[i]);
279                 if (ret < 0) {
280                         dev_warn(rc5t583->dev,
281                                 "Error in reading reg 0x%02x error: %d\n",
282                                 irq_mon_add[i], ret);
283                         int_sts[i] = 0;
284                         continue;
285                 }
286
287                 if (main_int_type[i] & RTC_INT) {
288                         rtc_int_sts = 0;
289                         if (int_sts[i] & 0x1)
290                                 rtc_int_sts |= BIT(6);
291                         if (int_sts[i] & 0x2)
292                                 rtc_int_sts |= BIT(7);
293                         if (int_sts[i] & 0x4)
294                                 rtc_int_sts |= BIT(0);
295                         if (int_sts[i] & 0x8)
296                                 rtc_int_sts |= BIT(5);
297                 }
298
299                 ret = rc5t583_write(rc5t583->dev, irq_clr_add[i],
300                                 ~int_sts[i]);
301                 if (ret < 0)
302                         dev_warn(rc5t583->dev,
303                                 "Error in reading reg 0x%02x error: %d\n",
304                                 irq_clr_add[i], ret);
305
306                 if (main_int_type[i] & RTC_INT)
307                         int_sts[i] = rtc_int_sts;
308         }
309
310         /* Merge gpio interrupts for rising and falling case*/
311         int_sts[7] |= int_sts[8];
312
313         /* Call interrupt handler if enabled */
314         for (i = 0; i < RC5T583_MAX_IRQS; ++i) {
315                 const struct rc5t583_irq_data *data = &rc5t583_irqs[i];
316                 if ((int_sts[data->mask_reg_index] & (1 << data->int_en_bit)) &&
317                         (rc5t583->group_irq_en[data->master_bit] &
318                                         (1 << data->grp_index)))
319                         handle_nested_irq(rc5t583->irq_base + i);
320         }
321
322         return IRQ_HANDLED;
323 }
324
325 static struct irq_chip rc5t583_irq_chip = {
326         .name = "rc5t583-irq",
327         .irq_mask = rc5t583_irq_mask,
328         .irq_unmask = rc5t583_irq_unmask,
329         .irq_bus_lock = rc5t583_irq_lock,
330         .irq_bus_sync_unlock = rc5t583_irq_sync_unlock,
331         .irq_set_type = rc5t583_irq_set_type,
332         .irq_set_wake = rc5t583_irq_set_wake,
333 };
334
335 int rc5t583_irq_init(struct rc5t583 *rc5t583, int irq, int irq_base)
336 {
337         int i, ret;
338
339         if (!irq_base) {
340                 dev_warn(rc5t583->dev, "No interrupt support on IRQ base\n");
341                 return -EINVAL;
342         }
343
344         mutex_init(&rc5t583->irq_lock);
345
346         /* Initailize all int register to 0 */
347         for (i = 0; i < RC5T583_MAX_INTERRUPT_EN_REGS; i++)  {
348                 ret = rc5t583_write(rc5t583->dev, irq_en_add[i],
349                                 rc5t583->irq_en_reg[i]);
350                 if (ret < 0)
351                         dev_warn(rc5t583->dev,
352                                 "Error in writing reg 0x%02x error: %d\n",
353                                 irq_en_add[i], ret);
354         }
355
356         for (i = 0; i < RC5T583_MAX_GPEDGE_REG; i++)  {
357                 ret = rc5t583_write(rc5t583->dev, gpedge_add[i],
358                                 rc5t583->gpedge_reg[i]);
359                 if (ret < 0)
360                         dev_warn(rc5t583->dev,
361                                 "Error in writing reg 0x%02x error: %d\n",
362                                 gpedge_add[i], ret);
363         }
364
365         ret = rc5t583_write(rc5t583->dev, RC5T583_INTC_INTEN, 0x0);
366         if (ret < 0)
367                 dev_warn(rc5t583->dev,
368                         "Error in writing reg 0x%02x error: %d\n",
369                         RC5T583_INTC_INTEN, ret);
370
371         /* Clear all interrupts in case they woke up active. */
372         for (i = 0; i < RC5T583_MAX_INTERRUPT_MASK_REGS; i++)  {
373                 ret = rc5t583_write(rc5t583->dev, irq_clr_add[i], 0);
374                 if (ret < 0)
375                         dev_warn(rc5t583->dev,
376                                 "Error in writing reg 0x%02x error: %d\n",
377                                 irq_clr_add[i], ret);
378         }
379
380         rc5t583->irq_base = irq_base;
381         rc5t583->chip_irq = irq;
382
383         for (i = 0; i < RC5T583_MAX_IRQS; i++) {
384                 int __irq = i + rc5t583->irq_base;
385                 irq_set_chip_data(__irq, rc5t583);
386                 irq_set_chip_and_handler(__irq, &rc5t583_irq_chip,
387                                          handle_simple_irq);
388                 irq_set_nested_thread(__irq, 1);
389                 irq_clear_status_flags(__irq, IRQ_NOREQUEST);
390         }
391
392         ret = request_threaded_irq(irq, NULL, rc5t583_irq, IRQF_ONESHOT,
393                                 "rc5t583", rc5t583);
394         if (ret < 0)
395                 dev_err(rc5t583->dev,
396                         "Error in registering interrupt error: %d\n", ret);
397         return ret;
398 }
399
400 int rc5t583_irq_exit(struct rc5t583 *rc5t583)
401 {
402         if (rc5t583->chip_irq)
403                 free_irq(rc5t583->chip_irq, rc5t583);
404         return 0;
405 }