drivers/mfd/lpc_ich.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  *  lpc_ich.c - LPC interface for Intel ICH
   4  *
   5  *  LPC bridge function of the Intel ICH contains many other
   6  *  functional units, such as Interrupt controllers, Timers,
   7  *  Power Management, System Management, GPIO, RTC, and LPC
   8  *  Configuration Registers.
   9  *
  10  *  This driver is derived from lpc_sch.
  11  *
  12  *  Copyright (c) 2017, 2021-2022 Intel Corporation
  13  *  Copyright (c) 2011 Extreme Engineering Solution, Inc.
  14  *  Author: Aaron Sierra <asierra@xes-inc.com>
  15  *
  16  *  This driver supports the following I/O Controller hubs:
  17  *      (See the intel documentation on http://developer.intel.com.)
  18  *      document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO)
  19  *      document number 290687-002, 298242-027: 82801BA (ICH2)
  20  *      document number 290733-003, 290739-013: 82801CA (ICH3-S)
  21  *      document number 290716-001, 290718-007: 82801CAM (ICH3-M)
  22  *      document number 290744-001, 290745-025: 82801DB (ICH4)
  23  *      document number 252337-001, 252663-008: 82801DBM (ICH4-M)
  24  *      document number 273599-001, 273645-002: 82801E (C-ICH)
  25  *      document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R)
  26  *      document number 300641-004, 300884-013: 6300ESB
  27  *      document number 301473-002, 301474-026: 82801F (ICH6)
  28  *      document number 313082-001, 313075-006: 631xESB, 632xESB
  29  *      document number 307013-003, 307014-024: 82801G (ICH7)
  30  *      document number 322896-001, 322897-001: NM10
  31  *      document number 313056-003, 313057-017: 82801H (ICH8)
  32  *      document number 316972-004, 316973-012: 82801I (ICH9)
  33  *      document number 319973-002, 319974-002: 82801J (ICH10)
  34  *      document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH)
  35  *      document number 320066-003, 320257-008: EP80597 (IICH)
  36  *      document number 324645-001, 324646-001: Cougar Point (CPT)
  37  */
  38
  39 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  40
  41 #include <linux/kernel.h>
  42 #include <linux/module.h>
  43 #include <linux/errno.h>
  44 #include <linux/acpi.h>
  45 #include <linux/pci.h>
  46 #include <linux/pinctrl/pinctrl.h>
  47 #include <linux/mfd/core.h>
  48 #include <linux/mfd/lpc_ich.h>
  49 #include <linux/platform_data/itco_wdt.h>
  50 #include <linux/platform_data/x86/p2sb.h>
  51
  52 #define ACPIBASE                0x40
  53 #define ACPIBASE_GPE_OFF        0x28
  54 #define ACPIBASE_GPE_END        0x2f
  55 #define ACPIBASE_SMI_OFF        0x30
  56 #define ACPIBASE_SMI_END        0x33
  57 #define ACPIBASE_PMC_OFF        0x08
  58 #define ACPIBASE_PMC_END        0x0c
  59 #define ACPIBASE_TCO_OFF        0x60
  60 #define ACPIBASE_TCO_END        0x7f
  61 #define ACPICTRL_PMCBASE        0x44
  62
  63 #define ACPIBASE_GCS_OFF        0x3410
  64 #define ACPIBASE_GCS_END        0x3414
  65
  66 #define SPIBASE_BYT             0x54
  67 #define SPIBASE_BYT_SZ          512
  68 #define SPIBASE_BYT_EN          BIT(1)
  69 #define BYT_BCR                 0xfc
  70 #define BYT_BCR_WPD             BIT(0)
  71
  72 #define SPIBASE_LPT             0x3800
  73 #define SPIBASE_LPT_SZ          512
  74 #define BCR                     0xdc
  75 #define BCR_WPD                 BIT(0)
  76
  77 #define GPIOBASE_ICH0           0x58
  78 #define GPIOCTRL_ICH0           0x5C
  79 #define GPIOBASE_ICH6           0x48
  80 #define GPIOCTRL_ICH6           0x4C
  81
  82 #define RCBABASE                0xf0
  83
  84 #define wdt_io_res(i) wdt_res(0, i)
  85 #define wdt_mem_res(i) wdt_res(ICH_RES_MEM_OFF, i)
  86 #define wdt_res(b, i) (&wdt_ich_res[(b) + (i)])
  87
  88 static struct resource wdt_ich_res[] = {
  89         /* ACPI - TCO */
  90         {
  91                 .flags = IORESOURCE_IO,
  92         },
  93         /* ACPI - SMI */
  94         {
  95                 .flags = IORESOURCE_IO,
  96         },
  97         /* GCS or PMC */
  98         {
  99                 .flags = IORESOURCE_MEM,
 100         },
 101 };
 102
 103 static struct resource gpio_ich_res[] = {
 104         /* GPIO */
 105         {
 106                 .flags = IORESOURCE_IO,
 107         },
 108         /* ACPI - GPE0 */
 109         {
 110                 .flags = IORESOURCE_IO,
 111         },
 112 };
 113
 114 static struct resource intel_spi_res[] = {
 115         {
 116                 .flags = IORESOURCE_MEM,
 117         }
 118 };
 119
 120 static struct mfd_cell lpc_ich_wdt_cell = {
 121         .name = "iTCO_wdt",
 122         .num_resources = ARRAY_SIZE(wdt_ich_res),
 123         .resources = wdt_ich_res,
 124         .ignore_resource_conflicts = true,
 125 };
 126
 127 static struct mfd_cell lpc_ich_gpio_cell = {
 128         .name = "gpio_ich",
 129         .num_resources = ARRAY_SIZE(gpio_ich_res),
 130         .resources = gpio_ich_res,
 131         .ignore_resource_conflicts = true,
 132 };
 133
 134 #define INTEL_GPIO_RESOURCE_SIZE        0x1000
 135
 136 struct lpc_ich_gpio_info {
 137         const char *hid;
 138         const struct mfd_cell *devices;
 139         size_t nr_devices;
 140         struct resource **resources;
 141         size_t nr_resources;
 142         const resource_size_t *offsets;
 143 };
 144
 145 #define APL_GPIO_NORTH          0
 146 #define APL_GPIO_NORTHWEST      1
 147 #define APL_GPIO_WEST           2
 148 #define APL_GPIO_SOUTHWEST      3
 149
 150 #define APL_GPIO_NR_DEVICES     4
 151 #define APL_GPIO_NR_RESOURCES   4
 152
 153 /* Offset data for Apollo Lake GPIO controllers */
 154 static const resource_size_t apl_gpio_offsets[APL_GPIO_NR_RESOURCES] = {
 155         [APL_GPIO_NORTH]        = 0xc50000,
 156         [APL_GPIO_NORTHWEST]    = 0xc40000,
 157         [APL_GPIO_WEST]         = 0xc70000,
 158         [APL_GPIO_SOUTHWEST]    = 0xc00000,
 159 };
 160
 161 #define APL_GPIO_IRQ                    14
 162
 163 static struct resource apl_gpio_resources[APL_GPIO_NR_DEVICES][2] = {
 164         [APL_GPIO_NORTH] = {
 165                 DEFINE_RES_MEM(0, 0),
 166                 DEFINE_RES_IRQ(APL_GPIO_IRQ),
 167         },
 168         [APL_GPIO_NORTHWEST] = {
 169                 DEFINE_RES_MEM(0, 0),
 170                 DEFINE_RES_IRQ(APL_GPIO_IRQ),
 171         },
 172         [APL_GPIO_WEST] = {
 173                 DEFINE_RES_MEM(0, 0),
 174                 DEFINE_RES_IRQ(APL_GPIO_IRQ),
 175         },
 176         [APL_GPIO_SOUTHWEST] = {
 177                 DEFINE_RES_MEM(0, 0),
 178                 DEFINE_RES_IRQ(APL_GPIO_IRQ),
 179         },
 180 };
 181
 182 static struct resource *apl_gpio_mem_resources[APL_GPIO_NR_RESOURCES] = {
 183         [APL_GPIO_NORTH] = &apl_gpio_resources[APL_GPIO_NORTH][0],
 184         [APL_GPIO_NORTHWEST] = &apl_gpio_resources[APL_GPIO_NORTHWEST][0],
 185         [APL_GPIO_WEST] = &apl_gpio_resources[APL_GPIO_WEST][0],
 186         [APL_GPIO_SOUTHWEST] = &apl_gpio_resources[APL_GPIO_SOUTHWEST][0],
 187 };
 188
 189 static const struct mfd_cell apl_gpio_devices[APL_GPIO_NR_DEVICES] = {
 190         [APL_GPIO_NORTH] = {
 191                 .name = "apollolake-pinctrl",
 192                 .id = APL_GPIO_NORTH,
 193                 .num_resources = ARRAY_SIZE(apl_gpio_resources[APL_GPIO_NORTH]),
 194                 .resources = apl_gpio_resources[APL_GPIO_NORTH],
 195                 .ignore_resource_conflicts = true,
 196         },
 197         [APL_GPIO_NORTHWEST] = {
 198                 .name = "apollolake-pinctrl",
 199                 .id = APL_GPIO_NORTHWEST,
 200                 .num_resources = ARRAY_SIZE(apl_gpio_resources[APL_GPIO_NORTHWEST]),
 201                 .resources = apl_gpio_resources[APL_GPIO_NORTHWEST],
 202                 .ignore_resource_conflicts = true,
 203         },
 204         [APL_GPIO_WEST] = {
 205                 .name = "apollolake-pinctrl",
 206                 .id = APL_GPIO_WEST,
 207                 .num_resources = ARRAY_SIZE(apl_gpio_resources[APL_GPIO_WEST]),
 208                 .resources = apl_gpio_resources[APL_GPIO_WEST],
 209                 .ignore_resource_conflicts = true,
 210         },
 211         [APL_GPIO_SOUTHWEST] = {
 212                 .name = "apollolake-pinctrl",
 213                 .id = APL_GPIO_SOUTHWEST,
 214                 .num_resources = ARRAY_SIZE(apl_gpio_resources[APL_GPIO_SOUTHWEST]),
 215                 .resources = apl_gpio_resources[APL_GPIO_SOUTHWEST],
 216                 .ignore_resource_conflicts = true,
 217         },
 218 };
 219
 220 static const struct lpc_ich_gpio_info apl_gpio_info = {
 221         .hid = "INT3452",
 222         .devices = apl_gpio_devices,
 223         .nr_devices = ARRAY_SIZE(apl_gpio_devices),
 224         .resources = apl_gpio_mem_resources,
 225         .nr_resources = ARRAY_SIZE(apl_gpio_mem_resources),
 226         .offsets = apl_gpio_offsets,
 227 };
 228
 229 #define DNV_GPIO_NORTH          0
 230 #define DNV_GPIO_SOUTH          1
 231
 232 #define DNV_GPIO_NR_DEVICES     1
 233 #define DNV_GPIO_NR_RESOURCES   2
 234
 235 /* Offset data for Denverton GPIO controllers */
 236 static const resource_size_t dnv_gpio_offsets[DNV_GPIO_NR_RESOURCES] = {
 237         [DNV_GPIO_NORTH]        = 0xc20000,
 238         [DNV_GPIO_SOUTH]        = 0xc50000,
 239 };
 240
 241 #define DNV_GPIO_IRQ                    14
 242
 243 static struct resource dnv_gpio_resources[DNV_GPIO_NR_RESOURCES + 1] = {
 244         [DNV_GPIO_NORTH] = DEFINE_RES_MEM(0, 0),
 245         [DNV_GPIO_SOUTH] = DEFINE_RES_MEM(0, 0),
 246         DEFINE_RES_IRQ(DNV_GPIO_IRQ),
 247 };
 248
 249 static struct resource *dnv_gpio_mem_resources[DNV_GPIO_NR_RESOURCES] = {
 250         [DNV_GPIO_NORTH] = &dnv_gpio_resources[DNV_GPIO_NORTH],
 251         [DNV_GPIO_SOUTH] = &dnv_gpio_resources[DNV_GPIO_SOUTH],
 252 };
 253
 254 static const struct mfd_cell dnv_gpio_devices[DNV_GPIO_NR_DEVICES] = {
 255         {
 256                 .name = "denverton-pinctrl",
 257                 .num_resources = ARRAY_SIZE(dnv_gpio_resources),
 258                 .resources = dnv_gpio_resources,
 259                 .ignore_resource_conflicts = true,
 260         },
 261 };
 262
 263 static const struct lpc_ich_gpio_info dnv_gpio_info = {
 264         .hid = "INTC3000",
 265         .devices = dnv_gpio_devices,
 266         .nr_devices = ARRAY_SIZE(dnv_gpio_devices),
 267         .resources = dnv_gpio_mem_resources,
 268         .nr_resources = ARRAY_SIZE(dnv_gpio_mem_resources),
 269         .offsets = dnv_gpio_offsets,
 270 };
 271
 272 static struct mfd_cell lpc_ich_spi_cell = {
 273         .name = "intel-spi",
 274         .num_resources = ARRAY_SIZE(intel_spi_res),
 275         .resources = intel_spi_res,
 276         .ignore_resource_conflicts = true,
 277 };
 278
 279 /* chipset related info */
 280 enum lpc_chipsets {
 281         LPC_ICH = 0,    /* ICH */
 282         LPC_ICH0,       /* ICH0 */
 283         LPC_ICH2,       /* ICH2 */
 284         LPC_ICH2M,      /* ICH2-M */
 285         LPC_ICH3,       /* ICH3-S */
 286         LPC_ICH3M,      /* ICH3-M */
 287         LPC_ICH4,       /* ICH4 */
 288         LPC_ICH4M,      /* ICH4-M */
 289         LPC_CICH,       /* C-ICH */
 290         LPC_ICH5,       /* ICH5 & ICH5R */
 291         LPC_6300ESB,    /* 6300ESB */
 292         LPC_ICH6,       /* ICH6 & ICH6R */
 293         LPC_ICH6M,      /* ICH6-M */
 294         LPC_ICH6W,      /* ICH6W & ICH6RW */
 295         LPC_631XESB,    /* 631xESB/632xESB */
 296         LPC_ICH7,       /* ICH7 & ICH7R */
 297         LPC_ICH7DH,     /* ICH7DH */
 298         LPC_ICH7M,      /* ICH7-M & ICH7-U */
 299         LPC_ICH7MDH,    /* ICH7-M DH */
 300         LPC_NM10,       /* NM10 */
 301         LPC_ICH8,       /* ICH8 & ICH8R */
 302         LPC_ICH8DH,     /* ICH8DH */
 303         LPC_ICH8DO,     /* ICH8DO */
 304         LPC_ICH8M,      /* ICH8M */
 305         LPC_ICH8ME,     /* ICH8M-E */
 306         LPC_ICH9,       /* ICH9 */
 307         LPC_ICH9R,      /* ICH9R */
 308         LPC_ICH9DH,     /* ICH9DH */
 309         LPC_ICH9DO,     /* ICH9DO */
 310         LPC_ICH9M,      /* ICH9M */
 311         LPC_ICH9ME,     /* ICH9M-E */
 312         LPC_ICH10,      /* ICH10 */
 313         LPC_ICH10R,     /* ICH10R */
 314         LPC_ICH10D,     /* ICH10D */
 315         LPC_ICH10DO,    /* ICH10DO */
 316         LPC_PCH,        /* PCH Desktop Full Featured */
 317         LPC_PCHM,       /* PCH Mobile Full Featured */
 318         LPC_P55,        /* P55 */
 319         LPC_PM55,       /* PM55 */
 320         LPC_H55,        /* H55 */
 321         LPC_QM57,       /* QM57 */
 322         LPC_H57,        /* H57 */
 323         LPC_HM55,       /* HM55 */
 324         LPC_Q57,        /* Q57 */
 325         LPC_HM57,       /* HM57 */
 326         LPC_PCHMSFF,    /* PCH Mobile SFF Full Featured */
 327         LPC_QS57,       /* QS57 */
 328         LPC_3400,       /* 3400 */
 329         LPC_3420,       /* 3420 */
 330         LPC_3450,       /* 3450 */
 331         LPC_EP80579,    /* EP80579 */
 332         LPC_CPT,        /* Cougar Point */
 333         LPC_CPTD,       /* Cougar Point Desktop */
 334         LPC_CPTM,       /* Cougar Point Mobile */
 335         LPC_PBG,        /* Patsburg */
 336         LPC_DH89XXCC,   /* DH89xxCC */
 337         LPC_PPT,        /* Panther Point */
 338         LPC_LPT,        /* Lynx Point */
 339         LPC_LPT_LP,     /* Lynx Point-LP */
 340         LPC_WBG,        /* Wellsburg */
 341         LPC_AVN,        /* Avoton SoC */
 342         LPC_BAYTRAIL,   /* Bay Trail SoC */
 343         LPC_COLETO,     /* Coleto Creek */
 344         LPC_WPT_LP,     /* Wildcat Point-LP */
 345         LPC_BRASWELL,   /* Braswell SoC */
 346         LPC_LEWISBURG,  /* Lewisburg */
 347         LPC_9S,         /* 9 Series */
 348         LPC_APL,        /* Apollo Lake SoC */
 349         LPC_DNV,        /* Denverton SoC */
 350         LPC_GLK,        /* Gemini Lake SoC */
 351         LPC_COUGARMOUNTAIN,/* Cougar Mountain SoC*/
 352 };
 353
 354 struct lpc_ich_priv {
 355         enum lpc_chipsets chipset;
 356
 357         int abase;              /* ACPI base */
 358         int actrl_pbase;        /* ACPI control or PMC base */
 359         int gbase;              /* GPIO base */
 360         int gctrl;              /* GPIO control */
 361
 362         int abase_save;         /* Cached ACPI base value */
 363         int actrl_pbase_save;           /* Cached ACPI control or PMC base value */
 364         int gctrl_save;         /* Cached GPIO control value */
 365 };
 366
 367 static struct lpc_ich_info lpc_chipset_info[] = {
 368         [LPC_ICH] = {
 369                 .name = "ICH",
 370                 .iTCO_version = 1,
 371         },
 372         [LPC_ICH0] = {
 373                 .name = "ICH0",
 374                 .iTCO_version = 1,
 375         },
 376         [LPC_ICH2] = {
 377                 .name = "ICH2",
 378                 .iTCO_version = 1,
 379         },
 380         [LPC_ICH2M] = {
 381                 .name = "ICH2-M",
 382                 .iTCO_version = 1,
 383         },
 384         [LPC_ICH3] = {
 385                 .name = "ICH3-S",
 386                 .iTCO_version = 1,
 387         },
 388         [LPC_ICH3M] = {
 389                 .name = "ICH3-M",
 390                 .iTCO_version = 1,
 391         },
 392         [LPC_ICH4] = {
 393                 .name = "ICH4",
 394                 .iTCO_version = 1,
 395         },
 396         [LPC_ICH4M] = {
 397                 .name = "ICH4-M",
 398                 .iTCO_version = 1,
 399         },
 400         [LPC_CICH] = {
 401                 .name = "C-ICH",
 402                 .iTCO_version = 1,
 403         },
 404         [LPC_ICH5] = {
 405                 .name = "ICH5 or ICH5R",
 406                 .iTCO_version = 1,
 407         },
 408         [LPC_6300ESB] = {
 409                 .name = "6300ESB",
 410                 .iTCO_version = 1,
 411         },
 412         [LPC_ICH6] = {
 413                 .name = "ICH6 or ICH6R",
 414                 .iTCO_version = 2,
 415                 .gpio_version = ICH_V6_GPIO,
 416         },
 417         [LPC_ICH6M] = {
 418                 .name = "ICH6-M",
 419                 .iTCO_version = 2,
 420                 .gpio_version = ICH_V6_GPIO,
 421         },
 422         [LPC_ICH6W] = {
 423                 .name = "ICH6W or ICH6RW",
 424                 .iTCO_version = 2,
 425                 .gpio_version = ICH_V6_GPIO,
 426         },
 427         [LPC_631XESB] = {
 428                 .name = "631xESB/632xESB",
 429                 .iTCO_version = 2,
 430                 .gpio_version = ICH_V6_GPIO,
 431         },
 432         [LPC_ICH7] = {
 433                 .name = "ICH7 or ICH7R",
 434                 .iTCO_version = 2,
 435                 .gpio_version = ICH_V7_GPIO,
 436         },
 437         [LPC_ICH7DH] = {
 438                 .name = "ICH7DH",
 439                 .iTCO_version = 2,
 440                 .gpio_version = ICH_V7_GPIO,
 441         },
 442         [LPC_ICH7M] = {
 443                 .name = "ICH7-M or ICH7-U",
 444                 .iTCO_version = 2,
 445                 .gpio_version = ICH_V7_GPIO,
 446         },
 447         [LPC_ICH7MDH] = {
 448                 .name = "ICH7-M DH",
 449                 .iTCO_version = 2,
 450                 .gpio_version = ICH_V7_GPIO,
 451         },
 452         [LPC_NM10] = {
 453                 .name = "NM10",
 454                 .iTCO_version = 2,
 455                 .gpio_version = ICH_V7_GPIO,
 456         },
 457         [LPC_ICH8] = {
 458                 .name = "ICH8 or ICH8R",
 459                 .iTCO_version = 2,
 460                 .gpio_version = ICH_V7_GPIO,
 461         },
 462         [LPC_ICH8DH] = {
 463                 .name = "ICH8DH",
 464                 .iTCO_version = 2,
 465                 .gpio_version = ICH_V7_GPIO,
 466         },
 467         [LPC_ICH8DO] = {
 468                 .name = "ICH8DO",
 469                 .iTCO_version = 2,
 470                 .gpio_version = ICH_V7_GPIO,
 471         },
 472         [LPC_ICH8M] = {
 473                 .name = "ICH8M",
 474                 .iTCO_version = 2,
 475                 .gpio_version = ICH_V7_GPIO,
 476         },
 477         [LPC_ICH8ME] = {
 478                 .name = "ICH8M-E",
 479                 .iTCO_version = 2,
 480                 .gpio_version = ICH_V7_GPIO,
 481         },
 482         [LPC_ICH9] = {
 483                 .name = "ICH9",
 484                 .iTCO_version = 2,
 485                 .gpio_version = ICH_V9_GPIO,
 486         },
 487         [LPC_ICH9R] = {
 488                 .name = "ICH9R",
 489                 .iTCO_version = 2,
 490                 .gpio_version = ICH_V9_GPIO,
 491         },
 492         [LPC_ICH9DH] = {
 493                 .name = "ICH9DH",
 494                 .iTCO_version = 2,
 495                 .gpio_version = ICH_V9_GPIO,
 496         },
 497         [LPC_ICH9DO] = {
 498                 .name = "ICH9DO",
 499                 .iTCO_version = 2,
 500                 .gpio_version = ICH_V9_GPIO,
 501         },
 502         [LPC_ICH9M] = {
 503                 .name = "ICH9M",
 504                 .iTCO_version = 2,
 505                 .gpio_version = ICH_V9_GPIO,
 506         },
 507         [LPC_ICH9ME] = {
 508                 .name = "ICH9M-E",
 509                 .iTCO_version = 2,
 510                 .gpio_version = ICH_V9_GPIO,
 511         },
 512         [LPC_ICH10] = {
 513                 .name = "ICH10",
 514                 .iTCO_version = 2,
 515                 .gpio_version = ICH_V10CONS_GPIO,
 516         },
 517         [LPC_ICH10R] = {
 518                 .name = "ICH10R",
 519                 .iTCO_version = 2,
 520                 .gpio_version = ICH_V10CONS_GPIO,
 521         },
 522         [LPC_ICH10D] = {
 523                 .name = "ICH10D",
 524                 .iTCO_version = 2,
 525                 .gpio_version = ICH_V10CORP_GPIO,
 526         },
 527         [LPC_ICH10DO] = {
 528                 .name = "ICH10DO",
 529                 .iTCO_version = 2,
 530                 .gpio_version = ICH_V10CORP_GPIO,
 531         },
 532         [LPC_PCH] = {
 533                 .name = "PCH Desktop Full Featured",
 534                 .iTCO_version = 2,
 535                 .gpio_version = ICH_V5_GPIO,
 536         },
 537         [LPC_PCHM] = {
 538                 .name = "PCH Mobile Full Featured",
 539                 .iTCO_version = 2,
 540                 .gpio_version = ICH_V5_GPIO,
 541         },
 542         [LPC_P55] = {
 543                 .name = "P55",
 544                 .iTCO_version = 2,
 545                 .gpio_version = ICH_V5_GPIO,
 546         },
 547         [LPC_PM55] = {
 548                 .name = "PM55",
 549                 .iTCO_version = 2,
 550                 .gpio_version = ICH_V5_GPIO,
 551         },
 552         [LPC_H55] = {
 553                 .name = "H55",
 554                 .iTCO_version = 2,
 555                 .gpio_version = ICH_V5_GPIO,
 556         },
 557         [LPC_QM57] = {
 558                 .name = "QM57",
 559                 .iTCO_version = 2,
 560                 .gpio_version = ICH_V5_GPIO,
 561         },
 562         [LPC_H57] = {
 563                 .name = "H57",
 564                 .iTCO_version = 2,
 565                 .gpio_version = ICH_V5_GPIO,
 566         },
 567         [LPC_HM55] = {
 568                 .name = "HM55",
 569                 .iTCO_version = 2,
 570                 .gpio_version = ICH_V5_GPIO,
 571         },
 572         [LPC_Q57] = {
 573                 .name = "Q57",
 574                 .iTCO_version = 2,
 575                 .gpio_version = ICH_V5_GPIO,
 576         },
 577         [LPC_HM57] = {
 578                 .name = "HM57",
 579                 .iTCO_version = 2,
 580                 .gpio_version = ICH_V5_GPIO,
 581         },
 582         [LPC_PCHMSFF] = {
 583                 .name = "PCH Mobile SFF Full Featured",
 584                 .iTCO_version = 2,
 585                 .gpio_version = ICH_V5_GPIO,
 586         },
 587         [LPC_QS57] = {
 588                 .name = "QS57",
 589                 .iTCO_version = 2,
 590                 .gpio_version = ICH_V5_GPIO,
 591         },
 592         [LPC_3400] = {
 593                 .name = "3400",
 594                 .iTCO_version = 2,
 595                 .gpio_version = ICH_V5_GPIO,
 596         },
 597         [LPC_3420] = {
 598                 .name = "3420",
 599                 .iTCO_version = 2,
 600                 .gpio_version = ICH_V5_GPIO,
 601         },
 602         [LPC_3450] = {
 603                 .name = "3450",
 604                 .iTCO_version = 2,
 605                 .gpio_version = ICH_V5_GPIO,
 606         },
 607         [LPC_EP80579] = {
 608                 .name = "EP80579",
 609                 .iTCO_version = 2,
 610         },
 611         [LPC_CPT] = {
 612                 .name = "Cougar Point",
 613                 .iTCO_version = 2,
 614                 .gpio_version = ICH_V5_GPIO,
 615         },
 616         [LPC_CPTD] = {
 617                 .name = "Cougar Point Desktop",
 618                 .iTCO_version = 2,
 619                 .gpio_version = ICH_V5_GPIO,
 620         },
 621         [LPC_CPTM] = {
 622                 .name = "Cougar Point Mobile",
 623                 .iTCO_version = 2,
 624                 .gpio_version = ICH_V5_GPIO,
 625         },
 626         [LPC_PBG] = {
 627                 .name = "Patsburg",
 628                 .iTCO_version = 2,
 629         },
 630         [LPC_DH89XXCC] = {
 631                 .name = "DH89xxCC",
 632                 .iTCO_version = 2,
 633                 .gpio_version = ICH_V5_GPIO,
 634         },
 635         [LPC_PPT] = {
 636                 .name = "Panther Point",
 637                 .iTCO_version = 2,
 638                 .gpio_version = ICH_V5_GPIO,
 639         },
 640         [LPC_LPT] = {
 641                 .name = "Lynx Point",
 642                 .iTCO_version = 2,
 643                 .gpio_version = ICH_V5_GPIO,
 644                 .spi_type = INTEL_SPI_LPT,
 645         },
 646         [LPC_LPT_LP] = {
 647                 .name = "Lynx Point_LP",
 648                 .iTCO_version = 2,
 649                 .spi_type = INTEL_SPI_LPT,
 650         },
 651         [LPC_WBG] = {
 652                 .name = "Wellsburg",
 653                 .iTCO_version = 2,
 654         },
 655         [LPC_AVN] = {
 656                 .name = "Avoton SoC",
 657                 .iTCO_version = 3,
 658                 .gpio_version = AVOTON_GPIO,
 659                 .spi_type = INTEL_SPI_BYT,
 660         },
 661         [LPC_BAYTRAIL] = {
 662                 .name = "Bay Trail SoC",
 663                 .iTCO_version = 3,
 664                 .spi_type = INTEL_SPI_BYT,
 665         },
 666         [LPC_COLETO] = {
 667                 .name = "Coleto Creek",
 668                 .iTCO_version = 2,
 669         },
 670         [LPC_WPT_LP] = {
 671                 .name = "Wildcat Point_LP",
 672                 .iTCO_version = 2,
 673                 .spi_type = INTEL_SPI_LPT,
 674         },
 675         [LPC_BRASWELL] = {
 676                 .name = "Braswell SoC",
 677                 .iTCO_version = 3,
 678                 .spi_type = INTEL_SPI_BYT,
 679         },
 680         [LPC_LEWISBURG] = {
 681                 .name = "Lewisburg",
 682                 .iTCO_version = 2,
 683         },
 684         [LPC_9S] = {
 685                 .name = "9 Series",
 686                 .iTCO_version = 2,
 687                 .gpio_version = ICH_V5_GPIO,
 688         },
 689         [LPC_APL] = {
 690                 .name = "Apollo Lake SoC",
 691                 .iTCO_version = 5,
 692                 .gpio_info = &apl_gpio_info,
 693                 .spi_type = INTEL_SPI_BXT,
 694         },
 695         [LPC_DNV] = {
 696                 .name = "Denverton SoC",
 697                 .gpio_info = &dnv_gpio_info,
 698         },
 699         [LPC_GLK] = {
 700                 .name = "Gemini Lake SoC",
 701                 .spi_type = INTEL_SPI_BXT,
 702         },
 703         [LPC_COUGARMOUNTAIN] = {
 704                 .name = "Cougar Mountain SoC",
 705                 .iTCO_version = 3,
 706         },
 707 };
 708
 709 /*
 710  * This data only exists for exporting the supported PCI ids
 711  * via MODULE_DEVICE_TABLE.  We do not actually register a
 712  * pci_driver, because the I/O Controller Hub has also other
 713  * functions that probably will be registered by other drivers.
 714  */
 715 static const struct pci_device_id lpc_ich_ids[] = {
 716         { PCI_VDEVICE(INTEL, 0x0f1c), LPC_BAYTRAIL},
 717         { PCI_VDEVICE(INTEL, 0x19dc), LPC_DNV},
 718         { PCI_VDEVICE(INTEL, 0x1c41), LPC_CPT},
 719         { PCI_VDEVICE(INTEL, 0x1c42), LPC_CPTD},
 720         { PCI_VDEVICE(INTEL, 0x1c43), LPC_CPTM},
 721         { PCI_VDEVICE(INTEL, 0x1c44), LPC_CPT},
 722         { PCI_VDEVICE(INTEL, 0x1c45), LPC_CPT},
 723         { PCI_VDEVICE(INTEL, 0x1c46), LPC_CPT},
 724         { PCI_VDEVICE(INTEL, 0x1c47), LPC_CPT},
 725         { PCI_VDEVICE(INTEL, 0x1c48), LPC_CPT},
 726         { PCI_VDEVICE(INTEL, 0x1c49), LPC_CPT},
 727         { PCI_VDEVICE(INTEL, 0x1c4a), LPC_CPT},
 728         { PCI_VDEVICE(INTEL, 0x1c4b), LPC_CPT},
 729         { PCI_VDEVICE(INTEL, 0x1c4c), LPC_CPT},
 730         { PCI_VDEVICE(INTEL, 0x1c4d), LPC_CPT},
 731         { PCI_VDEVICE(INTEL, 0x1c4e), LPC_CPT},
 732         { PCI_VDEVICE(INTEL, 0x1c4f), LPC_CPT},
 733         { PCI_VDEVICE(INTEL, 0x1c50), LPC_CPT},
 734         { PCI_VDEVICE(INTEL, 0x1c51), LPC_CPT},
 735         { PCI_VDEVICE(INTEL, 0x1c52), LPC_CPT},
 736         { PCI_VDEVICE(INTEL, 0x1c53), LPC_CPT},
 737         { PCI_VDEVICE(INTEL, 0x1c54), LPC_CPT},
 738         { PCI_VDEVICE(INTEL, 0x1c55), LPC_CPT},
 739         { PCI_VDEVICE(INTEL, 0x1c56), LPC_CPT},
 740         { PCI_VDEVICE(INTEL, 0x1c57), LPC_CPT},
 741         { PCI_VDEVICE(INTEL, 0x1c58), LPC_CPT},
 742         { PCI_VDEVICE(INTEL, 0x1c59), LPC_CPT},
 743         { PCI_VDEVICE(INTEL, 0x1c5a), LPC_CPT},
 744         { PCI_VDEVICE(INTEL, 0x1c5b), LPC_CPT},
 745         { PCI_VDEVICE(INTEL, 0x1c5c), LPC_CPT},
 746         { PCI_VDEVICE(INTEL, 0x1c5d), LPC_CPT},
 747         { PCI_VDEVICE(INTEL, 0x1c5e), LPC_CPT},
 748         { PCI_VDEVICE(INTEL, 0x1c5f), LPC_CPT},
 749         { PCI_VDEVICE(INTEL, 0x1d40), LPC_PBG},
 750         { PCI_VDEVICE(INTEL, 0x1d41), LPC_PBG},
 751         { PCI_VDEVICE(INTEL, 0x1e40), LPC_PPT},
 752         { PCI_VDEVICE(INTEL, 0x1e41), LPC_PPT},
 753         { PCI_VDEVICE(INTEL, 0x1e42), LPC_PPT},
 754         { PCI_VDEVICE(INTEL, 0x1e43), LPC_PPT},
 755         { PCI_VDEVICE(INTEL, 0x1e44), LPC_PPT},
 756         { PCI_VDEVICE(INTEL, 0x1e45), LPC_PPT},
 757         { PCI_VDEVICE(INTEL, 0x1e46), LPC_PPT},
 758         { PCI_VDEVICE(INTEL, 0x1e47), LPC_PPT},
 759         { PCI_VDEVICE(INTEL, 0x1e48), LPC_PPT},
 760         { PCI_VDEVICE(INTEL, 0x1e49), LPC_PPT},
 761         { PCI_VDEVICE(INTEL, 0x1e4a), LPC_PPT},
 762         { PCI_VDEVICE(INTEL, 0x1e4b), LPC_PPT},
 763         { PCI_VDEVICE(INTEL, 0x1e4c), LPC_PPT},
 764         { PCI_VDEVICE(INTEL, 0x1e4d), LPC_PPT},
 765         { PCI_VDEVICE(INTEL, 0x1e4e), LPC_PPT},
 766         { PCI_VDEVICE(INTEL, 0x1e4f), LPC_PPT},
 767         { PCI_VDEVICE(INTEL, 0x1e50), LPC_PPT},
 768         { PCI_VDEVICE(INTEL, 0x1e51), LPC_PPT},
 769         { PCI_VDEVICE(INTEL, 0x1e52), LPC_PPT},
 770         { PCI_VDEVICE(INTEL, 0x1e53), LPC_PPT},
 771         { PCI_VDEVICE(INTEL, 0x1e54), LPC_PPT},
 772         { PCI_VDEVICE(INTEL, 0x1e55), LPC_PPT},
 773         { PCI_VDEVICE(INTEL, 0x1e56), LPC_PPT},
 774         { PCI_VDEVICE(INTEL, 0x1e57), LPC_PPT},
 775         { PCI_VDEVICE(INTEL, 0x1e58), LPC_PPT},
 776         { PCI_VDEVICE(INTEL, 0x1e59), LPC_PPT},
 777         { PCI_VDEVICE(INTEL, 0x1e5a), LPC_PPT},
 778         { PCI_VDEVICE(INTEL, 0x1e5b), LPC_PPT},
 779         { PCI_VDEVICE(INTEL, 0x1e5c), LPC_PPT},
 780         { PCI_VDEVICE(INTEL, 0x1e5d), LPC_PPT},
 781         { PCI_VDEVICE(INTEL, 0x1e5e), LPC_PPT},
 782         { PCI_VDEVICE(INTEL, 0x1e5f), LPC_PPT},
 783         { PCI_VDEVICE(INTEL, 0x1f38), LPC_AVN},
 784         { PCI_VDEVICE(INTEL, 0x1f39), LPC_AVN},
 785         { PCI_VDEVICE(INTEL, 0x1f3a), LPC_AVN},
 786         { PCI_VDEVICE(INTEL, 0x1f3b), LPC_AVN},
 787         { PCI_VDEVICE(INTEL, 0x229c), LPC_BRASWELL},
 788         { PCI_VDEVICE(INTEL, 0x2310), LPC_DH89XXCC},
 789         { PCI_VDEVICE(INTEL, 0x2390), LPC_COLETO},
 790         { PCI_VDEVICE(INTEL, 0x2410), LPC_ICH},
 791         { PCI_VDEVICE(INTEL, 0x2420), LPC_ICH0},
 792         { PCI_VDEVICE(INTEL, 0x2440), LPC_ICH2},
 793         { PCI_VDEVICE(INTEL, 0x244c), LPC_ICH2M},
 794         { PCI_VDEVICE(INTEL, 0x2450), LPC_CICH},
 795         { PCI_VDEVICE(INTEL, 0x2480), LPC_ICH3},
 796         { PCI_VDEVICE(INTEL, 0x248c), LPC_ICH3M},
 797         { PCI_VDEVICE(INTEL, 0x24c0), LPC_ICH4},
 798         { PCI_VDEVICE(INTEL, 0x24cc), LPC_ICH4M},
 799         { PCI_VDEVICE(INTEL, 0x24d0), LPC_ICH5},
 800         { PCI_VDEVICE(INTEL, 0x25a1), LPC_6300ESB},
 801         { PCI_VDEVICE(INTEL, 0x2640), LPC_ICH6},
 802         { PCI_VDEVICE(INTEL, 0x2641), LPC_ICH6M},
 803         { PCI_VDEVICE(INTEL, 0x2642), LPC_ICH6W},
 804         { PCI_VDEVICE(INTEL, 0x2670), LPC_631XESB},
 805         { PCI_VDEVICE(INTEL, 0x2671), LPC_631XESB},
 806         { PCI_VDEVICE(INTEL, 0x2672), LPC_631XESB},
 807         { PCI_VDEVICE(INTEL, 0x2673), LPC_631XESB},
 808         { PCI_VDEVICE(INTEL, 0x2674), LPC_631XESB},
 809         { PCI_VDEVICE(INTEL, 0x2675), LPC_631XESB},
 810         { PCI_VDEVICE(INTEL, 0x2676), LPC_631XESB},
 811         { PCI_VDEVICE(INTEL, 0x2677), LPC_631XESB},
 812         { PCI_VDEVICE(INTEL, 0x2678), LPC_631XESB},
 813         { PCI_VDEVICE(INTEL, 0x2679), LPC_631XESB},
 814         { PCI_VDEVICE(INTEL, 0x267a), LPC_631XESB},
 815         { PCI_VDEVICE(INTEL, 0x267b), LPC_631XESB},
 816         { PCI_VDEVICE(INTEL, 0x267c), LPC_631XESB},
 817         { PCI_VDEVICE(INTEL, 0x267d), LPC_631XESB},
 818         { PCI_VDEVICE(INTEL, 0x267e), LPC_631XESB},
 819         { PCI_VDEVICE(INTEL, 0x267f), LPC_631XESB},
 820         { PCI_VDEVICE(INTEL, 0x27b0), LPC_ICH7DH},
 821         { PCI_VDEVICE(INTEL, 0x27b8), LPC_ICH7},
 822         { PCI_VDEVICE(INTEL, 0x27b9), LPC_ICH7M},
 823         { PCI_VDEVICE(INTEL, 0x27bc), LPC_NM10},
 824         { PCI_VDEVICE(INTEL, 0x27bd), LPC_ICH7MDH},
 825         { PCI_VDEVICE(INTEL, 0x2810), LPC_ICH8},
 826         { PCI_VDEVICE(INTEL, 0x2811), LPC_ICH8ME},
 827         { PCI_VDEVICE(INTEL, 0x2812), LPC_ICH8DH},
 828         { PCI_VDEVICE(INTEL, 0x2814), LPC_ICH8DO},
 829         { PCI_VDEVICE(INTEL, 0x2815), LPC_ICH8M},
 830         { PCI_VDEVICE(INTEL, 0x2912), LPC_ICH9DH},
 831         { PCI_VDEVICE(INTEL, 0x2914), LPC_ICH9DO},
 832         { PCI_VDEVICE(INTEL, 0x2916), LPC_ICH9R},
 833         { PCI_VDEVICE(INTEL, 0x2917), LPC_ICH9ME},
 834         { PCI_VDEVICE(INTEL, 0x2918), LPC_ICH9},
 835         { PCI_VDEVICE(INTEL, 0x2919), LPC_ICH9M},
 836         { PCI_VDEVICE(INTEL, 0x3197), LPC_GLK},
 837         { PCI_VDEVICE(INTEL, 0x2b9c), LPC_COUGARMOUNTAIN},
 838         { PCI_VDEVICE(INTEL, 0x3a14), LPC_ICH10DO},
 839         { PCI_VDEVICE(INTEL, 0x3a16), LPC_ICH10R},
 840         { PCI_VDEVICE(INTEL, 0x3a18), LPC_ICH10},
 841         { PCI_VDEVICE(INTEL, 0x3a1a), LPC_ICH10D},
 842         { PCI_VDEVICE(INTEL, 0x3b00), LPC_PCH},
 843         { PCI_VDEVICE(INTEL, 0x3b01), LPC_PCHM},
 844         { PCI_VDEVICE(INTEL, 0x3b02), LPC_P55},
 845         { PCI_VDEVICE(INTEL, 0x3b03), LPC_PM55},
 846         { PCI_VDEVICE(INTEL, 0x3b06), LPC_H55},
 847         { PCI_VDEVICE(INTEL, 0x3b07), LPC_QM57},
 848         { PCI_VDEVICE(INTEL, 0x3b08), LPC_H57},
 849         { PCI_VDEVICE(INTEL, 0x3b09), LPC_HM55},
 850         { PCI_VDEVICE(INTEL, 0x3b0a), LPC_Q57},
 851         { PCI_VDEVICE(INTEL, 0x3b0b), LPC_HM57},
 852         { PCI_VDEVICE(INTEL, 0x3b0d), LPC_PCHMSFF},
 853         { PCI_VDEVICE(INTEL, 0x3b0f), LPC_QS57},
 854         { PCI_VDEVICE(INTEL, 0x3b12), LPC_3400},
 855         { PCI_VDEVICE(INTEL, 0x3b14), LPC_3420},
 856         { PCI_VDEVICE(INTEL, 0x3b16), LPC_3450},
 857         { PCI_VDEVICE(INTEL, 0x5031), LPC_EP80579},
 858         { PCI_VDEVICE(INTEL, 0x5ae8), LPC_APL},
 859         { PCI_VDEVICE(INTEL, 0x8c40), LPC_LPT},
 860         { PCI_VDEVICE(INTEL, 0x8c41), LPC_LPT},
 861         { PCI_VDEVICE(INTEL, 0x8c42), LPC_LPT},
 862         { PCI_VDEVICE(INTEL, 0x8c43), LPC_LPT},
 863         { PCI_VDEVICE(INTEL, 0x8c44), LPC_LPT},
 864         { PCI_VDEVICE(INTEL, 0x8c45), LPC_LPT},
 865         { PCI_VDEVICE(INTEL, 0x8c46), LPC_LPT},
 866         { PCI_VDEVICE(INTEL, 0x8c47), LPC_LPT},
 867         { PCI_VDEVICE(INTEL, 0x8c48), LPC_LPT},
 868         { PCI_VDEVICE(INTEL, 0x8c49), LPC_LPT},
 869         { PCI_VDEVICE(INTEL, 0x8c4a), LPC_LPT},
 870         { PCI_VDEVICE(INTEL, 0x8c4b), LPC_LPT},
 871         { PCI_VDEVICE(INTEL, 0x8c4c), LPC_LPT},
 872         { PCI_VDEVICE(INTEL, 0x8c4d), LPC_LPT},
 873         { PCI_VDEVICE(INTEL, 0x8c4e), LPC_LPT},
 874         { PCI_VDEVICE(INTEL, 0x8c4f), LPC_LPT},
 875         { PCI_VDEVICE(INTEL, 0x8c50), LPC_LPT},
 876         { PCI_VDEVICE(INTEL, 0x8c51), LPC_LPT},
 877         { PCI_VDEVICE(INTEL, 0x8c52), LPC_LPT},
 878         { PCI_VDEVICE(INTEL, 0x8c53), LPC_LPT},
 879         { PCI_VDEVICE(INTEL, 0x8c54), LPC_LPT},
 880         { PCI_VDEVICE(INTEL, 0x8c55), LPC_LPT},
 881         { PCI_VDEVICE(INTEL, 0x8c56), LPC_LPT},
 882         { PCI_VDEVICE(INTEL, 0x8c57), LPC_LPT},
 883         { PCI_VDEVICE(INTEL, 0x8c58), LPC_LPT},
 884         { PCI_VDEVICE(INTEL, 0x8c59), LPC_LPT},
 885         { PCI_VDEVICE(INTEL, 0x8c5a), LPC_LPT},
 886         { PCI_VDEVICE(INTEL, 0x8c5b), LPC_LPT},
 887         { PCI_VDEVICE(INTEL, 0x8c5c), LPC_LPT},
 888         { PCI_VDEVICE(INTEL, 0x8c5d), LPC_LPT},
 889         { PCI_VDEVICE(INTEL, 0x8c5e), LPC_LPT},
 890         { PCI_VDEVICE(INTEL, 0x8c5f), LPC_LPT},
 891         { PCI_VDEVICE(INTEL, 0x8cc1), LPC_9S},
 892         { PCI_VDEVICE(INTEL, 0x8cc2), LPC_9S},
 893         { PCI_VDEVICE(INTEL, 0x8cc3), LPC_9S},
 894         { PCI_VDEVICE(INTEL, 0x8cc4), LPC_9S},
 895         { PCI_VDEVICE(INTEL, 0x8cc6), LPC_9S},
 896         { PCI_VDEVICE(INTEL, 0x8d40), LPC_WBG},
 897         { PCI_VDEVICE(INTEL, 0x8d41), LPC_WBG},
 898         { PCI_VDEVICE(INTEL, 0x8d42), LPC_WBG},
 899         { PCI_VDEVICE(INTEL, 0x8d43), LPC_WBG},
 900         { PCI_VDEVICE(INTEL, 0x8d44), LPC_WBG},
 901         { PCI_VDEVICE(INTEL, 0x8d45), LPC_WBG},
 902         { PCI_VDEVICE(INTEL, 0x8d46), LPC_WBG},
 903         { PCI_VDEVICE(INTEL, 0x8d47), LPC_WBG},
 904         { PCI_VDEVICE(INTEL, 0x8d48), LPC_WBG},
 905         { PCI_VDEVICE(INTEL, 0x8d49), LPC_WBG},
 906         { PCI_VDEVICE(INTEL, 0x8d4a), LPC_WBG},
 907         { PCI_VDEVICE(INTEL, 0x8d4b), LPC_WBG},
 908         { PCI_VDEVICE(INTEL, 0x8d4c), LPC_WBG},
 909         { PCI_VDEVICE(INTEL, 0x8d4d), LPC_WBG},
 910         { PCI_VDEVICE(INTEL, 0x8d4e), LPC_WBG},
 911         { PCI_VDEVICE(INTEL, 0x8d4f), LPC_WBG},
 912         { PCI_VDEVICE(INTEL, 0x8d50), LPC_WBG},
 913         { PCI_VDEVICE(INTEL, 0x8d51), LPC_WBG},
 914         { PCI_VDEVICE(INTEL, 0x8d52), LPC_WBG},
 915         { PCI_VDEVICE(INTEL, 0x8d53), LPC_WBG},
 916         { PCI_VDEVICE(INTEL, 0x8d54), LPC_WBG},
 917         { PCI_VDEVICE(INTEL, 0x8d55), LPC_WBG},
 918         { PCI_VDEVICE(INTEL, 0x8d56), LPC_WBG},
 919         { PCI_VDEVICE(INTEL, 0x8d57), LPC_WBG},
 920         { PCI_VDEVICE(INTEL, 0x8d58), LPC_WBG},
 921         { PCI_VDEVICE(INTEL, 0x8d59), LPC_WBG},
 922         { PCI_VDEVICE(INTEL, 0x8d5a), LPC_WBG},
 923         { PCI_VDEVICE(INTEL, 0x8d5b), LPC_WBG},
 924         { PCI_VDEVICE(INTEL, 0x8d5c), LPC_WBG},
 925         { PCI_VDEVICE(INTEL, 0x8d5d), LPC_WBG},
 926         { PCI_VDEVICE(INTEL, 0x8d5e), LPC_WBG},
 927         { PCI_VDEVICE(INTEL, 0x8d5f), LPC_WBG},
 928         { PCI_VDEVICE(INTEL, 0x9c40), LPC_LPT_LP},
 929         { PCI_VDEVICE(INTEL, 0x9c41), LPC_LPT_LP},
 930         { PCI_VDEVICE(INTEL, 0x9c42), LPC_LPT_LP},
 931         { PCI_VDEVICE(INTEL, 0x9c43), LPC_LPT_LP},
 932         { PCI_VDEVICE(INTEL, 0x9c44), LPC_LPT_LP},
 933         { PCI_VDEVICE(INTEL, 0x9c45), LPC_LPT_LP},
 934         { PCI_VDEVICE(INTEL, 0x9c46), LPC_LPT_LP},
 935         { PCI_VDEVICE(INTEL, 0x9c47), LPC_LPT_LP},
 936         { PCI_VDEVICE(INTEL, 0x9cc1), LPC_WPT_LP},
 937         { PCI_VDEVICE(INTEL, 0x9cc2), LPC_WPT_LP},
 938         { PCI_VDEVICE(INTEL, 0x9cc3), LPC_WPT_LP},
 939         { PCI_VDEVICE(INTEL, 0x9cc5), LPC_WPT_LP},
 940         { PCI_VDEVICE(INTEL, 0x9cc6), LPC_WPT_LP},
 941         { PCI_VDEVICE(INTEL, 0x9cc7), LPC_WPT_LP},
 942         { PCI_VDEVICE(INTEL, 0x9cc9), LPC_WPT_LP},
 943         { PCI_VDEVICE(INTEL, 0xa1c1), LPC_LEWISBURG},
 944         { PCI_VDEVICE(INTEL, 0xa1c2), LPC_LEWISBURG},
 945         { PCI_VDEVICE(INTEL, 0xa1c3), LPC_LEWISBURG},
 946         { PCI_VDEVICE(INTEL, 0xa1c4), LPC_LEWISBURG},
 947         { PCI_VDEVICE(INTEL, 0xa1c5), LPC_LEWISBURG},
 948         { PCI_VDEVICE(INTEL, 0xa1c6), LPC_LEWISBURG},
 949         { PCI_VDEVICE(INTEL, 0xa1c7), LPC_LEWISBURG},
 950         { PCI_VDEVICE(INTEL, 0xa242), LPC_LEWISBURG},
 951         { PCI_VDEVICE(INTEL, 0xa243), LPC_LEWISBURG},
 952         { 0, },                 /* End of list */
 953 };
 954 MODULE_DEVICE_TABLE(pci, lpc_ich_ids);
 955
 956 static void lpc_ich_restore_config_space(struct pci_dev *dev)
 957 {
 958         struct lpc_ich_priv *priv = pci_get_drvdata(dev);
 959
 960         if (priv->abase_save >= 0) {
 961                 pci_write_config_byte(dev, priv->abase, priv->abase_save);
 962                 priv->abase_save = -1;
 963         }
 964
 965         if (priv->actrl_pbase_save >= 0) {
 966                 pci_write_config_byte(dev, priv->actrl_pbase,
 967                         priv->actrl_pbase_save);
 968                 priv->actrl_pbase_save = -1;
 969         }
 970
 971         if (priv->gctrl_save >= 0) {
 972                 pci_write_config_byte(dev, priv->gctrl, priv->gctrl_save);
 973                 priv->gctrl_save = -1;
 974         }
 975 }
 976
 977 static void lpc_ich_enable_acpi_space(struct pci_dev *dev)
 978 {
 979         struct lpc_ich_priv *priv = pci_get_drvdata(dev);
 980         u8 reg_save;
 981
 982         switch (lpc_chipset_info[priv->chipset].iTCO_version) {
 983         case 3:
 984                 /*
 985                  * Some chipsets (eg Avoton) enable the ACPI space in the
 986                  * ACPI BASE register.
 987                  */
 988                 pci_read_config_byte(dev, priv->abase, &reg_save);
 989                 pci_write_config_byte(dev, priv->abase, reg_save | 0x2);
 990                 priv->abase_save = reg_save;
 991                 break;
 992         default:
 993                 /*
 994                  * Most chipsets enable the ACPI space in the ACPI control
 995                  * register.
 996                  */
 997                 pci_read_config_byte(dev, priv->actrl_pbase, &reg_save);
 998                 pci_write_config_byte(dev, priv->actrl_pbase, reg_save | 0x80);
 999                 priv->actrl_pbase_save = reg_save;
1000                 break;
1001         }
1002 }
1003
1004 static void lpc_ich_enable_gpio_space(struct pci_dev *dev)
1005 {
1006         struct lpc_ich_priv *priv = pci_get_drvdata(dev);
1007         u8 reg_save;
1008
1009         pci_read_config_byte(dev, priv->gctrl, &reg_save);
1010         pci_write_config_byte(dev, priv->gctrl, reg_save | 0x10);
1011         priv->gctrl_save = reg_save;
1012 }
1013
1014 static void lpc_ich_enable_pmc_space(struct pci_dev *dev)
1015 {
1016         struct lpc_ich_priv *priv = pci_get_drvdata(dev);
1017         u8 reg_save;
1018
1019         pci_read_config_byte(dev, priv->actrl_pbase, &reg_save);
1020         pci_write_config_byte(dev, priv->actrl_pbase, reg_save | 0x2);
1021
1022         priv->actrl_pbase_save = reg_save;
1023 }
1024
1025 static int lpc_ich_finalize_wdt_cell(struct pci_dev *dev)
1026 {
1027         struct itco_wdt_platform_data *pdata;
1028         struct lpc_ich_priv *priv = pci_get_drvdata(dev);
1029         struct lpc_ich_info *info;
1030         struct mfd_cell *cell = &lpc_ich_wdt_cell;
1031
1032         pdata = devm_kzalloc(&dev->dev, sizeof(*pdata), GFP_KERNEL);
1033         if (!pdata)
1034                 return -ENOMEM;
1035
1036         info = &lpc_chipset_info[priv->chipset];
1037
1038         pdata->version = info->iTCO_version;
1039         strscpy(pdata->name, info->name, sizeof(pdata->name));
1040
1041         cell->platform_data = pdata;
1042         cell->pdata_size = sizeof(*pdata);
1043         return 0;
1044 }
1045
1046 static void lpc_ich_finalize_gpio_cell(struct pci_dev *dev)
1047 {
1048         struct lpc_ich_priv *priv = pci_get_drvdata(dev);
1049         struct mfd_cell *cell = &lpc_ich_gpio_cell;
1050
1051         cell->platform_data = &lpc_chipset_info[priv->chipset];
1052         cell->pdata_size = sizeof(struct lpc_ich_info);
1053 }
1054
1055 /*
1056  * We don't check for resource conflict globally. There are 2 or 3 independent
1057  * GPIO groups and it's enough to have access to one of these to instantiate
1058  * the device.
1059  */
1060 static int lpc_ich_check_conflict_gpio(struct resource *res)
1061 {
1062         int ret;
1063         u8 use_gpio = 0;
1064
1065         if (resource_size(res) >= 0x50 &&
1066             !acpi_check_region(res->start + 0x40, 0x10, "LPC ICH GPIO3"))
1067                 use_gpio |= 1 << 2;
1068
1069         if (!acpi_check_region(res->start + 0x30, 0x10, "LPC ICH GPIO2"))
1070                 use_gpio |= 1 << 1;
1071
1072         ret = acpi_check_region(res->start + 0x00, 0x30, "LPC ICH GPIO1");
1073         if (!ret)
1074                 use_gpio |= 1 << 0;
1075
1076         return use_gpio ? use_gpio : ret;
1077 }
1078
1079 static int lpc_ich_init_gpio(struct pci_dev *dev)
1080 {
1081         struct lpc_ich_priv *priv = pci_get_drvdata(dev);
1082         u32 base_addr_cfg;
1083         u32 base_addr;
1084         int ret;
1085         bool acpi_conflict = false;
1086         struct resource *res;
1087
1088         /* Setup power management base register */
1089         pci_read_config_dword(dev, priv->abase, &base_addr_cfg);
1090         base_addr = base_addr_cfg & 0x0000ff80;
1091         if (!base_addr) {
1092                 dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n");
1093                 lpc_ich_gpio_cell.num_resources--;
1094                 goto gpe0_done;
1095         }
1096
1097         res = &gpio_ich_res[ICH_RES_GPE0];
1098         res->start = base_addr + ACPIBASE_GPE_OFF;
1099         res->end = base_addr + ACPIBASE_GPE_END;
1100         ret = acpi_check_resource_conflict(res);
1101         if (ret) {
1102                 /*
1103                  * This isn't fatal for the GPIO, but we have to make sure that
1104                  * the platform_device subsystem doesn't see this resource
1105                  * or it will register an invalid region.
1106                  */
1107                 lpc_ich_gpio_cell.num_resources--;
1108                 acpi_conflict = true;
1109         } else {
1110                 lpc_ich_enable_acpi_space(dev);
1111         }
1112
1113 gpe0_done:
1114         /* Setup GPIO base register */
1115         pci_read_config_dword(dev, priv->gbase, &base_addr_cfg);
1116         base_addr = base_addr_cfg & 0x0000ff80;
1117         if (!base_addr) {
1118                 dev_notice(&dev->dev, "I/O space for GPIO uninitialized\n");
1119                 ret = -ENODEV;
1120                 goto gpio_done;
1121         }
1122
1123         /* Older devices provide fewer GPIO and have a smaller resource size. */
1124         res = &gpio_ich_res[ICH_RES_GPIO];
1125         res->start = base_addr;
1126         switch (lpc_chipset_info[priv->chipset].gpio_version) {
1127         case ICH_V5_GPIO:
1128         case ICH_V10CORP_GPIO:
1129                 res->end = res->start + 128 - 1;
1130                 break;
1131         default:
1132                 res->end = res->start + 64 - 1;
1133                 break;
1134         }
1135
1136         ret = lpc_ich_check_conflict_gpio(res);
1137         if (ret < 0) {
1138                 /* this isn't necessarily fatal for the GPIO */
1139                 acpi_conflict = true;
1140                 goto gpio_done;
1141         }
1142         lpc_chipset_info[priv->chipset].use_gpio = ret;
1143         lpc_ich_enable_gpio_space(dev);
1144
1145         lpc_ich_finalize_gpio_cell(dev);
1146         ret = mfd_add_devices(&dev->dev, PLATFORM_DEVID_AUTO,
1147                               &lpc_ich_gpio_cell, 1, NULL, 0, NULL);
1148
1149 gpio_done:
1150         if (acpi_conflict)
1151                 pr_warn("Resource conflict(s) found affecting %s\n",
1152                                 lpc_ich_gpio_cell.name);
1153         return ret;
1154 }
1155
1156 static int lpc_ich_init_wdt(struct pci_dev *dev)
1157 {
1158         struct lpc_ich_priv *priv = pci_get_drvdata(dev);
1159         u32 base_addr_cfg;
1160         u32 base_addr;
1161         int ret;
1162         struct resource *res;
1163
1164         /* If we have ACPI based watchdog use that instead */
1165         if (acpi_has_watchdog())
1166                 return -ENODEV;
1167
1168         /* Setup power management base register */
1169         pci_read_config_dword(dev, priv->abase, &base_addr_cfg);
1170         base_addr = base_addr_cfg & 0x0000ff80;
1171         if (!base_addr) {
1172                 dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n");
1173                 ret = -ENODEV;
1174                 goto wdt_done;
1175         }
1176
1177         res = wdt_io_res(ICH_RES_IO_TCO);
1178         res->start = base_addr + ACPIBASE_TCO_OFF;
1179         res->end = base_addr + ACPIBASE_TCO_END;
1180
1181         res = wdt_io_res(ICH_RES_IO_SMI);
1182         res->start = base_addr + ACPIBASE_SMI_OFF;
1183         res->end = base_addr + ACPIBASE_SMI_END;
1184
1185         lpc_ich_enable_acpi_space(dev);
1186
1187         /*
1188          * iTCO v2:
1189          * Get the Memory-Mapped GCS register. To get access to it
1190          * we have to read RCBA from PCI Config space 0xf0 and use
1191          * it as base. GCS = RCBA + ICH6_GCS(0x3410).
1192          *
1193          * iTCO v3:
1194          * Get the Power Management Configuration register.  To get access
1195          * to it we have to read the PMC BASE from config space and address
1196          * the register at offset 0x8.
1197          */
1198         if (lpc_chipset_info[priv->chipset].iTCO_version == 1) {
1199                 /* Don't register iomem for TCO ver 1 */
1200                 lpc_ich_wdt_cell.num_resources--;
1201         } else if (lpc_chipset_info[priv->chipset].iTCO_version == 2) {
1202                 pci_read_config_dword(dev, RCBABASE, &base_addr_cfg);
1203                 base_addr = base_addr_cfg & 0xffffc000;
1204                 if (!(base_addr_cfg & 1)) {
1205                         dev_notice(&dev->dev, "RCBA is disabled by "
1206                                         "hardware/BIOS, device disabled\n");
1207                         ret = -ENODEV;
1208                         goto wdt_done;
1209                 }
1210                 res = wdt_mem_res(ICH_RES_MEM_GCS_PMC);
1211                 res->start = base_addr + ACPIBASE_GCS_OFF;
1212                 res->end = base_addr + ACPIBASE_GCS_END;
1213         } else if (lpc_chipset_info[priv->chipset].iTCO_version == 3) {
1214                 lpc_ich_enable_pmc_space(dev);
1215                 pci_read_config_dword(dev, ACPICTRL_PMCBASE, &base_addr_cfg);
1216                 base_addr = base_addr_cfg & 0xfffffe00;
1217
1218                 res = wdt_mem_res(ICH_RES_MEM_GCS_PMC);
1219                 res->start = base_addr + ACPIBASE_PMC_OFF;
1220                 res->end = base_addr + ACPIBASE_PMC_END;
1221         }
1222
1223         ret = lpc_ich_finalize_wdt_cell(dev);
1224         if (ret)
1225                 goto wdt_done;
1226
1227         ret = mfd_add_devices(&dev->dev, PLATFORM_DEVID_AUTO,
1228                               &lpc_ich_wdt_cell, 1, NULL, 0, NULL);
1229
1230 wdt_done:
1231         return ret;
1232 }
1233
1234 static int lpc_ich_init_pinctrl(struct pci_dev *dev)
1235 {
1236         struct lpc_ich_priv *priv = pci_get_drvdata(dev);
1237         const struct lpc_ich_gpio_info *info = lpc_chipset_info[priv->chipset].gpio_info;
1238         struct resource base;
1239         unsigned int i;
1240         int ret;
1241
1242         /* Check, if GPIO has been exported as an ACPI device */
1243         if (acpi_dev_present(info->hid, NULL, -1))
1244                 return -EEXIST;
1245
1246         ret = p2sb_bar(dev->bus, 0, &base);
1247         if (ret)
1248                 return ret;
1249
1250         for (i = 0; i < info->nr_resources; i++) {
1251                 struct resource *mem = info->resources[i];
1252                 resource_size_t offset = info->offsets[i];
1253
1254                 /* Fill MEM resource */
1255                 mem->start = base.start + offset;
1256                 mem->end = base.start + offset + INTEL_GPIO_RESOURCE_SIZE - 1;
1257                 mem->flags = base.flags;
1258         }
1259
1260         return mfd_add_devices(&dev->dev, 0, info->devices, info->nr_devices,
1261                                NULL, 0, NULL);
1262 }
1263
1264 static bool lpc_ich_byt_set_writeable(void __iomem *base, void *data)
1265 {
1266         u32 val;
1267
1268         val = readl(base + BYT_BCR);
1269         if (!(val & BYT_BCR_WPD)) {
1270                 val |= BYT_BCR_WPD;
1271                 writel(val, base + BYT_BCR);
1272                 val = readl(base + BYT_BCR);
1273         }
1274
1275         return val & BYT_BCR_WPD;
1276 }
1277
1278 static bool lpc_ich_set_writeable(struct pci_bus *bus, unsigned int devfn)
1279 {
1280         u32 bcr;
1281
1282         pci_bus_read_config_dword(bus, devfn, BCR, &bcr);
1283         if (!(bcr & BCR_WPD)) {
1284                 bcr |= BCR_WPD;
1285                 pci_bus_write_config_dword(bus, devfn, BCR, bcr);
1286                 pci_bus_read_config_dword(bus, devfn, BCR, &bcr);
1287         }
1288
1289         return bcr & BCR_WPD;
1290 }
1291
1292 static bool lpc_ich_lpt_set_writeable(void __iomem *base, void *data)
1293 {
1294         struct pci_dev *pdev = data;
1295
1296         return lpc_ich_set_writeable(pdev->bus, pdev->devfn);
1297 }
1298
1299 static bool lpc_ich_bxt_set_writeable(void __iomem *base, void *data)
1300 {
1301         struct pci_dev *pdev = data;
1302
1303         return lpc_ich_set_writeable(pdev->bus, PCI_DEVFN(13, 2));
1304 }
1305
1306 static int lpc_ich_init_spi(struct pci_dev *dev)
1307 {
1308         struct lpc_ich_priv *priv = pci_get_drvdata(dev);
1309         struct resource *res = &intel_spi_res[0];
1310         struct intel_spi_boardinfo *info;
1311         u32 spi_base, rcba;
1312         int ret;
1313
1314         info = devm_kzalloc(&dev->dev, sizeof(*info), GFP_KERNEL);
1315         if (!info)
1316                 return -ENOMEM;
1317
1318         info->type = lpc_chipset_info[priv->chipset].spi_type;
1319
1320         switch (info->type) {
1321         case INTEL_SPI_BYT:
1322                 pci_read_config_dword(dev, SPIBASE_BYT, &spi_base);
1323                 if (spi_base & SPIBASE_BYT_EN) {
1324                         res->start = spi_base & ~(SPIBASE_BYT_SZ - 1);
1325                         res->end = res->start + SPIBASE_BYT_SZ - 1;
1326
1327                         info->set_writeable = lpc_ich_byt_set_writeable;
1328                 }
1329                 break;
1330
1331         case INTEL_SPI_LPT:
1332                 pci_read_config_dword(dev, RCBABASE, &rcba);
1333                 if (rcba & 1) {
1334                         spi_base = round_down(rcba, SPIBASE_LPT_SZ);
1335                         res->start = spi_base + SPIBASE_LPT;
1336                         res->end = res->start + SPIBASE_LPT_SZ - 1;
1337
1338                         info->set_writeable = lpc_ich_lpt_set_writeable;
1339                         info->data = dev;
1340                 }
1341                 break;
1342
1343         case INTEL_SPI_BXT:
1344                 /*
1345                  * The P2SB is hidden by BIOS and we need to unhide it in
1346                  * order to read BAR of the SPI flash device. Once that is
1347                  * done we hide it again.
1348                  */
1349                 ret = p2sb_bar(dev->bus, PCI_DEVFN(13, 2), res);
1350                 if (ret)
1351                         return ret;
1352
1353                 info->set_writeable = lpc_ich_bxt_set_writeable;
1354                 info->data = dev;
1355                 break;
1356
1357         default:
1358                 return -EINVAL;
1359         }
1360
1361         if (!res->start)
1362                 return -ENODEV;
1363
1364         lpc_ich_spi_cell.platform_data = info;
1365         lpc_ich_spi_cell.pdata_size = sizeof(*info);
1366
1367         return mfd_add_devices(&dev->dev, PLATFORM_DEVID_NONE,
1368                                &lpc_ich_spi_cell, 1, NULL, 0, NULL);
1369 }
1370
1371 static int lpc_ich_probe(struct pci_dev *dev,
1372                                 const struct pci_device_id *id)
1373 {
1374         struct lpc_ich_priv *priv;
1375         int ret;
1376         bool cell_added = false;
1377
1378         priv = devm_kzalloc(&dev->dev,
1379                             sizeof(struct lpc_ich_priv), GFP_KERNEL);
1380         if (!priv)
1381                 return -ENOMEM;
1382
1383         priv->chipset = id->driver_data;
1384
1385         priv->actrl_pbase_save = -1;
1386         priv->abase_save = -1;
1387
1388         priv->abase = ACPIBASE;
1389         priv->actrl_pbase = ACPICTRL_PMCBASE;
1390
1391         priv->gctrl_save = -1;
1392         if (priv->chipset <= LPC_ICH5) {
1393                 priv->gbase = GPIOBASE_ICH0;
1394                 priv->gctrl = GPIOCTRL_ICH0;
1395         } else {
1396                 priv->gbase = GPIOBASE_ICH6;
1397                 priv->gctrl = GPIOCTRL_ICH6;
1398         }
1399
1400         pci_set_drvdata(dev, priv);
1401
1402         if (lpc_chipset_info[priv->chipset].iTCO_version) {
1403                 ret = lpc_ich_init_wdt(dev);
1404                 if (!ret)
1405                         cell_added = true;
1406         }
1407
1408         if (lpc_chipset_info[priv->chipset].gpio_version) {
1409                 ret = lpc_ich_init_gpio(dev);
1410                 if (!ret)
1411                         cell_added = true;
1412         }
1413
1414         if (lpc_chipset_info[priv->chipset].gpio_info) {
1415                 ret = lpc_ich_init_pinctrl(dev);
1416                 if (!ret)
1417                         cell_added = true;
1418         }
1419
1420         if (lpc_chipset_info[priv->chipset].spi_type) {
1421                 ret = lpc_ich_init_spi(dev);
1422                 if (!ret)
1423                         cell_added = true;
1424         }
1425
1426         /*
1427          * We only care if at least one or none of the cells registered
1428          * successfully.
1429          */
1430         if (!cell_added) {
1431                 dev_warn(&dev->dev, "No MFD cells added\n");
1432                 lpc_ich_restore_config_space(dev);
1433                 return -ENODEV;
1434         }
1435
1436         return 0;
1437 }
1438
1439 static void lpc_ich_remove(struct pci_dev *dev)
1440 {
1441         mfd_remove_devices(&dev->dev);
1442         lpc_ich_restore_config_space(dev);
1443 }
1444
1445 static struct pci_driver lpc_ich_driver = {
1446         .name           = "lpc_ich",
1447         .id_table       = lpc_ich_ids,
1448         .probe          = lpc_ich_probe,
1449         .remove         = lpc_ich_remove,
1450 };
1451
1452 module_pci_driver(lpc_ich_driver);
1453
1454 MODULE_AUTHOR("Aaron Sierra <asierra@xes-inc.com>");
1455 MODULE_DESCRIPTION("LPC interface for Intel ICH");
1456 MODULE_LICENSE("GPL");