GNU Linux-libre 5.10.219-gnu1
[releases.git] / drivers / mfd / lpc_ich.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  *  lpc_ich.c - LPC interface for Intel ICH
4  *
5  *  LPC bridge function of the Intel ICH contains many other
6  *  functional units, such as Interrupt controllers, Timers,
7  *  Power Management, System Management, GPIO, RTC, and LPC
8  *  Configuration Registers.
9  *
10  *  This driver is derived from lpc_sch.
11
12  *  Copyright (c) 2011 Extreme Engineering Solution, Inc.
13  *  Author: Aaron Sierra <asierra@xes-inc.com>
14  *
15  *  This driver supports the following I/O Controller hubs:
16  *      (See the intel documentation on http://developer.intel.com.)
17  *      document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO)
18  *      document number 290687-002, 298242-027: 82801BA (ICH2)
19  *      document number 290733-003, 290739-013: 82801CA (ICH3-S)
20  *      document number 290716-001, 290718-007: 82801CAM (ICH3-M)
21  *      document number 290744-001, 290745-025: 82801DB (ICH4)
22  *      document number 252337-001, 252663-008: 82801DBM (ICH4-M)
23  *      document number 273599-001, 273645-002: 82801E (C-ICH)
24  *      document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R)
25  *      document number 300641-004, 300884-013: 6300ESB
26  *      document number 301473-002, 301474-026: 82801F (ICH6)
27  *      document number 313082-001, 313075-006: 631xESB, 632xESB
28  *      document number 307013-003, 307014-024: 82801G (ICH7)
29  *      document number 322896-001, 322897-001: NM10
30  *      document number 313056-003, 313057-017: 82801H (ICH8)
31  *      document number 316972-004, 316973-012: 82801I (ICH9)
32  *      document number 319973-002, 319974-002: 82801J (ICH10)
33  *      document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH)
34  *      document number 320066-003, 320257-008: EP80597 (IICH)
35  *      document number 324645-001, 324646-001: Cougar Point (CPT)
36  */
37
38 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
39
40 #include <linux/kernel.h>
41 #include <linux/module.h>
42 #include <linux/errno.h>
43 #include <linux/acpi.h>
44 #include <linux/pci.h>
45 #include <linux/mfd/core.h>
46 #include <linux/mfd/lpc_ich.h>
47 #include <linux/platform_data/itco_wdt.h>
48
49 #define ACPIBASE                0x40
50 #define ACPIBASE_GPE_OFF        0x28
51 #define ACPIBASE_GPE_END        0x2f
52 #define ACPIBASE_SMI_OFF        0x30
53 #define ACPIBASE_SMI_END        0x33
54 #define ACPIBASE_PMC_OFF        0x08
55 #define ACPIBASE_PMC_END        0x0c
56 #define ACPIBASE_TCO_OFF        0x60
57 #define ACPIBASE_TCO_END        0x7f
58 #define ACPICTRL_PMCBASE        0x44
59
60 #define ACPIBASE_GCS_OFF        0x3410
61 #define ACPIBASE_GCS_END        0x3414
62
63 #define SPIBASE_BYT             0x54
64 #define SPIBASE_BYT_SZ          512
65 #define SPIBASE_BYT_EN          BIT(1)
66 #define BYT_BCR                 0xfc
67 #define BYT_BCR_WPD             BIT(0)
68
69 #define SPIBASE_LPT             0x3800
70 #define SPIBASE_LPT_SZ          512
71 #define BCR                     0xdc
72 #define BCR_WPD                 BIT(0)
73
74 #define SPIBASE_APL_SZ          4096
75
76 #define GPIOBASE_ICH0           0x58
77 #define GPIOCTRL_ICH0           0x5C
78 #define GPIOBASE_ICH6           0x48
79 #define GPIOCTRL_ICH6           0x4C
80
81 #define RCBABASE                0xf0
82
83 #define wdt_io_res(i) wdt_res(0, i)
84 #define wdt_mem_res(i) wdt_res(ICH_RES_MEM_OFF, i)
85 #define wdt_res(b, i) (&wdt_ich_res[(b) + (i)])
86
87 struct lpc_ich_priv {
88         int chipset;
89
90         int abase;              /* ACPI base */
91         int actrl_pbase;        /* ACPI control or PMC base */
92         int gbase;              /* GPIO base */
93         int gctrl;              /* GPIO control */
94
95         int abase_save;         /* Cached ACPI base value */
96         int actrl_pbase_save;           /* Cached ACPI control or PMC base value */
97         int gctrl_save;         /* Cached GPIO control value */
98 };
99
100 static struct resource wdt_ich_res[] = {
101         /* ACPI - TCO */
102         {
103                 .flags = IORESOURCE_IO,
104         },
105         /* ACPI - SMI */
106         {
107                 .flags = IORESOURCE_IO,
108         },
109         /* GCS or PMC */
110         {
111                 .flags = IORESOURCE_MEM,
112         },
113 };
114
115 static struct resource gpio_ich_res[] = {
116         /* GPIO */
117         {
118                 .flags = IORESOURCE_IO,
119         },
120         /* ACPI - GPE0 */
121         {
122                 .flags = IORESOURCE_IO,
123         },
124 };
125
126 static struct resource intel_spi_res[] = {
127         {
128                 .flags = IORESOURCE_MEM,
129         }
130 };
131
132 static struct mfd_cell lpc_ich_wdt_cell = {
133         .name = "iTCO_wdt",
134         .num_resources = ARRAY_SIZE(wdt_ich_res),
135         .resources = wdt_ich_res,
136         .ignore_resource_conflicts = true,
137 };
138
139 static struct mfd_cell lpc_ich_gpio_cell = {
140         .name = "gpio_ich",
141         .num_resources = ARRAY_SIZE(gpio_ich_res),
142         .resources = gpio_ich_res,
143         .ignore_resource_conflicts = true,
144 };
145
146
147 static struct mfd_cell lpc_ich_spi_cell = {
148         .name = "intel-spi",
149         .num_resources = ARRAY_SIZE(intel_spi_res),
150         .resources = intel_spi_res,
151         .ignore_resource_conflicts = true,
152 };
153
154 /* chipset related info */
155 enum lpc_chipsets {
156         LPC_ICH = 0,    /* ICH */
157         LPC_ICH0,       /* ICH0 */
158         LPC_ICH2,       /* ICH2 */
159         LPC_ICH2M,      /* ICH2-M */
160         LPC_ICH3,       /* ICH3-S */
161         LPC_ICH3M,      /* ICH3-M */
162         LPC_ICH4,       /* ICH4 */
163         LPC_ICH4M,      /* ICH4-M */
164         LPC_CICH,       /* C-ICH */
165         LPC_ICH5,       /* ICH5 & ICH5R */
166         LPC_6300ESB,    /* 6300ESB */
167         LPC_ICH6,       /* ICH6 & ICH6R */
168         LPC_ICH6M,      /* ICH6-M */
169         LPC_ICH6W,      /* ICH6W & ICH6RW */
170         LPC_631XESB,    /* 631xESB/632xESB */
171         LPC_ICH7,       /* ICH7 & ICH7R */
172         LPC_ICH7DH,     /* ICH7DH */
173         LPC_ICH7M,      /* ICH7-M & ICH7-U */
174         LPC_ICH7MDH,    /* ICH7-M DH */
175         LPC_NM10,       /* NM10 */
176         LPC_ICH8,       /* ICH8 & ICH8R */
177         LPC_ICH8DH,     /* ICH8DH */
178         LPC_ICH8DO,     /* ICH8DO */
179         LPC_ICH8M,      /* ICH8M */
180         LPC_ICH8ME,     /* ICH8M-E */
181         LPC_ICH9,       /* ICH9 */
182         LPC_ICH9R,      /* ICH9R */
183         LPC_ICH9DH,     /* ICH9DH */
184         LPC_ICH9DO,     /* ICH9DO */
185         LPC_ICH9M,      /* ICH9M */
186         LPC_ICH9ME,     /* ICH9M-E */
187         LPC_ICH10,      /* ICH10 */
188         LPC_ICH10R,     /* ICH10R */
189         LPC_ICH10D,     /* ICH10D */
190         LPC_ICH10DO,    /* ICH10DO */
191         LPC_PCH,        /* PCH Desktop Full Featured */
192         LPC_PCHM,       /* PCH Mobile Full Featured */
193         LPC_P55,        /* P55 */
194         LPC_PM55,       /* PM55 */
195         LPC_H55,        /* H55 */
196         LPC_QM57,       /* QM57 */
197         LPC_H57,        /* H57 */
198         LPC_HM55,       /* HM55 */
199         LPC_Q57,        /* Q57 */
200         LPC_HM57,       /* HM57 */
201         LPC_PCHMSFF,    /* PCH Mobile SFF Full Featured */
202         LPC_QS57,       /* QS57 */
203         LPC_3400,       /* 3400 */
204         LPC_3420,       /* 3420 */
205         LPC_3450,       /* 3450 */
206         LPC_EP80579,    /* EP80579 */
207         LPC_CPT,        /* Cougar Point */
208         LPC_CPTD,       /* Cougar Point Desktop */
209         LPC_CPTM,       /* Cougar Point Mobile */
210         LPC_PBG,        /* Patsburg */
211         LPC_DH89XXCC,   /* DH89xxCC */
212         LPC_PPT,        /* Panther Point */
213         LPC_LPT,        /* Lynx Point */
214         LPC_LPT_LP,     /* Lynx Point-LP */
215         LPC_WBG,        /* Wellsburg */
216         LPC_AVN,        /* Avoton SoC */
217         LPC_BAYTRAIL,   /* Bay Trail SoC */
218         LPC_COLETO,     /* Coleto Creek */
219         LPC_WPT_LP,     /* Wildcat Point-LP */
220         LPC_BRASWELL,   /* Braswell SoC */
221         LPC_LEWISBURG,  /* Lewisburg */
222         LPC_9S,         /* 9 Series */
223         LPC_APL,        /* Apollo Lake SoC */
224         LPC_GLK,        /* Gemini Lake SoC */
225         LPC_COUGARMOUNTAIN,/* Cougar Mountain SoC*/
226 };
227
228 static struct lpc_ich_info lpc_chipset_info[] = {
229         [LPC_ICH] = {
230                 .name = "ICH",
231                 .iTCO_version = 1,
232         },
233         [LPC_ICH0] = {
234                 .name = "ICH0",
235                 .iTCO_version = 1,
236         },
237         [LPC_ICH2] = {
238                 .name = "ICH2",
239                 .iTCO_version = 1,
240         },
241         [LPC_ICH2M] = {
242                 .name = "ICH2-M",
243                 .iTCO_version = 1,
244         },
245         [LPC_ICH3] = {
246                 .name = "ICH3-S",
247                 .iTCO_version = 1,
248         },
249         [LPC_ICH3M] = {
250                 .name = "ICH3-M",
251                 .iTCO_version = 1,
252         },
253         [LPC_ICH4] = {
254                 .name = "ICH4",
255                 .iTCO_version = 1,
256         },
257         [LPC_ICH4M] = {
258                 .name = "ICH4-M",
259                 .iTCO_version = 1,
260         },
261         [LPC_CICH] = {
262                 .name = "C-ICH",
263                 .iTCO_version = 1,
264         },
265         [LPC_ICH5] = {
266                 .name = "ICH5 or ICH5R",
267                 .iTCO_version = 1,
268         },
269         [LPC_6300ESB] = {
270                 .name = "6300ESB",
271                 .iTCO_version = 1,
272         },
273         [LPC_ICH6] = {
274                 .name = "ICH6 or ICH6R",
275                 .iTCO_version = 2,
276                 .gpio_version = ICH_V6_GPIO,
277         },
278         [LPC_ICH6M] = {
279                 .name = "ICH6-M",
280                 .iTCO_version = 2,
281                 .gpio_version = ICH_V6_GPIO,
282         },
283         [LPC_ICH6W] = {
284                 .name = "ICH6W or ICH6RW",
285                 .iTCO_version = 2,
286                 .gpio_version = ICH_V6_GPIO,
287         },
288         [LPC_631XESB] = {
289                 .name = "631xESB/632xESB",
290                 .iTCO_version = 2,
291                 .gpio_version = ICH_V6_GPIO,
292         },
293         [LPC_ICH7] = {
294                 .name = "ICH7 or ICH7R",
295                 .iTCO_version = 2,
296                 .gpio_version = ICH_V7_GPIO,
297         },
298         [LPC_ICH7DH] = {
299                 .name = "ICH7DH",
300                 .iTCO_version = 2,
301                 .gpio_version = ICH_V7_GPIO,
302         },
303         [LPC_ICH7M] = {
304                 .name = "ICH7-M or ICH7-U",
305                 .iTCO_version = 2,
306                 .gpio_version = ICH_V7_GPIO,
307         },
308         [LPC_ICH7MDH] = {
309                 .name = "ICH7-M DH",
310                 .iTCO_version = 2,
311                 .gpio_version = ICH_V7_GPIO,
312         },
313         [LPC_NM10] = {
314                 .name = "NM10",
315                 .iTCO_version = 2,
316                 .gpio_version = ICH_V7_GPIO,
317         },
318         [LPC_ICH8] = {
319                 .name = "ICH8 or ICH8R",
320                 .iTCO_version = 2,
321                 .gpio_version = ICH_V7_GPIO,
322         },
323         [LPC_ICH8DH] = {
324                 .name = "ICH8DH",
325                 .iTCO_version = 2,
326                 .gpio_version = ICH_V7_GPIO,
327         },
328         [LPC_ICH8DO] = {
329                 .name = "ICH8DO",
330                 .iTCO_version = 2,
331                 .gpio_version = ICH_V7_GPIO,
332         },
333         [LPC_ICH8M] = {
334                 .name = "ICH8M",
335                 .iTCO_version = 2,
336                 .gpio_version = ICH_V7_GPIO,
337         },
338         [LPC_ICH8ME] = {
339                 .name = "ICH8M-E",
340                 .iTCO_version = 2,
341                 .gpio_version = ICH_V7_GPIO,
342         },
343         [LPC_ICH9] = {
344                 .name = "ICH9",
345                 .iTCO_version = 2,
346                 .gpio_version = ICH_V9_GPIO,
347         },
348         [LPC_ICH9R] = {
349                 .name = "ICH9R",
350                 .iTCO_version = 2,
351                 .gpio_version = ICH_V9_GPIO,
352         },
353         [LPC_ICH9DH] = {
354                 .name = "ICH9DH",
355                 .iTCO_version = 2,
356                 .gpio_version = ICH_V9_GPIO,
357         },
358         [LPC_ICH9DO] = {
359                 .name = "ICH9DO",
360                 .iTCO_version = 2,
361                 .gpio_version = ICH_V9_GPIO,
362         },
363         [LPC_ICH9M] = {
364                 .name = "ICH9M",
365                 .iTCO_version = 2,
366                 .gpio_version = ICH_V9_GPIO,
367         },
368         [LPC_ICH9ME] = {
369                 .name = "ICH9M-E",
370                 .iTCO_version = 2,
371                 .gpio_version = ICH_V9_GPIO,
372         },
373         [LPC_ICH10] = {
374                 .name = "ICH10",
375                 .iTCO_version = 2,
376                 .gpio_version = ICH_V10CONS_GPIO,
377         },
378         [LPC_ICH10R] = {
379                 .name = "ICH10R",
380                 .iTCO_version = 2,
381                 .gpio_version = ICH_V10CONS_GPIO,
382         },
383         [LPC_ICH10D] = {
384                 .name = "ICH10D",
385                 .iTCO_version = 2,
386                 .gpio_version = ICH_V10CORP_GPIO,
387         },
388         [LPC_ICH10DO] = {
389                 .name = "ICH10DO",
390                 .iTCO_version = 2,
391                 .gpio_version = ICH_V10CORP_GPIO,
392         },
393         [LPC_PCH] = {
394                 .name = "PCH Desktop Full Featured",
395                 .iTCO_version = 2,
396                 .gpio_version = ICH_V5_GPIO,
397         },
398         [LPC_PCHM] = {
399                 .name = "PCH Mobile Full Featured",
400                 .iTCO_version = 2,
401                 .gpio_version = ICH_V5_GPIO,
402         },
403         [LPC_P55] = {
404                 .name = "P55",
405                 .iTCO_version = 2,
406                 .gpio_version = ICH_V5_GPIO,
407         },
408         [LPC_PM55] = {
409                 .name = "PM55",
410                 .iTCO_version = 2,
411                 .gpio_version = ICH_V5_GPIO,
412         },
413         [LPC_H55] = {
414                 .name = "H55",
415                 .iTCO_version = 2,
416                 .gpio_version = ICH_V5_GPIO,
417         },
418         [LPC_QM57] = {
419                 .name = "QM57",
420                 .iTCO_version = 2,
421                 .gpio_version = ICH_V5_GPIO,
422         },
423         [LPC_H57] = {
424                 .name = "H57",
425                 .iTCO_version = 2,
426                 .gpio_version = ICH_V5_GPIO,
427         },
428         [LPC_HM55] = {
429                 .name = "HM55",
430                 .iTCO_version = 2,
431                 .gpio_version = ICH_V5_GPIO,
432         },
433         [LPC_Q57] = {
434                 .name = "Q57",
435                 .iTCO_version = 2,
436                 .gpio_version = ICH_V5_GPIO,
437         },
438         [LPC_HM57] = {
439                 .name = "HM57",
440                 .iTCO_version = 2,
441                 .gpio_version = ICH_V5_GPIO,
442         },
443         [LPC_PCHMSFF] = {
444                 .name = "PCH Mobile SFF Full Featured",
445                 .iTCO_version = 2,
446                 .gpio_version = ICH_V5_GPIO,
447         },
448         [LPC_QS57] = {
449                 .name = "QS57",
450                 .iTCO_version = 2,
451                 .gpio_version = ICH_V5_GPIO,
452         },
453         [LPC_3400] = {
454                 .name = "3400",
455                 .iTCO_version = 2,
456                 .gpio_version = ICH_V5_GPIO,
457         },
458         [LPC_3420] = {
459                 .name = "3420",
460                 .iTCO_version = 2,
461                 .gpio_version = ICH_V5_GPIO,
462         },
463         [LPC_3450] = {
464                 .name = "3450",
465                 .iTCO_version = 2,
466                 .gpio_version = ICH_V5_GPIO,
467         },
468         [LPC_EP80579] = {
469                 .name = "EP80579",
470                 .iTCO_version = 2,
471         },
472         [LPC_CPT] = {
473                 .name = "Cougar Point",
474                 .iTCO_version = 2,
475                 .gpio_version = ICH_V5_GPIO,
476         },
477         [LPC_CPTD] = {
478                 .name = "Cougar Point Desktop",
479                 .iTCO_version = 2,
480                 .gpio_version = ICH_V5_GPIO,
481         },
482         [LPC_CPTM] = {
483                 .name = "Cougar Point Mobile",
484                 .iTCO_version = 2,
485                 .gpio_version = ICH_V5_GPIO,
486         },
487         [LPC_PBG] = {
488                 .name = "Patsburg",
489                 .iTCO_version = 2,
490         },
491         [LPC_DH89XXCC] = {
492                 .name = "DH89xxCC",
493                 .iTCO_version = 2,
494         },
495         [LPC_PPT] = {
496                 .name = "Panther Point",
497                 .iTCO_version = 2,
498                 .gpio_version = ICH_V5_GPIO,
499         },
500         [LPC_LPT] = {
501                 .name = "Lynx Point",
502                 .iTCO_version = 2,
503                 .gpio_version = ICH_V5_GPIO,
504                 .spi_type = INTEL_SPI_LPT,
505         },
506         [LPC_LPT_LP] = {
507                 .name = "Lynx Point_LP",
508                 .iTCO_version = 2,
509                 .spi_type = INTEL_SPI_LPT,
510         },
511         [LPC_WBG] = {
512                 .name = "Wellsburg",
513                 .iTCO_version = 2,
514         },
515         [LPC_AVN] = {
516                 .name = "Avoton SoC",
517                 .iTCO_version = 3,
518                 .gpio_version = AVOTON_GPIO,
519                 .spi_type = INTEL_SPI_BYT,
520         },
521         [LPC_BAYTRAIL] = {
522                 .name = "Bay Trail SoC",
523                 .iTCO_version = 3,
524                 .spi_type = INTEL_SPI_BYT,
525         },
526         [LPC_COLETO] = {
527                 .name = "Coleto Creek",
528                 .iTCO_version = 2,
529         },
530         [LPC_WPT_LP] = {
531                 .name = "Wildcat Point_LP",
532                 .iTCO_version = 2,
533                 .spi_type = INTEL_SPI_LPT,
534         },
535         [LPC_BRASWELL] = {
536                 .name = "Braswell SoC",
537                 .iTCO_version = 3,
538                 .spi_type = INTEL_SPI_BYT,
539         },
540         [LPC_LEWISBURG] = {
541                 .name = "Lewisburg",
542                 .iTCO_version = 2,
543         },
544         [LPC_9S] = {
545                 .name = "9 Series",
546                 .iTCO_version = 2,
547                 .gpio_version = ICH_V5_GPIO,
548         },
549         [LPC_APL] = {
550                 .name = "Apollo Lake SoC",
551                 .iTCO_version = 5,
552                 .spi_type = INTEL_SPI_BXT,
553         },
554         [LPC_GLK] = {
555                 .name = "Gemini Lake SoC",
556                 .spi_type = INTEL_SPI_BXT,
557         },
558         [LPC_COUGARMOUNTAIN] = {
559                 .name = "Cougar Mountain SoC",
560                 .iTCO_version = 3,
561         },
562 };
563
564 /*
565  * This data only exists for exporting the supported PCI ids
566  * via MODULE_DEVICE_TABLE.  We do not actually register a
567  * pci_driver, because the I/O Controller Hub has also other
568  * functions that probably will be registered by other drivers.
569  */
570 static const struct pci_device_id lpc_ich_ids[] = {
571         { PCI_VDEVICE(INTEL, 0x0f1c), LPC_BAYTRAIL},
572         { PCI_VDEVICE(INTEL, 0x1c41), LPC_CPT},
573         { PCI_VDEVICE(INTEL, 0x1c42), LPC_CPTD},
574         { PCI_VDEVICE(INTEL, 0x1c43), LPC_CPTM},
575         { PCI_VDEVICE(INTEL, 0x1c44), LPC_CPT},
576         { PCI_VDEVICE(INTEL, 0x1c45), LPC_CPT},
577         { PCI_VDEVICE(INTEL, 0x1c46), LPC_CPT},
578         { PCI_VDEVICE(INTEL, 0x1c47), LPC_CPT},
579         { PCI_VDEVICE(INTEL, 0x1c48), LPC_CPT},
580         { PCI_VDEVICE(INTEL, 0x1c49), LPC_CPT},
581         { PCI_VDEVICE(INTEL, 0x1c4a), LPC_CPT},
582         { PCI_VDEVICE(INTEL, 0x1c4b), LPC_CPT},
583         { PCI_VDEVICE(INTEL, 0x1c4c), LPC_CPT},
584         { PCI_VDEVICE(INTEL, 0x1c4d), LPC_CPT},
585         { PCI_VDEVICE(INTEL, 0x1c4e), LPC_CPT},
586         { PCI_VDEVICE(INTEL, 0x1c4f), LPC_CPT},
587         { PCI_VDEVICE(INTEL, 0x1c50), LPC_CPT},
588         { PCI_VDEVICE(INTEL, 0x1c51), LPC_CPT},
589         { PCI_VDEVICE(INTEL, 0x1c52), LPC_CPT},
590         { PCI_VDEVICE(INTEL, 0x1c53), LPC_CPT},
591         { PCI_VDEVICE(INTEL, 0x1c54), LPC_CPT},
592         { PCI_VDEVICE(INTEL, 0x1c55), LPC_CPT},
593         { PCI_VDEVICE(INTEL, 0x1c56), LPC_CPT},
594         { PCI_VDEVICE(INTEL, 0x1c57), LPC_CPT},
595         { PCI_VDEVICE(INTEL, 0x1c58), LPC_CPT},
596         { PCI_VDEVICE(INTEL, 0x1c59), LPC_CPT},
597         { PCI_VDEVICE(INTEL, 0x1c5a), LPC_CPT},
598         { PCI_VDEVICE(INTEL, 0x1c5b), LPC_CPT},
599         { PCI_VDEVICE(INTEL, 0x1c5c), LPC_CPT},
600         { PCI_VDEVICE(INTEL, 0x1c5d), LPC_CPT},
601         { PCI_VDEVICE(INTEL, 0x1c5e), LPC_CPT},
602         { PCI_VDEVICE(INTEL, 0x1c5f), LPC_CPT},
603         { PCI_VDEVICE(INTEL, 0x1d40), LPC_PBG},
604         { PCI_VDEVICE(INTEL, 0x1d41), LPC_PBG},
605         { PCI_VDEVICE(INTEL, 0x1e40), LPC_PPT},
606         { PCI_VDEVICE(INTEL, 0x1e41), LPC_PPT},
607         { PCI_VDEVICE(INTEL, 0x1e42), LPC_PPT},
608         { PCI_VDEVICE(INTEL, 0x1e43), LPC_PPT},
609         { PCI_VDEVICE(INTEL, 0x1e44), LPC_PPT},
610         { PCI_VDEVICE(INTEL, 0x1e45), LPC_PPT},
611         { PCI_VDEVICE(INTEL, 0x1e46), LPC_PPT},
612         { PCI_VDEVICE(INTEL, 0x1e47), LPC_PPT},
613         { PCI_VDEVICE(INTEL, 0x1e48), LPC_PPT},
614         { PCI_VDEVICE(INTEL, 0x1e49), LPC_PPT},
615         { PCI_VDEVICE(INTEL, 0x1e4a), LPC_PPT},
616         { PCI_VDEVICE(INTEL, 0x1e4b), LPC_PPT},
617         { PCI_VDEVICE(INTEL, 0x1e4c), LPC_PPT},
618         { PCI_VDEVICE(INTEL, 0x1e4d), LPC_PPT},
619         { PCI_VDEVICE(INTEL, 0x1e4e), LPC_PPT},
620         { PCI_VDEVICE(INTEL, 0x1e4f), LPC_PPT},
621         { PCI_VDEVICE(INTEL, 0x1e50), LPC_PPT},
622         { PCI_VDEVICE(INTEL, 0x1e51), LPC_PPT},
623         { PCI_VDEVICE(INTEL, 0x1e52), LPC_PPT},
624         { PCI_VDEVICE(INTEL, 0x1e53), LPC_PPT},
625         { PCI_VDEVICE(INTEL, 0x1e54), LPC_PPT},
626         { PCI_VDEVICE(INTEL, 0x1e55), LPC_PPT},
627         { PCI_VDEVICE(INTEL, 0x1e56), LPC_PPT},
628         { PCI_VDEVICE(INTEL, 0x1e57), LPC_PPT},
629         { PCI_VDEVICE(INTEL, 0x1e58), LPC_PPT},
630         { PCI_VDEVICE(INTEL, 0x1e59), LPC_PPT},
631         { PCI_VDEVICE(INTEL, 0x1e5a), LPC_PPT},
632         { PCI_VDEVICE(INTEL, 0x1e5b), LPC_PPT},
633         { PCI_VDEVICE(INTEL, 0x1e5c), LPC_PPT},
634         { PCI_VDEVICE(INTEL, 0x1e5d), LPC_PPT},
635         { PCI_VDEVICE(INTEL, 0x1e5e), LPC_PPT},
636         { PCI_VDEVICE(INTEL, 0x1e5f), LPC_PPT},
637         { PCI_VDEVICE(INTEL, 0x1f38), LPC_AVN},
638         { PCI_VDEVICE(INTEL, 0x1f39), LPC_AVN},
639         { PCI_VDEVICE(INTEL, 0x1f3a), LPC_AVN},
640         { PCI_VDEVICE(INTEL, 0x1f3b), LPC_AVN},
641         { PCI_VDEVICE(INTEL, 0x229c), LPC_BRASWELL},
642         { PCI_VDEVICE(INTEL, 0x2310), LPC_DH89XXCC},
643         { PCI_VDEVICE(INTEL, 0x2390), LPC_COLETO},
644         { PCI_VDEVICE(INTEL, 0x2410), LPC_ICH},
645         { PCI_VDEVICE(INTEL, 0x2420), LPC_ICH0},
646         { PCI_VDEVICE(INTEL, 0x2440), LPC_ICH2},
647         { PCI_VDEVICE(INTEL, 0x244c), LPC_ICH2M},
648         { PCI_VDEVICE(INTEL, 0x2450), LPC_CICH},
649         { PCI_VDEVICE(INTEL, 0x2480), LPC_ICH3},
650         { PCI_VDEVICE(INTEL, 0x248c), LPC_ICH3M},
651         { PCI_VDEVICE(INTEL, 0x24c0), LPC_ICH4},
652         { PCI_VDEVICE(INTEL, 0x24cc), LPC_ICH4M},
653         { PCI_VDEVICE(INTEL, 0x24d0), LPC_ICH5},
654         { PCI_VDEVICE(INTEL, 0x25a1), LPC_6300ESB},
655         { PCI_VDEVICE(INTEL, 0x2640), LPC_ICH6},
656         { PCI_VDEVICE(INTEL, 0x2641), LPC_ICH6M},
657         { PCI_VDEVICE(INTEL, 0x2642), LPC_ICH6W},
658         { PCI_VDEVICE(INTEL, 0x2670), LPC_631XESB},
659         { PCI_VDEVICE(INTEL, 0x2671), LPC_631XESB},
660         { PCI_VDEVICE(INTEL, 0x2672), LPC_631XESB},
661         { PCI_VDEVICE(INTEL, 0x2673), LPC_631XESB},
662         { PCI_VDEVICE(INTEL, 0x2674), LPC_631XESB},
663         { PCI_VDEVICE(INTEL, 0x2675), LPC_631XESB},
664         { PCI_VDEVICE(INTEL, 0x2676), LPC_631XESB},
665         { PCI_VDEVICE(INTEL, 0x2677), LPC_631XESB},
666         { PCI_VDEVICE(INTEL, 0x2678), LPC_631XESB},
667         { PCI_VDEVICE(INTEL, 0x2679), LPC_631XESB},
668         { PCI_VDEVICE(INTEL, 0x267a), LPC_631XESB},
669         { PCI_VDEVICE(INTEL, 0x267b), LPC_631XESB},
670         { PCI_VDEVICE(INTEL, 0x267c), LPC_631XESB},
671         { PCI_VDEVICE(INTEL, 0x267d), LPC_631XESB},
672         { PCI_VDEVICE(INTEL, 0x267e), LPC_631XESB},
673         { PCI_VDEVICE(INTEL, 0x267f), LPC_631XESB},
674         { PCI_VDEVICE(INTEL, 0x27b0), LPC_ICH7DH},
675         { PCI_VDEVICE(INTEL, 0x27b8), LPC_ICH7},
676         { PCI_VDEVICE(INTEL, 0x27b9), LPC_ICH7M},
677         { PCI_VDEVICE(INTEL, 0x27bc), LPC_NM10},
678         { PCI_VDEVICE(INTEL, 0x27bd), LPC_ICH7MDH},
679         { PCI_VDEVICE(INTEL, 0x2810), LPC_ICH8},
680         { PCI_VDEVICE(INTEL, 0x2811), LPC_ICH8ME},
681         { PCI_VDEVICE(INTEL, 0x2812), LPC_ICH8DH},
682         { PCI_VDEVICE(INTEL, 0x2814), LPC_ICH8DO},
683         { PCI_VDEVICE(INTEL, 0x2815), LPC_ICH8M},
684         { PCI_VDEVICE(INTEL, 0x2912), LPC_ICH9DH},
685         { PCI_VDEVICE(INTEL, 0x2914), LPC_ICH9DO},
686         { PCI_VDEVICE(INTEL, 0x2916), LPC_ICH9R},
687         { PCI_VDEVICE(INTEL, 0x2917), LPC_ICH9ME},
688         { PCI_VDEVICE(INTEL, 0x2918), LPC_ICH9},
689         { PCI_VDEVICE(INTEL, 0x2919), LPC_ICH9M},
690         { PCI_VDEVICE(INTEL, 0x3197), LPC_GLK},
691         { PCI_VDEVICE(INTEL, 0x2b9c), LPC_COUGARMOUNTAIN},
692         { PCI_VDEVICE(INTEL, 0x3a14), LPC_ICH10DO},
693         { PCI_VDEVICE(INTEL, 0x3a16), LPC_ICH10R},
694         { PCI_VDEVICE(INTEL, 0x3a18), LPC_ICH10},
695         { PCI_VDEVICE(INTEL, 0x3a1a), LPC_ICH10D},
696         { PCI_VDEVICE(INTEL, 0x3b00), LPC_PCH},
697         { PCI_VDEVICE(INTEL, 0x3b01), LPC_PCHM},
698         { PCI_VDEVICE(INTEL, 0x3b02), LPC_P55},
699         { PCI_VDEVICE(INTEL, 0x3b03), LPC_PM55},
700         { PCI_VDEVICE(INTEL, 0x3b06), LPC_H55},
701         { PCI_VDEVICE(INTEL, 0x3b07), LPC_QM57},
702         { PCI_VDEVICE(INTEL, 0x3b08), LPC_H57},
703         { PCI_VDEVICE(INTEL, 0x3b09), LPC_HM55},
704         { PCI_VDEVICE(INTEL, 0x3b0a), LPC_Q57},
705         { PCI_VDEVICE(INTEL, 0x3b0b), LPC_HM57},
706         { PCI_VDEVICE(INTEL, 0x3b0d), LPC_PCHMSFF},
707         { PCI_VDEVICE(INTEL, 0x3b0f), LPC_QS57},
708         { PCI_VDEVICE(INTEL, 0x3b12), LPC_3400},
709         { PCI_VDEVICE(INTEL, 0x3b14), LPC_3420},
710         { PCI_VDEVICE(INTEL, 0x3b16), LPC_3450},
711         { PCI_VDEVICE(INTEL, 0x5031), LPC_EP80579},
712         { PCI_VDEVICE(INTEL, 0x5ae8), LPC_APL},
713         { PCI_VDEVICE(INTEL, 0x8c40), LPC_LPT},
714         { PCI_VDEVICE(INTEL, 0x8c41), LPC_LPT},
715         { PCI_VDEVICE(INTEL, 0x8c42), LPC_LPT},
716         { PCI_VDEVICE(INTEL, 0x8c43), LPC_LPT},
717         { PCI_VDEVICE(INTEL, 0x8c44), LPC_LPT},
718         { PCI_VDEVICE(INTEL, 0x8c45), LPC_LPT},
719         { PCI_VDEVICE(INTEL, 0x8c46), LPC_LPT},
720         { PCI_VDEVICE(INTEL, 0x8c47), LPC_LPT},
721         { PCI_VDEVICE(INTEL, 0x8c48), LPC_LPT},
722         { PCI_VDEVICE(INTEL, 0x8c49), LPC_LPT},
723         { PCI_VDEVICE(INTEL, 0x8c4a), LPC_LPT},
724         { PCI_VDEVICE(INTEL, 0x8c4b), LPC_LPT},
725         { PCI_VDEVICE(INTEL, 0x8c4c), LPC_LPT},
726         { PCI_VDEVICE(INTEL, 0x8c4d), LPC_LPT},
727         { PCI_VDEVICE(INTEL, 0x8c4e), LPC_LPT},
728         { PCI_VDEVICE(INTEL, 0x8c4f), LPC_LPT},
729         { PCI_VDEVICE(INTEL, 0x8c50), LPC_LPT},
730         { PCI_VDEVICE(INTEL, 0x8c51), LPC_LPT},
731         { PCI_VDEVICE(INTEL, 0x8c52), LPC_LPT},
732         { PCI_VDEVICE(INTEL, 0x8c53), LPC_LPT},
733         { PCI_VDEVICE(INTEL, 0x8c54), LPC_LPT},
734         { PCI_VDEVICE(INTEL, 0x8c55), LPC_LPT},
735         { PCI_VDEVICE(INTEL, 0x8c56), LPC_LPT},
736         { PCI_VDEVICE(INTEL, 0x8c57), LPC_LPT},
737         { PCI_VDEVICE(INTEL, 0x8c58), LPC_LPT},
738         { PCI_VDEVICE(INTEL, 0x8c59), LPC_LPT},
739         { PCI_VDEVICE(INTEL, 0x8c5a), LPC_LPT},
740         { PCI_VDEVICE(INTEL, 0x8c5b), LPC_LPT},
741         { PCI_VDEVICE(INTEL, 0x8c5c), LPC_LPT},
742         { PCI_VDEVICE(INTEL, 0x8c5d), LPC_LPT},
743         { PCI_VDEVICE(INTEL, 0x8c5e), LPC_LPT},
744         { PCI_VDEVICE(INTEL, 0x8c5f), LPC_LPT},
745         { PCI_VDEVICE(INTEL, 0x8cc1), LPC_9S},
746         { PCI_VDEVICE(INTEL, 0x8cc2), LPC_9S},
747         { PCI_VDEVICE(INTEL, 0x8cc3), LPC_9S},
748         { PCI_VDEVICE(INTEL, 0x8cc4), LPC_9S},
749         { PCI_VDEVICE(INTEL, 0x8cc6), LPC_9S},
750         { PCI_VDEVICE(INTEL, 0x8d40), LPC_WBG},
751         { PCI_VDEVICE(INTEL, 0x8d41), LPC_WBG},
752         { PCI_VDEVICE(INTEL, 0x8d42), LPC_WBG},
753         { PCI_VDEVICE(INTEL, 0x8d43), LPC_WBG},
754         { PCI_VDEVICE(INTEL, 0x8d44), LPC_WBG},
755         { PCI_VDEVICE(INTEL, 0x8d45), LPC_WBG},
756         { PCI_VDEVICE(INTEL, 0x8d46), LPC_WBG},
757         { PCI_VDEVICE(INTEL, 0x8d47), LPC_WBG},
758         { PCI_VDEVICE(INTEL, 0x8d48), LPC_WBG},
759         { PCI_VDEVICE(INTEL, 0x8d49), LPC_WBG},
760         { PCI_VDEVICE(INTEL, 0x8d4a), LPC_WBG},
761         { PCI_VDEVICE(INTEL, 0x8d4b), LPC_WBG},
762         { PCI_VDEVICE(INTEL, 0x8d4c), LPC_WBG},
763         { PCI_VDEVICE(INTEL, 0x8d4d), LPC_WBG},
764         { PCI_VDEVICE(INTEL, 0x8d4e), LPC_WBG},
765         { PCI_VDEVICE(INTEL, 0x8d4f), LPC_WBG},
766         { PCI_VDEVICE(INTEL, 0x8d50), LPC_WBG},
767         { PCI_VDEVICE(INTEL, 0x8d51), LPC_WBG},
768         { PCI_VDEVICE(INTEL, 0x8d52), LPC_WBG},
769         { PCI_VDEVICE(INTEL, 0x8d53), LPC_WBG},
770         { PCI_VDEVICE(INTEL, 0x8d54), LPC_WBG},
771         { PCI_VDEVICE(INTEL, 0x8d55), LPC_WBG},
772         { PCI_VDEVICE(INTEL, 0x8d56), LPC_WBG},
773         { PCI_VDEVICE(INTEL, 0x8d57), LPC_WBG},
774         { PCI_VDEVICE(INTEL, 0x8d58), LPC_WBG},
775         { PCI_VDEVICE(INTEL, 0x8d59), LPC_WBG},
776         { PCI_VDEVICE(INTEL, 0x8d5a), LPC_WBG},
777         { PCI_VDEVICE(INTEL, 0x8d5b), LPC_WBG},
778         { PCI_VDEVICE(INTEL, 0x8d5c), LPC_WBG},
779         { PCI_VDEVICE(INTEL, 0x8d5d), LPC_WBG},
780         { PCI_VDEVICE(INTEL, 0x8d5e), LPC_WBG},
781         { PCI_VDEVICE(INTEL, 0x8d5f), LPC_WBG},
782         { PCI_VDEVICE(INTEL, 0x9c40), LPC_LPT_LP},
783         { PCI_VDEVICE(INTEL, 0x9c41), LPC_LPT_LP},
784         { PCI_VDEVICE(INTEL, 0x9c42), LPC_LPT_LP},
785         { PCI_VDEVICE(INTEL, 0x9c43), LPC_LPT_LP},
786         { PCI_VDEVICE(INTEL, 0x9c44), LPC_LPT_LP},
787         { PCI_VDEVICE(INTEL, 0x9c45), LPC_LPT_LP},
788         { PCI_VDEVICE(INTEL, 0x9c46), LPC_LPT_LP},
789         { PCI_VDEVICE(INTEL, 0x9c47), LPC_LPT_LP},
790         { PCI_VDEVICE(INTEL, 0x9cc1), LPC_WPT_LP},
791         { PCI_VDEVICE(INTEL, 0x9cc2), LPC_WPT_LP},
792         { PCI_VDEVICE(INTEL, 0x9cc3), LPC_WPT_LP},
793         { PCI_VDEVICE(INTEL, 0x9cc5), LPC_WPT_LP},
794         { PCI_VDEVICE(INTEL, 0x9cc6), LPC_WPT_LP},
795         { PCI_VDEVICE(INTEL, 0x9cc7), LPC_WPT_LP},
796         { PCI_VDEVICE(INTEL, 0x9cc9), LPC_WPT_LP},
797         { PCI_VDEVICE(INTEL, 0xa1c1), LPC_LEWISBURG},
798         { PCI_VDEVICE(INTEL, 0xa1c2), LPC_LEWISBURG},
799         { PCI_VDEVICE(INTEL, 0xa1c3), LPC_LEWISBURG},
800         { PCI_VDEVICE(INTEL, 0xa1c4), LPC_LEWISBURG},
801         { PCI_VDEVICE(INTEL, 0xa1c5), LPC_LEWISBURG},
802         { PCI_VDEVICE(INTEL, 0xa1c6), LPC_LEWISBURG},
803         { PCI_VDEVICE(INTEL, 0xa1c7), LPC_LEWISBURG},
804         { PCI_VDEVICE(INTEL, 0xa242), LPC_LEWISBURG},
805         { PCI_VDEVICE(INTEL, 0xa243), LPC_LEWISBURG},
806         { 0, },                 /* End of list */
807 };
808 MODULE_DEVICE_TABLE(pci, lpc_ich_ids);
809
810 static void lpc_ich_restore_config_space(struct pci_dev *dev)
811 {
812         struct lpc_ich_priv *priv = pci_get_drvdata(dev);
813
814         if (priv->abase_save >= 0) {
815                 pci_write_config_byte(dev, priv->abase, priv->abase_save);
816                 priv->abase_save = -1;
817         }
818
819         if (priv->actrl_pbase_save >= 0) {
820                 pci_write_config_byte(dev, priv->actrl_pbase,
821                         priv->actrl_pbase_save);
822                 priv->actrl_pbase_save = -1;
823         }
824
825         if (priv->gctrl_save >= 0) {
826                 pci_write_config_byte(dev, priv->gctrl, priv->gctrl_save);
827                 priv->gctrl_save = -1;
828         }
829 }
830
831 static void lpc_ich_enable_acpi_space(struct pci_dev *dev)
832 {
833         struct lpc_ich_priv *priv = pci_get_drvdata(dev);
834         u8 reg_save;
835
836         switch (lpc_chipset_info[priv->chipset].iTCO_version) {
837         case 3:
838                 /*
839                  * Some chipsets (eg Avoton) enable the ACPI space in the
840                  * ACPI BASE register.
841                  */
842                 pci_read_config_byte(dev, priv->abase, &reg_save);
843                 pci_write_config_byte(dev, priv->abase, reg_save | 0x2);
844                 priv->abase_save = reg_save;
845                 break;
846         default:
847                 /*
848                  * Most chipsets enable the ACPI space in the ACPI control
849                  * register.
850                  */
851                 pci_read_config_byte(dev, priv->actrl_pbase, &reg_save);
852                 pci_write_config_byte(dev, priv->actrl_pbase, reg_save | 0x80);
853                 priv->actrl_pbase_save = reg_save;
854                 break;
855         }
856 }
857
858 static void lpc_ich_enable_gpio_space(struct pci_dev *dev)
859 {
860         struct lpc_ich_priv *priv = pci_get_drvdata(dev);
861         u8 reg_save;
862
863         pci_read_config_byte(dev, priv->gctrl, &reg_save);
864         pci_write_config_byte(dev, priv->gctrl, reg_save | 0x10);
865         priv->gctrl_save = reg_save;
866 }
867
868 static void lpc_ich_enable_pmc_space(struct pci_dev *dev)
869 {
870         struct lpc_ich_priv *priv = pci_get_drvdata(dev);
871         u8 reg_save;
872
873         pci_read_config_byte(dev, priv->actrl_pbase, &reg_save);
874         pci_write_config_byte(dev, priv->actrl_pbase, reg_save | 0x2);
875
876         priv->actrl_pbase_save = reg_save;
877 }
878
879 static int lpc_ich_finalize_wdt_cell(struct pci_dev *dev)
880 {
881         struct itco_wdt_platform_data *pdata;
882         struct lpc_ich_priv *priv = pci_get_drvdata(dev);
883         struct lpc_ich_info *info;
884         struct mfd_cell *cell = &lpc_ich_wdt_cell;
885
886         pdata = devm_kzalloc(&dev->dev, sizeof(*pdata), GFP_KERNEL);
887         if (!pdata)
888                 return -ENOMEM;
889
890         info = &lpc_chipset_info[priv->chipset];
891
892         pdata->version = info->iTCO_version;
893         strlcpy(pdata->name, info->name, sizeof(pdata->name));
894
895         cell->platform_data = pdata;
896         cell->pdata_size = sizeof(*pdata);
897         return 0;
898 }
899
900 static void lpc_ich_finalize_gpio_cell(struct pci_dev *dev)
901 {
902         struct lpc_ich_priv *priv = pci_get_drvdata(dev);
903         struct mfd_cell *cell = &lpc_ich_gpio_cell;
904
905         cell->platform_data = &lpc_chipset_info[priv->chipset];
906         cell->pdata_size = sizeof(struct lpc_ich_info);
907 }
908
909 /*
910  * We don't check for resource conflict globally. There are 2 or 3 independent
911  * GPIO groups and it's enough to have access to one of these to instantiate
912  * the device.
913  */
914 static int lpc_ich_check_conflict_gpio(struct resource *res)
915 {
916         int ret;
917         u8 use_gpio = 0;
918
919         if (resource_size(res) >= 0x50 &&
920             !acpi_check_region(res->start + 0x40, 0x10, "LPC ICH GPIO3"))
921                 use_gpio |= 1 << 2;
922
923         if (!acpi_check_region(res->start + 0x30, 0x10, "LPC ICH GPIO2"))
924                 use_gpio |= 1 << 1;
925
926         ret = acpi_check_region(res->start + 0x00, 0x30, "LPC ICH GPIO1");
927         if (!ret)
928                 use_gpio |= 1 << 0;
929
930         return use_gpio ? use_gpio : ret;
931 }
932
933 static int lpc_ich_init_gpio(struct pci_dev *dev)
934 {
935         struct lpc_ich_priv *priv = pci_get_drvdata(dev);
936         u32 base_addr_cfg;
937         u32 base_addr;
938         int ret;
939         bool acpi_conflict = false;
940         struct resource *res;
941
942         /* Setup power management base register */
943         pci_read_config_dword(dev, priv->abase, &base_addr_cfg);
944         base_addr = base_addr_cfg & 0x0000ff80;
945         if (!base_addr) {
946                 dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n");
947                 lpc_ich_gpio_cell.num_resources--;
948                 goto gpe0_done;
949         }
950
951         res = &gpio_ich_res[ICH_RES_GPE0];
952         res->start = base_addr + ACPIBASE_GPE_OFF;
953         res->end = base_addr + ACPIBASE_GPE_END;
954         ret = acpi_check_resource_conflict(res);
955         if (ret) {
956                 /*
957                  * This isn't fatal for the GPIO, but we have to make sure that
958                  * the platform_device subsystem doesn't see this resource
959                  * or it will register an invalid region.
960                  */
961                 lpc_ich_gpio_cell.num_resources--;
962                 acpi_conflict = true;
963         } else {
964                 lpc_ich_enable_acpi_space(dev);
965         }
966
967 gpe0_done:
968         /* Setup GPIO base register */
969         pci_read_config_dword(dev, priv->gbase, &base_addr_cfg);
970         base_addr = base_addr_cfg & 0x0000ff80;
971         if (!base_addr) {
972                 dev_notice(&dev->dev, "I/O space for GPIO uninitialized\n");
973                 ret = -ENODEV;
974                 goto gpio_done;
975         }
976
977         /* Older devices provide fewer GPIO and have a smaller resource size. */
978         res = &gpio_ich_res[ICH_RES_GPIO];
979         res->start = base_addr;
980         switch (lpc_chipset_info[priv->chipset].gpio_version) {
981         case ICH_V5_GPIO:
982         case ICH_V10CORP_GPIO:
983                 res->end = res->start + 128 - 1;
984                 break;
985         default:
986                 res->end = res->start + 64 - 1;
987                 break;
988         }
989
990         ret = lpc_ich_check_conflict_gpio(res);
991         if (ret < 0) {
992                 /* this isn't necessarily fatal for the GPIO */
993                 acpi_conflict = true;
994                 goto gpio_done;
995         }
996         lpc_chipset_info[priv->chipset].use_gpio = ret;
997         lpc_ich_enable_gpio_space(dev);
998
999         lpc_ich_finalize_gpio_cell(dev);
1000         ret = mfd_add_devices(&dev->dev, PLATFORM_DEVID_AUTO,
1001                               &lpc_ich_gpio_cell, 1, NULL, 0, NULL);
1002
1003 gpio_done:
1004         if (acpi_conflict)
1005                 pr_warn("Resource conflict(s) found affecting %s\n",
1006                                 lpc_ich_gpio_cell.name);
1007         return ret;
1008 }
1009
1010 static int lpc_ich_init_wdt(struct pci_dev *dev)
1011 {
1012         struct lpc_ich_priv *priv = pci_get_drvdata(dev);
1013         u32 base_addr_cfg;
1014         u32 base_addr;
1015         int ret;
1016         struct resource *res;
1017
1018         /* If we have ACPI based watchdog use that instead */
1019         if (acpi_has_watchdog())
1020                 return -ENODEV;
1021
1022         /* Setup power management base register */
1023         pci_read_config_dword(dev, priv->abase, &base_addr_cfg);
1024         base_addr = base_addr_cfg & 0x0000ff80;
1025         if (!base_addr) {
1026                 dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n");
1027                 ret = -ENODEV;
1028                 goto wdt_done;
1029         }
1030
1031         res = wdt_io_res(ICH_RES_IO_TCO);
1032         res->start = base_addr + ACPIBASE_TCO_OFF;
1033         res->end = base_addr + ACPIBASE_TCO_END;
1034
1035         res = wdt_io_res(ICH_RES_IO_SMI);
1036         res->start = base_addr + ACPIBASE_SMI_OFF;
1037         res->end = base_addr + ACPIBASE_SMI_END;
1038
1039         lpc_ich_enable_acpi_space(dev);
1040
1041         /*
1042          * iTCO v2:
1043          * Get the Memory-Mapped GCS register. To get access to it
1044          * we have to read RCBA from PCI Config space 0xf0 and use
1045          * it as base. GCS = RCBA + ICH6_GCS(0x3410).
1046          *
1047          * iTCO v3:
1048          * Get the Power Management Configuration register.  To get access
1049          * to it we have to read the PMC BASE from config space and address
1050          * the register at offset 0x8.
1051          */
1052         if (lpc_chipset_info[priv->chipset].iTCO_version == 1) {
1053                 /* Don't register iomem for TCO ver 1 */
1054                 lpc_ich_wdt_cell.num_resources--;
1055         } else if (lpc_chipset_info[priv->chipset].iTCO_version == 2) {
1056                 pci_read_config_dword(dev, RCBABASE, &base_addr_cfg);
1057                 base_addr = base_addr_cfg & 0xffffc000;
1058                 if (!(base_addr_cfg & 1)) {
1059                         dev_notice(&dev->dev, "RCBA is disabled by "
1060                                         "hardware/BIOS, device disabled\n");
1061                         ret = -ENODEV;
1062                         goto wdt_done;
1063                 }
1064                 res = wdt_mem_res(ICH_RES_MEM_GCS_PMC);
1065                 res->start = base_addr + ACPIBASE_GCS_OFF;
1066                 res->end = base_addr + ACPIBASE_GCS_END;
1067         } else if (lpc_chipset_info[priv->chipset].iTCO_version == 3) {
1068                 lpc_ich_enable_pmc_space(dev);
1069                 pci_read_config_dword(dev, ACPICTRL_PMCBASE, &base_addr_cfg);
1070                 base_addr = base_addr_cfg & 0xfffffe00;
1071
1072                 res = wdt_mem_res(ICH_RES_MEM_GCS_PMC);
1073                 res->start = base_addr + ACPIBASE_PMC_OFF;
1074                 res->end = base_addr + ACPIBASE_PMC_END;
1075         }
1076
1077         ret = lpc_ich_finalize_wdt_cell(dev);
1078         if (ret)
1079                 goto wdt_done;
1080
1081         ret = mfd_add_devices(&dev->dev, PLATFORM_DEVID_AUTO,
1082                               &lpc_ich_wdt_cell, 1, NULL, 0, NULL);
1083
1084 wdt_done:
1085         return ret;
1086 }
1087
1088 static bool lpc_ich_byt_set_writeable(void __iomem *base, void *data)
1089 {
1090         u32 val;
1091
1092         val = readl(base + BYT_BCR);
1093         if (!(val & BYT_BCR_WPD)) {
1094                 val |= BYT_BCR_WPD;
1095                 writel(val, base + BYT_BCR);
1096                 val = readl(base + BYT_BCR);
1097         }
1098
1099         return val & BYT_BCR_WPD;
1100 }
1101
1102 static bool lpc_ich_lpt_set_writeable(void __iomem *base, void *data)
1103 {
1104         struct pci_dev *pdev = data;
1105         u32 bcr;
1106
1107         pci_read_config_dword(pdev, BCR, &bcr);
1108         if (!(bcr & BCR_WPD)) {
1109                 bcr |= BCR_WPD;
1110                 pci_write_config_dword(pdev, BCR, bcr);
1111                 pci_read_config_dword(pdev, BCR, &bcr);
1112         }
1113
1114         return bcr & BCR_WPD;
1115 }
1116
1117 static bool lpc_ich_bxt_set_writeable(void __iomem *base, void *data)
1118 {
1119         unsigned int spi = PCI_DEVFN(13, 2);
1120         struct pci_bus *bus = data;
1121         u32 bcr;
1122
1123         pci_bus_read_config_dword(bus, spi, BCR, &bcr);
1124         if (!(bcr & BCR_WPD)) {
1125                 bcr |= BCR_WPD;
1126                 pci_bus_write_config_dword(bus, spi, BCR, bcr);
1127                 pci_bus_read_config_dword(bus, spi, BCR, &bcr);
1128         }
1129
1130         return bcr & BCR_WPD;
1131 }
1132
1133 static int lpc_ich_init_spi(struct pci_dev *dev)
1134 {
1135         struct lpc_ich_priv *priv = pci_get_drvdata(dev);
1136         struct resource *res = &intel_spi_res[0];
1137         struct intel_spi_boardinfo *info;
1138         u32 spi_base, rcba;
1139
1140         info = devm_kzalloc(&dev->dev, sizeof(*info), GFP_KERNEL);
1141         if (!info)
1142                 return -ENOMEM;
1143
1144         info->type = lpc_chipset_info[priv->chipset].spi_type;
1145
1146         switch (info->type) {
1147         case INTEL_SPI_BYT:
1148                 pci_read_config_dword(dev, SPIBASE_BYT, &spi_base);
1149                 if (spi_base & SPIBASE_BYT_EN) {
1150                         res->start = spi_base & ~(SPIBASE_BYT_SZ - 1);
1151                         res->end = res->start + SPIBASE_BYT_SZ - 1;
1152
1153                         info->set_writeable = lpc_ich_byt_set_writeable;
1154                 }
1155                 break;
1156
1157         case INTEL_SPI_LPT:
1158                 pci_read_config_dword(dev, RCBABASE, &rcba);
1159                 if (rcba & 1) {
1160                         spi_base = round_down(rcba, SPIBASE_LPT_SZ);
1161                         res->start = spi_base + SPIBASE_LPT;
1162                         res->end = res->start + SPIBASE_LPT_SZ - 1;
1163
1164                         info->set_writeable = lpc_ich_lpt_set_writeable;
1165                         info->data = dev;
1166                 }
1167                 break;
1168
1169         case INTEL_SPI_BXT: {
1170                 unsigned int p2sb = PCI_DEVFN(13, 0);
1171                 unsigned int spi = PCI_DEVFN(13, 2);
1172                 struct pci_bus *bus = dev->bus;
1173
1174                 /*
1175                  * The P2SB is hidden by BIOS and we need to unhide it in
1176                  * order to read BAR of the SPI flash device. Once that is
1177                  * done we hide it again.
1178                  */
1179                 pci_bus_write_config_byte(bus, p2sb, 0xe1, 0x0);
1180                 pci_bus_read_config_dword(bus, spi, PCI_BASE_ADDRESS_0,
1181                                           &spi_base);
1182                 if (spi_base != ~0) {
1183                         res->start = spi_base & 0xfffffff0;
1184                         res->end = res->start + SPIBASE_APL_SZ - 1;
1185
1186                         info->set_writeable = lpc_ich_bxt_set_writeable;
1187                         info->data = bus;
1188                 }
1189
1190                 pci_bus_write_config_byte(bus, p2sb, 0xe1, 0x1);
1191                 break;
1192         }
1193
1194         default:
1195                 return -EINVAL;
1196         }
1197
1198         if (!res->start)
1199                 return -ENODEV;
1200
1201         lpc_ich_spi_cell.platform_data = info;
1202         lpc_ich_spi_cell.pdata_size = sizeof(*info);
1203
1204         return mfd_add_devices(&dev->dev, PLATFORM_DEVID_NONE,
1205                                &lpc_ich_spi_cell, 1, NULL, 0, NULL);
1206 }
1207
1208 static int lpc_ich_probe(struct pci_dev *dev,
1209                                 const struct pci_device_id *id)
1210 {
1211         struct lpc_ich_priv *priv;
1212         int ret;
1213         bool cell_added = false;
1214
1215         priv = devm_kzalloc(&dev->dev,
1216                             sizeof(struct lpc_ich_priv), GFP_KERNEL);
1217         if (!priv)
1218                 return -ENOMEM;
1219
1220         priv->chipset = id->driver_data;
1221
1222         priv->actrl_pbase_save = -1;
1223         priv->abase_save = -1;
1224
1225         priv->abase = ACPIBASE;
1226         priv->actrl_pbase = ACPICTRL_PMCBASE;
1227
1228         priv->gctrl_save = -1;
1229         if (priv->chipset <= LPC_ICH5) {
1230                 priv->gbase = GPIOBASE_ICH0;
1231                 priv->gctrl = GPIOCTRL_ICH0;
1232         } else {
1233                 priv->gbase = GPIOBASE_ICH6;
1234                 priv->gctrl = GPIOCTRL_ICH6;
1235         }
1236
1237         pci_set_drvdata(dev, priv);
1238
1239         if (lpc_chipset_info[priv->chipset].iTCO_version) {
1240                 ret = lpc_ich_init_wdt(dev);
1241                 if (!ret)
1242                         cell_added = true;
1243         }
1244
1245         if (lpc_chipset_info[priv->chipset].gpio_version) {
1246                 ret = lpc_ich_init_gpio(dev);
1247                 if (!ret)
1248                         cell_added = true;
1249         }
1250
1251         if (lpc_chipset_info[priv->chipset].spi_type) {
1252                 ret = lpc_ich_init_spi(dev);
1253                 if (!ret)
1254                         cell_added = true;
1255         }
1256
1257         /*
1258          * We only care if at least one or none of the cells registered
1259          * successfully.
1260          */
1261         if (!cell_added) {
1262                 dev_warn(&dev->dev, "No MFD cells added\n");
1263                 lpc_ich_restore_config_space(dev);
1264                 return -ENODEV;
1265         }
1266
1267         return 0;
1268 }
1269
1270 static void lpc_ich_remove(struct pci_dev *dev)
1271 {
1272         mfd_remove_devices(&dev->dev);
1273         lpc_ich_restore_config_space(dev);
1274 }
1275
1276 static struct pci_driver lpc_ich_driver = {
1277         .name           = "lpc_ich",
1278         .id_table       = lpc_ich_ids,
1279         .probe          = lpc_ich_probe,
1280         .remove         = lpc_ich_remove,
1281 };
1282
1283 module_pci_driver(lpc_ich_driver);
1284
1285 MODULE_AUTHOR("Aaron Sierra <asierra@xes-inc.com>");
1286 MODULE_DESCRIPTION("LPC interface for Intel ICH");
1287 MODULE_LICENSE("GPL");